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Enhanced
Features
s s s
Memory Systems Inc.
DM2202/2212 EDRAM 1Mb x 4 Enhanced Dynamic RAM
Product Specification
2Kbit SRAM Cache Memory for 12ns Random Reads Within a Page Fast 4Mbit DRAM Array for 30ns Access to Any New Page Write Posting Register for 12ns Random Writes and Burst Writes Within a Page (Hit or Miss) s 256-byte Wide DRAM to SRAM Bus for 14.2 Gigabytes/Sec Cache Fill s On-chip Cache Hit/Miss Comparators Maintain Cache Coherency on Writes
s s s s s s s
Hidden Precharge and Refresh Cycles Write-per-bit Option (DM2212) for Parity and Video Applications Extended 64ms Refresh Period for Low Standby Power 300 Mil Plastic SOJ and TSOP-II Package Options +5 and +3.3 Volt Power Supply Voltage Options Low Power, Self Refresh Mode Option Industrial Temperature Range Option
Description
The 4Mb Enhanced DRAM (EDRAM) combines raw speed with innovative architecture to offer the optimum cost-performance solution for high performance local or system main memory. In most high speed applications, no-wait-state performance can be achieved without secondary SRAM cache and without interleaving main memory banks at system clock speeds through 50MHz. Two-way interleave will allow nowait-state operation at clock speeds greater than 100MHz without the need of secondary SRAM cache. The EDRAM outperforms conventional SRAM cache plus DRAM memory systems by minimizing processor wait states for all possible bus events, not just cache hits. The combination of data and address latching, 2K of fast on-chip SRAM cache, and simplified on-chip cache control allows system level flexibility, performance, and overall memory cost reduction not available with any other high density memory component. Architectural similarity with JEDEC DRAMs allows a single memory controller design to support either slow JEDEC DRAMs or high speed EDRAMs. A system designed in this manner can provide a simple upgrade path to higher system performance.
Architecture
The EDRAM architecture has a simple integrated SRAM cache which allows it to operate much like a page mode or static column DRAM. The EDRAM's SRAM cache is integrated into the DRAM array as tightly coupled row registers. Memory reads always occur from the cache row register. When the internal comparator detects a page hit, only the SRAM is accessed and data is available in 12ns from column address. When a page read miss is detected, the new DRAM row is loaded into the cache and data is available at the output all within 30ns from row enable. Subsequent reads within the page (burst reads or random reads) can continue at 12ns cycle time. Since reads occur from the SRAM cache, the DRAM precharge can occur simultaneously without degrading performance. The on-chip refresh counter with independent refresh bus allows the EDRAM to be refreshed during cache reads. Memory writes are internally posted in 12ns and directed to the DRAM array. During a write hit, the on-chip address comparator activates a parallel write path to the SRAM cache to maintain
Functional Diagram
A0-8 Column Decoder
TSOP-II Pin Configuration
Column Add Latch 11 Bit Comp Sense Amps & Column Write Select /G I/O Control and Data Latches DQ0-3 /S Row Decoder Memory Array (2048 X 512 X 4) /WE
NC A0 NC A1 NC A3 A4 NC A5 /RE VCC VSS VSS A6 A7 A8 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VSS * VSS VSS DQ0 DQ1 DQ2 NC DQ3 /G VCC VCC VSS VSS /WE /S /F NC W/R NC /CAL A10 NC
SOJ Pin Configuration
/CAL
512 X 4 Cache (Row Register)
A0 A1 A3 A4 A5 /RE VCC VSS A6 A7 A8 A2 A9 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS DQ 0 DQ 1 DQ 2 DQ 3 /G VCC VSS /WE /S /F W/R /CAL A 10
A0-10
Last Row Read Add Latch Row Add Latch
/F W/R /RE
A0-9 Row Add and Refresh Control Refresh Counter
VCC VSS
A2 NC A9 VCC VCC*
* Reserved for future use
The information contained herein is subject to change without notice. Enhanced reserves the right to change or discontinue this product without notice.
(c) 1996 Enhanced Memory Systems Inc., 1850 Ramtron Drive, Colorado Springs, CO Telephone (800) 545-DRAM; Fax (719) 488-9095; http://www.csn.net/ramtron/enhanced
80921 38-2107-002
coherency. The EDRAM delivers 12ns cycle page mode memory writes. Memory writes do not affect the contents of the cache row register except during a cache hit. By integrating the SRAM cache as row registers in the DRAM array and keeping the on-chip control simple, the EDRAM is able to provide superior performance over standard slow 4Mb DRAMs. By eliminating the need for SRAMs and cache controllers, system cost, board space, and power can all be reduced.
providing new column addresses to the multiplex address inputs. New data is available at the output at time tAC after each column address change. During read cycles, it is possible to operate in either static column mode with /CAL=high or page mode with /CAL clocked to latch the column address. In page mode, data valid time is determined by either tAC or tCQV.
DRAM Read Miss A DRAM read request is initiated by clocking /RE with W/R low and /F & /CAL high. The EDRAM compares the new row address to Functional Description the LRR address latch (an 11-bit latch loaded on each /RE active The EDRAM is designed to provide optimum memory read miss cycle). If the row address does not match the LRR, the requested data is not in SRAM cache and a new row must be performance with high speed microprocessors. As a result, it is fetched from the DRAM. The EDRAM will load the new row data possible to perform simultaneous operations to the DRAM and SRAM cache sections of the EDRAM. This feature allows the EDRAM into the SRAM cache and update the LRR latch. The data at the to hide precharge and refresh operation during SRAM cache reads specified column address is available at the output pins at the greater of times tRAC, tAC, and tGQV. It is possible to bring /RE high and maximize SRAM cache hit rate by maintaining valid cache after time tRE since the new row data is safely latched into SRAM contents during write operations even if data is written to another memory page. These new functions, in conjunction with the faster cache. This allows the EDRAM to precharge the DRAM array while basic DRAM and cache speeds of the EDRAM, minimize processor data is accessed from SRAM cache. It is possible to access additional SRAM cache locations by providing new column addresses to the wait states. multiplex address inputs. New data is available at the output at time tAC after each column address change. During read cycles, it is EDRAM Basic Operating Modes possible to operate in either static column mode with /CAL=high or The EDRAM operating modes are specified in the table below. page mode with /CAL clocked to latch the column address. In page Hit and Miss Terminology mode, data valid time is determined by either tAC or tCQV. In this datasheet, "hit" and "miss" always refer to a hit or miss DRAM Write Hit to the page of data contained in the SRAM cache row register. This If a DRAM write request is initiated by clocking /RE while W/R, is always equal to the contents of the last row that was read from /CAL, /WE, and /F are high, the EDRAM will compare the new row (as modified by any write hit data). Writing to a new page does not address to the LRR address latch (an 11-bit address latch loaded cause the cache to be modified. on each /RE active read miss cycle). If the row address matches, DRAM Read Hit the EDRAM will write data to both the DRAM array and selected A DRAM read request is initiated by clocking /RE with W/R low SRAM cache simultaneously to maintain coherency. The write and /F & /CAL high. The EDRAM compares the new row address to address and data are posted to the DRAM as soon as the column the last row read address latch (LRR - an 11-bit latch loaded on address is latched by bringing /CAL low and the write data is each /RE active read miss cycle). If the row address matches the latched by bringing /WE low. The write address and data can be latched very quickly after the fall of /RE (tRAH + tASC for the column LRR, the requested data is already in the SRAM cache and no address and tDS for the data). During a write burst sequence, the DRAM memory reference is initiated. The data specified by the second write data can be posted at time tRSW after /RE. Subsequent column address is available at the output pins at the greater of writes within a page can occur with write cycle time tPC. With /G times tAC or tGQV. Since no DRAM activity is initiated, /RE can be brought high after time tRE1, and a shorter precharge time, tRP1, is enabled and /WE disabled, it is possible to perform cache read allowed. It is possible to access additional SRAM cache locations by operations while the /RE is activated in write hit mode. This allows EDRAM Basic Operating Modes
Function
Read Hit Read Miss Write Hit Write Miss Internal Refresh Low Power Standby Unallowed Mode Low Power Self-Refresh Option
/S
L L L L X H H H
/RE
H L
W/R
L L H H X X X H
/F
H H H H L X H H
/CAL
H H H H X H X L
/WE
X X H H X H X H
A0-10
Row = LRR Row LRR Row = LRR Row LRR X X X X
Comment
No DRAM Reference, Data in Cache DRAM Row to Cache Write to DRAM and Cache, Reads Enabled Write to DRAM, Cache Not Updated, Reads Disabled Cache Reads Enabled 1mA Standby Current Unallowed Mode (Except -L Option) Standby Current, Internal Refresh Clock (-L Option)
H = High; L = Low; X = Don't Care; = High-to-Low Transition; LRR = Last Row Read
1-20
Internal Refresh If /F is active (low) on the assertion of /RE, an internal refresh cycle is executed. This cycle refreshes the row address supplied by an internal refresh counter. This counter is incremented at the end of the cycle in preparation for the next /F refresh cycle. At least 1,024 /F cycles must be executed every 64ms. /F refresh cycles can be hidden because cache memory can be read under column address control throughout the entire /F cycle. Low Power Mode DRAM Write Miss The EDRAM enters its low power mode when /S is high. In this If a DRAM write request is initiated by clocking /RE while W/R, mode, the internal DRAM circuitry is powered down to reduce /CAL, /WE, and /F are high, the EDRAM will compare the new row standby current to 1mA. address to the LRR address latch (an 11-bit latch loaded on each /RE active read miss cycle). If the row address does not match, the Low Power, Self-Refresh Option When the low power, self refresh mode option is specified when EDRAM will write data to the DRAM array only and contents of the ordering the EDRAM, the EDRAM enters this mode when /RE is current cache are not modified. The write address and data are clocked while /S, W/R, /F, and /WE are high; and /CAL is low. In this posted to the DRAM as soon as the column address is latched by mode, the power is turned off to all I/O pins except /RE to minimize bringing /CAL low and the write data is latched by bringing /WE chip power, and an on-board refresh clock is enabled to perform selflow. The write address and data can be latched very quickly after refresh cycles using the on-board refresh counter. The EDRAM the fall of /RE (tRAH + tASC for the column address and tDS for the remains in this low power mode until /RE is brought high again to data). During a write burst sequence, the second write data can be terminate the mode. The EDRAM /RE input must remain high for t RP2 posted at time tRSW after /RE. Subsequent writes within a page can following exit from self-refresh mode to allow any on-going internal occur with write cycle time tPC. During a write miss sequence, refresh to terminate prior to the next memory operation. cache reads are inhibited and the output buffers are disabled Write-Per-Bit Operation (independently of /G) until time tWRR after /RE goes high. At the The DM2212 version of the 1Mb x 4 EDRAM offers a write-perend of a write sequence (after /CAL and /WE are brought high and bit capability which allows single bits of the memory to be selectively tRE is satisfied), /RE can be brought high to precharge the memory. written without altering other bits in the same word. This capability It is possible to perform cache reads concurrently with the may be useful for implementing parity or masking data in video precharge. During write sequences, a write operation is not graphics applications. The bits to be written are determined by a performed unless both /CAL and /WE are low. As a result, /CAL can bit mask data word which is placed on the I/O data pins DQ prior 0-3 be used as a byte write select in multi-chip systems. If /CAL is not to clocking /RE. The logic one bits in the mask data select the bits clocked on a write sequence, the memory will perform a /RE only to be written. As soon as the mask is latched by /RE, the mask data refresh to the selected row and data will remain unmodified. is removed and write data can be placed on the databus. The mask is only specified on the /RE transition. During page mode burst /RE Inactive Operation write operations, the same mask is used for all write operations. It is possible to read data from the SRAM cache without clocking +3.3 Volt Power Supply Operation /RE. This option is desirable when the external control logic is If the +3.3 volt power supply option is specified, the EDRAM capable of fast hit/miss comparison. In this case, the controller can avoid the time required to perform row/column multiplexing on hit will operate from a +3.3 volt 0.3 volt power supply and all inputs and outputs will have LVTTL/LVCMOS compatible signal levels. The cycles. This capability also allows the EDRAM to perform cache +3.3 volt EDRAM will not accept input levels which exceed the read operations during precharge and refresh cycles to minimize power supply voltage. If mixed I/O levels are expected in your wait states and reduce power. It is only necessary to select /S and system, please specify the +5 volt version of the EDRAM. /G and provide the appropriate column address to read data as shown in the table below. The row address of the SRAM cache /CAL Before /RE Refresh ("/CAS Before /RAS") /CAL before /RE refresh, a special case of internal refresh, is accessed without clocking /RE will be specified by the LRR address discussed in the "Reduced Pin Count Operation" section below. latch loaded during the last /RE active read cycle. To perform a cache read in static column mode, /CAL is held high, and the cache /RE Only Refresh Operation contents at the specified column address will be valid at time tAC Although /F refresh using the internal refresh counter is the after address is stable. To perform a cache read in page mode, recommended method of EDRAM refresh, it is possible to perform an /RE only refresh using an externally supplied row address. /RE refresh is performed by executing a write cycle (W/R and /F are Function /S /G /CAL A0-8 high) where /CAL is not clocked. This is necessary so that the current Cache Read (Static Column) L L H Column Address cache contents and LRR are not modified by the refresh operation. All combinations of addresses A0-9 must be sequenced every 64ms Cache Read (Page Mode) L L Column Address refresh period. A10 does not need to be cycled. Read refresh cycles H = High; L = Low; X = Don't Care; = Transitioning
1-21
read-modify-write, write-verify, or random read-write sequences within the page with 12ns cycle times (the first read cannot complete until after time tRAC2). At the end of a write sequence (after /CAL and /WE are brought high and tRE is satisfied), /RE can be brought high to precharge the memory. It is possible to perform cache reads concurrently with precharge. During write sequences, a write operation is not performed unless both /CAL and /WE are low. As a result, the /CAL input can be used as a byte write select in multi-chip systems. If /CAL is not clocked on a write sequence, the memory will perform a /RE only refresh to the selected row and data will remain unmodified.
/CAL is clocked to latch the column address. The cache data is valid at time tAC after the column address is setup to /CAL.
are not allowed because a DRAM refresh cycle does not occur when a read refresh address matches the LRR address latch.
Initialization Cycles A minimum of 10 initialization (start-up) cycles are required before normal operation is guaranteed. At least eight /F refresh cycles and two read cycles to different row addresses are necessary to complete initialization. /RE must be high for at least 300ns prior to initialization. Unallowed Mode Read, write, or /RE only refresh operations must not be performed to unselected memory banks by clocking /RE when /S is high. Reduced Pin Count Operation Although it is desirable to use all EDRAM control pins to optimize system performance, it is possible to simplify the interface to the EDRAM by either tying pins to ground or by tying one or more control inputs together. The /S input can be tied to ground if the low power standby modes are not required. The /CAL and /F pins can be tied together if hidden refresh operation is not required. In this case, a CBR refresh (/CAL before /RE) can be performed by holding the combined input low prior to /RE. A CBR refresh does not require that a row address be supplied when /RE is asserted. The timing is identical to /F refresh cycle timing. The /WE input can be tied to /CAL if independent posting of column addresses and data are not required during write operations. In this case, both column address and write data will be latched by the combined input during writes. W/R and /G can be tied together if reads are not performed during write hit cycles. If these techniques are used, the EDRAM will require only three control lines for operation (/RE, /CAS [combined /CAL, /F, and /WE], and W/R [combined W/R and /G]). The simplified control interface still allows the fast page read/write cycle times, fast random read/write times, and hidden precharge functions available with the EDRAM.
Pin Descriptions
/RE -- Row Enable This input is used to initiate DRAM read and write operations and latch a row address. It is not necessary to clock /RE to read data from the EDRAM SRAM row registers. On read operations, /RE can be brought high as soon as data is loaded into cache to allow early precharge. Pin Names
Pin Names
A0-10 /RE DQ0-3 /CAL W/R VCC Address Inputs Row Enable Data In/Data Out Column Address Latch Write/Read Control Power (+5V or +3.3V)
/CAL -- Column Address Latch This input is used to latch the column address and in combination with /WE to trigger write operations. When /CAL is high, the column address latch is transparent. When /CAL is low, the column address latch is closed and the output of the latch contains the address present while /CAL was high. W/R -- Write/Read This input along with /F specifies the type of DRAM operation initiated on the low going edge of /RE. When /F is high, W/R specifies either a write (logic high) or read operation (logic low). /F -- Refresh This input will initiate a DRAM refresh operation using the internal refresh counter as an address source when it is low on the low going edge of /RE. /WE -- Write Enable This input controls the latching of write data on the input data pins. A write operation is initiated when both /CAL and /WE are low. /G -- Output Enable This input controls the gating of read data to the output data pins during read operations. /S -- Chip Select This input is used to power up the I/O and clock circuitry. When /S is high, the EDRAM remains in its low power mode. /S must remain active throughout any read or write operation. With the exception of /F refresh cycles, /RE should never be clocked when /S is inactive. DQ0-3 -- Data Input/Output These bidirectional data pins are used to read and write data to the EDRAM. On the DM2212 write-per-bit memory, these pins are also used to specify the bit mask used during write operations. A0-10 -- Multiplex Address These inputs are used to specify the row and column addresses of the EDRAM data. The 11-bit row address is latched on the falling edge of /RE. The 9-bit column address can be specified at any other time to select read data from the SRAM cache or to specify the write column address during write cycles. VCC Power Supply These inputs are connected to the +5 or +3.3 volt power supply. VSS Ground These inputs are connected to the power supply ground connection.
Function
Pin Names
VSS /WE /G /F /S NC Ground Write Enable Output Enable Refresh Control
Function
Chip Select - Active/Standby Control Not Connected
1-22
AC Test Load and Waveforms
Load Circuit
+ 5.0 (+3.3 Volt Option) R1 = 828 R1 = 1178 (5.0 volt) (3.3 Volt Option) CL = 50pf VIL 5ns
VIN Timing Reference Point at VIL and VIH
Input Waveforms
VIH VIH
Output R2 = 295 (5.0 volt) R2 = 868 (3.3 Volt Option)
GND
VIL 5ns
Absolute Maximum Ratings
(Beyond Which Permanent Damage Could Result)
Capacitance
3.3V Option Rating
- .5 ~ 4.6v - .5 ~ 4.6v - .5 ~ 4.6v -40 ~ +85C -55 ~ 150C Class 1 20mA*
Description
Ratings
- 1 ~ 7v - 1 ~ 7v - 1 ~ 7v -40 ~ +85C -55 ~ 150C Class 1 50mA*
Max
6pf 7pf 2pf 6pf A0-10
Pins
Description
Input Voltage (VIN) Output Voltage (VOUT) Power Supply Voltage (VCC) Ambient Operating Temperature (TA) Storage Temperature (TS) Static Discharge Voltage (Per MIL-STD-883 Method 3015) Short Circuit O/P Current (IOUT)
*One output at a time; short duration.
Input Capacitance Input Capacitance Input Capacitance I/O Capacitance
/CAL, /RE, W/R, /WE, /F, /S /G DQ0-3
Electrical Characteristics
Symbol
VCC VIH VIL VOH VOL Ii(L) IO(L)
TA = 0 to 70C (Commercial), -40 to 85C (Industrial)
Parameters
Supply Voltage Input High Voltage Input Low Voltage Output High Level Output Low Level Input Leakage Current Output Leakage Current
L Option Min
3.0V 2.0V Vss-0.3V 2.4V 0.4V -5A -5A 5A 5A
Min
4.75V 2.4V Vss-0.5V 2.4V
Max
5.25V Vcc+0.5V 0.8V
Test Conditions
All Voltages Referenced to VSS
Max
3.6V VCC+0.3V 0.8V
IOUT = - 5mA (-2ma For 3.3 Volt Option) 0.4V IOUT = 4.2mA (2ma For 3.3 Volt Option) OV VIN Vcc to 0.5 Volt O VI/O Vcc
-10A -10A
10A 10A
Symbol
ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICCT
Operating Current
Random Read Fast Page Mode Read Static Column Read Random Write Fast Page Mode Write Standby Self-Refresh (-L Option) Average Typical Operating Current
33MHz Typ (1)
110mA 65mA 55mA 135mA 50mA 1mA
200 A
-12 Max
225mA 145mA 110mA 190mA 135mA 1mA
200 A
-15 Max
180mA 115mA 90mA 150mA 105mA 1mA
200 A
Test Condition
/RE, /CAL, and Addresses Cycling: tC = tC Minimum /CAL and Addresses Cycling: tPC = tPC Minimum Addresses Cycling: tSC = tSC Minimum /RE, /CAL, /WE, and Addresses Cycling: tC = tC Minimum /CAL, /WE, and Addresses Cycling: tPC = tPC Minimum All Control Inputs Stable VCC - 0.2V, Output Driven /S, /F, W/R, /WE, and A0-10 at VCC - 0.2V /RE and /CAL at VSS + 0.2V, I/O Open See "Estimating EDRAM Operating Power" Application Note
Notes
2, 3, 5 2, 4, 5 2, 4, 5 2, 3 2, 4
30mA
--
--
1
(1) "33MHz Typ" refers to worst case ICC expected in a system operating with a 33MHz memory bus. See power applications note for further details. This parameter is not 100% tested or guaranteed. (2) ICC is dependent on cycle rates and is measured with CMOS levels and the outputs open. (3) ICC is measured with a maximum of one address change while /RE = VIL. (4) ICC is measured with a maximum of one address change while /CAL = VIH. (5) /G is high.
1-23
Switching Characteristics
VCC = 5V 5% (+5 Volt Option), VCC = 3.3V 0.3V (+3.3 Volt Option), CL = 50pf, TA = 0 to 70C (Commercial), -40 to 85C (Industrial)
-12 Symbol
tAC(1) tACH tAQX tASC tASR tC tC1 tCAE tCAH tCH tCHR tCHW tCQV tCQX tCRP tCWL tDH tDMH tDMS tDS tGQV
(1)
-15 Max
12
Description
Column Address Access Time Column Address Valid to /CAL Inactive (Write Cycle) Column Address Change to Output Data Invalid Column Address Setup Time Row Address Setup Time Row Enable Cycle Time Row Enable Cycle Time, Cache Hit (Row=LRR), Read Cycle Only Column Address Latch Active Time Column Address Hold Time Column Address Latch High Time (Latch Transparent) /CAL Inactive Lead Time to /RE Inactive (Write Cycles Only) Column Address Latch High to Write Enable Low (Multiple Writes) Column Address Latch High to Data Valid Column Address Latch Inactive to Data Invalid Column Address Latch Setup Time to Row Enable /WE Low to /CAL Inactive Data Input Hold Time Mask Hold Time From Row Enable (Write-Per-Bit) Mask Setup Time to Row Enable (Write-Per-Bit) Data Input Setup Time Output Enable Access Time Output Enable to Output Drive Time Output Turn-Off Delay From Output Disabled (/G) /F and W/R Mode Select Hold Time /F and W/R Mode Select Setup Time /CAL, /G, W/R, and /WE Hold Time For /RE-Only Refresh /CAL, /G, W/R, and /WE Setup Time For /RE-Only Refresh Column Address Latch Cycle Time
Min
Min
Max
15
Units
ns ns ns ns ns ns ns ns ns ns ns ns
12 5 5 5 55 20 5 0 5 -2 0 15 5 5 5 0 1 5 5 5 0 0 0 5 0 5 12 30 15 30 1 30 100000 5 5
15 5 5 5 65 25 6 0 5 -2 0 17 5 5 5 0 1.5 5 5 5 0 0 0 5 0 5 15 35 17 35 1.5 35 100000 5 5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tGQX(2,3) tGQZ tMH tMSU tNRH tNRS tPC tRAC
(1) (4,5)
Row Enable Access Time, On a Cache Miss Row Enable Access Time, On a Cache Hit (Limit Becomes tAC) Row Enable Access Time for a Cache Write Hit Row Address Hold Time Row Enable Active Time
tRAC1(1) tRAC2 tRAH tRE
(1,6)
1-24
Switching Characteristics (continued)
VCC = 5V 5% (+5 Volt Option), VCC = 3.3V 0.3V% (+3.3 Volt Option), CL = 50pf, TA = 0 to 70C (Commercial), -40 to 85C (Industrial)
-12 Symbol
tRE1 tREF tRGX tRQX1 tRP(7) tRP1 tRP2 tRRH tRSH t RSW tRWL tSC tSHR tSQV
(1) (2,6)
-15 Max Min
10 64 64 10 12 0 25 10 100 0 15 40 15 15 0 12 15 0 0 5 10 1 15 5 0 5 5 12 15 0 0 5 16 18 15 15 10 15 10 15
Description
Row Enable Active Time, Cache Hit (Row=LRR) Read Cycle Refresh Period Output Enable Don't Care From Row Enable (Write, Cache Miss), O/P Hi Z Row Enable High to Output Turn-On After Write Miss Row Precharge Time Row Precharge Time, Cache Hit (Row=LRR) Read Cycle Row Precharge Time, Self-Refresh Mode Read Hold Time From Row Enable (Write Only) Last Write Address Latch to End of Write Row Enable to Column Address Latch Low For Second Write Last Write Enable to End of Write Column Address Cycle Time Select Hold From Row Enable Chip Select Access Time Output Turn-On From Select Low Output Turn-Off From Chip Select Select Setup Time to Row Enable Transition Time (Rise and Fall) Write Enable Cycle Time Column Address Latch Low to Write Enable Inactive Time Write Enable Hold After /RE Write Enable Inactive Time Write Enable Active Time
Min
8
Max
Units
ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
9 0 20 8 100 0 12 35 12 12 0
tSQX(2,3) tSQZ
(4,5)
0 0 5 1 12 5 0 5 5
12 8
tSSR tT tWC tWCH tWHR(7) tWI tWP tWQV
(1)
Data Valid From Write Enable High Data Output Turn-On From Write Enable High Data Turn-Off From Write Enable Low Write Enable Setup Time to Row Enable Write to Read Recovery (Following Write Miss) 0 0 5
tWQX(2,5) tWQZ
(3,4)
12 12
tWRP tWRR
(1) VOUT Timing Reference Point at 1.5V (2) Parameter Defines Time When Output is Enabled (Sourcing or Sinking Current) and is Not Referenced to VOH or VOL (3) Minimum Specification is Referenced from VIH and Maximum Specification is Referenced from VIL on Input Control Signal (4) Parameter Defines Time When Output Achieves Open-Circuit Condition and is Not Referenced to VOH or VOL (5) Minimum Specification is Referenced from VIL and Maximum Specification is Referenced from VIH on Input Control Signal (6) Access Parameter Applies When /CAL Has Not Been Asserted Prior to tRAC2 (7) For Write-Per-Bit Devices, tWHR is Limited By Data Input Setup Time, tDS
1-25
/RE Inactive Cache Read Hit (Static Column Mode)
/RE
/F
W/R
A0-8
A0-10
Column 1 t SC
Column 2 t SC
Column 3 t SC
Column 4
/CAL
/WE
t AC t AQX t AC t AQX Data 1 t GQV Data 2 t AC t AQX Data 3 Data 4 t GQZ t AC
DQ0-3
Open t GQX
/G
t SQX t SQV t SQZ
/S
Don't Care or Indeterminate NOTES: 1. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle.
1-26
/RE Inactive Cache Read Hit (Page Mode)
/RE
/F
W/R
t CAH
A0-10
Column 1 t ASC t CAH t CAE t PC
Column 2 t ASC t CH
Row
/CAL
t CQV
/WE
t AC t CQX
DQ0-3
Open t AC t GQX
Data 1 t GQZ t GQV t SQX t SQV t SQZ
Data 2
/G
/S
Don't Care or Indeterminate NOTES: 1. Data accessed during /RE inactive read is from the row address specified during the last /RE active read cycle.
1-27
/RE Active Cache Read Hit (Static Column Mode)
/RE
t RE1 t MSU t MH
t C1
t RP1
/F
t MSU t MH
W/R
t ASR t RAH
A0-8
A0-10
Row t CRP
Column 1 t SC
Column 2 t SC
Column 3 t SC
Column 4
/CAL
/WE
t AC t RAC1 t AQX Data 1 t AC t AQX Data 2 t AC t AQX Data 3 Data 4 t GQZ t GQV t SHR t SSR t SQZ t AC
DQ0-3
Open t GQX
/G
/S
Don't Care or Indeterminate
1-28
/RE Active Cache Read Hit (Page Mode)
/RE
t RE1 t MSU t MH
t C1 t RP1
/F
t MSU t MH
W/R
t ASR t RAH t CAH Column 1 t CRP t ASC t CAH t CAE t PC Column 2 t ASC t CH Row
A0-10
Row
/CAL
t CQV
/WE
t RAC1 t AC t CQX Data 1 t AC t GQX t GQZ t GQV t SHR t SSR t SQZ Data 2
DQ0-3
Open
/G
/S
Don't Care or Indeterminate
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/RE Active Cache Read Miss (Static Column Mode)
/RE
t MSU t MH
t RE
tC t RP
/F
t MSU t MH
W/R
t ASR
A0-10
t RAH
t SC Column 1
A0-8
A0-8
A0-10
A0-10
Row t CRP
Column 2
Row
/CAL
t AQX
/WE
t AC t RAC t AQX Data 1 t GQX t GQV t GQZ t SHR t SSR t SQZ Data 2 t AC
DQ0-3
Open
/G
/S
Don't Care or Indeterminate
1-30
/RE Active Cache Read Miss (Page Mode)
/RE
t MSU t MH
t RE
tC t RP
/F
t MSU t MH
W/R
t ASR
A0-10
t RAH Column 1 t ASC
A0-8
A0-8
t CAH
A0-10
A0-10
Row t CRP
Column 2 t ASC t CAH t CAE t PC t CH
Row
/CAL
t CQV
/WE
t RAC t AC t CQX Data 1 t AC t GQZ Data 2
DQ0-3
Open
/G
t SSR t GQX t GQV t SHR t SQZ
/S
Don't Care or Indeterminate
1-31
Burst Write (Hit or Miss) Followed By /RE Inactive Cache Reads
t RE
/RE
t MSU t MH t RP
/F
t MSU t MH
W/R
t ASR t RAH
A0-8
t RSW t ACH t CWL t CH t PC t CHW t WI
t CAH
A0-8 A0-8
A0-10
Row
A0-10
Column 1 t ASC t CAH t CAE
Column 2 t ACH t RSH t CAE t WCH t WP t WC t DH t DS Data 2
Column n t CHR t CWL
t CRP
/CAL
t WRP
t WP t WHR
t WCH
t RRH t WRR t AC Cache (Column n) t RQX1 t GQX
/WE
t DS
t RWL t DH
DQ0-3
Open
Data 1
/G
t SSR t GQV
/S
Don't Care or Indeterminate NOTES: 1. /G becomes a don't care after tRGX during a write miss.
1-32
Read/Write During Write Hit Cycle (Can Include Read-Modify-Write)
/RE
t MSU t MH
t RE
tC t RP
/F
t MSU t MH
W/R
t ASR t RAH
A0-8
t CHR t AC Column 2 t ACH t CAE t WCH t CQV Column 3 t RSH
A0-10
t CRP
Row
Column 1
t ASC
/CAL
t WRP
/WE
t RAC2 t AC
t WHR
t WP t AQX t DS
t CWL t RWL
t RRH
t WQV Read Data t t WQX t GQV
GQZ
DQ0-3
t GQX t GQV
Read Data
Write Data t DH t GQZ
/G
t SSR
/S
Don't Care or Indeterminate NOTES: 1. If column address one equals column address two, then a read-modify-write cycle is performed.
1-33
Write-Per-Bit Cycle (/G=High)
t RE
t RP
/RE
t RSH t ACH t CHR
/CAL
t RAH t ASR t ASC
t CAE
t CAH Column
A0-10
Row t MSU t MH
t CWL
W/R
t DMS t DMH Data t WRP t DS t DH t RRH t WP t RWL t WCH
DQ0-3
Mask
/WE
t WHR t MSU
/F
t SSR t MH t SHR
/S
Don't Care or Indeterminate NOTES: 1. Data mask bit high (1) enables bit write; data mask bit low (0) inhibits bit write. 2. Write-per-bit cycle valid only for DM2212.
1-34
/F Refresh Cycle
/RE
t RE t MSU t MH t RP
/F
Don't Care or Indeterminate NOTES: 1. During /F refresh cycles, the status of W/R, /WE, A0-10, /CAL, /S, and /G is a don't care. 2. /RE inactive cache reads may be performed in parallel with /F refresh cycles.
/RE-Only Refresh
/RE
t ASR t RAH
t RE
tC t RP
A 0-10
Row t NRS t NRH
/CAL, /WE, /G, W/R
t MSU t MH
/F
t SSR t SHR
/S
Don't Care or Indeterminate NOTES: 1. All binary combinations of A0-9 must be refreshed every 64ms interval. A10 does not have to be cycled, but must remain valid during row address setup and hold times. 2. /RE refresh is write cycle with no /CAL active cycle.
1-35
Low Power Self-Refresh Mode Option
/RE
t RP2
A 0-10
t MSU t MH
/CAL
t MSU
/F, W/R, /WE, /S
t MH
Don't Care or Indeterminate NOTES: 1. EDRAM self refreshes as long as /RE remains low. (Low Power Self Refresh part only). 2. When using the Low Power Self Refresh mode the following operations must be performed: If row addresses are being refreshed in an evenly distributed manner over the refresh interval using /F refresh cycles, then at least one /F refresh cycle must be performed immediately after exit from the Low Power Self Refesh Mode. If row addresses are being refreshed in any other manner (/F burst or /RE distributed or burst), then all rows must be refreshed immediately befor entry to and immediately after exit from the Low Power Self Refresh.
Part Numbering System
DM2202J 1 - 12I
Temperature Range No Designator = 0 to 70oC (Commercial) I = -40 to +85oC (Industrial) L = 0 to 70oC, Low Power Self-Refresh Access Time from Cache in Nanoseconds 12ns 15ns Power Supply Voltage No Designator = +5 Volts 1 = +3.3 Volts Packaging System J = 300 Mil, Plastic SOJ T = 300 Mil, Plastic TSOP-II I/O Width i.e., Power to Which 2 is Raised for I/O Width (x4) Special Feature Field 0 = No Write-Per-Bit 1 = Write-Per-Bit Capacity in Bits i.e., Power to Which 2 is Raised for Total Capacity (4Mbit) Dynamic Memory
1-36
Mechanical Data 28 Pin 300 Mil Plastic SOJ Package
Inches (mm) Optional Pin 1 Indicator
3 2 1
0.295 (7.493) 0.305 (7.747) 0.330 (8.382) 0.340 (8.636)
0.094 (2.39) 0.102 (2.59) 0.720 (18.288) 0.730 (18.542) 0.088 (2.24) 0.098 (2.48) 0.014 (.36) 0.019 (.48) 0.050 (1.27) 0.035 (0.89) 0.045 (1.14) 0.128 (3.251) 0.148 (3.759) Seating Plane 0.0091 (.23) 0.0125 (.32)
0.260 (6.604) 0.275 (6.985)
Mechanical Data 44 Pin 300 Mil Plastic TSOP-II Package
Inches (mm) 0.741 (18.81) MAX. 0.0315 (0.80) TYP.
0.040 (1.02) TYP.
0.040 (1.02) TYP.
0.040 (1.02) TYP.
7 TYP. 0.044 (1.13) MAX. 0.308 (7.82) 0.292 (7.42) 0.039 (1.00) 0.023 (0.60)
0.004 (0.10) 0.000 (0.00)
0.016 (0.40) 0.008 (0.20)
0.039 (1.00) TYP. 0.010 (0.24) 0.004 (0.09)
0.371 (9.42) 0.355 (9.02)
0.024 (0.60) 0.016 (0.40)
The information contained herein is subject to change without notice. Enhanced Memory Systems Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in an Enhanced product, nor does it convey or imply any license under patent or other rights.
1-37

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