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features ? compatible with mcs ? -51 products 4k bytes of in-system programmable (isp) flash memory ? endurance: 1000 write/erase cycles 4.0v to 5.5v operating range fully static operation: 0 hz to 33 mhz three-level program memory lock 128 x 8-bit internal ram 32 programmable i/o lines two 16-bit timer/counters six interrupt sources full duplex uart serial channel low-power idle and power-down modes interrupt recovery from power-down mode watchdog timer dual data pointer power-off flag fast programming time flexible isp programming (byte and page mode) green (pb/halide-free) packaging option 1. description the at89S51 is a low-power, high-performance cmos 8-bit microcontroller with 4k bytes of in-system programmable flash memory. the device is manufactured using atmel?s high-density nonvolatile memory technology and is compatible with the indus- try-standard 80c51 instruction set and pinout. the on-chip flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro- grammer. by combining a versatile 8-bit cpu with in-system programmable flash on a monolithic chip, the atmel at89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. the at89S51 provides the following standard features: 4k bytes of flash, 128 bytes of ram, 32 i/o lines, watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. in addition, the at89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. the idle mode stops the cpu while allowing the ram, timer/counters, serial port, and interrupt system to continue functioning. the power-down mode saves the ram con- tents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. 8-bit microcontroller with 4k bytes in-system programmable flash at89S51 2487c?micro?03/05
2 2487c?micro?03/05 at89S51 2. pin configurations 2.1 40-lead pdip 2.2 44-lead tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 p1.0 p1.1 p1.2 p1.3 p1.4 (mosi) p1.5 (miso) p1.6 (sck) p1.7 rst (rxd) p3.0 (txd) p3.1 (int0) p3.2 (int1) p3.3 (t0) p3.4 (t1) p3.5 (wr) p3.6 (rd) p3.7 xtal2 xtal1 gnd vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea/vpp ale/prog psen p2.7 (a15) p2.6 (a14) p2.5 (a13) p2.4 (a12) p2.3 (a11) p2.2 (a10) p2.1 (a9) p2.0 (a8) 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 (mosi) p1.5 (miso) p1.6 (sck) p1.7 rst (rxd) p3.0 nc (txd) p3.1 (int0) p3.2 (int1) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea/vpp nc ale/prog psen p2.7 (a15) p2.6 (a14) p2.5 (a13) p1.4 p1.3 p1.2 p1.1 p1.0 nc vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) (wr) p3.6 (rd) p3.7 xtal2 xtal1 gnd gnd (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 2.3 44-lead plcc 2.4 42-lead pdip 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 (mosi) p1.5 (miso) p1.6 (sck) p1.7 rst (rxd) p3.0 nc (txd) p3.1 (int0) p3.2 (int1) p3.3 (t0) p3.4 (t1) p3.5 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea/vpp nc ale/prog psen p2.7 (a15) p2.6 (a14) p2.5 (a13) 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 (wr) p3.6 (rd) p3.7 xtal2 xtal1 gnd nc (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 p1.4 p1.3 p1.2 p1.1 p1.0 nc vcc p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 rst (rxd) p3.0 (txd) p3.1 (int0) p3.2 (int1) p3.3 (t0) p3.4 (t1) p3.5 (wr) p3.6 (rd) p3.7 xtal2 xtal1 gnd pwrgnd (a8) p2.0 (a9) p2.1 (a10) p2.2 (a11) p2.3 (a12) p2.4 (a13) p2.5 (a14) p2.6 (a15) p2.7 p1.7 (sck) p1.6 (miso) p1.5 (mosi) p1.4 p1.3 p1.2 p1.1 p1.0 vdd pwrvdd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea/vpp ale/prog psen
3 2487c?micro?03/05 at89S51 3. block diagram port 2 drivers port 2 latch p2.0 - p2.7 flash port 0 latch ram program address register buffer pc incrementer program counter dual dptr instruction register b register interrupt, serial port, and timer blocks stack pointer acc tmp2 tmp1 alu psw timing and control port 1 drivers p1.0 - p1.7 port 3 latch port 3 drivers p3.0 - p3.7 osc gnd v cc psen ale/prog ea / v pp rst ram addr. register port 0 drivers p0.0 - p0.7 port 1 latch watch dog isp port program logic
4 2487c?micro?03/05 at89S51 4. pin description 4.1 vcc supply voltage (all packages except 42-pdip). 4.2 gnd ground (all packages except 42-pdip; for 42-pd ip gnd connects only t he logic core and the embedded program memory). 4.3 vdd supply voltage for the 42-pdip which connects only the logic core and the embedded program memory. 4.4 pwrvdd supply voltage for the 42-pdip which connects only the i/o pad drivers. the application board must connect both vdd and pwrvdd to the board supply voltage. 4.5 pwrgnd ground for the 42-pdip which connects only the i/o pad drivers. pwrgnd and gnd are weakly connected through the common silicon substrate, but not through any metal link. the application board must connect both gnd and pwrgnd to the board ground. 4.6 port 0 port 0 is an 8-bit open drain bi-directional i/o port. as an output port, each pin can sink eight ttl inputs. when 1s are written to port 0 pins, the pins can be used as high-impedance inputs. port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. in this mode, p0 has internal pull-ups. port 0 also receives the code bytes during flash programming and outputs the code bytes dur- ing program verification. external pull-ups are required during program verification . 4.7 port 1 port 1 is an 8-bit bi-directional i/o port with internal pull-ups. the port 1 output buffers can sink/source four ttl inputs. when 1s are written to port 1 pins, they are pulled high by the inter- nal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally being pulled low will source current (i il ) because of the internal pull-ups. port 1 also receives the low-order address bytes during flash programming and verification. port pin alternate functions p1.5 mosi (used for in-system programming) p1.6 miso (used for in-system programming) p1.7 sck (used for in-system programming)
5 2487c?micro?03/05 at89S51 4.8 port 2 port 2 is an 8-bit bi-directional i/o port with internal pull-ups. the port 2 output buffers can sink/source four ttl inputs. when 1s are written to port 2 pins, they are pulled high by the inter- nal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current (i il ) because of the internal pull-ups. port 2 emits the high-order address byte during fetches from external program memory and dur- ing accesses to external data memory that use 16-bit addresses (movx @ dptr). in this application, port 2 uses strong internal pull-ups when emitting 1s. during accesses to external data memory that use 8-bit addresses (movx @ ri), port 2 emits the contents of the p2 special function register. port 2 also receives the high-order address bits and some control signals during flash program- ming and verification. 4.9 port 3 port 3 is an 8-bit bi-directional i/o port with internal pull-ups. the port 3 output buffers can sink/source four ttl inputs. when 1s are written to port 3 pins, they are pulled high by the inter- nal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current (i il ) because of the pull-ups. port 3 receives some control signals for flash programming and verification. port 3 also serves the functions of various special features of the at89S51, as shown in the fol- lowing table. 4.10 rst reset input. a high on this pin for two machine cycles while the oscillator is running resets the device. this pin drives high for 98 oscillator periods after the watchdog times out. the dis- rto bit in sfr auxr (address 8eh) can be used to disable this feature. in the default state of bit disrto, the reset high out feature is enabled. 4.11 ale/prog address latch enable (ale) is an output pulse for latching the low byte of the address during accesses to external memory. this pin is also the program pulse input (prog ) during flash programming. port pin alternate functions p3.0 rxd (serial input port) p3.1 txd (serial output port) p3.2 int0 (external interrupt 0) p3.3 int1 (external interrupt 1) p3.4 t0 (timer 0 external input) p3.5 t1 (timer 1 external input) p3.6 wr (external data memory write strobe) p3.7 rd (external data memory read strobe)
6 2487c?micro?03/05 at89S51 in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. note, however, that one ale pulse is skipped dur- ing each access to external data memory. if desired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with the bit set, ale is active only during a movx or movc instruction. otherwise, the pin is weakly pulled high. setting the ale-disable bit has no effect if the microcontroller is in external execution mode. 4.12 psen program store enable (psen) is the read strobe to external program memory. when the at89S51 is executing code from external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to exter- nal data memory. 4.13 ea /vpp external access enable. ea must be strapped to gnd in order to enable the device to fetch code from external program memory locations starting at 0000h up to ffffh. note, however, that if lock bit 1 is programmed, ea will be internally latched on reset. ea should be strapped to v cc for internal program executions. this pin also receives the 12-volt programming enable voltage (v pp ) during flash programming. 4.14 xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. 4.15 xtal2 output from the inverting oscillator amplifier 5. special function registers a map of the on-chip memory area called the special function register (sfr) space is shown in table 5-1 . note that not all of the addresses are occupied, and unoccupied addresses may not be imple- mented on the chip. read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
7 2487c?micro?03/05 at89S51 user software should not write 1s to these unlisted locations, since they may be used in future products to invoke new fea- tures. in that case, the reset or inactive values of the new bits will always be 0. interrupt registers: the individual interrupt enable bits are in the ie register. two priorities can be set for each of the five interrupt sources in the ip register. table 5-1. at89S51 sfr map and reset values 0f8h 0ffh 0f0h b 00000000 0f7h 0e8h 0efh 0e0h acc 00000000 0e7h 0d8h 0dfh 0d0h psw 00000000 0d7h 0c8h 0cfh 0c0h 0c7h 0b8h ip xx000000 0bfh 0b0h p3 11111111 0b7h 0a8h ie 0x000000 0afh 0a0h p2 11111111 auxr1 xxxxxxx0 wdtrst xxxxxxxx 0a7h 98h scon 00000000 sbuf xxxxxxxx 9fh 90h p1 11111111 97h 88h tcon 00000000 tmod 00000000 tl0 00000000 tl1 00000000 th0 00000000 th1 00000000 auxr xxx00xx0 8fh 80h p0 11111111 sp 00000111 dp0l 00000000 dp0h 00000000 dp1l 00000000 dp1h 00000000 pcon 0xxx0000 87h
8 2487c?micro?03/05 at89S51 dual data pointer registers: to facilitate accessing both internal and external data memory, two banks of 16-bit data pointer registers are provided: dp0 at sfr address locations 82h- 83h and dp1 at 84h-85h. bit dps = 0 in sfr auxr1 selects dp0 and dps = 1 selects dp1. the user should always initialize the dps bit to the appropriate value before accessing the respective data pointer register. power off flag: the power off flag (pof) is located at bit 4 (pcon.4) in the pcon sfr. pof is set to ?1? during power up. it can be set and rest under software control and is not affected by reset. table 5-2. auxr: auxiliary register auxr address = 8eh reset value = xxx00xx0b not bit addressable ? ? ? wdidle disrto ? ? disale bit 765 4 3 2 1 0 ? reserved for future expansion disale disable/enable ale disale operating mode 0 ale is emitted at a constant rate of 1/6 the oscillator frequency 1 ale is active only during a movx or movc instruction disrto disable/enable reset-out disrto 0 reset pin is driven high after wdt times out 1 reset pin is input only wdidle disable/enable wdt in idle mode wdidle 0 wdt continues to count in idle mode 1 wdt halts counting in idle mode
9 2487c?micro?03/05 at89S51 6. memory organization mcs-51 devices have a separate address space for program and data memory. up to 64k bytes each of external program and data memory can be addressed. 6.1 program memory if the ea pin is connected to gnd, all program fetches are directed to external memory. on the at89S51, if ea is connected to v cc , program fetches to addresses 0000h through fffh are directed to internal memory and fetches to addresses 1000h through ffffh are directed to external memory. 6.2 data memory the at89S51 implements 128 bytes of on-chip ram. the 128 bytes are accessible via direct and indirect addressing modes. stack operations are examples of indirect addressing, so the 128 bytes of data ram are available as stack space. 7. watchdog timer (one-time enabled with reset-out) the wdt is intended as a recovery method in si tuations where the cpu may be subjected to software upsets. the wdt consists of a 14-bit counter and the watchdog timer reset (wdtrst) sfr. the wdt is defaulted to disable from exiting reset. to enable the wdt, a user must write 01eh and 0e1h in sequence to the wdtrst register (sfr location 0a6h). when the wdt is enabled, it will increment every machine cycle while the oscillator is running. the wdt timeout period is dependent on the external clock frequency. there is no way to disable the wdt except through reset (either hardware reset or wdt overflow reset). when wdt over- flows, it will drive an output reset high pulse at the rst pin. 7.1 using the wdt to enable the wdt, a user must write 01eh and 0e1h in sequence to the wdtrst register (sfr location 0a6h). when the wdt is enabled, t he user needs to service it by writing 01eh and 0e1h to wdtrst to avoid a wdt overflow. the 14-bit counter overflows when it reaches 16383 (3fffh), and this will reset the device. when the wdt is enabled, it will increment every machine cycle while the oscillator is running. this means the user must reset the wdt at least table 5-3. auxr1: auxiliary register 1 auxr1 address = a2h reset value = xxxxxxx0b not bit addressable ???? ? ? ? dps bit7654 3 2 1 0 ? reserved for future expansion dps data pointer register select dps 0 selects dptr registers dp0l, dp0h 1 selects dptr registers dp1l, dp1h
10 2487c?micro?03/05 at89S51 every 16383 machine cycles. to reset the wd t the user must write 01eh and 0e1h to wdtrst. wdtrst is a write-only register. the wdt counter cannot be read or written. when wdt overflows, it will generate an output reset pulse at the rst pin. the reset pulse dura- tion is 98xtosc, where tosc = 1/fosc. to make the best use of the wdt, it should be serviced in those sections of code that will perio dically be executed within the time required to prevent a wdt reset. 7.2 wdt during power-down and idle in power-down mode the oscillator stops, which means the wdt also stops. while in power- down mode, the user does not need to service the wdt. there are two methods of exiting power-down mode: by a hardware reset or via a level-activated external interrupt, which is enabled prior to entering power-down mode. when power-down is exited with hardware reset, servicing the wdt should occur as it normally does whenever the at89S51 is reset. exiting power-down with an interrupt is significantly different. the interrupt is held low long enough for the oscillator to stabilize. when the interrupt is brought high, the interrupt is serviced. to prevent the wdt from resetting the device while the interrupt pin is held low, the wdt is not started until the interrupt is pulled high. it is suggested that the wdt be reset during the interrupt service for the interrupt used to exit power-down mode. to ensure that the wdt does not overflow within a few states of exiting power-down, it is best to reset the wdt just before entering power-down mode. before going into the idle mode, the wdidle bit in sfr auxr is used to determine whether the wdt continues to count if enabled. the wdt keeps counting during idle (wdidle bit = 0) as the default state. to prevent the wdt from resetting the at89S51 while in idle mode, the user should always set up a timer that will periodically exit idle, service the wdt, and reenter idle mode. with wdidle bit enabled, the wdt will stop to count in idle mode and resumes the count upon exit from idle. 8. uart the uart in the at89S51 operates the same way as the uart in the at89c51. for further information on the uart operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/doc4316.pdf 9. timer 0 and 1 timer 0 and timer 1 in the at89S51 operate the same way as timer 0 and timer 1 in the at89c51. for further information on the timers? operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/doc4316.pdf
11 2487c?micro?03/05 at89S51 10. interrupts the at89S51 has a total of five interrupt vectors: two external interrupts (int0 and int1 ), two timer interrupts (timers 0 and 1), and the serial port interrupt. these interrupts are all shown in figure 10-1 . each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in special function register ie. ie also contai ns a global disable bit, ea, which disables all interrupts at once. note that table 10-1 shows that bit positions ie.6 and ie.5 are unimplemented. user software should not write 1s to these bit positions, since they may be used in future at89 products. the timer 0 and timer 1 flags, tf0 and tf1, are set at s5p2 of the cycle in which the timers overflow. the values are then polled by the circuitry in the next cycle. table 10-1. interrupt enable (ie) register (msb) (lsb) ea ? ? es et1 ex1 et0 ex0 enable bit = 1 enables the interrupt. enable bit = 0 disables the interrupt. symbol position function ea ie.7 disables all interrupts. if ea = 0, no interrupt is acknowledged. if ea = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. ? ie.6 reserved ? ie.5 reserved es ie.4 serial port interrupt enable bit et1 ie.3 timer 1 interrupt enable bit ex1 ie.2 external interrupt 1 enable bit et0 ie.1 timer 0 interrupt enable bit ex0 ie.0 external interrupt 0 enable bit user software should never write 1s to reserved bits, because they may be used in future at89 products.
12 2487c?micro?03/05 at89S51 figure 10-1. interrupt sources 11. oscillator characteristics xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in figure 11-1 . either a quartz crystal or ceramic resonator may be used. to drive the device from an external clock source, xtal2 should be left unconnected while xtal1 is driven, as shown in figure 11-2 . there are no requirements on the duty cycle of the external clock signal, since the input to the internal clock- ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. figure 11-1. oscillator connections note: c1, c2 = 30 pf 10 pf for crystals =40 pf 10 pf for ceramic resonators ie1 ie0 1 1 0 0 tf1 tf0 int1 int0 ti ri c2 xtal2 gnd xtal1 c1
13 2487c?micro?03/05 at89S51 figure 11-2. external clock drive configuration 12. idle mode in idle mode, the cpu puts itself to sleep while all the on-chip peripherals remain active. the mode is invoked by software. the content of the on-chip ram and all the special function regis- ters remain unchanged during this mode. the idle mode can be terminated by any enabled interrupt or by a hardware reset. note that when idle mode is terminated by a hardware reset, the device normally resumes pro- gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to e liminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory. 13. power-down mode in the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. the on-chip ram and special function registers retain their values until the power-down mode is terminated. exit from power-down mode can be initiated either by a hardware reset or by activation of an enabled external interrupt (int0 or int1 ). reset redefines the sfrs but does not change the on-chip ram. the reset should not be activated before v cc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. xtal2 xtal1 gnd nc external oscillator signal table 13-1. status of external pins during idle and power-down modes mode program memory ale psen port0 port1 port2 port3 idle internal 1 1 data data data data idle external 1 1 float data address data power-down internal 0 0 data data data data power-down external 0 0 float data data data
14 2487c?micro?03/05 at89S51 14. program memory lock bits the at89S51 has three lock bits that can be left unprogrammed (u) or can be programmed (p) to obtain the additional features listed in table 14-1 . when lock bit 1 is programmed, the logic level at the ea pin is sampled and latched during reset. if the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated. the latched value of ea must agree with the current logic level at that pin in order for the device to function properly. 15. programming the flash ? parallel mode the at89S51 is shipped with the on-chip flash memory array ready to be programmed. the programming interface needs a high-voltage (12-volt) program enable signal and is compatible with conventional third-party flash or eprom programmers. the at89S51 code memory array is programmed byte-by-byte. programming algorithm: before programming the at89S51, the address, data, and control signals should be set up according to the flash programming modes table ( table 17-1 ) and fig- ure 17-1 and figure 17-2 . to program the at89S51, take the following steps: 1. input the desired memory location on the address lines. 2. input the appropriate data byte on the data lines. 3. activate the correct combination of control signals. 4. raise ea /v pp to 12v. 5. pulse ale/prog once to program a byte in the flash array or the lock bits. the byte- write cycle is self-timed and typically takes no more than 50 s. repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. data polling: the at89S51 features data polling to indicate the end of a byte write cycle. dur- ing a write cycle, an attempted read of the last byte written will result in the complement of the written data on p0.7. once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. data polling may begin any time after a write cycle has been initiated. ready/busy : the progress of byte programming can also be monitored by the rdy/bsy output signal. p3.0 is pulled low after ale goes high during programming to indicate busy . p3.0 is pulled high again when programming is done to indicate ready. table 14-1. lock bit protection modes program lock bits lb1 lb2 lb3 protection type 1 u u u no program lock features 2puu movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the flash memory is disabled 3 p p u same as mode 2, but verify is also disabled 4 p p p same as mode 3, but external execution is also disabled
15 2487c?micro?03/05 at89S51 program verify: if lock bits lb1 and lb2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. the status of the individ- ual lock bits can be verified directly by reading them back. reading the signature bytes: the signature bytes are read by the same procedure as a nor- mal verification of locations 000h, 100h, and 200h, except that p3.6 and p3.7 must be pulled to a logic low. the values returned are as follows. (000h) = 1eh indicates manufactured by atmel (100h) = 51h indicates at89S51 (200h) = 06h chip erase: in the parallel programming mode, a chip erase operation is initiated by using the proper combination of control signals and by pulsing ale/prog low for a duration of 200 ns - 500 ns. in the serial programming mode, a chip erase operation is initiated by issuing the chip erase instruction. in this mode, chip erase is self-timed and takes about 500 ms. during chip erase, a serial read from any address location will return 00h at the data output. 16. programming the flash ? serial mode the code memory array can be programmed using the serial isp interface while rst is pulled to v cc . the serial interface consists of pins sck, mosi (input) and miso (output). after rst is set high, the programming enable instruction needs to be executed first before other operations can be executed. before a reprogramming sequence can occur, a chip erase operation is required. the chip erase operation turns the content of every memory location in the code array into ffh. either an external system clock can be supplied at pin xtal1 or a crystal needs to be connected across pins xtal1 and xtal2. the maximum serial clock (sck) frequency should be less than 1/16 of the crystal frequency. with a 33 mhz os cillator clock, the maximum sck frequency is 2 mhz. 16.1 serial programming algorithm to program and verify the at89S51 in the serial programming mode, the following sequence is recommended: 1. power-up sequence: a. apply power between vcc and gnd pins. b. set rst pin to ?h?. if a crystal is not connected across pins xtal1 and xtal2, apply a 3 mhz to 33 mhz clock to xtal1 pin and wait for at least 10 milliseconds. 2. enable serial programming by sending the programming enable serial instruction to pin mosi/p1.5. the frequency of the shift clock supplied at pin sck/p1.7 needs to be less than the cpu clock at xtal1 divided by 16. 3. the code array is programmed one byte at a time in either the byte or page mode. the write cycle is self-timed and typically takes less than 0.5 ms at 5v. 4. any memory location can be verified by using the read instruction that returns the con- tent at the selected address at serial output miso/p1.6.
16 2487c?micro?03/05 at89S51 5. at the end of a programming session, rst can be set low to commence normal device operation. power-off sequence (if needed): 1. set xtal1 to ?l? (if a crystal is not used). 2. set rst to ?l?. 3. turn v cc power off. data polling: the data polling feature is also available in the serial mode. in this mode, during a write cycle an attempted read of the last byte written will result in the complement of the msb of the serial output byte on miso. 16.2 serial programming instruction set the instruction set for serial programming follows a 4-byte protocol and is shown in the ?serial programming instruction set? on page 20 . 17. programming interface ? parallel mode every code byte in the flash array can be programmed by using the appropriate combination of control signals. the write operation cycle is self-timed and once initiated, will automatically time itself to completion. most major worldwide programming vendors offer worldwide support for the atmel at89 micro- controller series. please contact your local programming vendor for the appropriate software revision. notes: 1. each prog pulse is 200 ns - 500 ns for chip erase. 2. each prog pulse is 200 ns - 500 ns for write code data. 3. each prog pulse is 200 ns - 500 ns for write lock bits. 4. rdy/bsy signal is output on p3.0 during programming. 5. x = don?t care. table 17-1. flash programming modes mode v cc rst psen ale/ prog ea / v pp p2.6 p2.7 p3.3 p3.6 p3.7 p0.7-0 data p2.3-0 p1.7-0 address write code data 5v h l (2) 12v lhhhh d in a11-8 a7-0 read code data 5v h l h h l l l h h d out a11-8 a7-0 write lock bit 1 5v h l (3) 12vhhhhh x x x write lock bit 2 5v h l (3) 12v h h h l l x x x write lock bit 3 5v h l (3) 12v h l h h l x x x read lock bits 1, 2, 3 5v h l h h h h l h l p0.2, p0.3, p0.4 xx chip erase 5v h l (1) 12vhlhll x x x read atmel id 5v h l h h lllll 1eh 0000 00h read device id 5v h l h h lllll 51h 0001 00h read device id 5v h l h h lllll 06h 0010 00h
17 2487c?micro?03/05 at89S51 figure 17-1. programming the flash memory (parallel mode) figure 17-2. verifying the flash memory (parallel mode) p1.0-p1.7 p2.6 p3.6 p2.0 - p2.3 a0 - a7 addr. 0000h/fffh see flash programming modes table 3-33 mhz p0 v p2.7 pgm data prog v/v ih pp v ih ale p3.7 xtal2 ea rst psen xtal 1 gnd v cc at89S51 p3.3 p3.0 rdy/ bsy a8 - a11 cc p1.0-p1.7 p2.6 p3.6 p2.0 - p2.3 a0 - a7 addr. 0000h/fffh see flash programming modes table 3-33 mhz p0 p2.7 pgm data (use 10k pullups) v ih v ih ale p3.7 xtal 2 ea rst psen xtal1 gnd v cc at89S51 p3.3 a8 - a11 v cc
18 2487c?micro?03/05 at89S51 figure 18-1. flash programming and verification waveforms ? parallel mode 18. flash programming and verification characteristics (parallel mode) t a = 20c to 30c, v cc = 4.5 to 5.5v symbol parameter min max units v pp programming supply voltage 11.5 12.5 v i pp programming supply current 10 ma i cc v cc supply current 30 ma 1/t clcl oscillator frequency 3 33 mhz t avgl address setup to prog low 48 t clcl t ghax address hold after prog 48 t clcl t dvgl data setup to prog low 48 t clcl t ghdx data hold after prog 48 t clcl t ehsh p2.7 (enable ) high to v pp 48 t clcl t shgl v pp setup to prog low 10 s t ghsl v pp hold after prog 10 s t glgh prog width 0.2 1 s t avqv address to data valid 48t clcl t elqv enable low to data valid 48t clcl t ehqz data float after enable 048t clcl t ghbl prog high to busy low 1.0 s t wc byte write cycle time 50 s t glgh t ghsl t avgl t shgl t dvgl t ghax t avqv t ghdx t ehsh t elqv t wc busy ready t ghbl t ehqz p1.0 - p1.7 p2.0 - p2.3 ale/prog port 0 logic 1 logic 0 ea/v pp v pp p2.7 (enable) p3.0 (rdy/bsy) programming address verification address data i n data out
19 2487c?micro?03/05 at89S51 figure 18-2. flash memory serial downloading 19. flash programming and verification waveforms ? serial mode figure 19-1. serial programming waveforms p1.7/sck data output instruction input clock in 3-33 mhz p1.5/mosi v ih xtal2 rst xtal1 gnd v cc at89S51 p1.6/miso v cc 7654 32 10
20 2487c?micro?03/05 at89S51 note: 1. b1 = 0, b2 = 0 mode 1, no lock protection b1 = 0, b2 = 1 mode 2, lock bit 1 activated b1 = 1, b2 = 0 mode 3, lock bit 2 activated b1 = 1, b2 = 1 mode 4, lock bit 3 activated after reset signal is high, sck should be low for at least 64 system clocks before it goes high to clock in the enable data bytes. no pulsing of reset signal is necessary. sck should be no faster than 1/16 of the system clock at xtal1. for page read/write, the data always starts from byte 0 to 255. after the command byte and upper address byte are latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out. then the next instruction will be read y to be decoded. 20. serial programming instruction set instruction instruction format operation byte 1 byte 2 byte 3 byte 4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx 0110 1001 (output on miso) enable serial programming while rst is high chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx chip erase flash memory array read program memory (byte mode) 0010 0000 xxxx read data from program memory in the byte mode write program memory (byte mode) 0100 0000 xxxx write data to program memory in the byte mode write lock bits (1) 1010 1100 1110 00 xxxx xxxx xxxx xxxx write lock bits. see note (1). read lock bits 0010 0100 xxxx xxxx xxxx xxxx xxx xx read back current status of the lock bits (a programmed lock bit reads back as a ?1?) read signature bytes 0010 1000 xxxx xxx xxx0 signature byte read signature byte read program memory (page mode) 0011 0000 xxxx byte 0 byte 1... byte 255 read data from program memory in the page mode (256 bytes) write program memory (page mode) 0101 0000 xxxx byte 0 byte 1... byte 255 write data to program memory in the page mode (256 bytes) } each of the lock bit modes need to be activated sequentially be- fore mode 4 can be executed. d7 d6 d5 d4 d3 d2 d1 d0 a7 a6 a5 a4 a3 a2 a1 a0 a11 a10 a9 a8 b2 b1 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 lb3 lb2 lb1 a11 a10 a9 a8 a11 a10 a9 a8 a7 a11 a10 a9 a8
21 2487c?micro?03/05 at89S51 21. serial programming characteristics figure 21-1. serial programming timing mosi miso sck t ovsh t shsl t slsh t shox t sliv table 21-1. serial programming characteristics, t a = -40 c to 85 c, v cc = 4.0 - 5.5v (unless otherwise noted) symbol parameter min typ max units 1/t clcl oscillator frequency 3 33 mhz t clcl oscillator period 30 ns t shsl sck pulse width high 8 t clcl ns t slsh sck pulse width low 8 t clcl ns t ovsh mosi setup to sck high t clcl ns t shox mosi hold after sck high 2 t clcl ns t sliv sck low to miso valid 10 16 32 ns t erase chip erase instruction cycle time 500 ms t swc serial byte write cycle time 64 t clcl + 400 s 22. absolute maximum ratings* operating temperature.................................. -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c voltage on any pin with respect to ground .....................................-1.0v to +7.0v maximum operating voltage ............................................ 6.6v dc output current...................................................... 15.0 ma
22 2487c?micro?03/05 at89S51 notes: 1. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port: port 0: 26 ma ports 1, 2, 3: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. minimum v cc for power-down is 2v. 23. dc characteristics the values shown in this table are valid for t a = -40c to 85c and v cc = 4.0v to 5.5v, unless otherwise noted. symbol parameter condition min max units v il input low voltage (except ea ) -0.5 0.2 v cc -0.1 v v il1 input low voltage (ea ) -0.5 0.2 v cc -0.3 v v ih input high voltage (except xtal1, rst) 0.2 v cc +0.9 v cc +0.5 v v ih1 input high voltage (xtal1, rst) 0.7 v cc v cc +0.5 v v ol output low voltage (1) (ports 1,2,3) i ol = 1.6 ma 0.45 v v ol1 output low voltage (1) (port 0, ale, psen ) i ol = 3.2 ma 0.45 v v oh output high voltage (ports 1,2,3, ale, psen ) i oh = -60 a, v cc = 5v 10% 2.4 v i oh = -25 a 0.75 v cc v i oh = -10 a 0.9 v cc v v oh1 output high voltage (port 0 in external bus mode) i oh = -800 a, v cc = 5v 10% 2.4 v i oh = -300 a 0.75 v cc v i oh = -80 a 0.9 v cc v i il logical 0 input current (ports 1,2,3) v in = 0.45v -50 a i tl logical 1 to 0 transition current (ports 1,2,3) v in = 2v, v cc = 5v 10% -300 a i li input leakage current (port 0, ea )0.45 < v in < v cc 10 a rrst reset pulldown resistor 50 300 k ? c io pin capacitance test freq. = 1 mhz, t a = 25c 10 pf i cc power supply current active mode, 12 mhz 25 ma idle mode, 12 mhz 6.5 ma power-down mode (2) v cc = 5.5v 50 a
23 2487c?micro?03/05 at89S51 24. ac characteristics under operating conditions, load capacitance for port 0, ale/prog , and psen = 100 pf; load capacitance for all other outputs = 80 pf. 24.1 external program and data memory characteristics symbol parameter 12 mhz oscillator variable oscillator units min max min max 1/t clcl oscillator frequency 0 33 mhz t lhll ale pulse width 127 2 t clcl -40 ns t avll address valid to ale low 43 t clcl -25 ns t llax address hold after ale low 48 t clcl -25 ns t lliv ale low to valid instruction in 233 4 t clcl -65 ns t llpl ale low to psen low 43 t clcl -25 ns t plph psen pulse width 205 3 t clcl -45 ns t pliv psen low to valid instruction in 145 3 t clcl -60 ns t pxix input instruction hold after psen 00ns t pxiz input instruction float after psen 59 t clcl -25 ns t pxav psen to address valid 75 t clcl -8 ns t aviv address to valid instruction in 312 5 t clcl -80 ns t plaz psen low to address float 10 10 ns t rlrh rd pulse width 400 6 t clcl -100 ns t wlwh wr pulse width 400 6 t clcl -100 ns t rldv rd low to valid data in 252 5 t clcl -90 ns t rhdx data hold after rd 00ns t rhdz data float after rd 97 2 t clcl -28 ns t lldv ale low to valid data in 517 8 t clcl -150 ns t avdv address to valid data in 585 9 t clcl -165 ns t llwl ale low to rd or wr low 200 300 3 t clcl -50 3 t clcl +50 ns t avwl address to rd or wr low 203 4 t clcl -75 ns t qvwx data valid to wr transition 23 t clcl -30 ns t qvwh data valid to wr high 433 7 t clcl -130 ns t whqx data hold after wr 33 t clcl -25 ns t rlaz rd low to address float 0 0 ns t whlh rd or wr high to ale high 43 123 t clcl -25 t clcl +25 ns
24 2487c?micro?03/05 at89S51 25. external program memory read cycle 26. external data memory read cycle t lhll t lliv t pliv t llax t pxiz t plph t plaz t pxav t avll t llpl t aviv t pxix ale psen port 0 port 2 a8 - a15 a0 - a7 a0 - a7 a8 - a15 instr in t lhll t lldv t llwl t llax t whlh t avll t rlrh t avdv t avwl t rlaz t rhdx t rldv t rhdz a0 - a7 from ri or dpl ale psen rd port 0 port 2 p2.0 - p2.7 or a8 - a15 from dph a0 - a7 from pcl a8 - a15 from pch data in instr in
25 2487c?micro?03/05 at89S51 27. external data memory write cycle 28. external clock drive waveforms t lhll t llwl t llax t whlh t avll t wlwh t avwl t qvwx t qvwh t whqx a0 - a7 from ri or dpl ale psen wr port 0 port 2 p2.0 - p2.7 or a8 - a15 from dph a0 - a7 from pcl a8 - a15 from pch data out instr in t chcx t chcx t clcx t clcl t chcl t clch v - 0.5v cc 0.45v 0.2 v - 0.1v cc 0.7 v cc 29. external clock drive symbol parameter min max units 1/t clcl oscillator frequency 0 33 mhz t clcl clock period 30 ns t chcx high time 12 ns t clcx low time 12 ns t clch rise time 5 ns t chcl fall time 5 ns
26 2487c?micro?03/05 at89S51 31. shift register mode timing waveforms 32. ac testing input/output waveforms (1) note: 1. ac inputs during testing are driven at v cc - 0.5v for a logic 1 and 0.45v for a logic 0. timing measurements are made at v ih min. for a logic 1 and v il max. for a logic 0. 33. float waveforms (1) note: 1. for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs. a port pin begins t o float when a 100 mv change from the loaded v oh /v ol level occurs. 30. serial port timing: shift register mode test conditions the values in this table are valid for v cc = 4.0v to 5.5v and load capacitance = 80 pf. symbol parameter 12 mhz osc variable oscillator units min max min max t xlxl serial port clock cycle time 1.0 12 t clcl s t qvxh output data setup to clock rising edge 700 10 t clcl -133 ns t xhqx output data hold after clock rising edge 50 2 t clcl -80 ns t xhdx input data hold after clock rising edge 0 0 ns t xhdv clock rising edge to input data valid 700 10 t clcl -133 ns t xhdv t qvxh t xlxl t xhdx t xhqx ale input data clear ri output data write to sbuf instruction clock 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 set ti set ri 8 valid valid valid valid valid valid valid valid 0.45v test points v - 0.5v cc 0.2 v + 0.9v cc 0.2 v - 0.1v cc v load + 0.1v timing reference points v load - 0.1v load v v ol + 0.1v v ol - 0.1v
27 2487c?micro?03/05 at89S51 34. ordering information 34.1 standard package speed (mhz) power supply ordering code package operation range 24 4.0v to 5.5v at89S51-24ac at89S51-24jc at89S51-24pc at89S51-24sc 44a 44j 40p6 42ps6 commercial (0 c to 70 c) at89S51-24ai at89S51-24ji at89S51-24pi at89S51-24si 44a 44j 40p6 42ps6 industrial (-40 c to 85 c) 33 4.5v to 5.5v at89S51-33ac at89S51-33jc at89S51-33pc at89S51-33sc 44a 44j 40p6 42ps6 commercial (0 c to 70 c) 34.2 green package option (pb/halide-free) speed (mhz) power supply ordering code package operation range 24 4.0v to 5.5v at89S51-24au at89S51-24ju at89S51-24pu 44a 44j 40p6 industrial (-40 c to 85 c) package type 44a 44-lead, thin plastic gull wing quad flatpack (tqfp) 44j 44-lead, plastic j-leaded chip carrier (plcc) 40p6 40-pin, 0.600" wide, plastic dual inline package (pdip) 42ps6 42-pin, 0.600" wide, plastic dual inline package (pdip)
28 2487c?micro?03/05 at89S51 35. packaging information 35.1 44a ? tqfp 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44a, 44-lead, 10 x 10 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 44a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 0.45 c 0.09 0.20 l 0.45 0.75 e 0.80 typ
29 2487c?micro?03/05 at89S51 35.2 44j ? plcc notes: 1. this package conforms to jedec reference ms-018, variation ac. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 ? 4.572 a1 2.286 ? 3.048 a2 0.508 ? ? d 17.399 ? 17.653 d1 16.510 ? 16.662 note 2 e 17.399 ? 17.653 e1 16.510 ? 16.662 note 2 d2/e2 14.986 ? 16.002 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ common dimensions (unit of measure = mm) symbol min nom max note 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 44j , 44-lead, plastic j-leaded chip carrier (plcc) b 44j 10/04/01 2325 orchard parkway san jose, ca 95131 title drawing no. r rev.
30 2487c?micro?03/05 at89S51 35.3 40p6 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 40p6 , 40-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 40p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0?~ 15? d e eb common dimensions (unit of measure = mm) symbol min nom max note a 4.826 a1 0.381 d 52.070 52.578 note 2 e 15.240 15.875 e1 13.462 13.970 note 2 b 0.356 0.559 b1 1.041 1.651 l 3.048 3.556 c 0.203 0.381 eb 15.494 17.526 e 2.540 typ notes: 1. this package conforms to jedec reference ms-011, variation ac. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
31 2487c?micro?03/05 at89S51 35.4 42ps6 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 42ps6 , 42-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) a 42ps6 11/6/03 pin 1 e1 a1 b ref e b1 c l seating plane a 0?~ 15? d e eb common dimensions (unit of measure = mm) symbol min nom max note a 4.83 a1 0.51 d 36.70 36.96 note 2 e 15.24 15.88 e1 13.46 13.97 note 2 b 0.38 0.56 b1 0.76 1.27 l 3.05 3.43 c 0.20 0.30 eb 18.55 e 1.78 typ notes: 1. this package conforms to jedec reference ms-011, variation ac. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
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