1 ? fn7049 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved. elantec is a registered trademark of elantec semiconductor, inc. all other trademarks mentioned are the property of their respective owners. EL2142 data sheet september 1998, rev. b differential line receiver the EL2142 is a very high bandwidth amplifier designed to extract the difference signal from noisy environments, and is thus primarily targeted for applications such as receiving signals from twisted pair lines, or any application where common mode noise injection is likely to occur. the EL2142 is stable for a gain of one, and requires two external resistors to set the voltage gain. the output common mode level is set by the reference pin (v ref ), which has a -3db bandwidth of over 100mhz. generally, this pin is grounded, but it can be tied to any voltage reference. the output can deliver a minimum of 50ma and is short circuit protected to withstand a temporary overload condition. features differential input range 2.3v 150mhz 3db bandwidth 400v/s slewrate 5v supplies or single supply 50ma minimum output current output swing (100 ? load) to within 1.5v of supplies low power-11ma typical supply current applications twisted pair receiver differential line receiver vga over twisted pair adsl/hdsl receiver differential to single ended amplification. reception of analog signals in a noisy environment. pinout ordering information part number package temp. range pkg. no. EL2142cn 8-pin pdip -40c to +85c mdp0031 EL2142cs 8-pin soic -40c to +85c mdp0027 EL2142 (8-pin so, pdip) top view
2 absolute maximum ratings (t a = 25c) supply voltage (v cc ?v ee ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6v maximum output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60ma storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c lead temperature (<5 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +300c recommended operating temperature . . . . . . . . . . . -40c to 85c caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a dc electrical specifications v cc = +5v, v ee = -5v, t ee = 25c, v in = 0v, r l = 100, unless otherwise specified parameter description min typ max units v supply supply operating range (v cc -v ee ) 3.0 5.0 6.3 v i s power supply current (no load) 11 14 ma v os input referred offset voltage -25 10 40 mv i in input bias current (v in , v in b, v ref )-20620a z in differential input resistance 400 k ? c in differential input capacitance 1 pf v diff differential input range 2.0 2.3 v a vol open loop voltage gain 75 db v in input common mode voltage range -2.6 +4.0 v v out output voltage swing (50 ? load to gnd) 2.9 3.1 v i out (min) minimum output current 50 60 ma v n input referred voltage noise 36 nv/ hz v ref output voltage control range -2.5 +3.3 v psrr power supply rejection ratio 60 70 db cmrr2 input common mode rejection ratio (v in = 2v) 60 70 db cmrr1 input common mode rejection ratio (full v in range) 50 60 db EL2142
3 ac electrical specifications v cc = +5v, v ee = -5v, t a = 25c, v in = 0v, r load = 100, unless otherwise specified parameter description min typ max units bw(-3db) -3db bandwidth (gain =1) 150 mhz sr slewrate 400 v/s t stl settling time to 1% 15 ns gbwp gain bandwidth product 200 mhz v ref bw(-3db) v ref -3db bandwidth 130 mhz v ref sr v ref slewrate 100 v/sec dg differential gain at 3.58mhz 0.2 % d differential phase at 3.58mhz 0.2 pin descriptions pin number pin name function 1v fb feedback input 2v in non-inverting input 3v inb inverting input 4v ref sets output voltage level to v ref when v in =v inb 5nc 6v cc positive supply voltage 7v ee negative supply voltage 8v out output voltage EL2142
4 typical performance curves frequency response (gain = 1) i s vs supply voltage frequency response vs resistor r1 (gain = 4) v ref frequency response distortion vs frequency (gain = 3, r load = 100 ? ) v in = 2v pk-pk cmrr vs frequency EL2142
5 applications information gain equation v out = ((r2+r1)/r1) x (v in -v inb +v ref ) when r1 tied to gnd v out = ((r2+r1)/r1) x (v in -v inb ) when r1 tied to v ref choice of feedback resistor for a gain of one, v out may be shorted back to v fb , but 100 ? -200 ? improves the bandwidth. for gains greater than one, there is little to be gained from choosing resistor r1 value below 200 ? , for it would only result in increased power dissipation and potential signal distortion. above 200 ? , the bandwidth response will develop some peaking (for a gain of one), but substantially higher r1 values may be used for higher voltage gains, such as up to 1k ? at a gain of four before peaking will develop. capacitance considerations as with many high bandwidth amplifiers, the EL2142 prefers not to drive highly capacitive loads. it is best if the capacitance on v out is kept below 10pf if the user does not want gain peaking to develop. the v fb node forms a potential pole in the feedback loop, so capacitance should be minimized on this node for maximum bandwidth. the amount of capacitance tole rated on any of these nodes in an actual application will also be dependent on the gain setting and the resistor values in the feedback network. figure 1. typical twisted pair application 50 ? v fb 50 ? EL2142 v in v inb v ref v out 100 ? figure 2. coaxial cable driver pair application EL2142
6 figure 3. single supply receiver figure 4. compensated line receiver 50 ? v fb 50 ? EL2142 v in v inb v ref v out r2 r1 r3 c 1 z 0 = 100 ? EL2142
7 all intersil u.s. products are manufactured, asse mbled and tested utilizin g iso9000 quality systems. intersil corporation?s quality certifications c an be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com figure 5. two channel multiplexer EL2142
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