12-62 32-channel vacuum-fluorescent display driver package options device 40 pin dip 44 plastic chip carrier die HV518 HV518p HV518pj HV518x features n n 32 output lines n n 90v output swing n n active pull-down n n latches on all outputs n n up to 6mhz @ v dd = 5v n n -40 c to +85 c operation absolute maximum ratings supply voltage, v dd 1 -0.5v to +6.0v supply voltage, v pp 1 -0.5v to +90v logic input levels 1 -0.5v to v dd +0.5v continuous total power dissipation 2,3 1200mw operating temperature range -40 c to +85 c storage temperature range -65 c to +150 c lead temperature 1.6mm(1/16 inch) 260 c from case for 10 seconds notes: 1. all voltages referenced to gnd. 2. duty cycle is limited by the total power dissipated in the package. 3. for operation above 25 c ambient, derate linearly to 85 c at 20mw/ c. HV518 ordering information general description the HV518 is designed for vacuum fluorescent or dc plasma applications, where it can serve as a segment, digit or matrix display driver. each device has 32 outputs, 32 latches and a 32 bit cascadable shift register. serial data enters the shift register on the low-to-high transition of the clock input. with latch enable (le) high, parallel data is transferred to the output buffers through a 32-bit latch. when le is low the data is stored in the latch. when strobe is low, all outputs are enabled; if strobe is high, all outputs are low.
12-63 HV518 symbol parameter min typ max units conditions i dd supply current 10 ma v dd = 5v, f ch = 6.0 mhz i ddq quiescent supply current 0.5 ma v dd = 5.5v, v in = 0v i pp supply current 12 ma output high, t a = -40 c 7 10 ma output high, t a = 0 to +85 c 500 m a outputs low v oh high-level output voltage hvoutput 70.0 v i oh = -25ma serial output 4.5 4.9 5 v v dd = 5v, i oh = -20 m a v ol low-level output hvoutput 5 v i ol = 1ma serial output 0.06 0.8 v i ol =20 m a i ih high-level logic input current 0.1 1 m av ih = v dd i il low-level logic input current -0.1 -1 m av il = 0v note: the total number of on outputs times the duty cycle must not exceed the allowable package power disspation. electrical characteristics (over recommended ranges of operating free-air temperature and v dd . unless otherwise noted, v pp = 80v) symbol parameter min max unit conditions t d delay time, clock to data output v dd = 4.5v 600 ns c l =15 pf see figure 4 t dhl delay time, high-to-low-level, from latch enable v dd = 4.5v 1.5 m s see figure 5 hvoutput from strobe 1 see figure 6 t dlh delay time, low-to-high-level from latch enable v dd = 4.5v 1.5 m s see figure 5 hvoutput from strobe 1 see figure 6 t thl transition time, high-to-low-level, hvoutput v dd = 4.5v 3 m s see figure 6 t tlh transition time, low-to-high-level, hvoutput v dd = 4.5v 2.5 m s see figure 6 switching characteristics (v pp = 80v, c l = 50 pf, t a = 25 c, unless otherwise noted) symbol parameter min max units v dd logic voltage supply 4.5 5.5 v v pp high voltage supply 8 80 v v ih high-level input voltage (see fig.3.) v dd = 4.5v 3.5 v v il low-level input voltage (see fig. 3.) v dd = 4.5v 1 v i oh high-level output current -25 ma i ol low-level output current 2 ma f clk clock frequency (see figure 3) v dd = 4.5v 6.0 mhz t w(ckh) pulse duration , clock high v dd = 4.5v 83 ns t w(ckl) pulse duration , clock low v dd = 4.5v 83 ns t su setup time, data before clock v dd = 4.5v 75 ns t h hold time, data after clock v dd = 4.5v 75 ns t a operating free-air temperature -40 85 c note: power-up sequence should be the following: 1. connect ground. 2. apply v dd . 3. set all inputs (data, clk, enable, etc.) to a known state. 4. apply v pp . power-down sequence should be the reverse of the above. recommended operating conditions (t a = 25 c, unless otherwise noted)
12-64 HV518 t w(ckh) t w(ckl) t h t su 50% v ih v il v ih v il clock data in t w(ckh) t d 50% 50% clock data output v ih v il v oh v ol 50% 90% t or t dlh dhl 10% v oh v ol latch enable hv output v ih v il t tlh t thl 90% 10% t dlh t dhl v oh v ol strobe hv output v ih v il 50% v dd input gnd v pp gnd hv out logic inputs gnd data out logic data output high voltage outputs v dd input and output equivalent circuits parameter measurement information figure 3: input timing voltage waveforms figure 5 figure 4 figure 6: switching-time voltage waveforms note: for testing purposes, all input pulses have maximum rise and fall times of 30 nsec.
12-65 HV518 output data in le stb hv outputs x x h all low h h l high l h l low xll * * previous state valid irrelevant invalid valid previously stored data new data valid valid clock data in sr contents latch enable latch contents strobe hv output ? ? le latches hv 1 stb v pp d in d out clk 32-bit shift register out hv 32 out input data in clk data out hh ll x no change * * previous state block diagram truth tables typical operating sequence
12-66 HV518 6 40 41 42 43 44 1 2 3 4 5 39 38 37 36 35 34 33 32 31 30 29 18 28 27 26 25 24 23 22 21 20 19 7 8 9 10 11 12 13 14 15 16 17 top view 1 20 21 40 top view 40-pin dip pin configurations HV518 40 pin dual-in-line package pin function pin function 1v pp 21 clock 2 serial out 22 le 3hv out 32 23 hv out 16 4hv out 31 24 hv out 15 5hv out 30 25 hv out 14 6hv out 29 26 hv out 13 7hv out 28 27 hv out 12 8hv out 27 28 hv out 11 9hv out 26 29 hv out 10 10 hv out 25 30 hv out 9 11 hv out 24 31 hv out 8 12 hv out 23 32 hv out 7 13 hv out 22 33 hv out 6 14 hv out 21 34 hv out 5 15 hv out 20 35 hv out 4 16 hv out 19 36 hv out 3 17 hv out 18 37 hv out 2 18 hv out 17 38 hv out 1 19 strobe 39 data in 20 gnd 40 v dd HV518 44 pin j-lead package pin function pin function 1v pp 23 clock 2 serial out 24 le 3hv out 32 25 hv out 16 4hv out 31 26 hv out 15 5hv out 30 27 hv out 14 6 n/c 28 n/c 7hv out 29 29 n/c 8hv out 28 30 hv out 13 9hv out 27 31 hv out 12 10 hv out 26 32 hv out 11 11 hv out 25 33 hv out 10 12 hv out 24 34 hv out 9 13 hv out 23 35 hv out 8 14 hv out 22 36 hv out 7 15 hv out 21 37 hv out 6 16 hv out 20 38 hv out 5 17 hv out 19 39 hv out 4 18 n/c 40 hv out 3 19 hv out 18 41 hv out 2 20 hv out 17 42 hv out 1 21 strobe 43 data in 22 gnd 44 v dd package outline
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