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1. general description the ISP1362 is a single-chip universal serial bus (usb) on-the-go (otg) controller integrated with the advanced nxp slave host controller and the nxp isp1181b peripheral controller. the usb otg controller is compliant with ref . 1 on-the-go supplement to the usb 2.0 speci? cation re v . 1.0a . the host and peripheral controllers are compliant with ref . 2 univ ersal ser ial bus speci? cation re v . 2.0 (full-speed and low-speed support only), supporting data transfer at full-speed (12 mbit/s) and low-speed (1.5 mbit/s). the ISP1362 has two usb ports: port 1 and port 2. port 1 can be hardware con?gured to function as a downstream port, an upstream port or an otg port whereas port 2 can only be used as a downstream port. the otg port can switch roles from host to peripheral, or from peripheral to host. the otg port can become a host through host negotiation protocol (hnp) as speci?ed in the otg supplement. a usb product with otg capability can function either as a host or as a peripheral. for instance, with this dual-role capability, a pc peripheral such as a printer may switch roles from a peripheral to a host for connecting to a digital camera so that the printer can print pictures taken by the camera without using a pc. when a usb product with otg capability is inactive, the usb interface is turned off. this feature has made otg a technology well-suited for use in portable devices, such as, personal digital assistant (pda), digital still camera (dsc) and mobile phone, in which power consumption is a concern. the ISP1362 is an otg controller designed to perform such functions. 2. features n complies fully with: u ref . 2 univ ersal ser ial bus speci? cation re v . 2.0 u ref . 1 on-the-go supplement to the usb 2.0 speci? cation re v . 1.0a n supports data transfer at full-speed (12 mbit/s) and low-speed (1.5 mbit/s) n adapted from ref . 4 open host controller interf ace speci? cation f or usb release 1.0a n usb otg: u supports host negotiation protocol (hnp) and session request protocol (srp) for otg dual-role devices u provides status and control signals for software implementation of hnp and srp u provides programmable timers required for hnp and srp u supports built-in and external source of v bus u output current of the built-in charge pump is adjustable by using an external capacitor n usb host: ISP1362 single-chip universal serial bus on-the-go controller rev. 05 8 may 2007 product data sheet
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 2 of 152 nxp semiconductors ISP1362 single-chip usb otg controller u supports integrated physical 4096 bytes of multicon?guration memory u supports all four types of usb transfers: control, bulk, interrupt and isochronous u supports multiframe buffering for isochronous transfer u supports automatic interrupt polling rate mechanism u supports paired buffering for bulk transfer u directly addressable memory architecture; memory can be updated on-the-?y n usb device: u supports high performance usb interface device with integrated serial interface engine (sie), buffer memory and transceiver u supports fully autonomous and multicon?guration direct memory access (dma) operation u supports up to 14 programmable usb endpoints with two ?xed control in/out endpoints u supports integrated physical 2462 bytes of multicon?guration memory u supports endpoints with double buffering to increase throughput and ease real-time data transfer u supports controllable lazyclock (110 khz 50 %) output during suspend n supports two usb ports: port 1 and port 2 u port 1 can be con?gured to function as a downstream port, an upstream port or an otg port u port 2 can be used only as a downstream port n supports software-controlled connection to the usb bus (softconnect) n supports good usb connection indicator that blinks with traf?c (goodlink) n complies with usb power management requirements n supports internal power-on and low-voltage reset circuit, with possibility of a software reset n high-speed parallel interface to most cpus available in the market, such as hitachi sh-3, intel strongarm, nxp xa, fujitsu sparclite, nec and toshiba mips, arm7/9, freescale dragonball and powerpc reduced instruction set computer (risc): u 16-bit data bus u 10 mb/s data transfer rate between the microprocessor and the ISP1362 n supports programmed i/o (pio) or dma n supports suspend and remote wake-up n uses 12 mhz crystal or direct clock source with on-chip phase-locked loop (pll) for low electromagnetic interference (emi) n operates at 3.3 v power supply n operating temperature range from - 40 c to +85 c n available in 64-pin lqfp and tfbga packages 3. applications the ISP1362 can be used to implement a dual-role usb device in any application, usb host or usb peripheral, depending on the cable connection. if the dual-role device is connected to a typical usb peripheral, it behaves like a typical usb host. the dual-role device, however, can also be connected to a pc or any other usb host and behave like a typical usb peripheral.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 3 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 3.1 host/peripheral roles n mobile phone to/from: u mobile phone: exchange contact information u digital still camera: e-mail pictures or upload pictures to the web u mp3 player: upload, download and broadcast music u mass storage: upload and download ?les u scanner: scan business cards n digital still camera to/from: u digital still camera: exchange pictures u mobile phone: e-mail pictures, upload pictures to the web u printer: print pictures u mass storage: store pictures n printer to/from: u digital still camera: print pictures u scanner: print scanned image u mass storage: print ?les stored in a device n mp3 player to/from: u mp3 player: exchange songs u mass storage: upload and download songs n oscilloscope to/from: u printer: print screen image n personal digital assistant to/from: u personal digital assistant: exchange ?les u printer: print ?les u mobile phone: upload and download ?les u mp3 player: upload and download songs u scanner: scan pictures u mass storage: upload and download ?les u global positioning system (gps): obtain directions, mapping information u digital still camera: upload pictures u oscilloscope: con?gure oscilloscope
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 4 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 4. ordering information table 1. ordering information type number package name description version ISP1362bd lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 ISP1362ee tfbga64 plastic thin ?ne-pitch ball grid array package; 64 balls; body 6 6 0.8 mm sot543-1
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ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 6 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 6. pinning information 6.1 pinning fig 2. pin con?guration lqfp64 ISP1362bd dgnd id d2 h_dp2 d3 h_dm2 v cc otgmode d4 x2 d5 x1 d6 h_oc1 d7 h_oc2 dgnd v cc d8 gl d9 clkout d10 dgnd d11 h_pws2 v cc h_pws1 d12 d_suspend/d_wakeup d13 h_suspend/h_wakeup 004aaa050 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 d14 d15 dgnd rd cs wr test0 dreq1 dreq2 v cc dgnd dack1 dack2 int1 int2 reset d1 d0 a1 a0 test2 test1 v cc dgnd v dd(5v) v bus cp_cap2 cp_cap1 v cc agnd otg_dp1 otg_dm1 fig 3. pin con?guration tfbga64 004aaa151 ISP1362ee transparent top view k j h g f e c b a d 2468910 1357 ball a1 index area
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 7 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 6.2 pin description table 2. pin description symbol [1] pin type description lqfp64 tfbga64 dgnd 1 b1 - digital ground d2 2 c2 i/o bit 2 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, 3-state output d3 3 c1 i/o bit 3 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, 3-state output v cc 4 d2 - supply voltage (3.3 v); it is recommended that you connect a decoupling capacitor of 0.01 m f d4 5 d1 i/o bit 4 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, 3-state output d5 6 e2 i/o bit 5 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, 3-state output d6 7 e1 i/o bit 6 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, 3-state output d7 8 f2 i/o bit 7 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, 3-state output dgnd 9 f1 - digital ground d8 10 g2 i/o bit 8 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, 3-state output d9 11 g1 i/o bit 9 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, 3-state output d10 12 h2 i/o bit 10 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, 3-state output d11 13 h1 i/o bit 11 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, 3-state output
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 8 of 152 nxp semiconductors ISP1362 single-chip usb otg controller v cc 14 j2 - supply voltage (3.3 v); it is recommended that you connect a decoupling capacitor of 0.01 m f d12 15 j1 i/o bit 12 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, 3-state output d13 16 k1 i/o bit 13 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, 3-state output d14 17 k2 i/o bit 14 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, 3-state output d15 18 j3 i/o bit 15 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, 3-state output dgnd 19 k3 - digital ground rd 20 j4 i read strobe input; when asserted low, it indicates that the host controller/peripheral controller driver is requesting a read to the buffer memory or the internal registers of the host controller/peripheral controller input with hysteresis cs 21 k4 i chip select input (active low); enables the host controller/peripheral controller driver to access the buffer memory and registers of the host controller/peripheral controller input wr 22 j5 i write strobe input; when asserted low, it indicates that the host controller/peripheral controller driver is requesting a write to the buffer memory or the internal registers of the host controller/peripheral controller input with hysteresis test0 23 k5 i/o for test input and output; pulled high by a 100 k w resistor bidirectional, push-pull input, 3-state output dreq1 24 j6 o dma request output; when active, it signals the dma controller that a data transfer is requested by the host controller; the active level (high or low) of the request is programmed by using the hchardwarecon?guration register (20h/a0h) if the onedma bit of the hchardwarecon?guration register is set to logic 1, both the host controller and the peripheral controller dma channel will be routed to dreq1 and d a ck1. push-pull output table 2. pin description continued symbol [1] pin type description lqfp64 tfbga64
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 9 of 152 nxp semiconductors ISP1362 single-chip usb otg controller dreq2 25 k6 o dma request output; when active, it signals the dma controller that a data transfer is requested by the peripheral controller; the active level (high or low) of the request is programmed by using the dchardwarecon?guration register (bah/bbh) push-pull output v cc 26 j7 - supply voltage (3.3 v); it is recommended that you connect a decoupling capacitor of 0.01 m f dgnd 27 k7 - digital ground d a ck1 28 j8 i dma acknowledge input; indicates that a request for dma transfer from the host controller has been granted by the dma controller; the active level (high or low) of the acknowledge signal is programmed by using the hchardwarecon?guration register (20h/a0h); when not in use, this pin must be connected to v cc through a 10 k w resistor input with hysteresis d a ck2 29 k8 i dma acknowledge input; indicates that a request for dma transfer from the peripheral controller has been granted by the dma controller; the active level (high or low) of the acknowledge signal is programmed by using the dchardwarecon?guration register (bah/bbh); when not in use, this pin must be connected to v cc through a 10 k w resistor input with hysteresis int1 30 j9 o interrupt request from the host controller; provides a mechanism for the host controller to interrupt the microprocessor; for details, see hchardwarecon?guration register (20h/a0h) section 14.4.1 if the oneint bit of the hchardwarecon?guration register is set to logic 1, both the host controller and the peripheral controller interrupt request will be routed to int1. push-pull output int2 31 k9 o interrupt request from the peripheral controller; provides a mechanism for the peripheral controller to interrupt the microprocessor; for details, see dchardwarecon?guration register (bah/bbh) section 15.1.4 push-pull output reset 32 k10 i reset input input with hysteresis and internal pull-up resistor h_suspend/ h_w akeup 33 j10 i/o i/o pin (open-drain); goes high when the host controller is in suspend mode; a low pulse must be applied to this pin to wake up the host controller; connect a 100 k w resistor to v cc bidirectional, push-pull input, 3-state open-drain output d_suspend/ d_w akeup 34 h9 i/o i/o pin (open-drain); goes high when the peripheral controller is in suspend mode; a low pulse must be applied to this pin to wake up the peripheral controller; connect a 100 k w resistor to v cc bidirectional, push-pull input, 3-state open-drain output table 2. pin description continued symbol [1] pin type description lqfp64 tfbga64
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 10 of 152 nxp semiconductors ISP1362 single-chip usb otg controller h_psw1 35 h10 o connects to the external pmos switch; required when the external charge pump or external v bus is used for providing v bus to the downstream port low switches on the pmos providing v bus to the downstream port high switches off the pmos when not in use, leave this pin open open-drain output h_psw2 36 g9 o connects to the external pmos switch low switches on the pmos providing v bus to the downstream port high switches off the pmos when not in use, leave this pin open open-drain output dgnd 37 g10 - digital ground clkout 38 f9 o programmable clock output; the default clock frequency is 12 mhz and can be varied from 3 mhz to 48 mhz push-pull output gl 39 f10 o goodlink led indicator output; the led is off by default, blinks on at usb traf?c open-drain output; 4 ma v cc 40 e9 - supply voltage (3.3 v); it is recommended that you connect a decoupling capacitor of 0.01 m f h_oc2 41 e10 i overcurrent sense input for downstream port 2; both the digital and analog overcurrent inputs can be used for port 2, depending on the hardware mode register setting; when not in use, it is recommended that you connect this pin to the v dd(5v) pin h_oc1 42 d9 i overcurrent sensing input for downstream port 1; both the digital and analog overcurrent inputs can be used for port 1, depending on the hardware mode register setting; when not in use, it is recommended that you connect this pin to the v dd(5v) pin x1 43 d10 ai crystal input; directly connected to a 12 mhz crystal; when this pin is connected to an external clock oscillator, leave pin x2 open x2 44 c9 ao crystal output; directly connected to a 12 mhz crystal; when pin x1 is connected to an external clock oscillator, leave this pin open o tgmode 45 c10 i to select whether port 1 is operating in otg or non-otg mode; see t ab le 8 input with hysteresis h_dm2 46 b9 ai/o downstream d - signal; host only, port 2; when not in use, leave this pin open and set bit connectpulldown_ds2 of the hchardwarecon?guration register h_dp2 47 b10 ai/o downstream d+ signal; host only, port 2; when not in use, leave this pin open and set bit connectpulldown_ds2 of the hchardwarecon?guration register id 48 a10 i input pin for sensing otg id; the status of this input pin is re?ected in the otgstatus register (bit 0); see t ab le 8 input with hysteresis table 2. pin description continued symbol [1] pin type description lqfp64 tfbga64
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 11 of 152 nxp semiconductors ISP1362 single-chip usb otg controller [1] symbol names with an overscore (for example, name) represent active low signals. [2] in otg mode, this pin is pulled down by an internal resistor. otg_dm1 49 a9 ai/o d - signal of the otg port, the downstream host port 1 or the upstream device port; when not in use, leave this pin open and set bit connectpulldown_ds1 of the hchardwarecon?guration register [2] otg_dp1 50 b8 ai/o d+ signal of the otg port, the downstream host port 1 or the upstream device port; when not in use, leave this pin open and set bit connectpulldown_ds1 of the hchardwarecon?guration register [2] agnd 51 a8 - analog ground; used for otg atx v cc 52 b7 - supply voltage (3.3 v); it is recommended that you connect a decoupling capacitor of 0.01 m f cp_cap1 53 a7 ai/o charge pump capacitor pin 1; low esr; see section 10.6 cp_cap2 54 b6 ai/o charge pump capacitor pin 2; low esr; see section 10.6 v bus 55 a6 i/o analog input and output otg mode built-in charge pump output or v bus voltage comparators input; connect to pin v bus of the otg connector peripheral controller mode input as v bus sensing; connect to pin v bus of the upstream connector host controller mode not used; leave open v dd(5v) 56 b5 i supply reference voltage (5 v); to be used together with built-in overcurrent circuit; when built-in overcurrent circuit is not in use, this pin can be tied to v cc ; it is recommended that you connect a decoupling capacitor of 0.01 m f dgnd 57 a5 - digital ground v cc 58 b4 - supply voltage (3.3 v); it is recommended that you connect a decoupling capacitor of 0.01 m f test1 59 a4 i/o for test input and output, pulled to gnd by a 10 k w resistor bidirectional, push-pull input, 3-state output test2 60 b3 i/o for test input and output, pulled to gnd by a 10 k w resistor bidirectional, push-pull input, 3-state output a0 61 a3 i command or data phase input a1 62 b2 i low pio bus of the host controller is selected high pio bus of the peripheral controller is selected input d0 63 a2 i/o bit 0 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, 3-state output d1 64 a1 i/o bit 1 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, 3-state output table 2. pin description continued symbol [1] pin type description lqfp64 tfbga64
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 12 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 7. functional description 7.1 on-the-go (otg) controller the otg controller provides all the control, monitoring and switching functions required in otg operations. 7.2 advanced nxp slave host controller the advanced nxp slave host controller is designed for highly optimized usb host functionality. many advanced features are integrated to fully utilize the usb bandwidth. a number of tasks are performed at the hardware level. this reduces the requirement on the microprocessor and thus speeds up the system. 7.3 nxp peripheral controller the nxp peripheral controller is a high performance usb device with up to 14 programmable endpoints. these endpoints can be con?gured as double-buffered endpoints to further enhance the throughput. 7.4 phase-locked loop (pll) clock multiplier a 12 mhz-to-48 mhz clock multiplier pll is integrated on-chip. this allows the use of a low-cost 12 mhz crystal that also minimizes electromagnetic interference (emi) because of low frequency. no external components are required for the operation of pll. 7.5 usb and otg transceivers the integrated transceivers (for typical downstream port) directly interface to the usb connectors (type a) and cables through some termination resistors. the transceiver is compliant with ref . 2 univ ersal ser ial bus speci? cation re v . 2.0 . 7.6 overcurrent protection the ISP1362 has a built-in overcurrent protection circuitry. this feature monitors the current drawn on the downstream v bus and switches off v bus when the current exceeds the current threshold. the built-in overcurrent protection feature can be used when the port acts as a host port. 7.7 bus interface the bus interface connects the microprocessor to the usb host and the usb device, allowing fast and easy access to both. 7.8 peripheral controller and host controller buffer memory 4096 bytes (host) and 2462 bytes (device) of built-in memory provide suf?cient space for the buffering of usb traf?c. memory in the host controller is addressable by using the fast and versatile direct addressing method.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 13 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 7.9 goodlink indication of a good usb connection is provided through the goodlink technology (open-drain, maximum current: 4 ma). during enumeration, led indicators momentarily blink on corresponding to the enumeration traf?c of the ISP1362 ports. the led also blinks on whenever there is valid traf?c to the usb ports. in suspend mode, the led is off. this feature of goodlink provides a user-friendly indication on the status of the usb traf?c between the host and the hub, as well as the connected devices. it is a useful diagnostics tool to isolate faulty equipment, and helps to reduce ?eld support and hotline costs. 7.10 charge pump the charge pump generates a 5 v supply from 3.3 v to drive v bus when the ISP1362 is an a-device in otg mode. for details, see section 10.6 . 8. host and device bus interface the interface between the external microprocessor and the ISP1362 host controller (hc) and peripheral controller is separately handled by the individual bus interface circuitry. the host or device automultiplex selects the path for the host access or the device access. this selection is determined by the a1 address line. for any access to the host controller or peripheral controller registers, the command phase and the data phase are needed, which is determined by the a0 address line. all the functionality of the ISP1362 can be accessed using a group of registers and two buffer memory areas (one for the host controller and the other for the peripheral controller). registers can be accessed using programmed i/o (pio) mode. the buffer memory can be accessed using both pio and direct memory access (dma) modes. when cs is low (active), address pin a1 has priority over dreq and d a ck. therefore, as long as the cs pin is held low, the ISP1362 bus interface does not respond to any d a ck signals. when cs is high (inactive), the bus interface will respond to dreqn and d a ckn. address pin a1 will be ignored when cs is inactive. an active d a ckn signal when dreqn is inactive will be ignored. if dreq1, d a ck1, dreq2 and d a ck2 are active, the bus interface will be switched off to avoid potential data corruption. t ab le 3 provides the bus access priority for the ISP1362. [1] only to enable and disable the bus. depends only on the d a ck signal. table 3. bus access priority table for the ISP1362 priority cs a1 d a ck1 d a ck2 dreq1 dreq2 host controller and peripheral controller active 1 l l x x x x host controller 2lhx xxxper ipheral controller 3 h x l x h l host controller [1] 4 h x x l l h peripheral controller [1] 5 h x x x h h no driving
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 14 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 8.1 memory organization the buffer memory in the host controller uses a multicon?gurable direct addressing architecture. the 4096 bytes host controller buffer memory is shared by the istl0, istl1, intl and atl buffers. istl0 and istl1 are used for isochronous traf?c (double buffer), intl is used for interrupt traf?c, and atl is used for control and bulk traf?c. the allocation of the buffer memory follows the sequence istl0, istl1, intl, atl and unused memory. for example, consider that the buffer sizes of the istl, intl and atl buffers are 1024 bytes, 1024 bytes and 1024 bytes, respectively. then, istl0 will start from memory location 0, istl1 will start from memory location 1024 (size of istl0), intl will start from memory location 2048 (size of istl0 + size of istl1) and atl will start from memory location 3072 (size of istl0 + size of istl1 + size of intl). the host controller driver (hcd) has the responsibility to ensure that the sum of the four memory buffers does not exceed the total memory size. if this condition is violated, it will lead to data corruption. the buffer size must be a multiple of 2 bytes (one word). the buffer memory of the peripheral controller follows a similar architecture. details on the peripheral controller memory area allocation can be found in section 12.3 . note that the peripheral controller buffer memory does not support direct addressing mode. 8.1.1 memory organization for the host controller the host controller in the ISP1362 has a total of 4096 bytes of buffer memory. this buffer area is divided into four parts (see t ab le 4 and figure 4 ). the istl0 and istl1 buffers must have the same size. memory is allocated by the host controller according to the value set by the hcd in hcistlbuffersize, hcintlbuffersize and hcatlbuffersize. all buffer sizes must be multiples of 2 bytes (one word). table 4. buffer memory areas and their applications buffer memory area application istl0 and istl1 isochronous transfer (double buffering) intl interrupt transfer atl control and bulk transfer
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 15 of 152 nxp semiconductors ISP1362 single-chip usb otg controller the intl and atl buffers use blocked memory management scheme to enhance the status and control capability of each and every individual philips transfer descriptor (ptd) structure. the intl and atl buffers are further divided into blocks of equal sizes, depending on the value written to the hcatlblksize register (atl) and the hcintlblksize register (intl). the ISP1362 host controller supports up to 32 blocks in the atl and intl buffers. each of these blocks can be used for one complete ptd data. note that the block size does not include the 8 bytes ptd header and is strictly the size of the payload. both the atl and intl block sizes must be a multiple of double word (4 bytes). fig 4. recommended values of the ISP1362 buffer memory allocation 004aaa053 istl0 area (512 bytes) istl1 area (512 bytes) 0fffh intl area (512 bytes) atl area (1536 bytes) 0a00h 09ffh 0800h 07ffh 0400h 03ffh 0000h
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 16 of 152 nxp semiconductors ISP1362 single-chip usb otg controller figure 5 provides a snapshot of a sample atl or intl buffer area of 256 bytes with a block size of 64 bytes. the hcd may put a ptd with payload size of up to 64 bytes but not more. depending on the atl or intl buffer size, up to 32 atl blocks and 32 intl blocks can be allocated. note that a portion of the atl or intl buffer remains unused. this is allowed but can be avoided by choosing the appropriate atl or intl buffer size and block size. the istl0 or istl1 buffer memory (for isochronous transfer) uses a different memory management scheme (see figure 6 ). there is no ?xed block size for the istl buffer memory. while the ptd header remains 8 bytes for all ptds, the ptd payload can be of any size. the ptd payload, however, is padded to the next double word boundary when the host controller calculates the location of the next ptd header. the ISP1362 host controller checks the payload size from the total size ?eld of the ptd itself and calculates the location of the next ptd header based on this information. fig 5. a sample snapshot of the atl or intl memory management scheme 004aaa055 8 bytes ptd header 64 bytes ptd header payload are 8 bytes ptd header 64 bytes ptd header payload area 8 bytes ptd header 64 bytes ptd header payload area block of 72 bytes (64 + 8, where 64 is the block size defined) 72 bytes 72 bytes starting address of the atl or intl buffer area
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 17 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 8.1.2 memory organization for the peripheral controller the ISP1362 peripheral controller has a total of 2462 bytes of built-in buffer memory. this buffer memory is multicon?gurable to support the requirements of different applications. the peripheral controller buffer memory is divided into 16 areas to be used by control out, control in and 14 programmable endpoints. figure 7 provides a snapshot of the peripheral controller buffer memory. total size is a 10-bit ?eld in the ptd. fig 6. a sample snapshot of the istl memory management scheme 004aaa054 ptd header (total size = 64) ptd payload (64 bytes) ptd header (total size = 160) ptd payload (160 bytes) ptd header (total size = 32) ptd payload (32 bytes) 72 bytes (64 + 8) 168 bytes (160 + 8) 40 bytes (32 + 8) starting address of istl0 or istl1
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 18 of 152 nxp semiconductors ISP1362 single-chip usb otg controller the buffer memory is con?gured by dcendpointcon?guration registers (ecrs). although the control endpoint has a ?xed con?guration, all 16 endpoints (control out, control in and 14 programmable endpoints) must be con?gured before the peripheral controller internally allocates the buffer. the 14 programmable endpoints can be programmed into sizes ranging from 16 bytes to 1023 bytes, single or double buffering. the peripheral controller buffer memory for each endpoint can be accessed through the dcendpointstatusimage registers. 8.2 pio access mode the ISP1362 provides pio mode for external microprocessors to access its internal control registers and buffer memory. it occupies only four i/o ports or four memory locations of a microprocessor. an external microprocessor can read or write to the internal control registers and buffer memory of the ISP1362 through pio operating mode. figure 8 shows the pio interface between a microprocessor and the ISP1362. fig 7. peripheral controller buffer memory organization 004aaa057 control out (64 bytes) endpoint 1 (128 bytes) endpoint 2 (128 bytes) endpoint 3 (512 bytes) endpoint 4 (64 bytes) control in (64 bytes) endpoint 5 (64 bytes) endpoint 6 (96 bytes) endpoint 7 (96 bytes)
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 19 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 8.3 dma mode the ISP1362 also provides dma mode for external microprocessors to access the internal buffer memory of the ISP1362. the dma operation enables data to be transferred between the system memory of a microprocessor and the internal buffer memory of the ISP1362. remark: the dma operation must be controlled by the dma controller of the external microprocessor system (master). figure 9 shows the dma interface between a microprocessor system and the ISP1362. the ISP1362 provides two dma channels. dma channel 1 (controlled by the dreq1 and d a ck1 signals) is for the dma transfer between the system memory of a microprocessor and the internal buffer memory of the ISP1362 host controller. dma channel 2 (controlled by the dreq2 and d a ck2 signals) is for the dma transfer between the system memory of a microprocessor and the internal buffer memory of the ISP1362 peripheral controller. the ISP1362 provides an internal end-of-transfer (eot) signal to terminate the dma transfer. fig 8. pio interface between a microprocessor and the ISP1362 004aaa042 d [ 15:0 ] rd wr cs a2 irq2 micro- processor ISP1362 d [ 15:0 ] microprocessor bus interface rd wr cs a1 a1 irq1 a0 int1 int2 fig 9. dma interface between a microprocessor and the ISP1362 004aaa043 d [ 15:0 ] rd wr dack1 dreq1 micro- processor ISP1362 d [ 15:0 ] microprocessor bus interface rd wr dack1 dreq1 dack2 dreq2 dack2 dreq2
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 20 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 8.4 pio access to internal control registers t ab le 5 shows the i/o port addressing in the ISP1362. the complete i/o port address decoding must combine with the chip select signal ( cs) and address lines (a1 and a0). the direction of access of i/o ports, however, is controlled by the rd and wr signals. when rd is low, the microprocessor reads data from the data port of the ISP1362 (see figure 10 ). when wr is low, the microprocessor writes command to the command port or writes data to the data port (see figure 11 ). the register structure in the ISP1362 is a command-data register pair structure. a complete register access needs a command phase followed by a data phase. the command (also named as the index of a register) is used to inform the ISP1362 about the register that will be accessed at the data phase. on the 16-bit data bus of a microprocessor, a command occupies the lower byte and the upper byte is ?lled with zeros (see figure 12 ). for 32-bit registers, the access cycle is shown in figure 13 . it consists of a command phase followed by two data phases. table 5. i/o port addressing cs a1 a0 access data bus width description l l l r/w 16 bits host controller data port l l h w 16 bits host controller command port l h l r/w 16 bits peripheral controller data port l h h w 16 bits peripheral controller command port when a1 = l, the microprocessor accesses the host controller. when a1 = h, the microprocessor accesses the peripheral controller. fig 10. microprocessor access to the host controller or the peripheral controller 004aaa122 microprocessor bus interface host bus interface device bus interface bus interface a1 0 1
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 21 of 152 nxp semiconductors ISP1362 single-chip usb otg controller when a0 = l, the microprocessor accesses the data port. when a0 = h, the microprocessor accesses the command port. fig 11. access to internal control registers fig 12. pio register access 004aaa160 cmd/data switch commands control registers command register data port a0 command port . . . host or device bus interface 1 0 004aaa045 read 16-bit write 16-bit a0/a1 d[15:0] rd cs a0/a1 d[15:0] wr cs
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 22 of 152 nxp semiconductors ISP1362 single-chip usb otg controller the following is a sample code for pio access to internal control registers: unsigned long read_reg32(unsigned char reg_no) { unsigned int result_l,result_h; unsigned long result; outport(hc_com, reg_no); // command phase result_l = inport(hc_data); // data phase result_h = inport(hc_data); // data phase fig 13. pio access for a 16-bit or 32-bit register 004aaa046 a0/a1 d[15:0] rd cs wr a0/a1 d[15:0] rd cs wr reading from a 16-bit or 32-bit register 16-bit access 32-bit access command phase data phase second data phase for 32-bit register writing to a 16-bit or 32-bit register 16-bit access 32-bit access command phase data phase second data phase for 32-bit register
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 23 of 152 nxp semiconductors ISP1362 single-chip usb otg controller result = result_h; result = result<<16; result = result+result_l; return(result); } void write_reg32(unsigned char reg_no, unsigned long data2write) { unsigned int low_word; unsigned int hi_word; low_word=data2write&0x0000ffff; hi_word=(data2write&0xffff0000)>>16; outport(hc_com,reg_no|0x80); // command phase outport(hc_data,low_word); // data phase outport(hc_data,hi_word); // data phase } unsigned int read_reg16(unsigned char reg_no) { unsigned int result; outport(hc_com, reg_no); // command phase result = inport(hc_data); // data phase return(result); } void write_reg16(unsigned char reg_no, unsigned int data2write) { outport(hc_com,reg_no|0x80); // command phase outport(hc_data,data2write); // data phase } 8.5 pio access to the buffer memory the buffer memory in the ISP1362 can be addressed using either the direct addressing method or the indirect addressing method. 8.5.1 pio access to the buffer memory by using direct addressing this method uses the hcdirectaddresslength register to specify two parameters required to randomly access the ISP1362 buffer memory (total of 4096 bytes). these two parameters are: starting address location to start writing or reading data length number of bytes to write or read. the following is a sample code to set the hcdirectaddresslength register:
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 24 of 152 nxp semiconductors ISP1362 single-chip usb otg controller void set_diraddrlen(unsigned int data_length,unsigned int addr) { unsigned long regdata = 0; regdata =(long)(addr&0x7fff); regdata|=(((long)data_length)<<16); write_reg32(hcdiraddrlen,regdata); } after the proper value is written to the hcdirectaddresslength register, data is accessible from the hcdirectaddressdata register (called as hcdiraddr_port in the following sample code). a sample code to write word_size bytes of data from *w_ptr to the memory locations of the ISP1362 buffer starting from the address start_addr is as follows: void direct_write(unsigned int *w_ptr,unsigned int start_addr,unsigned int word_size) { unsigned int cnt = 0; set_diraddrlen(word_size*2,start_addr); outport(hc_com,hcdiraddr_port|0x80); // hc_com is system address of // hc command port do { outport(hc_data,*(w_ptr+cnt)); // hc_data is system address of // hc data port cnt++; } while(cntISP1362 memory. your program, however, needs the address location of each buffer area to access them. 8.5.2 pio access to the buffer memory by using indirect addressing indirect addressing is the addressing method that is compatible with nxp isp1161 addressing mode. this method uses a unique data port for each buffer memory area (atl, intl, istl0 and istl1). these four data areas share the hctransfercounter register that is used to indicate the number of bytes to be transferred. a sample code to write an array at *a_ptr into the atl memory area with word_size as the word size is given as follows: void write_atl(unsigned int *a_ptr, unsigned int word_size) { int cnt; write_reg16(hctransfercnt,word_size*2); outport(hc_com,hcatl_port|0x80); // hc_com is system address of hc // command port
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 25 of 152 nxp semiconductors ISP1362 single-chip usb otg controller cnt=0; do { outport(hc_data,*(a_ptr+cnt)); // hc_data is system address of hc // data port cnt++; } while(cnt<(word_size)); remark: the hctransfercounter register counts the number of bytes even though the transfer is in number of words. therefore, the transfer counter must be set to word_size 2. incorrect setting of the hctransfercounter register may cause the ISP1362 to go into an indeterminate state. the buffer memory access using indirect addressing always starts from location 0 of each buffer area. only the front portion of the memory (example: ?rst 64 bytes of a 1024 bytes buffer) can be accessed. therefore, to access a portion of the memory that does not start from memory location 0, all memory locations before that location must be accessed in a sequential order. the method is similar to the sequential ?le access method. 8.6 setting up a dma transfer the ISP1362 uses two dma channels to individually serve the host controller and the peripheral controller. the dma transfer allows the system cpu to work on other tasks while the dma controller transfers data to or from the ISP1362. the dma slave controller, in the ISP1362, is compatible with the 8327 type dma controller. the dma transfer can be used with direct addressing mode or indirect addressing mode. the registers used in these two modes are shown in t ab le 6 . [1] in direct addressing mode, hctransfercounter must be set to 0001h. 8.6.1 con?guring registers for a dma transfer to set up a dma transfer, the following host controller registers must be con?gured, depending on the type of transfer required: ? hchardwarecon?guration C dreq1 output polarity (bit 5) C d a ck1 input polarity (bit 6) C d a ck mode (bit 8) ? hc m pinterruptenable C if you want an interrupt to be generated after the dma transfer is complete, set eotinterruptenable (bit 3). ? hc m pinterrupt C before initiating the dma transfer, clear alleotinterrupt (bit 3). this bit is set when the dma transfer is complete. table 6. registers used in addressing modes addressing mode [1] hcdmacon?guration bit[3:1] total bytes to transfer direct addressing 1xxb hcdirectaddresslength indirect addressing 0xxb hctransfercounter
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 26 of 152 nxp semiconductors ISP1362 single-chip usb otg controller ? hctransfercounter C if dmacounterenable of the hcdmacon?guration register is set (that is, the dma counter is enabled), hctransfercounter must be set to the number of bytes to be transferred. ? hcdmacon?guration C read or write dma (bit 0) C targeted buffer: istl0, istl1, atl and intl (bits 1 to 3) C dma enable or disable (bit 4) C burst length (bits 5 to 6) C dma counter enable (bit 7) remark: con?gure the hcdmacon?guration register only after you have con?gured all the other registers. the ISP1362 will assert dreq1 once the dma enable bit in this register is set. 8.6.2 combining the two dma channels the ISP1362 allows systems with limited dma channels to use a single dma channel (dma1) for both the host controller and the peripheral controller. this option can be enabled by writing logic 1 to the onedma bit of the hchardwarecon?guration register. if this option is enabled, the polarity of the peripheral controller dma and the host controller dma must be set to dack active low and dreq active high. 8.7 interrupts various events in the host controller, the peripheral controller and the otg controller can be programmed to generate a hardware interrupt. by default, the interrupt generated by the host controller and the otg controller is routed out at the int1 pin and the interrupt generated by the peripheral controller is routed out at the int2 pin. 8.7.1 interrupt in the host controller and the otg controller there are two levels of interrupts represented by level 1 and level 2 (see figure 14 ).
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 27 of 152 nxp semiconductors ISP1362 single-chip usb otg controller fig 14. hc and otg interrupt logic istl_1_int 004aaa395 latch oneint interruptpinenable fno rhsc mie ue rd sf so rhsc fno ue rd sf so or or otg_irq_interruptenable atl_irq_interruptenable intl_irq_interruptenable clkready hcsuspendedenable oprinterruptenable eot_interruptenable istl_1_interruptenable istl_0_interruptenable sofinterruptenable otg_irq atl_irq intl_irq clkready hcsuspended opr_reg aiieotinterrupt istl_0_int sof_int from int2 le hchardwareconfiguration register hchardwareconfiguration register int1 level 1 hc m pinterrupt register hcinterruptenable register hcinterruptstatus register hc m pinterruptenable register otginterrupt register a_vbus_vld_c b_sess_end_c a_sess_vld_c b_sess_vld_c rmt_conn_c otg_suspnd otg_resume a_srp_det b_se0_srp otg_tmr_timeout id_reg_c otginterruptenable register a_vbus_vld_ie b_sess_end_ie a_sess_vld_ie b_sess_vld_ie rmt_conn_ie otg_suspnd_ie otg_resume_ie a_srp_det_ie b_se0_srp_ie otg_tmr_ie id_reg_ie or level 2 (otg group) level 2 (opr group)
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 28 of 152 nxp semiconductors ISP1362 single-chip usb otg controller interrupt level 2 (opr group) contains six possible interrupt events (recorded in the hcinterruptstatus register). when any of these events occurs, the corresponding bit will be set to logic 1, and if the corresponding bit in the hcinterruptenable register is also logic 1, the 6-input or gate will output logic 1. this output is combined with the value of mie (bit 31 of hcinterruptenable) using the and operation and logic 1 output at this and gate will cause the opr bit in the hc m pinterrupt register to be set to logic 1. interrupt level 2 (otg group) contains 11 possible interrupt events (recorded in the otginterrupt register). when any of these events occurs, the corresponding bit will be set to logic 1, and if the corresponding bit in the otginterruptenable register is also logic 1, the 11-input or gate will output logic 1 and cause the otg_irq bit in the hc m pinterrupt register to be set to logic 1. level 1 interrupts contains 10 possible interrupt events. the hc m pinterrupt and hc m pinterruptenable registers work in the same way as the hcinterruptstatus and hcinterruptenable registers. the output from the 10-input or gate is connected to a latch, which is controlled by interruptpinenable (the bit 0 of hchardwarecon?guration register). when the software wishes to temporarily disable the interrupt output of the ISP1362 host controller and otg controller, follow this procedure: 1. set the interruptpinenable bit in the hchardwarecon?guration register to logic 1. 2. clear all bits in the hc m pinterrupt register. 3. set the interruptpinenable bit to logic 0. to re-enable the interrupt generation, set the interruptpinenable bit to logic 1. remark: the interruptpinenable bit in the hchardwarecon?guration register controls the latch of the interrupt output. when this bit is set to logic 0, the interrupt output will remain unchanged, regardless of any operation on interrupt control registers. if int1 is asserted, and the hcd wishes to temporarily mask off the int signal without clearing the hc m pinterrupt register, follow this procedure: 1. make sure that the interruptpinenable bit is set to logic 1. 2. clear all bits in the hc m pinterruptenable register. 3. set the interruptpinenable bit to logic 0. to re-enable the interrupt generation: 1. set all bits in the hc m pinterruptenable register, according to the hcd requirements. 2. set the interruptpinenable bit to logic 1. 8.7.2 interrupt in the peripheral controller the registers that control the interrupt generation in the ISP1362 peripheral controller are: ? dcmode (bit 3) ? dchardwarecon?guration (bits 0 and 1) ? dcinterruptenable ? dcinterrupt
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 29 of 152 nxp semiconductors ISP1362 single-chip usb otg controller the dcmode register (bit 3) is the overall peripheral controller interrupt enable. dchardwarecon?guration determines the following features: ? level-triggered or edge-triggered (bit 1) ? output polarity (bit 0) for details on the interrupt logic in the peripheral controller, refer to ref . 5 interr upt control application note . 8.7.3 combining int1 and int2 in some embedded systems, interrupt inputs to the cpu are a very scarce resource. the system designer might want to use just one interrupt line to serve the host controller, the peripheral controller and the otg controller. in such a case, make sure the oneint feature is activated. when oneint (bit 9 of the hchardwarecon?guration register) is set to logic 1, both the int1 (hc or otg controller) interrupt and the int2 (peripheral controller) interrupt are routed to pin int1, thereby reducing hardware resource requirements. remark: both the host controller (or otg controller) and the peripheral controller interrupts must be set to the same polarity (active high or active low) and the same trigger type (edge or level). failure to conform to this will lead to unpredictable behavior of the ISP1362. 8.7.4 behavior difference between level-triggered and edge-triggered interrupts in many microprocessor systems, the operating system disables an interrupt when it is in an interrupt service routine (isr). if there is an interrupt event during this period, it will lead to level-triggered interrupt and edge-triggered interrupt. 8.7.4.1 level-triggered interrupt when the ISP1362 interrupt asserts, the operating system takes no action because it disables the interrupt when it is in the isr. the interrupt line of the ISP1362 remains asserted. when the operating system exits the isr and re-enables the interrupt processing, it sees the asserted interrupt line and immediately enters the isr. 8.7.4.2 edge-triggered interrupt when the ISP1362 outputs a pulse, the operating system takes no action because it disables the interrupt when it is in the isr. the interrupt line of the ISP1362 goes back to the inactive state. when the operating system exits the isr and re-enables the interrupt processing, it sees no pending interrupt. as a result, the interrupt is missed. if the system needs to know whether an interrupt (approximately 160 ns pulse width) occurs during this period, it may read the hc m pinterrupt register (see t ab le 69 ).
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 30 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 9. power-on reset (por) when v cc is directly connected to the reset pin, the internal por pulse width (t porp ) will typically be 800 ns. the pulse is started when v cc rises above v trip (2.03 v). to give a better view of the functionality, figure 15 shows a possible curve of v cc with dips at t2 to t3 and t4 to t5. if the dip at t4 to t5 is too short (that is, < 11 m s), the internal por pulse will not react and will remain low. the internal por starts with a high at t0. at t1, the detector will see the passing of the trip level and a delay element will add another t porp before it drops to low. the internal por pulse will be generated whenever v cc drops below v trip for more than 11 m s. the reset pin can be either connected to v cc (using the internal por circuit) or externally controlled (by the micro, asic, and so on). figure 16 shows the availability of the clock with respect to the external reset pulse. (1) porp = power-on reset pulse. fig 15. internal power-on reset timing stable external clock is available at a. fig 16. clock with respect to the external power-on reset 004aaa482 v cc t0 t1 t2 t3 t4 t5 v trip t porp porp (1) t porp reset external clock a 004aaa484
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 31 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 10. on-the-go (otg) controller 10.1 introduction otg is a supplement to the hi-speed usb (usb 2.0) speci?cation that augments existing usb peripherals by adding to these peripherals limited host capability to support other targeted usb peripherals. it is primarily targeted at portable devices because it addresses concerns related to such devices, such as a small connector and low power. non-portable devices (even standard hosts), nevertheless, can also bene?t from otg features. the ISP1362 otg controller is designed to perform all the tasks speci?ed in the otg supplement. it supports host negotiation protocol (hnp) and session request protocol (srp) for dual-role devices. the ISP1362 uses software implementation of hnp and srp for maximum ?exibility. a set of otg registers provides the control and status monitoring capabilities to support software hnp or srp. besides the normal usb transceiver, timers and analog components required by otg are also integrated on-chip. the analog components include: ? built-in 3.3 v-to-5 v charge pump ? voltage comparators ? pull-up or pull-down resistors on data lines ? charge or discharge resistors for v bus 10.2 dual-role device when port 1 of the ISP1362 is con?gured in otg mode, it can be used as an otg dual-role device. a dual-role device is a usb device that can function either as a host or as a peripheral. as a host, the ISP1362 can support all four types of transfers (control, bulk, isochronous and interrupt) at full-speed or low-speed. as a peripheral, the ISP1362 can support two control endpoints and up to 14 con?gurable endpoints, which can be programmed to any of the four transfer types. the default role of the ISP1362 is controlled by the id pin, which in turn is controlled by the type of plug connected to the mini-ab receptacle. if id = low (mini-a plug connected), it becomes an a-device, which is a host by default. if id = high (mini-b plug connected), it becomes a b-device, which is a peripheral by default. both the a-device and the b-device work on a session base. a session is de?ned as the period of time in which devices exchange data. a session starts when v bus is driven and ends when v bus is turned off. both the a-device and the b-device may start a session. during a session, the role of the host can be transferred back and forth between the a-device and the b-device any number of times by using hnp. if the a-device wants to start a session, it turns on v bus by enabling the charge pump. the b-device detects that v bus has risen above the b_sess_vld level and assumes the role of a peripheral, asserting its pull-up resistor on the dp line. the a-device detects the remote pull-up resistor and assumes the role of a host. then, the a-device can communicate with the b-device as long as it wishes. when the a-device ?nishes communicating with the b-device, the a-device turns-off v bus and both the devices ?nally go into the idle state. see figure 18 and figure 19 .
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 32 of 152 nxp semiconductors ISP1362 single-chip usb otg controller if the b-device wants to start a session, it must initiate srp by data line pulsing and v bus pulsing. when the a-device detects any of these srp events, it turns on its v bus (note that only the a-device is allowed to drive v bus ). the b-device assumes the role of a peripheral, and the a-device assumes the role of a host. the a-device detects that the b-device can support hnp by getting the otg descriptor from the b-device. the a-device will then enable the hnp hand-off by using setfeature (b_hnp_enable) and then go into the suspend state. the b-device signals claiming the host role by de-asserting its pull-up resistor. the a-device acknowledges by going into the peripheral state. the b-device then assumes the role of a host and communicates with the a-device as long as it wishes. when the b-device ?nishes communicating with the a-device, both the devices ?nally go into the idle state. see figure 18 and figure 19 . 10.3 session request protocol (srp) as a dual-role device, the ISP1362 can initiate and respond to srp. the b-device initiates srp by data line pulsing, followed by v bus pulsing. the a-device can detect either data line pulsing or v bus pulsing. 10.3.1 b-device initiating srp the ISP1362 can initiate srp by performing the following steps: 1. detect initial conditions [read id_reg, b_sess_end and se0_2ms (bits 0, 2 and 9) of the otgstatus register]. 2. start data line pulsing [set loc_conn (bit 4) of the otgcontrol register to logic 1]. 3. wait for 5 ms to 10 ms. 4. stop data line pulsing [set loc_conn (bit 4) of the otgcontrol register to logic 0]. 5. start v bus pulsing [set chrg_v bus (bit 1) of the otgcontrol register to logic 1]. 6. wait for 10 ms to 20 ms. 7. stop v bus pulsing [set chrg_v bus (bit 1) of the otgcontrol register to logic 0]. 8. discharge v bus for about 30 ms [by using dischrg_v bus (bit 2) of the otgcontrol register], optional. the b-device must complete both data line pulsing and v bus pulsing within 100 ms. 10.3.2 a-device responding to srp the a-device must be able to respond to one of the two srp events: data line pulsing or v bus pulsing. the ISP1362 allows you to choose which srp to support and has a mechanism to disable or enable the srp detection. this is useful for some applications under certain cases. for example, if the a-device battery is low, it may not want to turn on its v bus by detecting srp. in this case, it may choose to disable the srp detection function. when the data line srp detection is used, the ISP1362 can detect either the dp pulsing or the dm pulsing. this means a peripheral-only device can initiate data line pulsing srp through dp (full-speed) or dm (low-speed). a dual-role device will always initiate data line pulsing srp through dp because it is a full-speed device. ? steps to enable the srp detection by v bus pulsing: C set a_sel_srp (bit 9) of the otgcontrol register to logic 0.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 33 of 152 nxp semiconductors ISP1362 single-chip usb otg controller C set a_srp_det_en (bit 10) of the otgcontrol register to logic 1. ? steps to enable the srp detection by data line pulsing: C set a_sel_srp (bit 9) of the otgcontrol register to logic 1. C set a_srp_det_en (bit 10) of the otgcontrol register to logic 1. ? steps to disable the srp detection: C set a_srp_det_en (bit 10) of the otgcontrol register to logic 0. 10.4 host negotiation protocol (hnp) hnp is used to transfer control of the host role between the default host (a-device) and the default peripheral (b-device) during a session. when the a-device is ready to give up its role as a host, it will condition the b-device by setfeature (b_hnp_enable) and will go into suspend. if the b-device wants to use the bus at that time, it signals a disconnect to the a-device. then, the a-device will take the role of a peripheral and the b-device will take the role of a host. 10.4.1 sequence of hnp events the sequence of events for hnp as observed on the usb bus is illustrated in figure 17 . as can be seen in figure 17 : 1. the a-device completes using the bus and stops all bus activities (that is, suspends the bus). 2. the b-device detects that the bus is idle for more than 5 ms and begins hnp by turning off the pull-up on dp. this allows the bus to discharge to the se0 state. 3. the a-device detects se0 on the bus and recognizes this as a request from the b-device to become a host. the a-device responds by turning on its dp pull-up within 3 ms of ?rst detecting se0 on the bus. 4. after waiting for 30 m s to ensure that the dp line is not high because of the residual effect of the b-device pull-up, the b-device notices that the dp line is high and the dm line is low (that is, j state). this indicates that the a-device has recognized the fig 17. hnp sequence of events a-device 1 5 7 2 3 4 6 8 b-device 004aaa079 dp composite legend dp driven pull-up dominates pull-down dominates normal bus activity
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 34 of 152 nxp semiconductors ISP1362 single-chip usb otg controller hnp request from the b-device. at this point, the b-device becomes a host and asserts bus reset to start using the bus. the b-device must assert the bus reset (that is, se0) within 1 ms of the time that the a-device turns on its pull-up. 5. when the b-device completes using the bus, it stops all bus activities. optionally, the b-device may turn on its dp pull-up at this time. 6. the a-device detects lack of bus activities for more than 3 ms and turns off its dp pull-up. alternatively, if the a-device has no further need to communicate with the b-device, the a-device may turn off v bus and end the session. 7. the b-device turns on its pull-up. 8. after waiting 30 m s to ensure that the dp line is not high because of the residual effect of the a-device pull-up, the a-device notices that the dp line is high (and the dm line is low) indicating that the b-device is signaling a connect and is ready to respond as a peripheral. at this point, the a-device becomes a host and asserts the bus reset to start using the bus. 10.4.2 otg state diagrams figure 18 and figure 19 show the state diagrams for the dual-role a-device and the dual-role b-device, respectively. for a detailed explanation, refer to ref . 1 on-the-go supplement to the usb 2.0 speci? cation re v . 1.0a . the otg state machine is implemented with software. the inputs to the state machine come from four sources: hardware signals from the usb bus, software signals from the application program, internal variables with the state machines and timers: ? hardware inputs: include id, a_vbus_vld, a_sess_vld, b_sess_vld, b_sess_end, a_conn, b_conn, a_bus_suspend, b_bus_suspend, a_bus_resume, b_bus_resume, a_srp_det and b_se0_srp. all these inputs can be derived from the otginterrupt and otgstatus registers. ? software inputs: include a_bus_req, a_bus_drop and b_bus_req. ? internal variables: include a_set_b_hnp_en, b_hnp_enable and b_srp_done. ? timers: the hnp state machine uses four timers: a_wait_vrise_tmr, a_wait_bcon_tmr, a_aidl_bdis_tmr and b_ase0_brst, tmr. all timers are started on entry to and reset on exit from their associated states. the ISP1362 provides a programmable timer that can be used as any of these four timers.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 35 of 152 nxp semiconductors ISP1362 single-chip usb otg controller fig 18. dual-role a-device state diagram 004aaa077 a_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof/ a_vbus_err drv_vbus/ loc_conn/ loc_sof/ a_wait_vrise drv_vbus loc_conn/ loc_sof/ a_wait_bcon drv_vbus loc_conn/ loc_sof/ a_host drv_vbus loc_conn/ loc_sof a_wait_vfall drv_vbus/ loc_conn/ loc_sof/ a_peripheral drv_vbus loc_conn loc_sof/ a_suspend drv_vbus loc_conn/ loc_sof/ b_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof/ id start a_bus_drop/ & (a_bus_req | a_srp_det) id | a_bus_req | (a_sess_vld/ & b_conn/) a_bus_req | b_bus_resume a_bus_req/ | a_suspend_req a_vbus_vld/ a_vbus_vld/ a_vbus_vld/ b_conn a_vbus_vld/ id | a_bus_drop b_bus_suspend id | a_bus_drop | a_vbus_vld | a_wait_vrise_tmout id | a_bus_drop | a_wait_bcon_tmout id | b_conn/ | a_bus_drop b_conn/ & a_set_b_hnp_en b_conn/ & a_set_b_hnp_en/ id | a_bus_drop | a_aidl_bdis_tmout id | a_bus_drop
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 36 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 10.4.3 hnp implementation and otg state machine the otg state machine is the software behind all the otg functionality. it is implemented in the microprocessor system that is connected to the ISP1362. the ISP1362 provides all input status, the output control and timers to fully support the state machine transitions in figure 18 and figure 19 . these registers include: ? otgcontrol register: provides control to v bus driving, charging or discharging, data line pull-up or pull-down, srp detection, and so on. ? otgstatus register: provides status detection on v bus and data lines including id, v bus session valid, session end, overcurrent, bus status. ? otginterrupt register: provides interrupts for status change in otgstatus register bits and the otgtimer time-out event. ? otginterruptenable register: provides interrupt mask for otginterrupt register bits. ? otgtimer register: provides 0.01 ms base programmable timer for use in the otg state machine. the otg interrupt is generated on the int1 pin. it is shared with the host controller interrupt. to enable the otg interrupt, perform these steps: fig 19. dual-role b-device state diagram 004aaa078 b_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof/ b_srp_init pulse loc_conn pulse chrg_vbus loc_sof/ b_peripheral chrg_vbus/ loc_conn loc_sof/ b_host chrg_vbus/ loc_conn/ loc_sof b_wait_acon chrg_vbus/ loc_conn/ loc_sof/ a_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof/ id/ start b_bus_req/ | a_conn/ b_sess_vld id/ | b_sess_vld/ id/ | b_sess_vld/ id/ | b_sess_vld/ a_bus_resume | b_ase0_brst_tmout b_bus_req & b_hnp_en & a_bus_suspend a_conn b_bus_req & b_sess_end & b_se0_srp id/ | b_srp_done
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 37 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 1. set the polarity and level-triggering or edge-triggering mode of the hchardwarecon?guration register (bits 1 and 2, default is level-triggered, active low). 2. set the corresponding bits of the otginterruptenable register (bits 0 to 8, or some of them). 3. set bit otg_irq_interruptenable of the hc m pinterruptenable register (bit 9). 4. set bit interruptpinenable of the hchardwarecon?guration register (bit 0). when an interrupt is generated on int1, perform these steps in the isr to get the related otg status: 1. read the hc m pinterrupt register. if otg_irq (bit 9) is set, then step 2. 2. read the otginterrupt register. if any of the bits 0 to 4 are set, then step 3. 3. read the otgstatus register. the otg state machine routines are called when any of the inputs is changed. these inputs come from either otg registers (hardware) or application program (software). the outputs of the state machine include control signals to the otg register (for hardware) and states or error codes (for software). for more information, refer to nxp document ref . 3 isp136x embedded prog r amming guide (um10008) . 10.5 power saving in the idle state and during wake-up the ISP1362 can be put in power saving mode if the otg device is not in a session. this signi?cantly reduces the power consumption. in this mode, both the peripheral controller and the host controller are suspended. the pll and the oscillator are stopped, and the charge pump is in the suspend state. as an otg device, however, the ISP1362 is required to respond to the srp event. to support this, a lazyclock is kept running when the chip is in power saving mode. an srp event will wake-up the chip (that is, enable the pll and the oscillator). besides this, an id change or b_sess_vld detection can also wake-up the chip. these wake-up events can be enabled or disabled by programming the related bits of the otginterruptenable register before putting the chip in power saving mode. if the bit is set, then the corresponding event (status change) will wake-up the ISP1362. if the bit is cleared, then the corresponding event will not wake-up the ISP1362. you can also wake-up the ISP1362 from power saving mode by using software. this is accomplished by accessing any of the ISP1362 registers. accessing a register will assert cs of the ISP1362, and therefore, set it awake. 10.6 current capacity of the otg charge pump the ISP1362 uses a built-in charge pump to generate a 5 v v bus supply from a 3.3 v 0.3 v voltage source. the only external component required is a capacitor. the value of this capacitor depends on the amount of current drive required. t ab le 7 provides two recommended capacitor values and the corresponding current drive.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 38 of 152 nxp semiconductors ISP1362 single-chip usb otg controller the connection of the external capacitor (c ext ) is given in the partial schematics in figure 20 . remark: if the internal charge pump is not used, c ext is not required. 11. usb host controller (hc) 11.1 usb states of the host controller the usb host controller in the ISP1362 has four usb states: usboperational, usbreset, usbsuspend and usbresume. these states de?ne the responsibilities of the host controller related to the usb signaling and bus states. these signals are visible to the host controller driver (hcd), the software driver of the host controller, by using the control registers of the ISP1362 usb host controller. table 7. recommended capacitor values capacitance v cc current 27 nf 3.0 v to 3.6 v 8 ma 82 nf 3.0 v to 3.3 v 14 ma 3.3 v to 3.6 v 20 ma fig 20. external capacitors connection 004aaa154 ISP1362 v bus cp_cap2 cp_cap1 c ext otg v bus 4.7 m f 0.1 m f
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 39 of 152 nxp semiconductors ISP1362 single-chip usb otg controller the usb states are re?ected in the hostcontrollerfunctionalstate (hcfs) ?eld of the hccontrol register. the hcd is allowed to perform only usb state transitions shown in figure 21 . 11.2 usb traf?c generation usb traf?c can be generated only when the ISP1362 usb host controller is under the usboperational state. therefore, the hcd must set the ISP1362 usb hc in the usboperational state. this is done by setting the hcfs ?eld of the hccontrol register before generating usb traf?c. a brief ?ow of the usb traf?c generation is described as follows: 1. reset the ISP1362 by using the reset pin or the software reset. 2. set the physical size of the atl, interrupt, istl0 and istl1 buffers. 3. write 32-bit hexadecimal value 8000 00fdh to the hcinterruptenable register. this will enable all the interrupt events in the register to trigger the hardware interrupt (see section 14.1.5 ). 4. write 16-bit hexadecimal value 002dh to the hchardwarecon?guration register. this will set up the host controller to level triggered and active high interrupt setting (see section 14.4.1 ). 5. write 0500 0b02h to hcrhdescriptora and 0000 0000h to hcrhdescriptorb. 6. write 16-bit hexadecimal value 0680h to the hccontrol register to set the ISP1362 into operation mode (see section 14.1.2 ). 7. read the hcrhportstatus[1] and hcrhportstatus[2] registers. these registers contain 32-bit hexadecimal value 0001 0100h (see section 14.3.4 ). 8. connect a full-speed device to one of the downstream ports or use a 1.5 k w resistor to pull up the dp line (to emulate a full-speed device). fig 21. usb host controller states of the ISP1362 mgt947 usboperational usbsuspend usbresume usbresume write or remote wake-up usbreset usboperational write usboperational write usbsuspend write usbreset write usbreset write usbreset write hardware or software reset
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 40 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 9. read the hcrhportstatus[1] and hcrhportstatus[2] registers. the hexadecimal value of one of the registers must change to 0001 0101h, indicating that a device connection has been detected. 10. write 32-bit hexadecimal value 0000 0102h into either hcrhportstatus[1] or hcrhportstatus[2], depending on the port that is being used. 11. read the hcrhportstatus[1] and hcrhportstatus[2] registers. depending on which port the usb device is connected to, one of the registers should contain hexadecimal value 0001 0103h. sof packets should be visible on dp and dm now. the hcfmnumber register contains the current frame number, which is updated every milliseconds. remark: the generation of sof is completely performed by the ISP1362 hardware. in this state of operation, if a ptd is written to the buffer memory, it will be processed and sent. 11.3 usb ports the ISP1362 has two usb ports: port 1 and port 2. port 1 can be con?gured as a downstream port (host), an upstream port (device) or a dual-role port (otg). port 2 is a ?xed downstream port. the function of port 1 depends on two input pins of the ISP1362, namely id and o tgmode. in otg mode, port 2 operates as an internal host. it is not advisable to expose host port 2 to external devices because it will not respond to the srp and hnp protocols. besides, the current capability of v bus may be different from the otg ports. the usb compliance checklist states that one and only one usb mini-ab receptacle is allowed on an otg device. 11.4 philips transfer descriptor (ptd) ptd provides a communication channel between the hcd and the ISP1362 usb host controller. a ptd consists of a ptd header and a payload data. the size of the ptd header is 8 bytes, and it contains information required for data transfer, such as data packet size, transfer status and transfer token types. payload data to be transferred within a particular frame must have a ptd as the header (see figure 22 ). the ISP1362 has three types of ptds: control and bulk transfer (aperiodic transfer) ptd, interrupt transfer ptd and isochronous (iso) transfer ptd. in the control and bulk transfer ptd and the interrupt transfer ptd, the buffer area is separated into equal sized blocks that are determined by hcatlblksize and hcintlblksize. for example, if the block size is de?ned as 32 bytes, the ?rst ptd table 8. port 1 function o tgmode id function of port 1 lxotg h l host h h peripheral
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 41 of 152 nxp semiconductors ISP1362 single-chip usb otg controller structure in the memory buffer will have an offset of 0 bytes and the second ptd structure will have an offset of 40 bytes [sum of the block size (32 bytes) and the ptd header size (8 bytes)]. because of the ?xed block size of the ISP1362 host controller, however, even a ptd with 4 bytes of payload will occupy all the 40 bytes in a block. in the isochronous ptd, the host controller uses a more ?exible method to calculate the ptd offset because each ptd can have a different payload size. the actual amount of space for the payload, however, must be a multiple of double word. therefore, a 10 bytes payload must have a reserved data size of 12 bytes. take for example there are four ptds in the istl0 buffer area with payload sizes of 200 bytes, 10 bytes, 1023 bytes and 30 bytes. then, the offset of each of these ptds will be as follows: ptd1 (200 bytes) offset = 0 ptd2 (10 bytes) offset = (200 + 8) = 208 ptd3 (1023 bytes) offset = (200 + 8) + (12 + 8) = 228 ptd4 (30 bytes) offset = (200 + 8) + (12 + 8) + (1024 + 8) = 1260 the ptd data stored in the host controller buffer memory will not be processed, unless the respective control bits (atl_active, intl_active, istl0_bufferfull or istl1_bufferfull) in hcbufferstatus are set. the ptd data in the atl or interrupt buffer memory can be disabled by setting the respective skip bit in hcatlptdskipmap and hcintlptdskipmap. to skip a particular ptd in the atl or interrupt buffer, the hcd may set the corresponding bit of the skipmap register. for example, setting the hcatlptdskipmap register to 0011h will cause the host controller to skip the ?rst and the ?fth ptds in the atl buffer memory. certain ?elds in the ptd header are used by the host controller to inform the hcd about the status of the transfer. these ?elds are indicated by the status update by hc column. these ?elds are updated after every transaction to re?ect the current status of the ptd. fig 22. ptd data stored in the buffer memory 004aaa121 ptd header buffer memory payload data ptd data #1 ptd header payload data payload data ptd header ptd data #2 ptd data #n top bottom
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 42 of 152 nxp semiconductors ISP1362 single-chip usb otg controller [1] all reserved bits should be set to logic 0. [1] all reserved bits should be set to logic 0. table 9. generic ptd structure: bit allocation bit [1] 7 6 5 4 3 2 1 0 byte 0 actualbytes[7:0] byte 1 completioncode[3:0] active toggle actualbytes[9:8] byte 2 maxpktsize[7:0] byte 3 endpointnumber[3:0] b3[3] speed maxpktsize[9:8] byte 4 totalbytes[7:0] byte 5 b5[7] b5[6] reserved dirtoken[1:0] totalbytes[9:8] byte 6 reserved functionaddress[6:0] byte 7 b7[7:0] table 10. special ?elds for atl, interrupt and iso bit [1] atl interrupt istl (iso) b3[3] reserved reserved last b5[6] ping-pong reserved reserved b5[7] paired reserved reserved b7[7:0] reserved pollingrate[7:5]; startingframe[4:0] startingframe
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 43 of 152 nxp semiconductors ISP1362 single-chip usb otg controller table 11. generic ptd structure: bit description name status update by hc description actualbytes[9:0] yes this ?eld contains the number of bytes that were transferred for this ptd. completioncode[3:0] yes 0000 noerror general transfer descriptor (td) or isochronous data packet processing completed with no detected errors. 0001 crc the last data packet from the endpoint contained a cyclic redundancy check (crc) error. 0010 bitstuf?ng the last data packet from the endpoint contained a bit stuf?ng violation. 0011 datatogglemismatch the last packet from the endpoint had data toggle packet id (pid) that did not match the expected value. 0100 stall td was moved to the done queue because the endpoint returned a stall pid. 0101 devicenot responding the device did not respond to the token (in) or did not provide a handshake (out). 0110 pidcheckfailure the check bits on pid from the endpoint failed on data pid (in) or handshake (out). 0111 unexpectedpid the received pid was not valid when encountered, or the pid value is not de?ned. 1000 dataoverrun the amount of data returned by the endpoint exceeded either the size of the maximum data packet allowed from the endpoint (found in the maxpacketsize ?eld of ed) or the remaining buffer size. 1001 dataunderrun the endpoint returned is less than maxpacketsize and that amount was not suf?cient to ?ll the speci?ed buffer. 1010 - reserved 1011 - reserved 1100 bufferoverrun during an in, the host controller received data from the endpoint faster than it could be written to the system memory. 1101 bufferunderrun during an out, the host controller could not retrieve data from the system memory fast enough to keep up with the usb data rate. active yes set to logic 1 by ?rmware to enable the execution of transactions by the host controller. when the transaction associated with this descriptor is completed, the host controller sets this bit to logic 0, indicating that a transaction for this element should not be executed when it is next encountered in the schedule. toggle yes this bit is used to generate or compare the data pid value (data0 or data1) for in and out transactions. it is updated after each successful transmission or reception of a data packet. maxpktsize[9:0] no this indicates the maximum number of bytes that can be sent to or received from the endpoint in a single data packet. endpointnumber[3:0] no this is the usb address of the endpoint within the function.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 44 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 11.5 features of the control and bulk transfer (aperiodic transfer) ? a paired ptd is a special feature that provides high performance single endpoint bulk transfer and handles set-up enumeration sequence within 1 ms. a paired ptd consists of two ptds serving the same endpoint of a device that are set active and placed in the atl ram at the same time. a paired ptd is specially designed for high performance of a single endpoint. they are identi?ed by hardware by using the paired bit in the ptd. ? possible to send up to a maximum of 18 usb bulk packets in 1 ms frame (1.152 mb/s) by using the paired ptd feature. ? provides the status of every transfer endpoints (ptd) by monitoring the hcatlptddonemap of the ISP1362. this register provides information on which ptd transfers are complete. ? sets the irq after the user-speci?ed number of transfers is done. ? skips any ptd that is wasting bandwidth by using hcatlptdskipmap. b3[3] last (ptd) no this indicates that it is the last ptd of a list. logic 1 means that this ptd is the last ptd. the last ptd is used only for iso. this bit is not used in the interrupt and atl transfers. the last ptd is indicated by the hcintllastptd and hcatllastptd registers. speed (low) no this bit indicates the speed of the endpoint. 0 full-speed 1 low-speed totalbytes[9:0] no this speci?es the total number of bytes to be transferred with this data structure. this can be greater than maxpacketsize. b5[6] ping-pong no 0 this is the ping buffer of the paired buffer. paired must be logic 1. 1 this is the pong buffer of the paired buffer. paired must be logic 1. b5[7] paired no if this bit is set to logic 1, two ptds of the same endpoint and address can be made active at the same time. this bit is used with the ping-pong bit. the ?rst paired ptd always starts with ping = 0. the pong ptd payload can be sent out only if the ping ptd payload is sent out. you can also monitor ram_buffer _status to see which ptd is currently active on the usb line. dirtoken[1:0] no 00 set up 01 out 10 in 11 reserved functionaddress[6:0] no this ?eld contains the usb address of the function containing the endpoint that this ptd refers to. b7[7:5] pollingrate b7[4:0] startingframe (interrupt only) no these two ?elds together select a start frame number (5 bits) and polls the interrupt device at a rate speci?ed by pollingrate (3 bits); see section 11.6 . b7[7:0] startingframe (iso only) no the host controller compares this byte with the current frame number (can be accessed from the hcfmnumber register). the ptd will be processed and sent out only if the starting frame number equals to the current frame number. table 11. generic ptd structure: bit description continued name status update by hc description
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 45 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 11.5.1 sending a usb device request (get descriptor) this section provides an example on how a usb transfer descriptor get descriptor (commonly used in device enumeration) is used to illustrate the ISP1362 ptd application. to perform this example, make sure the ISP1362 is in the operational state, and then connect a usb device (for example, a usb mouse) to a port. remark: for details on the usb device request, refer to chapter 9 of ref . 2 univ ersal ser ial bus speci? cation re v . 2.0 . 11.5.1.1 step 1 set the hcatlblksize, hcatlptdskipmap and hcatllastptd registers to 0008h, fffeh and 0001h, respectively. 11.5.1.2 step 2 a ptd is then constructed based on the information given in the following sample code. this sample code places information into the correct bit location within the 8 bytes of the ptd structure. actualbytes (10 bits) = 0x00 completioncode (4 bits) = 0x0f active (1 bit) = 1 toggle (1 bit) = 0 maxpacketsize (10 bits) = 8 endpointnumber (4 bits) = 0 speed (1 bit) = 0 (full-speed; use 1 for low-speed) dirtoken (2 bits) = 0 (setup token) totalbytes (10 bits) = 8 completedptd 0xf800, 0x0008, 0x0008, 0x0000 11.5.1.3 step 3 this array is then appended with an 8 bytes payload that speci?es the type of request the host controller wants to send. for example, for get descriptor, the payload is 0680h, 0100h, 0000h, 0012h. 11.5.1.4 step 4 the 16 bytes of data is now a complete ptd with an accompanying payload. this array is then copied into the atl buffer area. t ab le 12 shows the atl buffer area. 11.5.1.5 step 5 after copying data into the atl buffer, the host controller must be noti?ed that the atl buffer is now full and ready to be processed. the atl_active bit of the hcbufferstatus register must be set to logic 1 to inform the host controller that the data in the atl buffer is now ready for processing. once the atl_active bit of the hcbufferstatus register is set, the usb packet is sent out. the active bit in the ptd is cleared once the ptd is sent. depending on the outcome of the usb transfer, the 4-bit completion code is updated. table 12. atl buffer area offset 0 1 2 3 4 5 6 7 data f800h 0008h 0008h 0000h 0680h 0100h 0000h 0012h
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 46 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 11.6 features of the interrupt transfer ? an interrupt transaction is periodically sent out, according to the interrupt polling rate as de?ned in the ptd. ? an interrupt transaction causes an interrupt to the cpu only if the transaction is ack-ed or has error conditions, such as stall or no respond. an ack condition occurs if data is received on the in token or data is sent out on the out token. ? an interrupt is activated only once every ms as long as there is ack for different interrupt transactions in the interrupt transfer buffer. ? each interrupt transfer (ptd) placed in the intl buffer can automatically hold or send data for more than 1 ms. this can be done using the parameters in the ptd. 11.7 features of the isochronous (iso) transfer ? supports multi-buffering by using the istl0 or istl1 toggling mechanism. ? the cpu can decide (in ms) how fast it can serve the ISP1362. this gives the cpu the ?exibility to decide how much time it takes to read and ?ll in the iso data. ? the istl buffer can be updated on-the-?y by using the direct addressing memory architecture. 11.8 overcurrent protection circuit the ISP1362 has a built-in overcurrent protection circuitry. you can enable or disable this feature by setting or resetting analogocenable (bit 10) of the hchardwarecon?guration register. if this feature is disabled, it is assumed that there is an external overcurrent protection circuitry. 11.8.1 using internal overcurrent detection circuit an application using the internal overcurrent detection circuit and internal 15 k w pull-down resistors is shown in figure 23 , where dmn denotes either otg_dm1 or h_dm2, while dpn denotes either otg_dp1 or h_dp2. in this example, the hcd must set both analogocenable and connectpulldown_ds1 (bit 10 and bit 12 of the hchardwarecon?guration register, respectively) to logic 1. when h_ocn detects an overcurrent status on a downstream port, h_pswn will output high to turn off the 5 v power supply to downstream port v bus . when there is no such detection, h_pswn will output low to turn on the 5 v power supply to downstream port v bus . table 13. interrupt polling n bits [7:5] startingframe n[4:0] interrupt polling interval (2 n ) in ms 0 frame 0 to 31 1 1 frame 0 to 31 2 2 frame 0 to 31 4 3 frame 0 to 31 8 4 frame 0 to 31 16 5 frame 0 to 31 32 6 frame 0 to 31 64 7 frame 0 to 31 128
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 47 of 152 nxp semiconductors ISP1362 single-chip usb otg controller in general applications, you can use a p-channel mosfet as the power switch for v bus . connect the 5 v power supply to the source pole of the p-channel mosfet, v bus to the drain pole, and h_pswn to the gate pole. this voltage drop ( d v) across the drain and source poles can be called the overcurrent trip voltage. for the internal overcurrent detection circuit, a voltage comparator has been designed-in, with a nominal voltage threshold of 75 mv. therefore, when the overcurrent trip voltage ( d v) exceeds the voltage threshold, h_pswn will output a high level to turn off the p-channel mosfet. if the p-channel mosfet has r dson of 150 m w , the overcurrent threshold will be 500 ma. the selection of a p-channel mosfet with a different r dson will result in a different overcurrent threshold. 11.8.2 using external overcurrent detection circuit when v cc (pin 56) is connected to the 3.3 v power supply instead of the 5 v power supply, the internal overcurrent detection circuit cannot be used. an external overcurrent detection circuit must be used instead. nevertheless, regardless of the v cc connection, an external overcurrent detection circuit can be used from time to time. to use an external overcurrent detection circuit, set analogocenable, bit 10 of register hchardwarecon?guration, to logic 0. by default, this bit is set to logic 0 after reset. therefore, the hcd does not need to clear this bit. figure 24 shows how to use an external overcurrent detection circuit. (1) 100 m f for the host port, or 4.7 m f for the otg port. fig 23. using internal overcurrent detection circuit 004aaa148 h_ocn h_pswn v bus dm dp gnd chassis chassis 1 2 3 4 5 6 c41 (1) dgnd psu_5v v dd(5v) c17 0.1 m f dgnd dgnd fb2 p_channel mosfet c18 0.1 m f r31 10 k w source drain gate
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 48 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 11.8.3 overcurrent detection circuit using internal charge pump in otg mode when port 1 is operating in otg mode, you may choose to use the internal charge pump to provide 5 v v bus , or supply v bus from an external source. in this mode, the overcurrent condition is detected by a drop in v bus that will be sensed by the built-in comparator. the overcurrent condition causes a change in the a_vbus_vld bit of the otgstatus register. the software must clear the drv_vbus bit in the otgcontrol register when it detects the a_vbus_vld bit turning to logic 0. (1) 100 m f for the host port, or 4.7 m f for the otg port. fig 24. using external overcurrent detection circuit 004aaa149 h_ocn v bus oc en v in v out oc detection psu_5v dm dp gnd chassis chassis 1 2 3 4 5 6 c41 (1) dgnd c17 0.1 m f dgnd dgnd fb2 h_pswn (1) 100 m f for the host port, or 4.7 m f for the otg port. fig 25. using internal charge pump 004aaa150 v bus dm dp gnd chassis chassis 1 2 3 4 5 6 c41 (1) dgnd c17 0.1 m f dgnd dgnd fb2 v bus n.c. h_ocn h_pswn
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 49 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 11.8.4 overcurrent detection circuit using external 5 v power source in otg mode in otg mode using external 5 v power source for v bus , the circuit and the operation are the same as that for non-otg mode (see section 11.8.1 and section 11.8.2 ). 11.9 ISP1362 host controller power management in the ISP1362, the host controller and the peripheral controller are suspended and woken up individually. the h_suspend/ h_w akeup and d_suspend/ d_w akeup pins must be pulled-up by a large resistor (100 k w ). in the suspend state, these pins are high. to wake up the host controller, these pins must be pulled low. the ISP1362 can partially be suspended (only the host controller or only the peripheral controller). in the partially suspended state, the clock circuit and pll continue to work. to save power, both the host controller and the peripheral controller must be set to suspend mode. the host controller can be suspended by writing 06c0h to the hccontrol register. the host controller can be set awake by one of the following ways: ? a low pulse on the h_suspend/ h_w akeup pin, minimum length of pulse is 25 ns. ? a low pulse on the chip select ( cs) pin, minimum length of pulse is 25 ns. ? a resume signal by usb devices connected to the downstream port. on waking up from the suspend state, the clock to the host controller will sustain for 5 ms. within this 5 ms, the hcd must set the host controller to operational mode by writing 0680h to the hccontrol register. if the hccontrol register remains in the suspend state (06c0h) after waking up the host controller, the host controller will return to the suspend state after 5 ms. 12. usb peripheral controller the design of the peripheral controller in the ISP1362 is compatible with the nxp isp1181b usb full-speed interface device ic. the functionality of the peripheral controller in the ISP1362 is similar to the isp1181b in 16-bit bus mode. in addition, the command and register sets are also the same. in general, the peripheral controller in the ISP1362 provides 16 endpoints for the usb device implementation. each endpoint can be allocated ram space in the on-chip ping pong buffer ram. remark: the ping pong buffer ram for the peripheral controller is independent of the buffer ram for the host controller. when the buffer ram is full, the peripheral controller transfers the data in the buffer ram to the usb bus. when the buffer ram is empty, an interrupt is generated to notify the microprocessor to feed in data. the transfer of data between a microprocessor and the peripheral controller can be done in either programmed i/o (pio) mode or in direct memory access (dma) mode.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 50 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 12.1 peripheral controller data transfer operation the following sessions explain how the peripheral controller in the ISP1362 handles an in data transfer and an out data transfer. an in data transfer means transfer from the ISP1362 to an external usb host (through the upstream port), and an out transfer means transfer from an external usb host to the ISP1362. in device mode, the ISP1362 acts as a usb device. 12.1.1 in data transfer 1. the arrival of the in token is detected by the serial interface engine (sie) by decoding the packet identi?er (pid). 2. the sie also checks the device number and the endpoint number to verify whether they are okay. 3. if the endpoint is enabled, the sie checks the contents of the dcendpointstatus register (esr). if the endpoint is full, the contents of the buffer memory are sent during the data phase else an nak handshake is sent. 4. after the data phase, the sie expects a handshake (ack) from the host (except for iso endpoints). 5. on receiving the handshake (ack), the sie updates the contents of the dcendpointstatus and dcinterrupt registers, which in turn generates an interrupt to the microprocessor. for iso endpoints, the dcinterrupt register is updated as soon as data is sent because there is no handshake phase. 6. on receiving an interrupt, the microprocessor reads the dcinterrupt register. it knows which endpoint has generated the interrupt and reads the contents of the corresponding esr. if the buffer is empty, it ?lls up the buffer so that data can be sent by the sie at the next in token phase. 12.1.2 out data transfer 1. the arrival of the out token is detected by the sie by decoding the pid. 2. the sie checks the device and endpoint numbers to verify whether they are okay. 3. if the endpoint is enabled, the sie checks the contents of the esr. if the endpoint is empty, the data from usb is stored in the buffer memory during the data phase else a nak handshake is sent. 4. after the data phase, the sie sends a handshake (ack) to the host (except for iso endpoints). 5. the sie updates the contents of the dcendpointstatus register and the dcinterrupt register, which in turn generates an interrupt to the microprocessor. for iso endpoints, the dcinterrupt register is updated as soon as data is received because there is no handshake phase. 6. on receiving an interrupt, the microprocessor reads the dcinterrupt register. it knows which endpoint has generated the interrupt and reads the content of the corresponding esr. if the buffer is full, it empties the buffer so that data can be received by the sie at the next out token phase.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 51 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 12.2 device dma transfer 12.2.1 dma for an in endpoint (internal peripheral controller to the external usb host) when the internal dma handler is enabled and at least one buffer (ping or pong) is free, the dreq2 line is asserted. the external dma controller then starts negotiating for control of the bus. as soon as it has access, it asserts the d a ck2 line and starts writing data. the burst length is programmable. when the number of bytes equal to the burst length has been written, the dreq2 line is de-asserted. as a result, the dma controller de-asserts the d a ck2 line and releases the bus. at that moment, the whole cycle restarts for the next burst. when the buffer is full, the dreq2 line is de-asserted and the buffer is validated (which means that it is sent to the host at the next in token). when the dma transfer is terminated, the buffer is also validated (even if it is not full). a dma transfer is terminated when any of the following conditions is met: ? the dma count is complete. ? dmaen = 0. remark: if the onedma bit in the hchardwarecon?guration register is set to logic 1, peripheral controller dma controller handshake signals dreq2 and d a ck2 are routed to dreq1 and d a ck1. 12.2.2 dma for out endpoint (external usb host to internal peripheral controller) when the internal dma handler is enabled and at least one buffer is full, the dreq2 line is asserted. the external dma controller then starts negotiating for control of the bus, and as soon as it has access, it asserts the d a ck2 line and starts reading data. the burst length is programmable. when the number of bytes equal to the burst length has been read, the dreq2 line is de-asserted. as a result, the dma controller de-asserts the d a ck2 line and releases the bus. at that moment, the whole cycle restarts for the next burst. when all the data is read, the dreq2 line is de-asserted and the buffer is cleared (this means that it can be overwritten when a new packet arrives). a dma transfer is terminated when any of the following conditions are met: ? the dma count is complete. ? dmaen = 0. remark: if the onedma bit in the hchardwarecon?guration register is set to logic 1, peripheral controller dma controller handshake signals dreq2 and d a ck2 are routed to dreq1 and d a ck1. when the dma transfer is terminated, the buffer is also cleared (even if data is not completely read) and the dma handler is automatically disabled. for the next dma transfer, the dma controller as well as the dma handler must be re-enabled.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 52 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 12.3 endpoint description 12.3.1 endpoints with programmable buffer memory size each usb device is logically composed of several independent endpoints. an endpoint acts as a terminus of a communication ?ow between the usb host and the usb device. at design time, each endpoint is assigned a unique number (endpoint identi?er, see t ab le 14 ). the combination of the device address (given by the host during enumeration), the endpoint number, and the transfer direction allows each endpoint to be uniquely referenced. the peripheral controller has 16 endpoints: endpoint 0 (control in and out) and 14 con?gurable endpoints, which can individually be de?ned as interrupt, bulk or isochronous: in or out. each enabled endpoint has an associated buffer memory, which can be accessed either by using programmed i/o interface mode or by using dma mode. 12.3.2 endpoint access t ab le 14 lists the endpoint access modes and programmability. all endpoints support i/o mode access. endpoints 1 to 14 also support dma mode access. the peripheral controller buffer memory dma access is selected and enabled using bits epidx[3:0] and dmaen of the dcdmacon?guration register. a detailed description of the peripheral controller dma operation is given in section 12.4 . [1] the total amount of the buffer memory storage allocated to enabled endpoints must not exceed 2462 bytes. [2] in: input for the usb host (peripheral controller transmits); out: output from the usb host (peripheral controller receives) . [3] the data ?ow direction is determined by the epdir bit of the dcendpointcon?guration register. 12.3.3 endpoint buffer memory size the size of the buffer memory determines the maximum packet size that the hardware can support for a given endpoint. only enabled endpoints are allocated space in the shared buffer memory storage, disabled endpoints have zero bytes. t ab le 15 lists the programmable buffer memory sizes. the following bits of the dcendpointcon?guration register (ecr) affect the buffer memory allocation: ? endpoint enable bit (fifoen) ? size bits of an enabled endpoint (ffosz[3:0]) ? isochronous bit of an enabled endpoint (ffoiso) remark: a register change that affects the allocation of the shared buffer memory storage among endpoints must not be made while valid data is present in any buffer memory of the enabled endpoints. such changes renders all buffer memory contents unde?ned. table 14. endpoint access and programmability endpoint identi?er buffer memory size (bytes) [1] double buffering pio mode access dma mode access endpoint type 0 64 (?xed) no yes no control out [2] [3] 0 64 (?xed) no yes no control in [2] [3] 1 to 14 programmable supported supported supported programmable
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 53 of 152 nxp semiconductors ISP1362 single-chip usb otg controller each programmable buffer memory can independently be con?gured by using its ecr, but the total physical size of all enabled endpoints (in plus out) must not exceed 2462 bytes. t ab le 16 shows an example of a con?guration ?tting in the maximum available space of 2462 bytes. the total number of logical bytes in the example is 1311. the physical storage capacity used for double buffering is managed by the device hardware and is transparent to the user. 12.3.4 endpoint initialization in response to standard usb request set interface, ?rmware must program all the 16 ecrs of the peripheral controller in sequence (see t ab le 14 ), whether endpoints are enabled or not. the hardware then automatically allocates the buffer memory storage space. if all endpoints have successfully been con?gured, ?rmware must return an empty packet to the control in endpoint to acknowledge success to the host. if there are errors in the endpoint con?guration, ?rmware must stall the control in endpoint. table 15. programmable buffer memory size ffosz[3:0] non-isochronous isochronous 0000 8 bytes 16 bytes 0001 16 bytes 32 bytes 0010 32 bytes 48 bytes 0011 64 bytes 64 bytes 0100 reserved 96 bytes 0101 reserved 128 bytes 0110 reserved 160 bytes 0111 reserved 192 bytes 1000 reserved 256 bytes 1001 reserved 320 bytes 1010 reserved 384 bytes 1011 reserved 512 bytes 1100 reserved 640 bytes 1101 reserved 768 bytes 1110 reserved 896 bytes 1111 reserved 1023 bytes table 16. memory con?guration example physical size (bytes) logical size (bytes) endpoint description 64 64 control in (64 bytes ?xed) 64 64 control out (64 bytes ?xed) 2046 1023 double-buffered 1023 bytes isochronous endpoint 16 16 16 bytes interrupt out 16 16 16 bytes interrupt in 128 64 double-buffered 64 bytes bulk out 128 64 double-buffered 64 bytes bulk in
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 54 of 152 nxp semiconductors ISP1362 single-chip usb otg controller when reset by hardware or by the usb bus occurs, the peripheral controller disables all endpoints and clears all ecrs, except the control endpoint that is ?xed and always enabled. an endpoint initialization can be done at any time. it is, however, valid only after enumeration. 12.3.5 endpoint i/o mode access when an endpoint event occurs (a packet is transmitted or received), the associated endpoint interrupt bits (epn) of the dcinterrupt register (ir) are set by the sie. the ?rmware then responds to the interrupt and selects the endpoint for processing. the endpoint interrupt bit is cleared by reading the dcendpointstatus register (esr). the esr also contains information on the status of the endpoint buffer. for an out (= receive) endpoint, the packet length and packet data can be read from the peripheral controller by using the read buffer command. when the whole packet has been read, ?rmware sends a clear buffer command to enable the reception of new packets. for an in (= transmit) endpoint, the packet length and data to be sent can be written to the peripheral controller by using the write buffer command. when the whole packet has been written to the buffer, ?rmware sends a validate buffer command to enable data transmission to the host. 12.3.6 special actions on control endpoints control endpoints require special ?rmware actions. the arrival of a set-up packet ?ushes the in buffer and disables the validate buffer and clear buffer commands for the control in and out endpoints. the microprocessor must re-enable these commands by sending an acknowledge set-up command to both the control endpoints. this ensures that the last set-up packet stays in the buffer and that no packets can be sent back to the host, until the microprocessor has explicitly acknowledged that it has received the set-up packet. 12.4 peripheral controller dma transfer direct memory access (dma) is a method to transfer data from one location to another in a computer system, without the intervention of the cpu. many different implementations of dma exist. the peripheral controller supports 8237 compatible mode. 8237 compatible mode: based on the dma subsystem of the ibm personal computers (pc, at and all its successors and clones). this architecture uses the intel 8237 dma controller and has separate address spaces for memory and i/o. the following features are supported: ? single-cycle or burst transfers (up to 16 bytes per cycle) ? programmable transfer direction (read or write) ? multiple end-of-transfer (eot) sources: internal conditions, short or empty packet ? programmable signal levels on pins dreq2 and d a ck2
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 55 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 12.4.1 selecting an endpoint for the dma transfer the target endpoint for dma access is selected using bits epdix[3:0] of the dcdmacon?guration register, as shown in t ab le 17 . the transfer direction (read or write) is automatically set by the epdir bit in the associated ecr, to match the selected endpoint type (out endpoint: read; in endpoint: write). automatically asserting input d a ck2 selects the endpoint speci?ed in the dcdmacon?guration register, regardless of the current endpoint used for i/o mode access. 12.4.2 8237 compatible mode this mode is selected by clearing the dakoly bit of the dchardwarecon?guration register (see t ab le 115 ). the pin functions for this mode are shown in t ab le 18 . the dma subsystem of an ibm-compatible pc is based on the intel 8237 dma controller. it operates as a ?y-by dma controller. data is not stored in the dma controller, but it is transferred between an i/o port and a memory address. a typical example of the peripheral controller in 8237 compatible dma mode is given in figure 26 . table 17. endpoint selection for the dma transfer endpoint identi?er epidx[3:0] transfer direction epdir = 0 epdir = 1 1 0010 out: read in: write 2 0011 out: read in: write 3 0100 out: read in: write 4 0101 out: read in: write 5 0110 out: read in: write 6 0111 out: read in: write 7 1000 out: read in: write 8 1001 out: read in: write 9 1010 out: read in: write 10 1011 out: read in: write 11 1100 out: read in: write 12 1101 out: read in: write 13 1110 out: read in: write 14 1111 out: read in: write table 18. 8237 compatible mode: pin functions symbol description i/o function dreq2 dma request of peripheral controller o peripheral controller requests a dma transfer d a ck2 dma acknowledge of peripheral controller i dma controller con?rms the transfer eot end of transfer i dma controller terminates the transfer rd read strobe i instructs the peripheral controller to put data on the bus wr write strobe i instructs the peripheral controller to get data from the bus
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 56 of 152 nxp semiconductors ISP1362 single-chip usb otg controller the 8237 has two control signals for each dma channel: dreq (dma request) and d a ck (dma acknowledge). general control signals are hrq (hold request) and hlda (hold acknowledge). the bus operation is controlled by memr (memory read), memw (memory write), ior (i/o read) and io w (i/o write). the following example shows the steps that occur in a typical dma transfer: 1. the peripheral controller receives a data packet in one of its endpoint buffer memory. the packet must be transferred to memory address 1234h. 2. the peripheral controller asserts the dreq2 signal requesting the 8237 for a dma transfer. 3. the 8237 requests the cpu to release the bus, by asserting the hrq signal. 4. after completing the current instruction cycle, the cpu places bus control signals ( memr, memw, ior and io w) and address lines in 3-state and asserts hlda to inform the 8237 that it has control of the bus. 5. the 8237 now sets its address lines to 1234h and activates the memw and ior control signals. 6. the 8237 asserts d a ck to inform the peripheral controller that it will start a dma transfer. 7. the peripheral controller now places the word to be transferred on the data bus lines because its rd signal was asserted by the 8237. 8. the 8237 waits one dma clock period and then de-asserts memw and ior. this latches and stores the word at the desired memory location. it also informs the peripheral controller that the data on the bus lines has been transferred. 9. the peripheral controller de-asserts the dreq2 signal to indicate to the 8237 that dma is no longer needed. in single cycle mode , this is done after each byte or word; in burst mode , following the last transferred byte or word of the dma cycle. 10. the 8237 de-asserts the d a ck output, indicating that the peripheral controller must stop placing data on the bus. 11. the 8237 places bus control signals ( memr, memw, ior and io w) and address lines in 3-state and de-asserts the hrq signal, informing the cpu that it has released the bus. fig 26. peripheral controller in 8327 compatible dma mode d[15:0] cpu 004aaa047 ram ISP1362 dma controller 8237 dreq2 dack2 dreq hrq hlda hrq hlda dack ior iow memr memw rd wr
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 57 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 12. the cpu acknowledges control of the bus by de-asserting hlda. after activating the bus control lines ( memr, memw, ior and io w) and address lines, the cpu resumes the execution of instructions. for a typical bulk transfer, the preceding process is repeated 32 times, once for each word. after each word, the dcaddress register in the dma controller is incremented by two and the byte counter is decremented by two. when using the 16-bit dma, the number of transfers is 32, and address incrementing and byte counter decrementing is done by two for each word. 12.4.3 end-of-transfer conditions 12.4.3.1 bulk endpoints a dma transfer to or from a bulk endpoint can be terminated by any of the following conditions (bit names refer to the dcdmacon?guration register, see t ab le 119 and t ab le 120 ): ? the dma transfer completes as programmed in the dcdmacounter register (cntren = 1). ? a short packet is received on an enabled out endpoint (shortp = 1). ? dma operation is disabled by clearing the dmaen bit. dcdmacounter register an eot from the dcdmacounter register is enabled by setting bit cntren of the dcdmacon?guration register. the peripheral controller has a 16-bit dcdmacounter register, which speci?es the number of bytes to be transferred. when dma is enabled (dmaen = 1), the internal dma counter is loaded with the value from the dcdmacounter register. when the internal counter completes the transfer as programmed in the dma counter, an eot condition is generated and the dma operation stops. short packet normally, the transfer byte count must be set using a control endpoint before any dma transfer takes place. when a short packet has been enabled as eot indicator (shortp = 1), the transfer size is determined by the presence of a short packet in data. this mechanism permits the use of a fully autonomous data transfer protocol. when reading from an out endpoint, reception of a short packet at an out token will stop the dma operation after transferring the data bytes of this packet. [1] the dma transfer stops. no interrupt, however, is generated. table 19. summary of eot conditions for a bulk endpoint eot condition out endpoint in endpoint dcdmacounter register transfer completes as programmed in the dcdmacounter register transfer completes as programmed in the dcdmacounter register short packet short packet is received and transferred counter reaches zero in the middle of the buffer dmaen bit of the dcdmacon?guration register dmaen = 0 [1] dmaen = 0 [1]
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 58 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 12.4.3.2 isochronous endpoints a dma transfer to or from an isochronous endpoint can be terminated by any of the following conditions (bit names refer to the dcdmacon?guration register, see t ab le 119 and t ab le 120 ): ? the dma transfer completes as programmed in the dcdmacounter register (cntren = 1). ? an end-of-packet (eop) signal is detected. ? dma operation is disabled by clearing bit dmaen. 12.5 ISP1362 peripheral controller suspend and resume 12.5.1 suspend conditions the peripheral controller in the ISP1362 detects a usb suspend condition in either of the following cases: ? constant idle state is present on the usb bus for 3 ms. ? v bus is lost. bus-powered devices that are suspended must not consume more than 500 m a of current. this is achieved by shutting down the power to system components or supplying them with a reduced voltage. the steps leading the peripheral controller to the suspend state are as follows: 1. in the event of no sof for 3 ms, the peripheral controller in the ISP1362 sets bit suspnd of the dcinterrupt register. this will generate an interrupt if bit iesusp of the dcinterruptenable register is set. 2. when the ?rmware detects a suspend condition (through iesusp), it must prepare all system components for the suspend state: a. all the signals connected to the peripheral controller in the ISP1362 must enter appropriate states to meet the power consumption requirements of the suspend state. b. all the input pins of the peripheral controller in the ISP1362 must have a cmos logic 0 or logic 1 level. 3. in the interrupt service routine, the ?rmware must check the current status of the usb bus. when bit bustatus of the dcinterrupt register is logic 0, the usb bus has left suspend mode and the process must be aborted. otherwise, the next step can be executed. 4. to meet the suspend current requirements for a bus-powered device, internal clocks must be switched off by clearing bit clkrun of the dchardwarecon?guration register. 5. when ?rmware has set and cleared the gosusp bit of the dcmode register, the peripheral controller in the ISP1362 enters the suspend state. it sets the d_suspend/ d_w akeup pin to high and switches off internal clocks after 2 ms. table 20. recommended eot usage for isochronous endpoints eot condition out endpoint in endpoint dcdmacounter register zero do not use preferred
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 59 of 152 nxp semiconductors ISP1362 single-chip usb otg controller the peripheral controller in the ISP1362 will remain in the suspend state for at least 5 ms, before responding to external wake-up events, such as global resume, bus traf?c, cs active or low pulse on the d_suspend/ d_w akeup pin. figure 27 shows a typical timing diagram for the peripheral controller suspend and resume operations. in figure 27 : a indicates the point at which the usb bus goes to the idle state. b after detecting the suspend interrupt, set and clear the gosusp bit in the mode register. c indicates resume condition, which can be a resume signal from the host, a low pulse on the d_suspend/ d_w akeup pin, or a low pulse on the cs pin. d indicates remote wake-up. the ISP1362 will drive a k-state on the usb bus for 10 ms after the d_suspend/ d_w akeup pin goes low or the cs pin goes low. 12.5.2 resume conditions wake-up from the suspend state is initiated either by the usb host or by the application: ? usb host: drives a k-state on the usb bus (global resume). ? application: remote wake-up using a low pulse on pin d_suspend/ d_w akeup or a low pulse on pin cs (if enabled using bit wkupcs of the dchardwarecon?guration register). the steps of a wake-up sequence are as follows: fig 27. suspend and resume timing 004aaa483 int2 > 5 ms suspend interrupt usb bus gosusp (bit) cs idle state 10 ms k-state > 3 ms 1.8 ms to 2.2 ms 0.5 ms to 3.5 ms resume interrupt a d b c d_suspend/d_wakeup
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 60 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 1. the internal oscillator and the pll multiplier are re-enabled. when stabilized, clock signals are routed to all internal circuits of the peripheral controller in the ISP1362. 2. the d_suspend/ d_w akeup pin goes low, and the resume bit of the dcinterrupt register is set. this will generate an interrupt if bit ieresume of the dcinterruptenable register is set. 3. after 5 ms of starting the wake-up sequence, the peripheral controller in the ISP1362 resumes its normal functionality (this can be set to 100 m s by setting pin test0 to high). 4. in a remote wake-up, the peripheral controller in the ISP1362 drives a k-state on the usb bus for 10 ms. 5. the application restores itself and other system components to normal operating mode. 6. after wake-up, internal registers of the peripheral controller in the ISP1362 are read and write-protected to prevent corruption by inadvertent writing during power-up of external components. the ?rmware must send an unlock device command to the peripheral controller in the ISP1362 to restore its full functionality. 13. otg registers 13.1 otgcontrol register (r/w: 62h/e2h) code (hex): 62 read code (hex): e2 write table 21. otg control registers overview command (hex) register width references functionality read write 62 e2 otgcontrol 16 section 13.1 on page 60 otg operation registers 67 n/a otgstatus 16 section 13.2 on page 62 68 e8 otginterrupt 16 section 13.3 on page 63 69 e9 otginterruptenable 16 section 13.4 on page 65 6a ea otgtimer 32 section 13.5 on page 66 6c ec otgalttimer 32 section 13.6 on page 67 table 22. otgcontrol register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved otg_se0_ en a_srp_ det_en a_sel_ srp sel_hc_ dc reset ---- 0001 access ----r/wr/wr/wr/w bit 7 6 5 4 3 2 1 0 symbol loc_ pulldn_ dm loc_ pulldn_ dp a_rdis_ lcon_en loc_ conn sel_cp_ ext dischrg_ vbus chrg_ vbus drv_ vbus reset 11000000 access r/w r/w r/w r/w r/w r/w r/w r/w
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 61 of 152 nxp semiconductors ISP1362 single-chip usb otg controller table 23. otgcontrol register: bit description bit symbol description 15 to 12 - reserved 11 otg_se0_ en this bit is used by the host controller to send se0 on remote connect. 0 no se0 sent on remote connect detection 1 se0 (bus reset) sent on remote connect detection remark: this bit is normally set when the b-device goes into the b_wait_acon state (recommended sequence: loc_conn = 0 ? delay ? 50 m s ? otg_se0_en = 1 ? sel_hc_dc = 0) and is cleared when it comes out of the b_wait_acon state. 10 a_srp_det _en this bit is for the a-device only. if set, the a_srp_det bit in the otginterrupt register will be set on detecting an srp event. 0 disable 1 enable 9 a_sel_srp this bit is for the a-device to select a method to detect the srp event (v bus pulsing or data line pulsing). 0 a-device responds to the v bus pulsing 1 a-device responds to the data line pulsing 8 sel_hc_dc this bit is used to select either the peripheral controller or the host controller that interfaces with the transceiver. 0 host controller sie is connected to the otg transceiver 1 peripheral controller sie is connected to the otg transceiver 7 loc_ pulldn_dm 0 disconnects the on-chip pull-down resistor on dm of the otg port 1 connects the on-chip pull-down resistor on dm of the otg port 6 loc_ pulldn_dp 0 disconnects the on-chip pull-down resistor on dp of the otg port 1 connects the on-chip pull-down resistor on dp of the otg port 5 a_rdis_ lcon_en this bit is for the a-device only. if set, the chip will automatically enable its pull-up resistor on dp on detecting a remote disconnect event. if cleared, the dp pull-up is controlled by the loc_conn bit. 0 disable 1 enable remark: this bit is normally set when the a-device goes into the a_suspend state and is cleared when it comes out of the a_suspend state. the loc_conn bit must be set before clearing this bit. 4 loc_conn 0 disconnect the on-chip pull-up resistor on dp of the otg port 1 connect the on-chip pull-up resistor on dp of the otg port 3 sel_cp_ ext this bit is for the a-device only. this bit is used to choose the power source to drive v bus . 0 use on-chip charge pump to drive v bus 1 use external power source (5 v) to drive v bus remark: when using the external power source, the h_psw1 pin serves as the power switch that is controlled by the drv_vbus bit of this register.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 62 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 13.2 otgstatus register (r: 67h) code (hex): 67 read only 2 dischrg_ vbus this bit is for the b-device only. if set, it will enable a pull-down resistor on v bus , which will help to speed up discharging of v bus below session end threshold voltage. 0 disable 1 enable 1 chrg_vbus this bit is for the b-device only. if set, it will charge v bus through a resistor. 0 disable charging v bus of the otg port 1 enable charging v bus of the otg port 0 drv_vbus this bit is used to enable the on-chip charge pump or external power source to drive v bus . for the b-device, it shall not enable this bit at any time. 0 disable driving v bus of the otg port 1 enable driving v bus of the otg port table 23. otgcontrol register: bit description continued bit symbol description table 24. otgstatus register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved se0_2ms reserved reset ------0- access ------r- bit 7 6 5 4 3 2 1 0 symbol reserved rmt_ conn b_sess_ vld a_sess_ vld b_sess_ end a_vbus_ vld id_reg reset - - 000101 access - - rrrrrr table 25. otgstatus register: bit description bit symbol description 15 to 10 - reserved 9 se0_2ms 0 bus is in se0 for less than 2 ms 1 bus is in se0 for more than 2 ms 8 to 6 - reserved 5 rmt_conn 0 remote pull-up resistor disconnected 1 remote pull-up resistor connected remark: when the local pull-up resistor on the dp line is disabled, a 50 m s delay is applied before the rmt_conn detection is enabled. 4 b_sess_vld for the b-device (id_reg = 1), this bit is a b-device session valid indicator (b_sess_vld). 0 v bus is lower than vb_sess_vld 1 v bus is higher than vb_sess_vld
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 63 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 13.3 otginterrupt register (r/w: 68h/e8h) code (hex): 68 read code (hex): e8 write 3 a_sess_vld for the a-device (id_reg = 0), this bit is an a-device session valid indicator (a_sess_vld). 0 v bus is lower than va_sess_vld 1 v bus is higher than va_sess_vld 2 b_sess_end for the b-device (id_reg = 1), this bit is a b-device session end indicator (b_sess_end). 0 v bus is higher than vb_sess_end 1 v bus is lower than vb_sess_end 1 a_vbus_vld for the a-device (id_reg = 0), this bit is an a-device v bus valid indicator (a_vbus_vld). 0 v bus is lower than va_vbus_vld 1 v bus is higher than va_vbus_vld 0 id_reg this bit re?ects the logic level of the id pin. 0 id pin is low (mini-a plug is inserted in the devices mini-ab receptacle) 1 id pin is high (no plug or mini-b plug is inserted in the devices mini-ab receptacle) table 25. otgstatus register: bit description continued bit symbol description table 26. otginterrupt register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved otg_tmr_ timeout b_se0_ srp a_srp_ det reset -----000 access -----r/wr/wr/w bit 7 6 5 4 3 2 1 0 symbol otg_ resume otg_ suspnd rmt_ conn_c b_sess_ vld_c a_sess_ vld_c b_sess_ end_c a_vbus_ vld_c id_reg_c reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 64 of 152 nxp semiconductors ISP1362 single-chip usb otg controller table 27. otginterrupt register: bit description bit symbol description 15 to 11 - reserved 10 otg_tmr_ timeout this bit is set whenever the otg timer attains time-out. writing logic 1 clears this bit. writing logic 0 has no effect. 0 no event 1 otg timer time-out 9 b_se0_srp this bit is set whenever the device detects more than 2 ms of se0. writing logic 1 clears this bit. writing logic 0 has no effect. 0 no event 1 bus has been in se0 for more than 2 ms 8 a_srp_det this bit is used to detect the session request event (srp) from the remote device. the srp event can be either v bus pulsing or data line pulsing. bit 9 (a_sel_srp) of the otgcontrol register determines which srp is selected. writing logic 1 clears this bit. writing logic 0 has no effect. 0 no event 1 srp is detected 7 otg_ resume this bit is used to detect a j to k state change when the device is in the suspend state. writing logic 1 clears this bit. writing logic 0 has no effect. 0 no event 1 a resume signal (j ? k) is detected when the bus is in the suspend state 6 otg_ suspnd this bit is set whenever the otg port goes into the suspend state (bus idle for > 3 ms). write logic 1 to clear this bit. writing logic 0 has no effect. 0 no event 1 suspend (bus idle for > 3 ms) 5 rmt_ conn_c this bit is set whenever the rmt_conn bit of the otgstatus register changes. write logic 1 to clear this bit. writing logic 0 has no effect. 0 no event 1 rmt_conn bit has changed 4 b_sess_ vld_c this bit is set whenever the b_sess_vld bit of the otgstatus register changes. write logic 1 to clear this bit. writing logic 0 has no effect. 0 no event 1 bit b_sess_vld has changed 3 a_sess_ vld_c this bit is set whenever the a_sess_vld bit of the otgstatus register changes. write logic 1 to clear this bit. writing logic 0 has no effect. 0 no event 1 bit a_sess_vld has changed
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 65 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 13.4 otginterruptenable register (r/w: 69h/e9h) code (hex): 69 read code (hex): e9 write 2 b_sess_ end_c this bit is set whenever the b_sess_end bit of the otgstatus register changes. write logic 1 to clear this bit. writing logic 0 has no effect. 0 no event 1 bit b_sess_end has changed 1 a_vbus_ vld_c this bit is set whenever the a_vbus_vld bit of the otgstatus register changes. write logic 1 to clear this bit. writing logic 0 has no effect. 0 no event 1 bit a_vbus_vld has changed 0 id_reg_c this bit is set whenever the id_reg bit of the otgstatus register changes. this is an indication that the mini-a plug is inserted or removed (that is, the id pin is shorted to ground or pulled high). write logic 1 to clear this bit. writing logic 0 has no effect. 0 no event 1 id_reg bit has changed table 27. otginterrupt register: bit description continued bit symbol description table 28. otginterruptenable register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved otg_ tmr_ie b_se0_ srp_ie a_srp_ det_ie reset -----000 access -----r/wr/wr/w bit 7 6 5 4 3 2 1 0 symbol otg_ resume_ ie otg_ suspnd_ ie rmt_ conn_ie b_sess_ vld_ie a_sess_ vld_ie b_sess_ end_ie a_vbus_ vld_ie id_reg_ ie reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 29. otginterruptenable register: bit description bit symbol description 15 to 11 - reserved 10 otg_tmr_ie logic 1 enables interrupt when the otg timer attains time-out. logic 0 disables interrupt. 9 b_se0_srp_ie logic 1 enables interrupt on detecting the b_se0_srp status change. logic 0 disables interrupt. 8 a_srp_det_ie logic 1 enables interrupt on detecting the srp event. logic 0 disables interrupt. 7 otg_resume_ie logic 1 enables interrupt on detecting bus resume (j to k only) event. logic 0 disables interrupt.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 66 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 13.5 otgtimer register (r/w: 6ah/eah) code (hex): 6a read code (hex): ea write 6 otg_suspnd_ie logic 1 enables interrupt on detecting the bus suspend status change. logic 0 disables interrupt. 5 rmt_conn_ie logic 1 enables interrupt on detecting the rmt_conn status change. logic 0 disables interrupt. 4 b_sess_vld_ie logic 1 enables interrupt on detecting b_sess_vld status change. logic 0 disables interrupt. 3 a_sess_vld_ie logic 1 enables interrupt on detecting a_sess_vld status change. logic 0 disables interrupt. 2 b_sess_end_ie logic 1 enables interrupt on detecting b_sess_end status change. logic 0 disables interrupt. 1 a_vbus_vld_ie logic 1 enables interrupt on detecting a_vbus_vld status change. logic 0 disables interrupt. 0 id_reg_ie logic 1 enables interrupt on detecting the id_reg status change. logic 0 disables interrupt. table 29. otginterruptenable register: bit description continued bit symbol description table 30. otgtimer register: bit allocation bit 31 30 29 28 27 26 25 24 symbol start_ tmr reserved reset 0------- access r/w------- bit 23 22 21 20 19 18 17 16 symbol tmr_init_value[23:16] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol tmr_init_value[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol tmr_init_value[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 67 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 13.6 otgalttimer register (r/w: 6ch/ech) code (hex): 6c read code (hex): ec write table 31. otgtimer register: bit description bit symbol description 31 start_tmr this is the start or stop bit of the otg timer. writing logic 1 will cause the otg timer to load tmr_init_value into the counter and start to count. writing logic 0 will stop the timer. this bit is automatically cleared when the otg timer is timed out. 0 stop the timer 1 start the timer 30 to 24 - reserved 23 to 0 tmr_init_ value[23:0] these bits de?ne the initial value used by the otg timer. the timer interval is 0.01 ms. maximum timer allowed is 167.772 s. table 32. otgalttimer register: bit allocation bit 31 30 29 28 27 26 25 24 symbol start_ tmr reserved reset 0------- access r/w------- bit 23 22 21 20 19 18 17 16 symbol current_time[23:16] reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol current_time[15:8] reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol current_time[7:0] reset 00000000 access rrrrrrrr
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 68 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14. host controller registers the host controller contains a set of on-chip control registers. these registers can be read or written by the host controller driver (hcd). the operational registers are made compatible to open host controller interface (ohci) operational registers. this enables the ohci hcd to be easily ported to the ISP1362. reserved bits may be de?ned in future releases of this speci?cation. to ensure interoperability, the hcd that does not use a reserved ?eld must not assume that the reserved ?eld contains logic 0. furthermore, the hcd must always preserve the values of the reserved ?eld. when a r/w register is modi?ed, the hcd must ?rst read the register, modify the desired bits and then write the register with the reserved bits still containing the read value. alternatively, the hcd can maintain an in-memory copy of previously written values that can be modi?ed and then written to the host controller register. when there is a write to set or clear the register, bits written to reserved ?elds must be logic 0. as shown in t ab le 34 , the offset locations (commands to read registers) of these operational registers (32-bit registers) are similar to those de?ned in the ohci speci?cation. the addresses, however, are equal to offset divided by 4. table 33. otgalttimer register: bit description bit symbol description 31 start_ tmr this is the start or stop bit of the otg timer 2. writing logic 1 will cause otg timer 2 to start counting from 0. when the counter reaches ff ffffh, this bit is auto-cleared (the counter is stopped). writing logic 0 will stop the counting. if any bit of the otginterrupt register is set and the corresponding bit of the otginterruptenable register is also set, this bit will be auto-cleared and the current value of the counter will be written to the current_time ?eld. 0 stop the timer 1 start the timer 30 to 24 - reserved 23 to 0 current_ time when read, these bits give the current value of the timer. the actual time is current_time 0.01 ms. table 34. host controller registers overview command (hex) register width reference functionality read write 00 n/a hcrevision 32 section 14.1.1 on page 70 hc control and status registers 01 81 hccontrol 32 section 14.1.2 on page 70 02 82 hccommandstatus 32 section 14.1.3 on page 72 03 83 hcinterruptstatus 32 section 14.1.4 on page 73 04 84 hcinterruptenable 32 section 14.1.5 on page 74 05 85 hcinterruptdisable 32 section 14.1.6 on page 75 0d 8d hcfminterval 32 section 14.2.1 on page 76 hc frame counter registers 0e 8e hcfmremaining 32 section 14.2.2 on page 77 0f 8f hcfmnumber 32 section 14.2.3 on page 78 11 91 hclsthreshold 32 section 14.2.4 on page 79
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 69 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 12 92 hcrhdescriptora 32 section 14.3.1 on page 80 hc root hub registers 13 93 hcrhdescriptorb 32 section 14.3.2 on page 82 14 94 hcrhstatus 32 section 14.3.3 on page 83 15 95 hcrhportstatus[1] 32 section 14.3.4 on page 84 16 96 hcrhportstatus[2] 32 section 14.3.4 on page 84 20 a0 hchardwarecon?guration 16 section 14.4.1 on page 88 hc dma and interrupt control registers 21 a1 hcdmacon?guration 16 section 14.4.2 on page 90 22 a2 hctransfercounter 16 section 14.4.3 on page 91 24 a4 hc m pinterrupt 16 section 14.4.4 on page 91 25 a5 hc m pinterruptenable 16 section 14.4.5 on page 93 27 n/a hcchipid 16 section 14.5.1 on page 94 hc miscellaneous registers 28 a8 hcscratch 16 section 14.5.2 on page 94 n/a a9 hcsoftwarereset 16 section 14.5.3 on page 95 2c ac hcbufferstatus 16 section 14.6.1 on page 95 hc buffer ram control registers 32 b2 hcdirectaddresslength 32 section 14.6.2 on page 96 45 c5 hcdirectaddressdata 16 section 14.6.3 on page 97 30 b0 hcistlbuffersize 16 section 14.7.1 on page 97 iso transfer registers 40 c0 hcistl0bufferport 16 section 14.7.2 on page 97 42 c2 hcistl1bufferport 16 section 14.7.3 on page 98 47 c7 hcistltogglerate 16 section 14.7.4 on page 98 33 b3 hcintlbuffersize 16 section 14.8.1 on page 99 interrupt transfer registers 43 c3 hcintlbufferport 16 section 14.8.2 on page 99 53 d3 hcintlblksize 16 section 14.8.3 on page 100 17 n/a hcintlptddonemap 32 section 14.8.4 on page 100 18 98 hcintlptdskipmap 32 section 14.8.5 on page 100 19 99 hcintllastptd 32 section 14.8.6 on page 101 1a n/a hcintlcurrentactiveptd 16 section 14.8.7 on page 101 34 b4 hcatlbuffersize 16 section 14.9.1 on page 102 aperiodic transfer registers 44 c4 hcatlbufferport 16 section 14.9.2 on page 102 54 d4 hcatlblksize 16 section 14.9.3 on page 102 1b n/a hcatlptddonemap 32 section 14.9.4 on page 103 1c 9c hcatlptdskipmap 32 section 14.9.5 on page 103 1d 9d hcatllastptd 32 section 14.9.6 on page 104 1e n/a hcatlcurrentactiveptd 16 section 14.9.7 on page 104 51 d1 hcatlptddonethresholdcount 16 section 14.9.8 on page 105 52 d2 hcatlptddonethresholdtimeout 16 section 14.9.9 on page 105 table 34. host controller registers overview continued command (hex) register width reference functionality read write
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 70 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.1 hc control and status registers 14.1.1 hcrevision register (r: 00h) the bit allocation of the hcrevision register is given in t ab le 35 . code (hex): 00 read only 14.1.2 hccontrol register (r/w: 01h/81h) the hccontrol register de?nes operating modes for the host controller. the rwe bit is modi?ed only by the hcd. t ab le 37 shows the bit allocation of the register. code (hex): 01 read code (hex): 81 write table 35. hcrevision register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access -------- bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access -------- bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol rev[7:0] reset 00010001 access rrrrrrrr table 36. hcrevision register: bit description bit symbol description 31 to 8 - reserved 7 to 0 rev[7:0] revision: this read-only ?eld contains the binary-coded decimal (bcd) representation of the version of the hci speci?cation that is implemented by this host controller. table 37. hccontrol register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access --------
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 71 of 152 nxp semiconductors ISP1362 single-chip usb otg controller bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access -------- bit 15 14 13 12 11 10 9 8 symbol reserved rwe rwc reserved reset -----00- access -----r/wr/w- bit 7 6 5 4 3 2 1 0 symbol hcfs[1:0] reserved reset 00------ access r/wr/w------ table 38. hccontrol register: bit description bit symbol description 31 to 11 - reserved 10 rwe remotewakeupenable: this bit is used by the hcd to enable or disable the remote wake-up feature on detecting upstream resume signaling. when this bit and the resumedetected (rd) bit in hcinterruptstatus are set, a remote wake-up is signaled to the host system. setting this bit has no impact on the generation of hardware interrupt. 9rwc remotewakeupconnected: this bit indicates whether the host controller supports remote wake-up signaling. if remote wake-up is supported and used by the system, it is the responsibility of the system ?rmware to set this bit during post. the host controller clears the bit on a hardware reset but does not alter it on a software reset. remote wake-up signaling of the host system is host-bus-speci?c and is not described in this speci?cation. 8 - reserved 7 to 6 hcfs[1:0] hostcontrollerfunctionalstate for usb 00 usbreset 01 usbresume 10 usboperational 11 usbsuspend a transition to usboperational from another state causes start-of-frame (sof) generation to begin 1 ms later. the hcd may determine whether the host controller has begun sending sofs by reading the startofframe (sf) ?eld of hcinterruptstatus. this ?eld may be changed by the host controller only when it is in the usbsuspend state. the host controller may move from the usbsuspend state to the usbresume state after detecting the resume signaling from a downstream port. the host controller enters usbreset either by a software reset or by a hardware reset. the latter also resets the root hub and asserts subsequent reset signaling to downstream ports. 5 to 0 - reserved
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 72 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.1.3 hccommandstatus register (r/w: 02h/82h) the hccommandstatus register is a 4 bytes register, and the bit allocation is given in t ab le 39 . this register is used by the host controller to receive commands issued by the hcd, and it also re?ects the current status of the host controller. to the hcd, it appears to be a write to set register. the host controller must ensure that bits written as logic 1 become set in the register while bits written as logic 0 remain unchanged in the register. the hcd may issue multiple distinct commands to the host controller without concern for corrupting previously issued commands. the hcd has normal read access to all bits. the schedulingoverruncount (soc) ?eld indicates the number of frames with which the host controller has detected the scheduling overrun error. this occurs when the periodic list does not complete before the end-of-frame (eof). when a scheduling overrun error is detected, the host controller increments the counter and sets the schedulingoverrun (so) ?eld of the hcinterruptstatus register. code (hex): 02 read code (hex): 82 write table 39. hccommandstatus register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access -------- bit 23 22 21 20 19 18 17 16 symbol reserved soc[1:0] reset ------00 access ------rr bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol reserved hcr reset -------0 access -------r/w
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 73 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.1.4 hcinterruptstatus register (r/w: 03h/83h) this register (bit allocation: t ab le 41 ) provides the status of the events that cause hardware interrupts. when an event occurs, the host controller sets the corresponding bit in this register. when a bit is set, a hardware interrupt is generated if the corresponding interrupt is enabled in the hcinterruptenable register (see section 14.1.5 ) and the masterinterruptenable (mie) bit is set. the hcd must write logic 1 to the speci?c bits to clear the corresponding interrupt bits. the hcd cannot set any of these bits. code (hex): 03 read code (hex): 83 write table 40. hccommandstatus register: bit description bit symbol description 31 to 18 - reserved 17 to 16 soc[1:0] schedulingoverruncount: this ?eld is incremented on each scheduling overrun error. it is initialized to 00b and wraps around at 11b. it will be incremented when a scheduling overrun is detected even if schedulingoverrun in hcinterruptstatus has already been set. this is used by the hcd to monitor any persistent scheduling problems. 15 to 1 - reserved 0 hcr hostcontrollerreset: this bit is set by the hcd to initiate a software reset to the host controller. regardless of the functional state of the host controller, it moves to the usbsuspend state in which most of operational registers are reset, except those stated otherwise. this bit is cleared by the host controller on completing the reset operation. the reset operation must be completed within 10 ms. this bit, when set, will not cause a reset to the root hub and no subsequent reset signaling will be asserted to its downstream ports. table 41. hcinterruptstatus register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access -------- bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access -------- bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol reserved rhsc fno ue rd sf reserved so reset - 00000 - 0 access - r/w r/w r/w r/w r/w - r/w
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 74 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.1.5 hcinterruptenable register (r/w: 04h/84h) each enable bit in the hcinterruptenable register corresponds to an associated interrupt bit in the hcinterruptstatus register. the hcinterruptenable register is used to control which events generate a hardware interrupt. when the following three conditions occur: ? a bit is set in the hcinterruptstatus register. ? the corresponding bit in the hcinterruptenable register is set. ? the masterinterruptenable (mie) bit is set. then, a hardware interrupt is requested on the host bus. writing logic 1 to a bit in the hcinterruptenable register sets the corresponding bit, whereas writing logic 0 to a bit in this register leaves the corresponding bit unchanged. on a read, the current value of this register is returned. t ab le 43 contains the bit allocation of the register. code (hex): 04 read code (hex): 84 write table 42. hcinterruptstatus register: bit description bit symbol description 31 to 7 - reserved 6 rhsc roothubstatuschange: this bit is set when any of the bits of hcrhportstatus[numberofdownstreamport] has changed. 5 fno framenumberover?ow: this bit is set when the msb of the hcfmnumber register (bit 15) changes from logic 0 to logic 1 or from logic 1 to logic 0. 4ue unrecoverableerror: this bit is set when the host controller detects a system error not related to the usb. the host controller should not proceed with any processing nor signaling before the system error is corrected. the hcd clears this bit after the host controller is reset. nxp host controller interface: always set to logic 0. 3rd resumedetected: this bit is set when the host controller detects that a device on the usb is asserting resume signaling. it is the transition from no resume signaling to resume signaling, causing this bit to be set. this bit is not set when the hcd sets the usbresume state. 2sf startofframe: at the start of each frame, this bit is set by the host controller and an sof is generated. 1 - reserved 0so schedulingoverrun: this bit is set when the schedule is overrun for the current frame. a scheduling overrun also causes schedulingoverruncount (soc) of hccommandstatus to be incremented. table 43. hcinterruptenable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol mie reserved reset 0------- access r/w-------
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 75 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.1.6 hcinterruptdisable register (r/w: 05h/85h) each disable bit in the hcinterruptdisable register corresponds to an associated interrupt bit in the hcinterruptstatus register. the hcinterruptdisable register is coupled with the hcinterruptenable register. therefore, writing logic 1 to a bit in this register clears the corresponding bit in the hcinterruptenable register, whereas writing logic 0 to a bit in this register leaves the corresponding bit in the hcinterruptenable register unchanged. on a read, the current value of the hcinterruptenable register is returned. t ab le 45 provides the bit allocation of the hcinterruptdisable register. code (hex): 05 read code (hex): 85 write bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access -------- bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol reserved rhsc fno ue rd sf reserved so reset - 00000 - 0 access - r/w r/w r/w r/w r/w - r/w table 44. hcinterruptenable register: bit description bit symbol description 31 mie masterinterruptenable by the hcd: logic 0 is ignored by the host controller. logic 1 enables interrupt generation by events speci?ed in other bits of this register. 30 to 7 - reserved 6 rhsc 0 ignore 1 enable interrupt generation because of root hub status change 5 fno 0 ignore 1 enable interrupt generation because of frame number over?ow 4ue 0 ignore 1 enable interrupt generation because of unrecoverable error 3rd 0 ignore 1 enable interrupt generation because of resume detect 2sf 0 ignore 1 enable interrupt generation because of start-of-frame 1 - reserved 0so 0 ignore 1 enable interrupt generation because of scheduling overrun
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 76 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.2 hc frame counter registers 14.2.1 hcfminterval register (r/w: 0dh/8dh) the hcfminterval register (bit allocation: t ab le 47 ) contains a 14-bit value that indicates the bit time interval in a frame between two consecutive sofs. in addition, it contains a 15-bit value, indicating the full-speed maximum packet size that the host controller may transmit or receive without causing a scheduling overrun. the hcd may carry out minor table 45. hcinterruptdisable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol mie reserved reset 0------- access r/w------- bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access -------- bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol reserved rhsc fno ue rd sf reserved so reset - 00000 - 0 access - r/w r/w r/w r/w r/w - r/w table 46. hcinterruptdisable register: bit description bit symbol description 31 mie logic 0 is ignored by the host controller. logic 1 disables interrupt generation. this ?eld is set after a hardware or software reset. 30 to 7 - reserved 6 rhsc 0 ignore 1 disable interrupt generation because of root hub status change 5 fno 0 ignore 1 disable interrupt generation because of frame number over?ow 4ue 0 ignore 1 disable interrupt generation because of unrecoverable error 3rd 0 ignore 1 disable interrupt generation because of resume detect 2sf 0 ignore 1 disable interrupt generation because of start-of-frame 1 - reserved 0so 0 ignore 1 disable interrupt generation because of scheduling overrun
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 77 of 152 nxp semiconductors ISP1362 single-chip usb otg controller adjustments on frameinterval by writing a new value over the present one at each sof. this provides the programmability necessary for the host controller to synchronize with an external clocking resource and to adjust any unknown local clock offset. code (hex): 0d read code (hex): 8d write 14.2.2 hcfmremaining register (r/w: 0eh/8eh) the hcfmremaining register is a 14-bit down counter, showing the bit time remaining in the current frame. the bit allocation is given in t ab le 49 . code (hex): 0e read table 47. hcfminterval register: bit allocation bit 31 30 29 28 27 26 25 24 symbol fit fsmps[14:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol fsmps[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved fi[13:8] reset - - 101110 access - - r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol fi[7:0] reset 11011111 access r/w r/w r/w r/w r/w r/w r/w r/w table 48. hcfminterval register: bit description bit symbol description 31 fit frameintervaltoggle: the hcd toggles this bit whenever it loads a new value to frameinterval. 30 to 16 fsmps [14:0] fslargestdatapacket: speci?es a value that is loaded into the largest data packet counter at the beginning of each frame. the counter value represents the largest amount of data in bits that can be sent or received by the host controller in a single transaction at any given time, without causing a scheduling overrun. the ?eld value is calculated by the hcd. 15 to 14 - reserved 13 to 0 fi[13:0] frameinterval: speci?es the interval between two consecutive sofs in bit times. the nominal value is set to 11999. the hcd must store the current value of this ?eld before resetting the host controller. setting the hostcontrollerreset (hcr) ?eld of the hccommandstatus register causes the host controller to reset this ?eld to its nominal value. the hcd may choose to restore the stored value on completing the reset sequence.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 78 of 152 nxp semiconductors ISP1362 single-chip usb otg controller code (hex): 8e write 14.2.3 hcfmnumber register (r/w: 0fh/8fh) the hcfmnumber register is a 16-bit counter, and the bit allocation is given in t ab le 51 .it provides a timing reference for events happening in the host controller and the hcd. the hcd may use the 16-bit value speci?ed in this register and generate a 32-bit frame number, without requiring frequent access to the register. code (hex): 0f read code (hex): 8f write table 49. hcfmremaining register: bit allocation bit 31 30 29 28 27 26 25 24 symbol frt reserved reset 0------- access r/w------- bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access -------- bit 15 14 13 12 11 10 9 8 symbol reserved fr[13:8] reset - - 000000 access - - r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol fr[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 50. hcfmremaining register: bit description bit symbol description 31 frt frameremainingtoggle: this bit is loaded from the frameintervaltoggle (fit) ?eld of hcfminterval whenever frameremaining (fr) reaches 0. this bit is used by the hcd for synchronization between frameinterval (fi) and frameremaining (fr). 30 to 14 - reserved 13 to 0 fr[13:0] frameremaining: this counter is decremented at each bit time. when it reaches zero, it is reset by loading the frameinterval (fi) value speci?ed in hcfminterval at the next bit time boundary. when entering the usboperational state, the host controller reloads it with the content of the frameinterval (fi) part of the hcfminterval register and uses the updated value from the next sof.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 79 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.2.4 hclsthreshold register (r/w: 11h/91h) the hclsthreshold register contains an 11-bit value. this value is used by the host controller to determine whether to start a transfer of a maximum of 8 bytes ls packet before the eof. the hcd is not allowed to change this value. t ab le 53 shows the bit allocation of the register. code (hex): 11 read code (hex): 91 write table 51. hcfmnumber register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access -------- bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access -------- bit 15 14 13 12 11 10 9 8 symbol fn[15:8] reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol fn[7:0] reset 00000000 access rrrrrrrr table 52. hcfmnumber register: bit description bit symbol description 31 to 16 - reserved 15 to 0 fn[15:0] framenumber: this is incremented when hcfmremaining is reloaded. the value will be rolled over to 0h after ffffh. when the usboperational state is entered, this is automatically incremented. table 53. hclsthreshold register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access -------- bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access --------
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 80 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.3 hc root hub registers all registers included in this partition are dedicated to the usb root hub, which is an integral part of the host controller although it is functionally a separate entity. the hcd emulates usb driver (usbd) accesses to the root hub by using a register interface. the hcd maintains many usb-de?ned hub features that are not required to be supported in hardware. for example, the hubs device, con?guration, interface and endpoint descriptors are maintained only in the hcd, as well as some static ?elds of the class descriptor. the hcd also maintains and decodes the address of the root hub device and other trivial operations that are better suited to software than to hardware. root hub registers are developed to maintain the similarity of bit organization and operation to typical hubs found in the system. four registers are de?ned as follows: ? hcrhdescriptora ? hcrhdescriptorb ? hcrhstatus ? hcrhportstatus[1:ndp] each register is read and written as a double word. these registers are only written during initialization to correspond with the system implementation. the hcrhdescriptora and hcrhdescriptorb registers can be read or written, regardless of the usb states of the host controller. you can write to hcrhstatus and hcrhportstatus only when the host controller is in the usboperational state. 14.3.1 hcrhdescriptora register (r/w: 12h/92h) the hcrhdescriptora register is the ?rst of two registers describing the characteristics of the root hub. the bit allocation is given in t ab le 55 . code (hex): 12 read bit 15 14 13 12 11 10 9 8 symbol reserved lst[10:8] reset -----110 access -----r/wr/wr/w bit 7 6 5 4 3 2 1 0 symbol lst[7:0] reset 00101000 access r/w r/w r/w r/w r/w r/w r/w r/w table 54. hclsthreshold register: bit description bit symbol description 31 to 11 - reserved 10 to 0 lst[10:0] lsthreshold: contains a value that is compared to the frameremaining (fr) ?eld before a low-speed transaction is initiated. the transaction is started only if frameremaining (fr) 3 this ?eld. the value is calculated by the hcd. the hcd must consider transmission and set-up overhead, while calculating this value.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 81 of 152 nxp semiconductors ISP1362 single-chip usb otg controller code (hex): 92 write table 55. hcrhdescriptora register: bit description bit 31 30 29 28 27 26 25 24 symbol potpgt[7:0] reset 11111111 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved reset -------- access -------- bit 15 14 13 12 11 10 9 8 symbol reserved nocp ocpm dt nps psm reset - - - 01001 access - - - r/w r/w r r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved ndp[1:0] reset ------10 access ------rr table 56. hcrhdescriptora register: bit description bit symbol description 31 to 24 potpgt [7:0] powerontopowergoodtime: this byte speci?es the duration hcd must wait before accessing a powered-on port of the root hub. it is implementation speci?c. the unit of time is 2 ms. the duration is calculated as potpgt 2ms. 23 to 13 - reserved 12 nocp noovercurrentprotection: this bit describes how the overcurrent status for root hub ports are reported. when this bit is cleared, the overcurrentprotectionmode (ocpm) ?eld speci?es global or per-port reporting. 0 overcurrent status is collectively reported for all downstream ports. 1 no overcurrent reporting supported. 11 ocpm overcurrentprotectionmode: this bit describes how the overcurrent status for root hub ports are reported. at reset, this ?eld should re?ect the same mode as powerswitchingmode. this ?eld is valid only if the noovercurrentprotection (nocp) ?eld is cleared. 0 overcurrent status is collectively reported for all downstream ports. 1 overcurrent status is reported on a per-port basis. on power up, clear this bit and then set it to logic 1. 10 dt devicetype: this bit speci?es that the root hub is not a compound device; it is not permitted. this ?eld should always read as 0. 9 nps nopowerswitching: this bit is used to specify whether power switching is supported or ports are always powered. it is implementation speci?c. when this bit is cleared, the powerswitchingmode (psm) bit speci?es global or per-port switching. 0 ports are power switched. 1 ports are always powered on when the host controller is powered on.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 82 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.3.2 hcrhdescriptorb register (r/w: 13h/93h) the hcrhdescriptorb register is the second of two registers describing the characteristics of the root hub. these ?elds are written during initialization to correspond to the system implementation. t ab le 57 shows the bit allocation of the register. code (hex): 13 read code (hex): 93 write 8 psm powerswitchingmode: this bit is used to specify how the power switching of root hub ports is controlled. it is implementation speci?c. this ?eld is valid only if the nopowerswitching (nps) ?eld is cleared. 0 all ports are powered at the same time. 1 each port is individually powered. this mode allows port power to be controlled by either the global switch or per-port switching. if the portpowercontrolmask (ppcm) bit is set, the port responds to only port power commands (set/clearportpower). if the port mask is cleared, then the port is controlled only by the global power switch (set/clearglobalpower). 7 to 2 - reserved 1 to 0 ndp[1:0] numberofdownstreamport: these bits specify the number of downstream ports supported by the root hub. the ISP1362 supports two ports and therefore, the value is 2. table 56. hcrhdescriptora register: bit description continued bit symbol description table 57. hcrhdescriptorb register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access -------- bit 23 22 21 20 19 18 17 16 symbol reserved ppcm[2:0] reset ----- is access -----r/wr/wr/w bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol reserved dr[2:0] reset ----- is access -----r/wr/wr/w
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 83 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.3.3 hcrhstatus register (r/w: 14h/94h) the hcrhstatus register is divided into two parts. the lower word of a double-word represents the hub status ?eld and the upper word represents the hub status change ?eld. reserved bits should always be written as logic 0. see t ab le 59 for bit allocation of the register. code (hex): 14 read code (hex): 94 write table 58. hcrhdescriptorb register: bit description bit symbol description 31 to 19 - reserved 18 to 16 ppcm[2:0] portpowercontrolmask: each bit indicates whether a port is affected by a global power control command when powerswitchingmode is set. when set, the power state of the port is only affected by per-port power control (set/clearportpower). when cleared, the port is controlled by the global power switch (set/clearglobalpower). if the device is con?gured to global switching mode (powerswitchingmode = 0), this ?eld is not valid. bit 2 ganged-power mask on port 2 bit 1 ganged-power mask on port 1 bit 0 reserved 15 to 3 - reserved 2 to 0 dr[2:0] deviceremovable: each bit is dedicated to a port of the root hub. when cleared, the attached device is removable. when set, the attached device is not removable. bit 2 device attached to port 2 bit 1 device attached to port 1 bit 0 reserved table 59. hcrhstatus register: bit allocation bit 31 30 29 28 27 26 25 24 symbol crwe reserved reset 0------- access w------- bit 23 22 21 20 19 18 17 16 symbol reserved ccic lpsc reset ------00 access ------r/wr/w bit 15 14 13 12 11 10 9 8 symbol drwe reserved reset 0------- access r/w------- bit 7 6 5 4 3 2 1 0 symbol reserved oci lps reset ------00 access ------rr/w
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 84 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.3.4 hcrhportstatus[1:2] register (r/w [1]: 15h/95h; [2]: 16h/96h) the hcrhportstatus[1:2] register is used to control and report port events on a per-port basis. numberofdownstreamport represents the number of hcrhportstatus registers that are implemented in hardware. the lower word is used to re?ect the port status, whereas the upper word re?ects status change bits. some status bits are implemented with special write behavior. reserved bits should always be written logic 0. the bit allocation of the hcrhportstatus[1:2] register is given in t ab le 61 . code (hex): [1] = 15, [2] = 16 read code (hex): [1] = 95, [2] = 96 write table 60. hcrhstatus register: bit description bit symbol description 31 crwe on write clearremotewakeupenable: writing logic 1 clears deviceremotewakeupenable (drwe). writing logic 0 has no effect. 30 to 18 - reserved 17 ccic overcurrentindicatorchange: this bit is set by hardware when a change has occurred to the overcurrentindicator (oci) ?eld of this register. the hcd clears this bit by writing logic 1. writing logic 0 has no effect. 16 lpsc on read localpowerstatuschange: the root hub does not support the local power status feature. therefore, this bit is always read as logic 0. on write setglobalpower: in global power mode (powerswitchingmode = 0), logic 1 is written to this bit to turn on power to all ports (clear portpowerstatus). in per-port power mode, it sets portpowerstatus only on ports whose portpowercontrolmask bit is not set. writing logic 0 has no effect. 15 drwe on read deviceremotewakeupenable: this bit enables bit connectstatuschange as a resume event, causing a state transition from usbsuspend to usbresume and setting the resumedetected interrupt. 0 connectstatuschange is not a remote wake-up event 1 connectstatuschange is a remote wake-up event on write setremotewakeupenable: writing logic 1 sets deviceremotewakeupenable. writing logic 0 has no effect. 14 to 2 - reserved 1 oci overcurrentindicator: this bit reports overcurrent conditions when global reporting is implemented. when set, an overcurrent condition exists. when cleared, all power operations are normal. if per-port overcurrent protection is implemented, this bit is always logic 0. 0 lps on read localpowerstatus: the root hub does not support the local power status feature. therefore, this bit is always read as logic 0. on write clearglobalpower: in global power mode (powerswitchingmode = 0), logic 1 is written to this bit to turn-off power to all ports (clear portpowerstatus). in per-port power mode, it clears portpowerstatus only on ports whose portpowercontrolmask bit is not set. writing logic 0 has no effect. table 61. hcrhportstatus[1:2] register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access --------
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 85 of 152 nxp semiconductors ISP1362 single-chip usb otg controller bit 23 22 21 20 19 18 17 16 symbol reserved prsc ocic pssc pesc csc reset - - - 00000 access - - - r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved lsda pps reset ------00 access ------r/wr/w bit 7 6 5 4 3 2 1 0 symbol reserved prs poci pss pes ccs reset - - - 00000 access - - - r/w r/w r/w r/w r/w table 62. hcrhportstatus[1:2] register: bit description bit symbol description 31 to 21 - reserved 20 prsc portresetstatuschange: this bit is set at the end of the 10 ms port reset signal. the hcd writes logic 1 to clear this bit. writing logic 0 has no effect. 0 port reset is not complete 1 port reset is complete 19 ocic portovercurrentindicatorchange: this bit is valid only if overcurrent conditions are reported on a per-port basis. this bit is set when the root hub changes the portovercurrentindicator (poci) bit. the hcd writes logic 1 to clear this bit. writing logic 0 has no effect. 0 no change in portovercurrentindicator (poci) 1 portovercurrentindicator (poci) has changed 18 pssc portsuspendstatuschange: this bit is set when the full resume sequence is complete. this sequence includes the 20 ms resume pulse, ls eop and 3 ms re-synchronization delay. the hcd writes logic 1 to clear this bit. writing logic 0 has no effect. this bit is also cleared when portresetstatuschange is set. 0 resume is not completed 1 resume is completed 17 pesc portenablestatuschange: this bit is set when hardware events cause the portenablestatus (pes) bit to be cleared. changes from the hcd writes do not set this bit. the hcd writes logic 1 to clear this bit. writing logic 0 has no effect. 0 no change in portenablestatus (pes) 1 change in portenablestatus (pes)
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 86 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 16 csc connectstatuschange: this bit is set whenever a connect or disconnect event occurs. the hcd writes logic 1 to clear this bit. writing logic 0 has no effect. if currentconnectstatus (ccs) is cleared when a setportreset, setportenable or setportsuspend write occurs, this bit is set to force the driver to re-evaluate the connection status because these writes should not occur if the port is disconnected. 0 no change in currentconnectstatus (ccs) 1 change in currentconnectstatus (ccs) remark: if the deviceremovable[ndp] bit is set, this bit is set only after a root hub reset to inform the system that the device is attached. 15 to 10 - reserved 9 lsda on read lowspeeddeviceattached: this bit indicates the speed of the device attached to this port. when set, a low-speed device is attached to this port. when cleared, a full-speed device is attached to this port. this ?eld is valid only when currentconnectstatus (ccs) is set. 0 full-speed device attached 1 low-speed device attached on write clearportpower: the hcd clears the portpowerstatus (pps) bit by writing logic 1 to this bit. writing logic 0 has no effect. 8 pps on read portpowerstatus: this bit re?ects the port power status, regardless of the type of power switching implemented. this bit is cleared if an overcurrent condition is detected. the hcd sets this bit by writing setportpower or setglobalpower. the hcd clears this bit by writing clearportpower or clearglobalpower. powerswitchingmode (pcm) and portpowercontrolmask[ndp] (ppcm[ndp]) determine which power control switches are enabled. in global switching mode (powerswitchingmode = 0), only the set/clearglobalpower command controls this bit. in the per-port power switching (powerswitchingmode = 1), if the portpowercontrolmask[ndp] (ppcm[ndp]) bit for the port is set, only set/clearportpower commands are enabled. if the mask is not set, only set/clearglobalpower commands are enabled. when port power is disabled, currentconnectstatus (ccs), portenablestatus (pes), portsuspendstatus (pss) and portresetstatus (prs) should be reset. 0 port power is off 1 port power is on on write setportpower: the hcd writes logic 1 to set the portpowerstatus (pps) bit. writing logic 0 has no effect. remark: this bit always reads logic 1 if power switching is not supported. 7 to 5 - reserved table 62. hcrhportstatus[1:2] register: bit description continued bit symbol description
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 87 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 4 prs on read portresetstatus: when this bit is set by a write to setportreset, port reset signaling is asserted. when reset is completed, this bit is cleared when portresetstatuschange (prsc) is set. this bit cannot be set if currentconnectstatus (ccs) is cleared. 0 port reset signal is not active 1 port reset signal is active on write setportreset: the hcd sets the port reset signaling by writing logic 1 to this bit. writing logic 0 has no effect. if currentconnectstatus (ccs) is cleared, this write does not set portresetstatus (prs) but instead sets connectstatuschange (csc). this informs the driver that it attempted to reset a disconnected port. 3 poci on read portovercurrentindicator: this bit is valid only when the root hub is con?gured in such a way that overcurrent conditions are reported on a per-port basis. if per-port overcurrent reporting is not supported, this bit is set to logic 0. if cleared, all power operations are normal for this port. if set, an overcurrent condition exists on this port. this bit always re?ects the overcurrent input signal. 0 no overcurrent condition 1 overcurrent condition detected on write clearsuspendstatus: the hcd writes logic 1 to initiate a resume. writing logic 0 has no effect. a resume is initiated only if portsuspendstatus (pss) is set. 2 pss on read portsuspendstatus: this bit indicates whether the port is suspended or is in the resume sequence. it is set by a portsuspendstatus write and cleared when portsuspendstatuschange (pssc) is set at the end of the resume interval. this bit cannot be set if currentconnectstatus (ccs) is cleared. this bit is also cleared when portresetstatuschange (prsc) is set at the end of the port reset or when the host controller is placed in the usbresume state. if an upstream resume is in progress, it should propagate to the host controller. 0 port is not suspended 1 port is suspended on write setportsuspend: the hcd sets the portsuspendstatus (pss) bit by writing logic 1 to this bit. writing logic 0 has no effect. if currentconnectstatus (ccs) is cleared, this write does not set portsuspendstatus (pss); instead it sets connectstatuschange (csc). this informs the driver that it attempted to suspend a disconnected port. table 62. hcrhportstatus[1:2] register: bit description continued bit symbol description
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 88 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.4 hc dma and interrupt control registers 14.4.1 hchardwarecon?guration register (r/w: 20h/a0h) the bit allocation of the hchardwarecon?guration register is given in t ab le 63 . code (hex): 20 read code (hex): a0 write 1 pes on read portenablestatus: this bit indicates whether the port is enabled or disabled. the root hub may clear this bit when an overcurrent condition, disconnect event, switched-off power or operational bus error, such as babble, is detected. this change also causes portenablestatuschange to be set. the hcd sets this bit by writing setportenable and clears it by writing clearportenable. this bit cannot be set when currentconnectstatus (ccs) is cleared. this bit is also set, if it is not already, at the completion of a port reset when portresetstatuschange is set or port suspend when portsuspendstatuschange is set. 0 port is disabled 1 port is enabled on write setportenable: the hcd sets portenablestatus (pes) by writing logic 1. writing logic 0 has no effect. if currentconnectstatus (ccs) is cleared, this write does not set portenablestatus (pes), but instead sets connectstatuschange (csc). this informs the driver that it attempted to enable a disconnected port. 0 ccs on read currentconnectstatus: this bit re?ects the current state of the downstream port. 0 no device connected 1 device connected on write clearportenable: the hcd writes logic 1 to this bit to clear the portenablestatus (pes) bit. writing logic 0 has no effect. currentconnectstatus (csc) is not affected by any write. remark: this bit always reads logic 1 when the attached device is nonremovable (deviceremovable[ndp]). table 62. hcrhportstatus[1:2] register: bit description continued bit symbol description table 63. hchardwarecon?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol disable suspend_ wakeup global power down connect pulldown _ds2 connect pulldown _ds1 suspend clknotstop analogoc enable oneint dack mode reset 00000 000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol onedma dackinput polarity dreq output polarity databuswidth[1:0] interrupt output polarity interrupt pintrigger interruptpin enable reset 00101 000 access r/w r/w r/w r/w r/w r/w r/w r/w
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 89 of 152 nxp semiconductors ISP1362 single-chip usb otg controller table 64. hchardwarecon?guration register: bit description bit symbol description 15 disablesuspend_wakeup this bit when set to logic 1 disables the function of the d_suspend/ d_w akeup and h_suspend/ h_w akeup pins. therefore, these pins will always remain high and pulling them low does not wake-up the host controller and the peripheral controller. 14 globalpowerdown set this bit to logic 1 to reduce power consumption of the otg atx in suspend mode. 13 connectpulldown_ds2 0 disconnect built-in pull-down resistors on h_dm2 and h_dp2 1 connect built-in pull-down resistors on h_dm2 and h_dp2 for the downstream port 2 remark: port 2 is always used as a host port. 12 connectpulldown_ds1 0 disconnect built-in pull-down resistors on otg_dm1 and otg_dp1 1 connect built-in pull-down resistors on otg_dm1 and otg_dp1 remark: this bit is effective only when port 1 is con?gured as the host port (the o tgmode pin is high, and the id pin is low). when port 1 is con?gured as the otg port, (the o tgmode pin is low), the pull-down resistors on otg_dm1 and otg_dp1 are controlled by the loc_pull_dn_dp and loc_pull_dn_dm bits of the otgcontrol register. 11 suspendclknotstop 0 clock can be stopped when suspended 1 clock cannot be stopped when suspended 10 analogocenable 0 use external overcurrent detection; digital input 1 use on-chip overcurrent detection; analog input 9 oneint 0 host controller interrupt routed to int1, peripheral controller interrupt routed to int2 1 host controller and peripheral controller interrupts routed to int1 only, int2 is unused 8 dackmode 0 normal operation; d a ck1 is used with read and write signals 1 reserved 7 onedma 0 host controller dma request and acknowledge are routed to dreq1 and d a ck1, peripheral controller dma request and acknowledge are routed to dreq2 and d a ck2 1 host controller and peripheral controller dma requests and acknowledges are routed to dreq1 and d a ck1; dreq2 and d a ck2 unused 6 dackinputpolarity 0 d a ck1 is active low 1 d a ck1 is active high
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 90 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.4.2 hcdmacon?guration register (r/w: 21h/a1h) t ab le 65 contains the bit allocation of the hcdmacon?guration register. code (hex): 21 read code (hex): a1 write 5 dreqoutputpolarity 0 dreq1 is active low 1 dreq1 is active high 4 to 3 databuswidth[1:0] 01 microprocessor interface data bus width is 16 bits others reserved 2 interruptoutputpolarity 0 int1 interrupt is active low; power-up value 1 int1 interrupt is active high 1 interruptpintrigger 0 int1 interrupt is level-triggered; power-up value 1 int1 interrupt is edge-triggered 0 interruptpinenable 0 power-up value 1 global interrupt pin int1 is enabled; this bit should be used with the hc m pinterruptenable register to enable pin int1 table 64. hchardwarecon?guration register: bit description continued bit symbol description table 65. hcdmacon?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol dmacounter enable burstlen[1:0] dma enable buffer_type_select[2:0] dmaread writeselect reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 66. hcdmacon?guration register: bit description bit symbol description 15 to 8 - reserved 7 dmacounterenable 0 reserved 1 dma counter is enabled. once the counter is enabled, the hcd must initialize the hctransfercounter register to a non-zero value for dreq to be raised after the dmaenable bit is set to high. 6 to 5 burstlen[1:0] 00 single-cycle burst dma 01 4-cycle burst dma 10 8-cycle burst dma 11 reserved i/o bus with 32-bit data path width supports only single and four cycle dma burst.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 91 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.4.3 hctransfercounter register (r/w: 22h/a2h) regardless of pio or dma data transfer modes, this register is used to initialize the number of bytes to be transferred to or from the istl, intl or atl buffer ram. for the count value loaded in the register to take effect, the hcd is required to set bit 7 of the hcdmacon?guration register to logic 1. when the count value has reached, the host controller must generate an internal eot signal to set bit 2 of the hc m pinterrupt register, alleotinterrupt, and update the hcbufferstatus register. the bit allocation of the hctransfercounter register is given in t ab le 68 . code (hex): 22 read code (hex): a2 write 14.4.4 hc m pinterrupt register (r/w: 24h/a4h) all the bits in this register are active at power-on reset. none of the active bits, however, will cause an interrupt on the interrupt pin (int1), unless they are set by the respective bits in the hc m pinterruptenable register and bit 0 of the hchardwarecon?guration register is also set. the bits in this register are cleared only when you write to this register, indicating the bits to be cleared. to clear all the enabled bits in this register, the hcd must write ffh to this register. the bit allocation of the hc m pinterrupt register is given in t ab le 69 . code (hex): 24 read code (hex): a4 write 4 dmaenable 0 dma is disabled 1 dma is enabled this bit needs to be reset when the dma transfer is completed. 3 to 1 buffer_type_select[2:0] see t ab le 67 . 0 dmareadwriteselect 0 read from the buffer memory of the host controller 1 write to the buffer memory of the host controller table 67. buffer_type_select[2:0]: bit description bit 3 bit 2 bit 1 buffer type 0 0 0 istl0 (default) 0 0 1 istl1 0 1 0 intl 011atl 1 x x direct addressing table 66. hcdmacon?guration register: bit description continued bit symbol description table 68. hctransfercounter register: bit description bit symbol access value description 15 to 0 countervalue[15:0] r/w 0000h number of data bytes to be read from or written to the buffer ram.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 92 of 152 nxp semiconductors ISP1362 single-chip usb otg controller table 69. hc m pinterrupt register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved otg_irq atl_irq reset ------00 access ------r/wr/w bit 7 6 5 4 3 2 1 0 symbol intl_irq clkready hc suspended opr_reg alleot interrupt istl1_ int istl0_ int sof_int reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 70. hc m pinterrupt register: bit description bit symbol description 15 to 10 - reserved 9 otg_irq 0 no event 1 the otg interrupt event must read the otginterrupt register to get the cause of the interrupt. 8 atl_irq 0 no event 1 count value of the hcatlptddonethresholdcount register or the time-out value of the hcatlptddonethresholdtimeout register has reached. the microprocessor is required to read hcatlptddonemap to check the ptds that have completed their transactions. 7 intl_irq 0 no event 1 the host controller has detected the last ptd, and there is at least one interrupt transaction that has received ack from the device. the microprocessor is required to read hcintlptddonemap to check the ptds that have received ack from the device. 6 clkready 0 no event 1 the host controller has awakened from the suspend state, and its internal clock has turned on again. 5hc suspended 0 no event 1 the host controller has been suspended and no usb activities are sent from the microprocessor for each ms. the microprocessor can suspend the host controller by setting bits 6 and 7 of the hccontrol register to logic 1. once the host controller is suspended, no sof needs to be sent to the devices connected to downstream ports. 4 opr_reg 0 no event 1 a host controller operation has caused a hardware interrupt. it is necessary for the hcd to read the hcinterruptstatus register to determine the cause of the interrupt. 3 alleot interrupt 0 no event 1 data transfer has been completed by using the pio transfer or the dma transfer. this bit is set either when the value of the hctransfercounter register has reached zero, or the eot pin of the host controller is triggered by an external signal.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 93 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.4.5 hc m pinterruptenable register (r/w: 25h/a5h) bits 9 to 0 in this register are the same as those in the hc m pinterrupt register. the bits in this register are used together with bit 0 of the hchardwarecon?guration register to enable or disable the bits in the hc m pinterrupt register. at power-on, all the bits in this register are masked with logic 0. this means no interrupt request output on interrupt pin int1 can be generated. when a bit is set to logic 1, the interrupt for that bit is enabled. the bit allocation of the register is given in t ab le 71 . code (hex): 25 read code (hex): a5 write 2 istl1_ int 0 no event 1 the transaction of the last ptd stored in the istl1 buffer has been completed. the microprocessor is required to read data from the istl1 buffer. the hcd must ?rst read the hcbufferstatus register to check the status of the istl1 buffer, before reading data to the microprocessor. 1 istl0_ int 0 no event 1 the transaction of the last ptd stored in the istl0 buffer has been completed. the microprocessor is required to read data from the istl0 buffer. the hcd must ?rst read the hcbufferstatus register to check the status of the istl0 buffer, before reading data to the microprocessor. 0 sof_int 0 no event 1 the host controller is in the sof state and it indicates the start of a new frame. the hcd must ?rst read the hcbufferstatus register to check the status of the istl buffer, before reading data to the microprocessor. for the microprocessor to perform the dma transfer of iso data from or to the istl buffer, the host controller must ?rst initialize the hcdmacon?guration register. table 70. hc m pinterrupt register: bit description continued bit symbol description table 71. hc m pinterruptenable register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved otg_irq_ interrupt enable atl_irq_ interrupt enable reset ------00 access ------r/wr/w bit 7 6 5 4 3 2 1 0 symbol intl_irq_ interrupt enable clkready hc suspended enable opr interrupt enable eot interrupt enable istl1 interrupt enable istl0 interrupt enable sof interrupt enable reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 94 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.5 hc miscellaneous registers 14.5.1 hcchipid register (r: 27h) this register contains the id of the ISP1362. the upper byte identi?es the product name (here 36h stands for the ISP1362). the lower byte indicates the revision number of the product, including engineering samples. t ab le 73 contains the bit description of the register. code (hex): 27 read only 14.5.2 hcscratch register (r/w: 28h/a8h) this register is for the hcd to save and restore values when required. the bit description is given in t ab le 74 . code (hex): 28 read code (hex): a8 write table 72. hc m pinterruptenable register: bit description bit symbol description 15 to 10 - reserved 9 otg_irq_interruptenable 0 power-up value 1 enables the otg_irq interrupt 8 atl_irq_interruptenable 0 power-up value 1 enables the atl_irq interrupt 7 intl_irq_interruptenable 0 power-up value 1 enables the int_irq interrupt 6 clkready 0 power-up value 1 enables the clkready interrupt 5 hcsuspendedenable 0 power-up value 1 enables the host controller suspended interrupt 4 oprinterruptenable 0 power-up value 1 enables the 32-bit operational registers interrupt 3 eotinterruptenable 0 power-up value 1 enables the eot interrupt 2 istl1interruptenable 0 power-up value 1 enables the istl1 interrupt 1 istl0interruptenable 0 power-up value 1 enables the istl0 interrupt 0 sofinterruptenable 0 power-up value 1 enables the sof interrupt table 73. hcchipid register: bit description bit symbol access value description 15 to 0 chipid[15:0] r 3630h chip id of the ISP1362.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 95 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.5.3 hcsoftwarereset register (w: a9h) this register provides a means for the software reset of the host controller. to reset the host controller, the hcd must write a reset value of f6h to this register. on receiving this reset value, the host controller resets all the host controller and otg registers, except its buffer memory. t ab le 75 contains the bit description of the register. code (hex): a9 write only 14.6 hc buffer ram control registers 14.6.1 hcbufferstatus register (r/w: 2ch/ach) the bit allocation of the hcbufferstatus register is given in t ab le 76 . code (hex): 2c read code (hex): ac write table 74. hcscratch register: bit description bit symbol access value description 15 to 0 scratch[15:0] r/w 0000h scratch register value. table 75. hcsoftwarereset register: bit description bit symbol access value description 15 to 0 resetvalue[15:0] w 0000h writing a reset value of f6h causes the host controller to reset all the host controller and otg registers, except its buffer memory. table 76. hcbufferstatus register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved pairedptd pingpong istl1 bufferdone istl0 bufferdone reset -----000 access -----rrr bit 7 6 5 4 3 2 1 0 symbol reserved istl1_ active status istl0_ active status reset_hw pingpong reg atl_active intl_ active istl1 bufferfull istl0 bufferfull reset - 0000000 access - r r r/w r/w r/w r/w r/w table 77. hcbufferstatus register: bit description bit symbol description 15 to 11 - reserved 10 pairedptdpingpong 0 ping of the paired ptd in atl is active. 1 pong of the paired ptd in atl is active. 9 istl1bufferdone 0 the istl1 buffer has not yet been read by the host controller. 1 the istl1 buffer has been read by the host controller.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 96 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.6.2 hcdirectaddresslength register (r/w: 32h/b2h) the hcdirectaddresslength register is used for direct addressing of the istl, intl or atl buffers. this register speci?es the starting address of the buffer and byte count of data to be addressed. therefore, it allows the programmer to randomly access the buffer. the bit allocation of the register is given in t ab le 78 . code (hex): 32 read code (hex): b2 write 8 istl0bufferdone 0 the istl0 buffer has not yet been read by the host controller. 1 the istl0 buffer has been read by the host controller. 7 - reserved 6 istl1_activestatus 0 the istl1 buffer is not accessed by the slave host. 1 the istl1 buffer is accessed by the slave host. 5 istl0_activestatus 0 the istl0 buffer is not accessed by the slave host. 1 the istl0 buffer is accessed by the slave host. 4 reset_hwpingpong reg 0to1 resets the internal hardware ping pong register to 0 when atl_active is 0. the hardware ping pong register can be read from bit 10 of this register. 1to0 has no effect. 3 atl_active 0 the host controller does not process the atl buffer. 1 the host controller processes the atl buffer. 2 intl_active 0 the host controller does not process the intl buffer. 1 the host controller processes the intl buffer. 1 istl1bufferfull 0 the host controller does not process the istl1 buffer. 1 the host controller processes the istl1 buffer. 0 istl0bufferfull 0 the host controller does not process the istl0 buffer. 1 the host controller processes the istl0 buffer. table 77. hcbufferstatus register: bit description continued bit symbol description table 78. hcdirectaddresslength register: bit allocation bit 31 30 29 28 27 26 25 24 symbol databytecount[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol databytecount[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved bufferstartaddress[14:8] reset 00000000 access - r/w r/w r/w r/w r/w r/w r/w
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 97 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.6.3 hcdirectaddressdata register (r/w: 45h/c5h) this is a data port for the hcd to access the istl, intl or atl buffers under direct addressing mode. t ab le 80 contains the bit description of the register. code (hex): 45 read code (hex): c5 write 14.7 isochronous (iso) transfer registers 14.7.1 hcistlbuffersize register (r/w: 30h/b0h) this register requires you to allocate the size of the buffer to be used for iso transactions. the buffer size speci?ed in the register is applied to the istl0 and istl1 buffers. therefore, istl0 and istl1 always have the same buffer size. t ab le 81 shows the bit description of the register. code (hex): 30 read code (hex): b0 write 14.7.2 hcistl0bufferport register (r/w: 40h/c0h) in addition to the hcdirectaddressdata register, the ISP1362 provides this register to act as another data port to access the istl0 buffer. the starting address to access the buffer is always ?xed at 0000h. therefore, random access of the istl0 buffer is not allowed. the bit description of the register is given in t ab le 82 . code (hex): 40 read code (hex): c0 write bit 7 6 5 4 3 2 1 0 symbol bufferstartaddress[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 79. hcdirectaddresslength register: bit description bit symbol description 31 to 16 databytecount[15:0] total number of bytes to be accessed. 15 - reserved 14 to 0 bufferstartaddress[14:0] the starting address of the buffer to access data. table 80. hcdirectaddressdata register: bit description bit symbol access value description 15 to 0 dataword [15:0] r/w 0000h the data port to access the istl, intl or atl buffers. the address of the buffer and byte count of the data must be speci?ed in the hcdirectaddresslength register. table 81. hcistlbuffersize register: bit description bit symbol access value description 15 to 0 istlbuffersize[15:0] r/w 0000h the size of the buffer to be used for iso transactions and must be speci?ed in bytes.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 98 of 152 nxp semiconductors ISP1362 single-chip usb otg controller the hcd is ?rst required to initialize the hctransfercounter register with the byte count to be transferred and check the hcbufferstatus register. the hcd then sends the command (40h to read from the istl0 buffer, and c0h to write to the istl0 buffer) to the host controller through the i/o port of the microprocessor. after the command is sent, the hcd starts reading data from the istl0 buffer or writing data to the istl0 buffer. while the hcd is accessing the buffer, the buffer pointer of istl0 also automatically increases. when the pointer has reached the initialized byte count of the hctransfercounter register, the host controller sets the alleotinterrupt bit of the hc m pinterrupt register to logic 1 and updates the hcbufferstatus register. 14.7.3 hcistl1bufferport register (r/w: 42h/c2h) in addition to the hcdirectaddressdata register, the ISP1362 provides this register to act as another data port to access the istl1 buffer. the starting address to access the buffer is always ?xed at 0000h. therefore, random access of the istl1 buffer is not allowed. the bit description of the register is given in t ab le 83 . code (hex): 42 read code (hex): c2 write the hcd is ?rst required to initialize the hctransfercounter register with the byte count to be transferred and check the hcbufferstatus register. the hcd then sends the command (42h to read from the istl1 buffer, and c2h to write to the istl1 buffer) to the host controller through the i/o port of the microprocessor. after the command is sent, the hcd starts reading data from the istl1 buffer or writing data to the istl1 buffer. while the hcd is accessing the buffer, the buffer pointer of istl1 also automatically increases. when the pointer has reached the initialized byte count of the hctransfercounter register, the host controller sets the alleotinterrupt bit in the hc m pinterrupt register to logic 1 and updates the hcbufferstatus register. 14.7.4 hcistltogglerate register (r/w: 47h/c7h) the rate of toggling between istl0 and istl1 is programmable. the hcistltogglerate register is provided to program the required toggle rate in the range of 0 ms to 15 ms at intervals of 1 ms. the bit allocation of the register is shown in t ab le 84 . code (hex): 47 read code (hex): c7 write table 82. hcistl0bufferport register: bit description bit symbol access value description 15 to 0 dataword[15:0] r/w 0000h the data in the istl0 buffer to be accessed through this data port. table 83. hcistl1bufferport register: bit description bit symbol access value description 15 to 0 dataword[15:0] r/w 0000h data in the istl1 buffer to be accessed through this data port. table 84. hcistltogglerate register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access --------
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 99 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.8 interrupt transfer registers 14.8.1 hcintlbuffersize register (r/w: 33h/b3h) this register allows you to allocate the size of the intl buffer to be used for interrupt transactions. the default value of the buffer size is set to 128 bytes, and the maximum allowable allocated size is 4096 bytes. t ab le 86 shows the bit description of the register. code (hex): 33 read code (hex): b3 write 14.8.2 hcintlbufferport register (r/w: 43h/c3h) in addition to the hcdirectaddressdata register, the ISP1362 provides this register to act as another data port to access the intl buffer. the starting address to access the buffer is always ?xed at 0000h. therefore, random access of the intl buffer is not allowed. the bit description of the hcintlbufferport register is given in t ab le 87 . code (hex): 43 read code (hex): c3 write the hcd is ?rst required to initialize the hctransfercounter register with the byte count to be transferred and check the hcbufferstatus register. the hcd then sends the command (43h to read the intl buffer, and c3h to write to the intl buffer) to the host controller through the i/o port of the microprocessor. after the command is sent, the hcd starts reading data from the intl buffer or writing data to the intl buffer. while the hcd is accessing the buffer, the buffer pointer of intl also automatically increases. when the pointer has reached the initialized byte count of the hctransfercounter register, the host controller sets the alleotinterrupt bit of the hc m pinterrupt register to logic 1 and updates the hcbufferstatus register. bit 7 6 5 4 3 2 1 0 symbol reserved istltogglerate[3:0] reset ---- 0000 access ----r/wr/wr/wr/w table 85. hcistltogglerate register: bit description bit symbol description 15 to 4 - reserved 3 to 0 istltogglerate[3:0] the required toggle rate in ms. table 86. hcintlbuffersize register: bit description bit symbol access value description 15 to 0 intlbuffersize[15:0] r/w 0080h the size of the buffer to be used for interrupt transactions and must be speci?ed in bytes. table 87. hcintlbufferport register: bit description bit symbol access value description 15 to 0 dataword[15:0] r/w 0000h data in the intl buffer to be accessed through this data port.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 100 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.8.3 hcintlblksize register (r/w: 53h/d3h) the ISP1362 requires the intl buffer to be partitioned into several equal sized blocks so that the host controller can skip the current ptd and proceed to process the next ptd easily. the block size of the intl buffer is required to be speci?ed in this register and must be a multiple of 8 bytes. the default value of the block size is 64 bytes, and the maximum allowable block size is 1024 bytes. t ab le 88 shows the bit allocation of the register. code (hex): 53 read code (hex): d3 write 14.8.4 hcintlptddonemap register (r: 17h) this is a 32-bit register, and the bit description is given in t ab le 90 . every bit of the register represents the processing status of a ptd. bit 0 of the register represents the ?rst ptd stored in the intl buffer, bit 1 represents the second ptd stored in the buffer, and so on. the register is updated once every ms by the host controller and is cleared on read by the hcd. bits that are set represent its corresponding ptds are processed by the host controller and the ack token is received from the device. code (hex): 17 read only 14.8.5 hcintlptdskipmap register (r/w: 18h/98h) this is a 32-bit register, and the bit description is given in t ab le 91 . bit 0 of the register represents the ?rst ptd stored in the intl buffer, bit 1 represents the second ptd stored in the buffer, and so on. when a bit is set by the hcd, the corresponding ptd is skipped and is not processed by the host controller. the host controller processes the skipped table 88. hcintlblksize register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved blocksize[9:8] reset ------00 access ------r/wr/w bit 7 6 5 4 3 2 1 0 symbol blocksize[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 89. hcintlblksize register: bit description bit symbol description 15 to 10 - reserved 9 to 0 blocksize[9:0] the block size of the intl buffer. table 90. hcintlptddonemap register: bit description bit symbol access value description 31 to 0 ptddonebits[31:0] r 0000h 0 the ptd stored in the intl buffer has not successfully been processed by the host controller. 1 the ptd stored in the intl buffer has successfully been processed by the host controller.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 101 of 152 nxp semiconductors ISP1362 single-chip usb otg controller ptd if the hcd has reset its corresponding skipped bit to logic 0. clearing the corresponding bit in the hcintlptdskipmap register when there is no valid data in the block will cause unpredictable behavior of the host controller. code (hex): 18 read code (hex): 98 write 14.8.6 hcintllastptd register (r/w: 19h/99h) this is a 32-bit register, and t ab le 92 shows its bit description. bit 0 of the register represents the ?rst ptd stored in the intl buffer, bit 1 represents the second ptd stored in the buffer, and so on. the bit that is set to logic 1 by the hcd is used as an indication to the host controller that its corresponding ptd is the last ptd stored in the intl buffer. when the processing of the last ptd is complete, the host controller proceeds to process atl transactions. code (hex): 19 read code (hex): 99 write 14.8.7 hcintlcurrentactiveptd register (r: 1ah) this register indicates which ptd stored in the intl buffer is currently active and is updated by the host controller. the hcd can use it as a buffer pointer to decide which ptd locations are currently free to ?ll in new ptds to the buffer. this indication is to prevent the hcd from accidentally writing into the currently active ptd buffer location. t ab le 93 shows the bit allocation of the register. code (hex): 1a read only table 91. hcintlptdskipmap register: bit description bit symbol access value description 31 to 0 skipbits[31:0] r/w 0000h 0 the host controller processes the ptd. 1 the host controller skips processing the ptd. table 92. hcintllastptd register: bit description bit symbol access value description 31 to 0 lastptdbits[31:0] r/w 0000h 0 the ptd is not the last ptd stored in the buffer. 1 the ptd is the last ptd stored in the buffer. table 93. hcintlcurrentactiveptd register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol reserved activeptd[4:0] reset - - - 00000 access - - - rrrrr
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 102 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.9 control and bulk transfer (aperiodic transfer) registers 14.9.1 hcatlbuffersize register (r/w: 34h/b4h) this register allows you to allocate the size of the atl buffer to be used for aperiodic transactions. the default value of the buffer size is set to 512 bytes, and the maximum allowable allocated size is 4096 bytes. the bit description of the register is given in t ab le 95 . code (hex): 34 read code (hex): b4 write 14.9.2 hcatlbufferport register (r/w: 44h/c4h) in addition to the hcdirectaddressdata register, the ISP1362 provides this register to act as another data port to access the atl buffer. the starting address to access the buffer is always ?xed at 0000h. therefore, random access of the atl buffer is not allowed. the bit description of the hcatlbufferport register is given in t ab le 96 . code (hex): 44 read code (hex): c4 write the hcd is ?rst required to initialize the hctransfercounter register with the byte count to be transferred and check the hcbufferstatus register. the hcd then sends the command (44h to read from the atl buffer, and c4h to write to the atl buffer) to the host controller through the i/o port of the microprocessor. after the command is sent, the hcd starts reading data from the atl buffer or writing data to the atl buffer. while the hcd is accessing the buffer, the buffer pointer of atl also automatically increases. when the pointer has reached the initialized byte count of the hctransfercounter register, the host controller sets the alleotinterrupt bit of the hc m pinterrupt register to logic 1 and updates the hcbufferstatus register. 14.9.3 hcatlblksize register (r/w: 54h/d4h) the ISP1362 partitions the atl buffer into several equal sized blocks so that the host controller can skip the current ptd and proceed to process the next ptd easily. the block size of the atl buffer must be speci?ed in this register and must be a multiple of 8 bytes. the bit allocation of the hcatlblksize register is given in t ab le 97 . table 94. hcintlcurrentactiveptd register: bit description bit symbol description 15 to 5 - reserved 4 to 0 activeptd[4:0] this 5-bit number represents the ptd that is currently active. table 95. hcatlbuffersize register: bit description bit symbol access value description 15 to 0 atlbuffersize[15:0] r/w 0200h the size of the buffer to be used for aperiodic transactions and must be speci?ed in bytes. table 96. hcatlbufferport register: bit description bit symbol access value description 15 to 0 dataword[15:0] r/w 0000h the data of the atl buffer to be accessed through this data port.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 103 of 152 nxp semiconductors ISP1362 single-chip usb otg controller code (hex): 54 read code (hex): d4 write 14.9.4 hcatlptddonemap register (r: 1bh) this is a 32-bit register. the bit description of the register is given in t ab le 99 . every bit of the register represents the processing status of a ptd. bit 0 of the register represents the ?rst ptd stored in the atl buffer, bit 1 represents the second ptd stored in the buffer, and so on. the register is immediately updated after the completion of each atl ptd processing. it is cleared when read by the hcd. bits that are set represent its corresponding ptds have been processed by the host controller and an ack token has been received from the device. code (hex): 1b read only 14.9.5 hcatlptdskipmap register (r/w: 1ch/9ch) this is a 32-bit register, and the bit description is given in t ab le 100 . bit 0 of the register represents the ?rst ptd stored in the atl buffer, bit 1 represents the second ptd stored in the buffer, and so on. when the bit is set by the hcd, the corresponding ptd is skipped and is not processed by the host controller. the host controller processes the skipped ptd only if the hcd has reset its corresponding skipped bit to logic 0. clearing the corresponding bit in the hcatlptdskipmap register when there is no valid data in the block will cause unpredictable behavior of the host controller. code (hex): 1c read code (hex): 9c write table 97. hcatlblksize register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved blocksize[9:8] reset ------00 access ------r/wr/w bit 7 6 5 4 3 2 1 0 symbol blocksize[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 98. hcatlblksize register: bit description bit symbol description 15 to 10 - reserved 9 to 0 blocksize[9:0] the block size of the atl buffer. table 99. hcatlptddonemap register: bit description bit symbol access value description 31 to 0 ptddonebits [31:0] r 0000h 0 the ptd stored in the atl buffer was not successfully processed by the host controller. 1 the ptd stored in the atl buffer was successfully processed by the host controller.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 104 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.9.6 hcatllastptd register (r/w: 1dh/9dh) this is a 32-bit register. t ab le 101 gives the bit description of the register. bit 0 of the register represents the ?rst ptd stored in the atl buffer, bit 1 represents the second ptd stored in the buffer, and so on. the bit that is set to logic 1 by the hcd is used as an indication to the host controller that its corresponding ptd is the last ptd stored in the atl buffer. when the processing of the last ptd is complete, the host controller loops back to process the ?rst ptd stored in the buffer. code (hex): 1d read code (hex): 9d write 14.9.7 hcatlcurrentactiveptd register (r: 1eh) this register indicates which ptd stored in the atl buffer is currently active and is updated by the host controller. the hcd can use it as a buffer pointer to decide which ptd locations are currently free to ?ll in new ptds to the buffer. this indication helps to prevent the hcd from accidentally writing into the currently active ptd buffer location. t ab le 102 shows the bit allocation of the register. code (hex): 1e read only table 100. hcatlptdskipmap register: bit description bit symbol access value description 31 to 0 skipbits [31:0] r/w 0000h 0 the host controller processes the ptd. 1 the host controller skips processing the ptd. table 101. hcatllastptd register: bit description bit symbol access value description 31 to 0 lastptd bits[31:0] r/w 0000h 0 the ptd is not the last ptd stored in the buffer. 1 the ptd is the last ptd stored in the buffer. table 102. hcatlcurrentactiveptd register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol reserved activeptd[4:0] reset - - - 00000 access - - - rrrrr table 103. hcatlcurrentactiveptd register: bit description bit symbol description 15 to 5 - reserved 4 to 0 activeptd[4:0] this 5-bit number represents the ptd that is currently active.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 105 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 14.9.8 hcatlptddonethresholdcount register (r/w: 51h/d1h) this register speci?es the number of atl ptds to be done to trigger an atl interrupt. if set to 08h, the host controller will trigger the atl interrupt (in the hc m pinterrupt register) once every eight atl ptds are done. t ab le 104 shows the bit allocation of the register. remark: do not write 0000h to this register. code (hex): 51 read code (hex): d1 write 14.9.9 hcatlptddonethresholdtimeout register (r/w: 52h/d2h) this is a time-out register used to generate an atl interrupt. the value in this register indicates the maximum allowable time in milliseconds for the host controller to retry a nak transaction. this register can be used in combination with hcatlptddonethresholdcount. t ab le 106 shows the bit allocation of the hcatlptddonethresholdcount register. remark: if the time-out indication is not required by software, or there is no active ptd in the atl buffer, write 0000h to this register. code (hex): 52 read code (hex): d2 write table 104. hcatlptddonethresholdcount register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol reserved ptddonecount[4:0] reset - - - 00001 access - - - r/w r/w r/w r/w r/w table 105. hcatlptddonethresholdcount register: bit description bit symbol description 15 to 5 - reserved 4 to 0 ptddonecount [4:0] number of ptds to be processed by the host controller to generate an atl interrupt. table 106. hcatlptddonethresholdtimeout register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved reset -------- access -------- bit 7 6 5 4 3 2 1 0 symbol ptddonetimeout[7:0] reset 00000001 access r/w r/w r/w r/w r/w r/w r/w r/w
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 106 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 15. peripheral controller registers the functions and registers of the peripheral controller are accessed using commands, which consist of a command code followed by optional data bytes (read or write action). an overview of the available commands and registers is given in t ab le 108 . a complete access consists of two phases: 1. command phase: when address pin a0 = high, the peripheral controller interprets the data on the lower byte of the bus (bits d7 to d0) as command code. commands without a data phase are immediately executed. 2. data phase (optional): when address pin a0 = low, the peripheral controller transfers the data on the bus to or from a register or endpoint buffer memory. in case of multi-byte registers, the least signi?cant byte or word is accessed ?rst. the following applies to a register or buffer memory access in 16-bit bus mode: ? the upper byte (bits d15 to d8) in the command phase or the unde?ned byte in the data phase are ignored. ? the access of registers is word-aligned: byte access is not allowed. ? if the packet length is odd, the upper byte of the last word in an in endpoint buffer is not transmitted to the host. when reading from an out endpoint buffer, the upper byte of the last word must be ignored by the ?rmware. the packet length is stored in the ?rst two bytes of the endpoint buffer. table 107. hcatlptddonethresholdtimeout register: bit description bit symbol description 15 to 8 - reserved 7 to 0 ptddonetimeout[7:0 ] maximum allowable time in ms for the host controller to retry a transaction with nak returned. table 108. peripheral controller command and register overview name destination code (hex) transaction [1] initialization commands write control out con?guration dcendpointcon?guration register endpoint 0 out 20 write 1 byte [2] write control in con?guration dcendpointcon?guration register endpoint 0 in 21 write 1 byte [2] write endpoint n con?guration (n = 1 to 14) dcendpointcon?guration register endpoint 1 to 14 22 to 2f write 1 byte [2] read control out con?guration dcendpointcon?guration register endpoint 0 out 30 read 1 byte [2] read control in con?guration dcendpointcon?guration register endpoint 0 in 31 read 1 byte [2] read endpoint n con?guration (n = 1 to 14) dcendpointcon?guration register endpoint 1 to 14 32 to 3f read 1 byte [2] write or read device address dcaddress register b6/b7 write or read 1 byte [2] write or read mode register dcmode register b8/b9 write or read 1 byte [2] write or read hardware con?guration dchardwarecon?guration register ba/bb write or read 2 bytes
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 107 of 152 nxp semiconductors ISP1362 single-chip usb otg controller write or read dcinterruptenable register dcinterruptenable register c2/c3 write or read 4 bytes write or read dma con?guration dcdmacon?guration register f0/f1 write or read 2 bytes write or read dma counter dcdmacounter register f2/f3 write or read 2 bytes reset device resets all registers f6 - data ?ow commands write control out buffer illegal: endpoint is read-only (00) - write control in buffer buffer memory endpoint 0 in 01 n 64 bytes write endpoint n buffer (n = 1 to 14) buffer memory endpoint 1 to 14 (in endpoints only) 02 to 0f isochronous: n 1023 bytes interrupt/bulk: n 64 bytes read control out buffer buffer memory endpoint 0 out 10 n 64 bytes read control in buffer illegal: endpoint is write-only (11) - read endpoint n buffer (n = 1 to 14) buffer memory endpoint 1 to 14 (out endpoints only) 12 to 1f isochronous: n 1023 bytes [3] interrupt/bulk: n 64 bytes stall control out endpoint endpoint 0 out 40 - stall control in endpoint endpoint 0 in 41 - stall endpoint n (n = 1 to 14) endpoint 1 to 14 42 to 4f - read control out status dcendpointstatus register endpoint 0 out 50 read 1 byte [2] read control in status dcendpointstatus register endpoint 0 in 51 read 1 byte [2] read endpoint n status (n = 1 to 14) dcendpointstatus register n endpoint 1 to 14 52 to 5f read 1 byte [2] validate control out buffer illegal: in endpoints only [4] (60) - validate control in buffer buffer memory endpoint 0 in [4] 61 - validate endpoint n buffer (n = 1 to 14) buffer memory endpoint 1 to 14 (in endpoints only) [4] 62 to 6f - clear control out buffer buffer memory endpoint 0 out 70 - clear control in buffer illegal [5] (71) - clear endpoint n buffer (n = 1 to 14) buffer memory endpoint 1 to 14 (out endpoints only) [5] 72 to 7f unstall control out endpoint endpoint 0 out 80 - unstall control in endpoint endpoint 0 in 81 - unstall endpoint n (n = 1 to 14) endpoint 1 to 14 82 to 8f - check control out status [6] dcendpointstatusimage register endpoint 0 out d0 read 1 byte [2] check control in status [6] dcendpointstatusimage register endpoint 0 in d1 read 1 byte [2] check endpoint n status (n = 1 to 14) [6] dcendpointstatusimage register n endpoint 1 to 14 d2 to df read 1 byte [2] acknowledge set up endpoint 0 in and out f4 - table 108. peripheral controller command and register overview continued name destination code (hex) transaction [1]
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 108 of 152 nxp semiconductors ISP1362 single-chip usb otg controller [1] with n representing the number of bytes, the number of words for 16-bit bus width is: (n + 1) divided by 2. [2] when accessing an 8-bit register in 16-bit mode, the upper byte is invalid. [3] during the isochronous transfer in 16-bit mode, because n 1023, ?rmware must manage the upper byte. [4] validating an out endpoint buffer causes unpredictable behavior of the peripheral controller. [5] clearing an in endpoint buffer causes unpredictable behavior of the peripheral controller. [6] reads a copy of the status register, executing this command does not clear any status bits or interrupt bits. 15.1 initialization commands initialization commands are used during the enumeration process of the usb network. these commands are used to con?gure and enable embedded endpoints. they also serve to set the usb assigned address of the peripheral controller and to perform a device reset. 15.1.1 dcendpointcon?guration register (r/w: 30h to 3fh/20h to 2fh) this command is used to access the dcendpointcon?guration register (ecr) of the target endpoint. it de?nes the endpoint type (isochronous or bulk/interrupt), direction (out/in), buffer memory size and buffering scheme. it also enables the endpoint buffer memory. the register bit allocation is shown in t ab le 109 . a bus reset will disable all endpoints. the allocation of the buffer memory takes place only after all 16 endpoints have been con?gured in sequence (from endpoint 0 out to endpoint 14). although control endpoints have ?xed con?gurations, they must be included in the initialization sequence and must be con?gured with their default values (see t ab le 14 ). automatic buffer memory allocation starts when endpoint 14 has been con?gured. remark: if any change is made to an endpoint con?guration that affects the allocated memory (size, enable/disable), the buffer memory contents of all endpoints becomes invalid. therefore, all valid data must be removed from enabled endpoints before changing the con?guration. code (hex): 20 to 2f write (control out, control in, endpoints 1 to 14) code (hex): 30 to 3f read (control out, control in, endpoints 1 to 14) transaction write or read 1 byte (code or data) general commands read control out error code dcerrorcode register endpoint 0 out a0 read 1 byte [2] read control in error code dcerrorcode register endpoint 0 in a1 read 1 byte [2] read endpoint n error code (n = 1 to 14) dcerrorcode register endpoint 1 to 14 a2 to af read 1 byte [2] unlock device all registers with write access b0 write 2 bytes write or read dcscratch register dcscratch register b2/b3 write or read 2 bytes read frame number dcframenumber register b4 read 1 byte or 2 bytes read chip id dcchipid register b5 read 2 bytes read dcinterrupt register dcinterrupt register c0 read 4 bytes table 108. peripheral controller command and register overview continued name destination code (hex) transaction [1]
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 109 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 15.1.2 dcaddress register (r/w: b7h/b6h) this command is used to set the usb assigned address in the dcaddress register and enable the usb device. the dcaddress register bit allocation is shown in t ab le 111 . a usb bus reset sets the device address to 00h (internally) and enables the device. the value of the dcaddress register (accessible by the microprocessor) is not altered by the usb bus reset. in response to standard usb request set address, ?rmware must issue a write device address command, followed by sending an empty packet to the host. the new device address is activated when the host acknowledges the empty packet. code (hex): b6/b7 write or read dcaddress register transaction write or read 1 byte (code or data) 15.1.3 dcmode register (r/w: b9h/b8h) this command is used to access the dcmode register, which consists of 1 byte (bit allocation: see t ab le 113 ). in 16-bit bus mode, the upper byte is ignored. the dcmode register controls the dma bus width, resume and suspend modes, interrupt activity, and softconnect operation. it can be used to enable debug mode, in which all errors and not acknowledge (nak) conditions will generate an interrupt. table 109. dcendpointcon?guration register: bit allocation bit 7 6 5 4 3 2 1 0 symbol fifoen epdir dblbuf ffoiso ffosz[3:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 110. dcendpointcon?guration register: bit description bit symbol description 7 fifoen logic 1 enables the fifo buffer. logic 0 disables the fifo buffer. 6 epdir this bit de?nes the endpoint direction (0 = out, 1 = in); it also determines the dma transfer direction (0 = read, 1 = write). 5 dblbuf logic 1 enables the double buffering. 4 ffoiso logic 1 indicates an isochronous endpoint. logic 0 indicates a bulk or interrupt endpoint. 3 to 0 ffosz[3:0] selects the buffer memory size according to t ab le 15 . table 111. dcaddress register: bit allocation bit 7 6 5 4 3 2 1 0 symbol deven devadr[6:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 112. dcaddress register: bit description bit symbol description 7 deven logic 1 enables the device. 6 to 0 devadr[6:0] this ?eld speci?es the usb device address.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 110 of 152 nxp semiconductors ISP1362 single-chip usb otg controller code (hex): b8/b9 write or read dcmode register transaction write or read 1 byte (code or data) [1] unchanged by a bus reset. 15.1.4 dchardwarecon?guration register (r/w: bbh/bah) this command is used to access the dchardwarecon?guration register, which consists of 2 bytes. the ?rst (lower) byte contains the device con?guration and control values, the second (upper) byte holds clock control bits and the clock division factor. the bit allocation is given in t ab le 115 . a bus reset will not change any of programmed bit values. the dchardwarecon?guration register controls the connection to the usb bus, clock activity and power supply during the suspend state, as well as output clock frequency, dma operating mode and pin con?gurations (polarity, signaling mode). code (hex): ba/bb write or read dchardwarecon?guration register transaction write or read 2 bytes (code or data) table 113. dcmode register: bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved gosusp reserved intena dbgmod reserved softct reset 1 [1] 0000 [1] 0 [1] 0 [1] 0 [1] access r/w r/w r/w r/w r/w r/w r/w r/w table 114. dcmode register: bit description bit symbol description 7 to 6 - reserved 5 gosusp writing logic 1 followed by logic 0 will activate suspend mode. 4 - reserved 3 intena logic 1 enables all interrupts. bus reset value: unchanged. 2 dbgmod logic 1 enables debug mode, in which all naks and errors will generate an interrupt. logic 0 selects normal operation, in which interrupts are generated on every ack (bulk or interrupt endpoints) or after every data transfer (isochronous endpoints). bus reset value: unchanged. 1 - reserved 0 softct logic 1 enables softconnect. this bit is ignored if extpul = 1 in the dchardwarecon?guration register (see t ab le 115 ). bus reset value: unchanged. remark: in otg mode, this bit is ignored. the loc_conn bit of the otgcontrol register controls the pull-up resistor on the otg_dp1 pin. table 115. dchardwarecon?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved extpul nolazy clkrun ckdiv[3:0] reset - 0100011 access - r/w r/w r/w r/w r/w r/w r/w
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 111 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 15.1.5 dcinterruptenable register (r/w: c3h/c2h) this command is used to individually enable or disable interrupts from all endpoints, as well as interrupts caused by events on the usb bus (sof, eot, suspend, resume, reset). a bus reset will not change any of the programmed bit values. bit 7 6 5 4 3 2 1 0 symbol dakoly drqpol dakpol reserved wkupcs reserved intlvl intpol reset 01000100 access r/w r/w r/w - r/w r/w r/w r/w table 116. dchardwarecon?guration register: bit description bit symbol description 15 - reserved 14 extpul logic 1 indicates that an external 1.5 k w pull-up resistor is used on pin otg_dp1 (in device mode) and that softconnect is not used. bus reset value: unchanged. 13 nolazy logic 1 disables output on pin clkout of the lazyclock frequency (115 khz 50 %) during the suspend state. logic 0 causes pin clkout to switch to lazyclock output after approximately 2 ms delay, following the setting of bit gosusp of the dcmode register. bus reset value: unchanged. 12 clkrun logic 1 indicates that internal clocks are always running, even during the suspend state. logic 0 switches off the internal oscillator and pll, when they are not needed. during the suspend state, this bit must be made logic 0 to meet suspend current requirements. the clock is stopped after a delay of approximately 2 ms, following the setting of bit gosusp of the dcmode register. bus reset value: unchanged. 11 to 8 ckdiv[3:0] this ?eld speci?es clock division factor n, which controls the clock frequency on output clkout pin. the output frequency in mhz is given by . the clock frequency range is 3 mhz to 48 mhz (n = 0 to 15), with a reset value of 12 mhz (n = 3). the hardware design guarantees no glitches during frequency change. bus reset value: unchanged. 7 dakoly logic 1 selects dack-only dma mode. logic 0 selects 8237 compatible dma mode. bus reset value: unchanged. 6 drqpol selects the dreq2 pin signal polarity (0 = active low; 1 = active high). bus reset value: unchanged. 5 dakpol selects the d a ck2 pin signal polarity (0 = active low; 1 = active high). bus reset value: unchanged. 4 - reserved 3 wkupcs logic 1 enables remote wake-up using a low level on input cs. bus reset value: unchanged. 2 - reserved 1 intlvl selects interrupt signaling mode on output (0 = level; 1 = pulsed). in pulsed mode, an interrupt produces 166 ns pulse. bus reset value: unchanged. 0 intpol selects the int2 signal polarity (0 = active low; 1 = active high). bus reset value: unchanged. 48 n 1 + ()
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 112 of 152 nxp semiconductors ISP1362 single-chip usb otg controller the command accesses the dcinterruptenable register, which consists of 4 bytes. the bit allocation is given in t ab le 117 . code (hex): c2/c3 write or read dcinterruptenable register transaction write or read 4 bytes (code or data) table 117. dcinterruptenable register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access -------- bit 23 22 21 20 19 18 17 16 symbol iep14 iep13 iep12 iep11 iep10 iep9 iep8 iep7 reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol iep6 iep5 iep4 iep3 iep2 iep1 iep0in iep0out reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved sp_ieeot iepsof iesof ieeot iesusp ieresm ierst reset - 0000000 access - r/w r/w r/w r/w r/w r/w r/w table 118. dcinterruptenable register: bit description bit symbol description 31 to 24 - reserved; must write logic 0 23 to 10 iep14 to iep1 logic 1 enables interrupts from the indicated endpoint. logic 0 disables interrupts from the indicated endpoint. 9 iep0in logic 1 enables interrupts from the control in endpoint. logic 0 disables interrupts from the control in endpoint. 8 iep0out logic 1 enables interrupts from the control out endpoint. logic 0 disables interrupts from the control out endpoint. 7 - reserved 6 sp_ieeot logic 1 enables interrupt on detecting a short packet. logic 0 disables interrupt. 5 iepsof logic 1 enables 1 ms interrupts on detecting pseudo sof. logic 0 disables interrupts. 4 iesof logic 1 enables interrupt on the sof detection. logic 0 disables interrupt. 3 ieeot logic 1 enables interrupt on the eot detection. logic 0 disables interrupt.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 113 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 15.1.6 dcdmacon?guration (r/w: f1h/f0h) this command de?nes the dma con?guration of the peripheral controller, and enables or disables dma transfers. the command accesses the dcdmacon?guration register, which consists of two bytes. the bit allocation is given in t ab le 119 . a bus reset will clear bit dmaen (dma disabled), all other bits remain unchanged. code (hex): f0/f1 write or read dma con?guration transaction write or read 2 bytes (code or data) [1] unchanged by a bus reset. 2 iesusp logic 1 enables interrupt on detecting a suspend state. logic 0 disables interrupt. 1 ieresm logic 1 enables interrupt on detecting a resume state. logic 0 disables interrupt. 0 ierst logic 1 enables interrupt on detecting a bus reset. logic 0 disables interrupt. table 118. dcinterruptenable register: bit description continued bit symbol description table 119. dcdmacon?guration register: bit allocation bit 15 14 13 12 11 10 9 8 symbol cntren shortp reserved reset 0 [1] 0 [1] ------ access r/wr/w------ bit 7 6 5 4 3 2 1 0 symbol epdix[3:0] dmaen reserved burstl[1:0] reset 0 [1] 0 [1] 0 [1] 0 [1] 0-0 [1] 0 [1] access r/w r/w r/w r/w r/w - r/w r/w table 120. dcdmacon?guration register: bit description bit symbol description 15 cntren logic 1 enables the generation of an eot condition, when the dcdmacounter register reaches zero. bus reset value: unchanged. 14 shortp logic 1 enables short or empty packet mode. when receiving (out endpoint) a short or empty packet, an eot condition is generated. when transmitting (in endpoint), this bit must be cleared. bus reset value: unchanged. 13 to 8 - reserved 7 to 4 epdix[3:0] indicates the destination endpoint for dma, see t ab le 17 .
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 114 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 15.1.7 dcdmacounter register (r/w: f3h/f2h) this command accesses the dcdmacounter register, which consists of two bytes. the bit allocation is given in t ab le 121 . writing to the register sets the number of bytes for a dma transfer. reading the register returns the number of remaining bytes in the current transfer. a bus reset will not change programmed bit values. the internal dma counter is automatically reloaded from the dcdmacounter register. for details, see section 15.1.6 . code (hex): f2/f3 write or read dcdmacounter register transaction write or read 2 bytes (code or data) 15.1.8 reset device (f6h) this command resets the peripheral controller in the same way as an external hardware reset by using input reset. all registers are initialized to their reset values. code (hex): f6 reset the device transaction none (code only) 3 dmaen writing logic 1 enables dma transfer, logic 0 forces the end of an ongoing dma transfer. reading this bit indicates whether dma is enabled or not (0 = dma stopped; 1 = dma enabled). this bit is cleared by a bus reset. 2 - reserved 1 to 0 burstl[1:0] selects the dma burst length: 00 single-cycle mode (1 byte) 01 burst mode (4 bytes) 10 burst mode (8 bytes) 11 burst mode (16 bytes) bus reset value: unchanged. table 120. dcdmacon?guration register: bit description continued bit symbol description table 121. dcdmacounter register: bit allocation bit 15 14 13 12 11 10 9 8 symbol dmacr[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dmacr[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 122. dcdmacounter register: bit description bit symbol description 15 to 0 dmacr[15:0] this ?eld indicates the number of bytes for a dma transfer.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 115 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 15.2 data ?ow commands data ?ow commands are used to manage data transmission between usb endpoints and the system microprocessor. much of the data ?ow is initiated using an interrupt to the microprocessor. data ?ow commands are used to access endpoints and determine whether the endpoint buffer memory contains valid data. remark: the in buffer of an endpoint contains input data for the host. the out buffer receives output data from the host. 15.2.1 write or read endpoint buffer (r/w: 10h,12h to 1fh/01h to 0fh) this command is used to access endpoint buffer memory to read/write. first, the buffer pointer is reset to the start of the buffer. following the command, a maximum of (n + 2) bytes can be written or read, n represents the size of the endpoint buffer. for 16-bit access, the maximum number of words is (m + 1), with m given as (n + 1) divided by 2. after each read or write action, the buffer pointer is automatically incremented by two. in direct memory access (dma), the ?rst two bytes or the ?rst word (the packet length) is skipped: transfers start at the third byte or the second word of the endpoint buffer. when reading, the peripheral controller can detect the last byte or word by using the eop condition. when writing to a bulk or interrupt endpoint, the endpoint buffer must be completely ?lled before sending data to the host. exception: when a dma transfer is stopped by an external eot condition, the current buffer content (full or not) is sent to the host. remark: reading data after a write endpoint buffer command or writing data after a read endpoint buffer command data will cause unpredictable behavior of the peripheral controller. code (hex): 01 to 0f write (control in, endpoints 1 to 14) code (hex): 10, 12 to 1f read (control out, endpoints 1 to 14) transaction write or read maximum n+2b ytes (isochronous endpoint: n 1023, bulk/interrupt endpoint: n 32) (code or data) the data in the endpoint buffer memory must be organized as shown in t ab le 123 . an example of endpoint buffer memory access is given in t ab le 124 . table 123. endpoint buffer memory organization word # description 0 (lower byte) packet length (lower byte) 0 (upper byte) packet length (upper byte) 1 (lower byte) data byte 1 1 (upper byte) data byte 2 m = (n + 1) / 2 data byte n
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 116 of 152 nxp semiconductors ISP1362 single-chip usb otg controller remark: there is no protection against writing or reading past a buffers boundary, against writing into an out buffer or reading from an in buffer. any of these actions can cause an incorrect operation. data residing in an out buffer is only meaningful after a successful transaction. exception: during the dma access of a double-buffered endpoint, the buffer pointer automatically points to the secondary buffer after reaching the end of the primary buffer. 15.2.2 read endpoint status (r: 50h to 5fh) this command is used to read the status of an endpoint buffer memory. the command accesses the dcendpointstatus register, the bit allocation of which is shown in t ab le 125 . reading the dcendpointstatus register will clear the interrupt bit set for the corresponding endpoint in the dcinterrupt register (see t ab le 141 ). all bits of the dcendpointstatus register are read-only. bit epstal is controlled by the stall or unstall commands and by the reception of a set-up token (see section 15.2.3 ). code (hex): 50 to 5f read (control out, control in, endpoints 1 to 14) transaction read 1 byte (code only) table 124. example of endpoint buffer memory access a0 phase bus lines word # description high command d[7:0] - command code (00h to 1fh) d[15:8] - ignored low data d[15:0] 0 packet length low data d[15:0] 1 data word 1 (data byte 2, data byte 1) low data d[15:0] 2 data word 2 (data byte 4, data byte 3) table 125. dcendpointstatus register: bit allocation bit 7 6 5 4 3 2 1 0 symbol epstal epfull1 epfull0 data_pid over write setupt cpubuf reserved reset 0000000 - access rrrrrrr - table 126. dcendpointstatus register: bit description bit symbol description 7 epstal this bit indicates whether the endpoint is stalled or not (1 = stalled; 0 = not stalled). set to logic 1 by a stall endpoint command, cleared to logic 0 by an unstall endpoint command. the endpoint is automatically unstalled on receiving a set-up token. 6 epfull1 logic 1 indicates that the secondary endpoint buffer is full. 5 epfull0 logic 1 indicates that the primary endpoint buffer is full. 4 data_pid this bit indicates data pid of the next packet (0 = data pid; 1 = data1 pid).
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 117 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 15.2.3 stall endpoint or unstall endpoint (40h to 4fh/80h to 8fh) these commands are used to stall or unstall an endpoint. the commands modify the content of the dcendpointstatus register (see t ab le 125 ). a stalled control endpoint is automatically unstalled when it receives a set-up token, regardless of the packet content. if the endpoint must stay in its stalled state, the microprocessor can re-stall it with the stall endpoint command. when a stalled endpoint is unstalled (either by using the unstall endpoint command or by receiving a set-up token), it is also re-initialized. this ?ushes the buffer: if it is an out buffer, it waits for a data 0 pid; if it is an in buffer, it writes a data 0 pid. code (hex): 40 to 4f stall (control out, control in, endpoints 1 to 14) code (hex): 80 to 8f unstall (control out, control in, endpoints 1 to 14) transaction none (code only) 15.2.4 validate endpoint buffer (61h to 6fh) this command signals the presence of valid data for transmission to the usb host. the validation occurs by setting the buffer full ?ag of the selected in endpoint. this indicates that the data in the buffer is valid and can be sent to the host, when the next in token is received. for a double-buffered endpoint, this command switches the current buffer memory for cpu access. remark: for special aspects of the control in endpoint, see section 12.3.6 . code (hex): 61 to 6f validate endpoint buffer (control in, endpoints 1 to 14) transaction none (code only) 15.2.5 clear endpoint buffer (70h, 72h to 7fh) this command unlocks and clears the buffer of the selected out endpoint, allowing the reception of new packets. reception of a complete packet causes the buffer full ?ag of an out endpoint to be set. any subsequent packets are refused by returning a nak condition, until the buffer is unlocked using this command. for a double-buffered endpoint, this command switches the current buffer memory for cpu access. remark: for special aspects of the control out endpoint, see section 12.3.6 . 3 overwrite this bit is set by hardware. logic 1 indicates that a new set-up packet has overwritten the previous set-up information, before it was acknowledged or before the endpoint was stalled. once writing of the set-up data is completed, a read back of this register clears this bit. firmware must check this bit before sending an acknowledge set-up command or stalling the endpoint. on reading logic 1, ?rmware must stop ongoing set-up actions and wait for a new set-up packet. 2 setupt logic 1 indicates that the buffer contains a set-up packet. 1 cpubuf this bit indicates which buffer is currently selected for the cpu access (0 = primary buffer; 1 = secondary buffer). 0 - reserved table 126. dcendpointstatus register: bit description continued bit symbol description
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 118 of 152 nxp semiconductors ISP1362 single-chip usb otg controller code (hex): 70, 72 to 7f clear endpoint buffer (control out, endpoints 1 to 14) transaction none (code only) 15.2.6 dcendpointstatusimage register (d0h to dfh) this command is used to check the status of the selected endpoint buffer memory, without clearing any status or interrupt bits. the command accesses the dcendpointstatusimage register, which contains a copy of the dcendpointstatus register. the bit allocation of the dcendpointstatusimage register is shown in t ab le 127 . code (hex): d0 to df check status (control out, control in, endpoints 1 to 14) transaction write or read 1 byte (code or data) 15.2.7 acknowledge set up (f4h) this command acknowledges to the host that a set-up packet is received. the arrival of a set-up packet disables the validate buffer and clear buffer commands for the control in and out endpoints. the microprocessor must re-enable these commands by sending an acknowledge set-up command, see section 12.3.6 . code (hex): f4 acknowledge set up transaction none (code only) table 127. dcendpointstatusimage register: bit allocation bit 7 6 5 4 3 2 1 0 symbol epstal epfull1 epfull0 data_pid over write setupt cpubuf reserved reset 0000000 - access rrrrrrr - table 128. dcendpointstatusimage register: bit description bit symbol description 7 epstal this bit indicates whether the endpoint is stalled or not (1 = stalled; 0 = not stalled). 6 epfull1 logic 1 indicates that the secondary endpoint buffer is full. 5 epfull0 logic 1 indicates that the primary endpoint buffer is full. 4 data_pid this bit indicates data pid of the next packet (0 = data0 pid; 1 = data1 pid). 3 overwrite this bit is set by hardware. logic 1 indicates that a new set-up packet has overwritten the previous set-up information, before it was acknowledged or before the endpoint was stalled. once writing of the set-up data is completed, a read back of this register clears this bit. firmware must check this bit before sending an acknowledge set-up command or stalling the endpoint. on reading logic 1, ?rmware must stop ongoing set-up actions and wait for a new set-up packet. 2 setupt logic 1 indicates that the buffer contains a set-up packet. 1 cpubuf this bit indicates which buffer is currently selected for cpu access (0 = primary buffer; 1 = secondary buffer). 0 - reserved
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 119 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 15.3 general commands 15.3.1 read endpoint error code (r: a0h to afh) this command returns the status of the last transaction of the selected endpoint, as stored in the dcerrorcode register. each new transaction overwrites the previous status information. the bit allocation of the dcerrorcode register is shown in t ab le 129 . code (hex): a0 to af read error code (control out, control in, endpoints 1 to 14) transaction read 1 byte (code or data) table 129. dcerrorcode register: bit allocation bit 7 6 5 4 3 2 1 0 symbol unread data01 reserved error[3:0] rtok reset 00 - 00000 access rr - rrrrr table 130. dcerrorcode register: bit description bit symbol description 7 unread logic 1 indicates that a new event occurred before the previous status is read. 6 data01 this bit indicates the pid type of the last successfully received or transmitted packet (0 = data0 pid; 1 = data1 pid). 5 - reserved 4 to 1 error[3:0] error code. for error description, see t ab le 131 . 0 rtok logic 1 indicates that data was successfully received or transmitted. table 131. transaction error codes error code (binary) description 0000 no error 0001 pid encoding error; bits 7 to 4 are not the inverse of bits 3 to 0 0010 pid unknown; encoding is valid, but pid does not exist 0011 unexpected packet; packet is not of the expected type (token, data or acknowledge) or is a set-up token to a non-control endpoint 0100 token crc error 0101 data crc error 0110 time-out error 0111 babble error 1000 unexpected end-of-packet 1001 sent or received nak (not acknowledge) 1010 sent stall; a token was received, but the endpoint was stalled 1011 over?ow; the received packet was larger than the available buffer space 1100 sent empty packet (iso only) 1101 bit stuf?ng error 1110 sync error 1111 wrong (unexpected) toggle bit in data pid; data was ignored
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 120 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 15.3.2 unlock device (b0h) this command unlocks the peripheral controller from write-protection mode after a resume. in the suspend state, all registers and buffer memory are write-protected to prevent data corruption by external devices during a resume. also, the register access to read is possible only after the unlock device command is executed. after waking up from the suspend state, ?rmware must unlock registers and buffer memory by using this command, by writing the unlock code (aa37h) into the dclock register (8-bit bus: lower byte ?rst). the bit allocation of the dclock register is given in t ab le 132 . code (hex): b0 unlock the device transaction write 2 bytes (unlock code) (code or data) 15.3.3 dcscratch register (r/w: b3h/b2h) this command accesses the 16-bit dcscratch register, which can be used by ?rmware to save and restore information. for example, the device status before powering down in the suspend state. the register bit allocation is given in t ab le 134 . code (hex): b2/b3 write or read dcscratch register transaction write or read 2 bytes (code or data) table 132. dclock register: bit allocation bit 15 14 13 12 11 10 9 8 symbol unlock[15:8] = aah reset 10101010 access wwwwwwww bit 7 6 5 4 3 2 1 0 symbol unlock[7:0] = 37h reset 00110111 access wwwwwwww table 133. dclock register: bit description bit symbol description 15 to 0 unlock[15:0] sending data aa37h unlocks internal registers and buffer memory to write, following a resume. table 134. dcscratch information register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved sfir[12:8] reset - - - 00000 access - - - r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol sfir[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 121 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 15.3.4 dcframenumber register (r: b4h) this command returns the frame number of the last successfully received sof. it is followed by reading one word from the dcframenumber register, containing the frame number. the dcframenumber register is shown in t ab le 136 . remark: after a bus reset, the value of the dcframenumber register is unde?ned. code (hex): b4 read frame number transaction read 1 byte or 2 bytes (code or data) [1] reset value unde?ned after a bus reset. 15.3.5 dcchipid (r: b5h) this command reads the chip identi?cation code and hardware version number. the ?rmware must check this information to determine supported functions and features. this command accesses the dcchipid register, which is shown in t ab le 139 . code (hex): b5 read chip id transaction read 2 bytes (code or data) table 135. dcscratch information register: bit description bit symbol description 15 to 13 - reserved; must be logic 0 12 to 0 sfir[12:0] scratch information register table 136. dcframenumber register: bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved sofr[9:8] reset [1] -----000 access -----rrr bit 7 6 5 4 3 2 1 0 symbol sofr[7:0] reset [1] 00000000 access rrrrrrrr table 137. dcframenumber register: bit description bit symbol description 15 to 11 - reserved 10 to 0 sofr[9:0] frame number table 138. example of the dcframenumber register access a0 phase bus lines word# description high command d[15:8] - ignored d[7:0] - command code (b4h) low data d[15:0] 0 frame number
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 122 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 15.3.6 dcinterrupt register (r: c0h) this command indicates the sources of interrupts as stored in the 4 bytes dcinterrupt register. each individual endpoint has its own interrupt bit. the bit allocation of the dcinterrupt register is shown in t ab le 141 . bit bustatus is used to verify the current bus status in the interrupt service routine. interrupts are enabled using the dcinterruptenable register, see section 15.1.5 . while reading the dcinterrupt register, it is recommended that both 2 bytes words are read completely. code (hex): c0 read dcinterrupt register transaction read 4 bytes (code or data) table 139. dcchipid register: bit allocation bit 15 14 13 12 11 10 9 8 symbol chipidh[7:0] reset 00110110 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol chipidl[7:0] reset 00110000 access rrrrrrrr table 140. dcchipid register: bit description bit symbol description 15 to 8 chipidh[7:0] chip id code (36h) 7 to 0 chipidl[7:0] silicon version (30h, with 30 representing the bcd encoded version number) table 141. dcinterrupt register: bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved reset -------- access -------- bit 23 22 21 20 19 18 17 16 symbol ep14 ep13 ep12 ep11 ep10 ep9 ep8 ep7 reset 00000000 access rrrrrrrr bit 15 14 13 12 11 10 9 8 symbol ep6 ep5 ep4 ep3 ep2 ep1 ep0in ep0out reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol bustatus sp_eot psof sof eot suspnd resume reset reset 00000000 access rrrrrrrr
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 123 of 152 nxp semiconductors ISP1362 single-chip usb otg controller table 142. dcinterrupt register: bit description bit symbol description 31 to 24 - reserved 23 to 10 ep14 to ep1 logic 1 indicates the interrupt source(s): endpoints 14 to 1. 9 ep0in logic 1 indicates the interrupt source: control in endpoint. 8 ep0out logic 1 indicates the interrupt source: control out endpoint. 7 bustatus monitors the current usb bus status (0 = awake, 1 = suspend). 6 sp_eot logic 1 indicates that an eot interrupt has occurred for a short period. 5 psof logic 1 indicates that an interrupt is issued every 1 ms because of the pseudo sof; after three missed sofs, the suspend state is entered. 4 sof logic 1 indicates that an sof condition was detected. 3 eot logic 1 indicates that an internal eot condition was generated by the dma counter reaching zero. 2 suspnd logic 1 indicates that an awake to suspend change of state was detected on the usb bus. 1 resume logic 1 indicates that a resume state was detected. 0 reset logic 1 indicates that a bus reset condition was detected.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 124 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 16. limiting values [1] equivalent to discharging a 100 pf capacitor through a 1.5 k w resistor (human body model). 17. recommended operating conditions [1] input voltage on digital i/o lines. table 143. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage - 0.5 +4.6 v v i input voltage - 0.5 +6.0 v i lu latch-up current v i < 0 v or v i > v cc - 100 ma v esd electrostatic discharge voltage i li < 1 m a [1] - 2000 +2000 v t stg storage temperature - 60 +150 c table 144. recommended operating conditions dp represents otg_dp1 and h_dp2, and dm represents otg_dm1 and h_dm2. symbol parameter conditions min typ max unit v cc supply voltage 3.0 3.3 3.6 v v i input voltage 3.3 v tolerant pins [1] 0 3.3 3.6 v 5 v tolerant pins [1] 0 5.0 5.5 v on pin x1 when external clock is used 3.0 3.3 3.6 v v ia(i/o) input voltage on analog i/o lines pins dp and dm 0 - 3.6 v v o(od) open-drain output pull-up voltage 5 v tolerant pins 0 - 5.5 v non 5 v tolerant pins 0 - 3.6 v t amb ambient temperature - 40 - +85 c
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 125 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 18. static characteristics [1] the power consumption on the charge pump is not included. [1] not applicable for open-drain outputs. [2] these values are applicable to transistor inputs. the value will be different if internal pull-up or pull-down resistors are used. table 145. static characteristics: supply pins v cc = 3.3 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit i cc(hc) operating supply current for the host controller peripheral controller suspended -33- ma i cc(dc) operating supply current for the peripheral controller host controller suspended - 20 - ma i cc(hc+dc) operating supply current for the host and the device -50- ma i cc(susp) suspend supply current host controller and peripheral controller are suspended [1] -60- m a table 146. static characteristics: digital pins v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit input levels v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v schmitt-trigger inputs v th(lh) positive-going threshold voltage 1.4 - 1.9 v v th(hl) negative-going threshold voltage 0.9 - 1.5 v v hys hysteresis voltage 0.4 - 0.7 v output levels v ol low-level output voltage i ol = 4 ma - - 0.4 v i ol = 20 m a - - 0.1 v v oh high-level output voltage i oh = 4 ma [1] 2.4 - - v i oh = 20 m av cc - 0.1 v - - v leakage current i li input leakage current [2] - 5-+5 m a c in pin capacitance pin to gnd - - 5 pf open-drain outputs i oz off-state output current - 5-+5 m a
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 126 of 152 nxp semiconductors ISP1362 single-chip usb otg controller [1] dp represents otg_dp1 and h_dp2, and dm represents otg_dm1 and h_dm2. d+ is the usb positive data line and d - is the usb negative data line. [2] includes external resistors of 18 w 10 % on h_dp2 and h_dm2, and 27 w 10 % on otg_dp1 and otg_dm1. [3] in suspend mode, the minimum voltage is 2.7 v. table 147. static characteristics: analog i/o pins (d+, d - ) v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. [1] symbol parameter conditions min typ max unit input levels v di differential input sensitivity | v i(d+) - v i(d - ) | 0.2 - - v v cm differential common mode voltage includes v di range 0.8 - 2.5 v v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v output levels v ol low-level output voltage r l = 1.5 k w to +3.6 v - - 0.3 v v oh high-level output voltage r l = 15 k w to gnd 2.8 - 3.6 v leakage current i lz off-state leakage current - 10 - +10 m a capacitance c in transceiver capacitance pin to gnd - - 10 pf resistance r pd(otg) pull-down resistance on pins otg_dp1 and otg_dm1 enable internal resistors 14.25 - 24.8 k w r pd(h) pull-down resistance on pins h_dp2 and h_dm2 enable internal resistors 10 - 20 k w r pu(otg) pull-up resistance on otg_dp1 bus idle 900 - 1575 w bus driven 1425 - 3090 w z drv driver output impedance steady-state drive [2] 29 - 44 w z inp input impedance 10 - - m w termination v term termination voltage for upstream port pull up (r pu ) [3] 3.0 - 3.6 v table 148. static characteristics: charge pump v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; c load = 2 m f; unless otherwise speci?ed. symbol parameter conditions min typ max unit v bus regulated v bus voltage i load = 8 ma from v bus(otg) ; see figure 29 - 5 5.25 v i load maximum load current external capacitor of 27 nf; v cc = 3.0 v to 3.6 v --8ma external capacitor of 82 nf; v cc = 3.0 v to 3.3 v - - 14 ma external capacitor of 82 nf; v cc = 3.3 v to 3.6 v - - 20 ma c load output capacitance 1 - 6.5 m f v bus(leak) v bus(otg) leakage voltage v bus(otg) not driven - - 0.2 v
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 127 of 152 nxp semiconductors ISP1362 single-chip usb otg controller i cc(cp)(susp) suspend supply current for charge pump globalpowerdown bit of the hchardwarecon?guration register is logic 0 --45 m a globalpowerdown bit of the hchardwarecon?guration register is logic 1 --15 m a i cc(cp) operating supply current in charge pump mode atx is idle i load = 8 ma - - 20 ma i load = 0 ma - - 300 m a v th(vbus_vld) v bus valid threshold 4.4 - - v v th(sess_end) v bus session end threshold 0.2 - 0.8 v v hys(sess_end) v bus session end hysteresis - 150 - mv v th(asess_vld) v bus a valid threshold 0.8 - 2 v v hys(asess_vld) v bus a valid hysteresis - 200 - mv v th(bsess_vld) v bus b valid threshold 2 - 4 v v hys(bsess_vld) v bus b valid hysteresis - 200 - mv e ef?ciency when loaded i load = 8 ma; v in = 3 v; see figure 28 -75-% i vbus(leak) leakage current from v bus -15- m a r vbus(pu) v bus pull-up resistance pull to v cc when enabled 281 - - w r vbus(pd) v bus pull-down resistance pull to gnd when enabled 656 - - w r vbus(idle) v bus idle impedance for the a-device when id = low and drv_vbus = 0 40 - 100 k w r vbus(active) v bus active pull-down impedance when id = high and drv_vbus =1 - 350 - k w table 148. static characteristics: charge pump continued v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; c load = 2 m f; unless otherwise speci?ed. symbol parameter conditions min typ max unit 82 nf charge pump capacitor. fig 28. ef?ciency as a function of load current i load (ma) 0 25 20 10 15 5 001aaf829 40 60 20 80 100 e efficiency (%) 0 v cc = 3.0 v 3.3 v 3.6 v
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 128 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 82 nf charge pump capacitor. fig 29. output voltage as a function of load current i load (ma) 0 25 20 10 15 5 001aaf830 4.8 5.0 5.2 v bus (v) 4.6 v cc = 3.6 v 3.3 v 3.0 v
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 129 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 19. dynamic characteristics [1] dependent on the crystal oscillator startup time. [2] tolerance of the clock frequency is 50 ppm. [1] dp represents otg_dp1 and h_dp2, and dm represents otg_dm1 and h_dm2. test circuit. [2] excluding the ?rst transition from the idle state. [3] characterized only, not tested. limits guaranteed by design. table 149. dynamic characteristics v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit reset t w( reset) pulse width on input reset crystal oscillator running 10 - - ms crystal oscillator stopped [1] ---ms crystal oscillator f xtal crystal frequency [2] - 12 - mhz r s series resistance - - 100 w c load load capacitance c x1 , c x2 = 22 pf - 12 - pf external clock input j external clock jitter - - 500 ps t duty clock duty cycle 45 50 55 % t cr rise time - - 3 ns t cf fall time - - 3 ns table 150. dynamic characteristics: analog i/o lines (d+, d - ) v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; c l = 50 pf; r pu = 1.5 k w 5 % on dp to v term ; unless otherwise speci?ed. [1] symbol parameter conditions min typ max unit driver characteristics t fr rise time c l = 50 pf; 10 % to 90 % of | v oh - v ol | 4 - 20 ns t ff fall time c l = 50 pf; 90 % to 10 % of | v oh - v ol | 4 - 20 ns frfm differential rise time/fall time matching (t fr /t ff ) [2] 90 - 111.11 % v crs output signal crossover voltage [2] [3] 1.3 - 2.0 v table 151. dynamic characteristics: charge pump v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; c load =2 m f; unless otherwise speci?ed. symbol parameter conditions min typ max unit driver characteristics t start-up rise time to v bus = 4.4 v i load = 8 ma; c load = 10 m f - - 100 ms t comp_clk clock period 1.5 - 3 m s t vbus(valid_dly) minimum time v bus(valid) error 100 - 200 m s
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 130 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 19.1 programmed i/o timing ? if you are accessing only the host controller, then the host controller programmed i/o timing applies. ? if you are accessing only the peripheral controller, then the peripheral controller programmed i/o timing applies. ? if you are accessing both the host controller and the peripheral controller, then the peripheral controller programmed i/o timing applies. 19.1.1 host controller programmed i/o timing t vbus(pulse) v bus pulsing time 10 - 30 ms t vbus(valid_dly) v bus pull-down time 50 - - ms v ripple output ripple with constant load i load = 8ma --50mv table 151. dynamic characteristics: charge pump continued v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; c load =2 m f; unless otherwise speci?ed. symbol parameter conditions min typ max unit table 152. dynamic characteristics: host controller programmed interface timing v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit t as address set-up time before cs 5 - - ns t ah address hold time after wr 2 - - ns read timing t shsl_r ?rst rd/ wr after command (a0 = high) register access 300 - - ns t shsl_b ?rst rd/ wr after command (a0 = high) buffer access 462 - - ns t slrl cs low to rd low 0 - - ns t rhsh rd high to cs high 0 - - ns t rl rd low pulse width 33 - - ns t rhrl rd high to next rd low 110 - - ns t rc rd cycle 143 - - ns t rhdz rd data hold time - - 3 ns t rldv rd low to data valid - - 22 ns write timing t wl wr low pulse width 26 - - ns t whwl wr high to next wr low 110 - - ns t wc wr cycle 136 - - ns t slwl cs low to wr low 0 - - ns t whsh wr high to cs high 0 - - ns t wdsu wr data set-up time 3 - - ns t wdh wr data hold time 4 - - ns
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 131 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 19.1.2 peripheral controller programmed i/o timing fig 30. host controller programmed interface timing mgt969 a0 d [ 15:0 ] d [ 15:0 ] wr rd cs data valid data valid data valid data valid data valid data valid data valid data valid data valid t shsl t rlrh t rhrl t rldv t wl t whwl t wdh t wdsu t rc t wc t rhdz t slrl t rhsh t slwl t whsh t ah t as table 153. dynamic characteristics: peripheral controller programmed interface timing v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit read timing (see figure 31 ) t rhax address hold time after rd high 0 - - ns t avrl address set-up time before rd low 0 - - ns t shdz data outputs high-impedance time after cs high --3ns t rhsh chip deselect time after rd high 0 - - ns t rlrh rd pulse width 25 - - ns t rldv data valid time after rd low - - 22 ns t shrl cs high until next ISP1362 rd 120 - - ns t shrl + t rlrh + t rhsh read cycle time 180 - - ns write timing (see figure 32 ) t whax address hold time after wr high 1 - - ns t avwl address set-up time before wr low 0 - - ns t shwl cs high until next ISP1362 wr 120 - - ns t shwl +t wlwh +t whsh write cycle time [1] 180 - - ns t wlwh wr pulse width 22 - - ns
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 132 of 152 nxp semiconductors ISP1362 single-chip usb otg controller [1] in the command to data phase, the minimum value of the write command to the read data or write data cycle time must be 205 ns . t whsh chip deselect time after wr high 0 - - ns t dvwh data set-up time before wr high 5 - - ns t whdz data hold time after wr high 3 - - ns table 153. dynamic characteristics: peripheral controller programmed interface timing continued v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit (1) for t shrl both cs and rd must be de-asserted. (2) programmable polarity: shown as active low. fig 31. peripheral controller programmed interface read timing (i/o and 8237 compatible dma) 004aaa105 a0 t rhax t avrl t rlrh t rldv t shdz t shrl (1) d[15:0] rd cs/dack2 (2) t rhsh
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 133 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 19.2 dma timing 19.2.1 host controller single-cycle dma timing [1] t rhal + t ds + t alrl (1) for t shwl , both cs and wr must be de-asserted. (2) programmable polarity: shown as active low. fig 32. peripheral controller programmed interface write timing (i/o and 8237 compatible dma) 004aaa106 cs/dack2 (2) a0 d[15:0] wr t whax t avwl t whdz t dvwh t wlwh t whsh t shwl (1) table 154. dynamic characteristics: host controller single-cycle dma timing v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit read/write timing t rl rd pulse width 33 - - ns t rldv read process data set-up time 30 - - ns t rhdz read process data hold time 0 - - ns t wsu write process data set-up time 5 - - ns t whd write process data hold time 0 - - ns t ahrh d a ck1 high to dreq1 high 72 - - ns t alrl d a ck1 low to dreq1 low - - 21 ns t dc dreq1 cycle [1] --ns t shah rd/ wr high to d a ck1 high 0 - - ns t rhal dreq1 high to d a ck1 low 0 - - ns t ds dreq1 pulse spacing 146 - - ns
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 134 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 19.2.2 host controller burst mode dma timing [1] t slal + (4 or 8)t rc + t ds fig 33. host controller single-cycle dma timing 004aaa107 dreq1 dack1 d [ 15:0 ] (read) d [ 15:0 ] (write) rd or wr t ds t ahrh t dc data valid data valid t alrl t rhal t whd t wsu t rldv t rhdz t shah table 155. dynamic characteristics: host controller burst mode dma timing v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit read/write timing (for 4-cycle and 8-cycle burst mode) t rl rd/ wr low pulse width 42 - - ns t rhrl rd/ wr high to next rd/ wr low 60 - - ns t rc rd/ wr cycle 102 - - ns t slrl rd/ wr low to dreq1 low 22 - 64 ns t shah rd/ wr high to d a ck1 high 0 - - ns t rhal dreq1 high to d a ck1 low 0 - ns t dc dreq1 cycle [1] --ns t ds(read) dreq1 pulse spacing (read) 4-cycle burst mode 105 - - ns 8-cycle burst mode 150 - - ns t ds(write) dreq1 pulse spacing (write) 4-cycle burst mode 72 - - ns 8-cycle burst mode 167 - - ns
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 135 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 19.2.3 peripheral controller single-cycle dma timing (8237 mode) 19.2.4 peripheral controller single-cycle dma read timing in dack-only mode fig 34. host controller burst mode dma timing 004aaa108 t rhrl t ds t rhsh dreq1 dack1 rd or wr t slrl t shah t rlrh t rc t rhal table 156. dynamic characteristics: peripheral controller single-cycle dma timing (8237 mode) v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit t asrp dreq2 off after d a ck2 on - - 40 ns t cy(dreq2) cycle time signal dreq2 180 - - ns (1) programmable polarity: shown as active low. fig 35. peripheral controller single-cycle dma timing (8237 mode) 004aaa111 dreq2 dack2 (1) t asrp t rc table 157. dynamic characteristics: peripheral controller single-cycle dma read timing in dack-only mode v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit t asrp dreq off after d a ck on - - 40 ns t asap d a ck pulse width 25 - - ns t asap + t aprs dreq on after d a ck off 180 - - ns t asdv data valid after d a ck on - - 22 ns t apdz data hold after d a ck off - - 3 ns
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 136 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 19.2.5 peripheral controller single-cycle dma write timing in dack-only mode (1) programmable polarity: shown as active low. fig 36. peripheral controller single-cycle dma read timing in dack-only mode 004aaa112 dack2 (1) dreq2 t asrp t aprs t asdv t apdz data t asap table 158. dynamic characteristics: peripheral controller single-cycle dma write timing in dack-only mode v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit t asrp dreq2 off after d a ck2 on - - 40 ns t asap d a ck2 pulse width 25 - - ns t asap + t aprs dreq2 on after d a ck2 off 180 - - ns t asdv data valid after d a ck2 on - - 22 ns t apdz data hold after d a ck2 off - - 3 ns (1) programmable polarity: shown as active low. fig 37. peripheral controller single-cycle dma write timing in dack-only mode 004aaa113 dack2 (1) dreq2 t asrp t aprs t asdv t apdz data t asap
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 137 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 19.2.6 peripheral controller burst mode dma timing table 159. dynamic characteristics: peripheral controller burst mode dma timing v cc = 3.0 v to 3.6 v; gnd = 0 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit t rsih input rd/ wr high after dreq on 22 - - ns t ilrp dreq off after input rd/ wr low ---ns t ihap d a ck off after input rd/ wr high 0 - 60 ns t ihil dma burst repeat interval (input rd/ wr high to low) t rl or t wl is 30 ns (min) 160 - - ns (1) programmable polarity: shown as active low. fig 38. peripheral controller burst mode dma timing 004aaa115 dack2 (1) dreq2 t rsih t ilrp t ihil t ihap rd or wr
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 138 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 20. package outline fig 39. package outline sot314-2 (lqfp64) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 139 of 152 nxp semiconductors ISP1362 single-chip usb otg controller fig 40. package outline sot543-1 (tfbga64) ball a1 index area 0.5 a 1 b a 2 unit d y e references outline version european projection issue date 00-11-22 02-04-09 iec jedec jeita mm 1.1 0.25 0.15 0.85 0.75 6.1 5.9 y 1 6.1 5.9 0.35 0.25 0.08 dimensions (mm are the original dimensions) sot543-1 mo-195 - - - - - - e 0.15 0.1 e 1 4.5 e 2 4.5 v 0.05 w 0 2.5 5 mm scale sot543-1 tfbga64: plastic thin fine-pitch ball grid array package; 64 balls; body 6 x 6 x 0.8 mm a max. a a 2 a 1 detail x x d e a b c d e f h j k g 2468910 1357 b a ball a1 index area y y 1 c e e e 1 b c e 2 1/2 e 1/2 e a c c b ? v m ? w m
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 140 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 21. soldering this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 21.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 21.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus pbsn soldering 21.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 141 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 21.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 41 ) than a pbsn process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 160 and 161 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 41 . table 160. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 161. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 142 of 152 nxp semiconductors ISP1362 single-chip usb otg controller for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 22. abbreviations msl: moisture sensitivity level fig 41. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 162. abbreviations acronym description ack acknowledge asic application-speci?c integrated circuit atl asynchronous transfer list atx analog usb transceiver cmos complementary metal-oxide semiconductor crc cyclic redundancy check dma direct memory access dsc digital still camera ed endpoint descriptor ehci enhanced host controller interface emi electromagnetic interference eof end-of-frame eop end-of-packet eot end-of-transfer esr equivalent series resistance gps global positioning system hc host controller hcca host controller communication area hcd host controller driver
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 143 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 23. references [1] on-the-go supplement to the usb 2.0 speci?cation rev. 1.0a [2] universal serial bus speci?cation rev. 2.0 [3] isp136x embedded programming guide (um10008) [4] open host controller interface speci?cation for usb release 1.0a [5] interrupt control application note hnp host negotiation protocol intl interrupt transfer list is implementation-speci?c iso isochronous isr interrupt service routine istl isochronous transfer list ls low-speed mosfet metal-oxide semiconductor field-effect transistor msb most signi?cant bit nak not acknowledged ohci open host controller interface opr operational otg on-the-go pda personal digital assistant pid packet identi?er pio programmed input/output pll phase-locked loop pmos positive metal-oxide semiconductor por power-on reset porp power-on reset pulse post power-on self test ptd philips transfer descriptor risc reduced instruction set computing sie serial interface engine sof start-of-frame srp session request protocol td transfer descriptor usb universal serial bus usbd universal serial bus device table 162. abbreviations continued acronym description
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 144 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 24. revision history table 163. revision history document id release date data sheet status change notice supersedes ISP1362_5 20070508 product data sheet - ISP1362-04 modi?cations: ? the format of this data sheet has been redesigned to comply with the new presentation and information standard of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? section 2 f eatures : updated. ? t ab le 2 pin descr iption : removed table note all i/o pads are 5 v tolerant. ? t ab le 29 otginterr uptenab le register : bit descr iption : updated description for all the bits. ? section 14 host controller registers : updated the ?rst paragraph. ? t ab le 36 hcre vision register : bit descr iption : updated description for bits 7 to 0. ? t ab le 38 hccontrol register : bit descr iption : updated description for bits 7 to 6. ? section 14.1.4 hcinterr uptstatus register (r/w: 03h/83h) : updated the ?rst paragraph. ? t ab le 42 hcinterr uptstatus register : bit descr iption : updated description for bits 6 and 0. ? t ab le 46 hcinterr uptdisab le register : bit descr iption : updated description for bit 31. ? t ab le 52 hcfmnumber register : bit descr iption : updated description for bits 15 to 0. ? section 14.2.4 hclsthreshold register (r/w: 11h/91h) : updated the ?rst paragraph. ? t ab le 54 hclsthreshold register : bit descr iption : updated description for bits 10 to 0. ? section 14.3 hc root hub registers : updated the last paragraph. ? t ab le 56 hcrhdescr iptora register : bit descr iption : updated description for bits 1 to 0. ? section 14.3.2 hcrhdescr iptorb register (r/w: 13h/93h) : updated the ?rst paragraph. ? section 14.3.4 hcrhp or tstatus[1:2] register (r/w [1]: 15h/95h; [2]: 16h/96h) : updated the ?rst paragraph. ? t ab le 64 hchardw arecon? gur ation register : bit descr iption : updated description for bits 8, 6 and 5. ? section 14.4.4 hcmpinterr upt register (r/w: 24h/a4h) : removed the second paragraph. ? t ab le 75 hcsoftw arereset register : bit descr iption : updated the description column. ? section 14.9.8 hca tlptddonethresholdcount register (r/w: 51h/d1h) : updated the ?rst paragraph. ? t ab le 105 hca tlptddonethresholdcount register : bit descr iption : updated description for bits 4to0. ? section 14.9.9 hca tlptddonethresholdtimeout register (r/w: 52h/d2h) : updated the ?rst paragraph. ? t ab le 110 dcendpointcon? gur ation register : bit descr iption : updated description for bits 7 and 5. ? t ab le 114 dcmode register : bit descr iption : updated description for bit 2. ? section 15.1.5 dcinterr uptenab le register (r/w: c3h/c2h) : updated the ?rst paragraph. ? t ab le 118 dcinterr uptenab le register : bit descr iption : updated the description column. ? section 15.1.7 dcdma counter register (r/w: f3h/f2h) : updated the second paragraph. ? t ab le 122 dcdma counter register : bit descr iption : added description for bits 15 to 0. ? t ab le 126 dcendpointstatus register : bit descr iption : updated description for bit 3. ? t ab le 128 dcendpointstatusimage register : bit descr iption : updated description for bit 3. ? t ab le 144 recommended oper ating conditions : added v i(clk) and removed 1.8 v tolerant under v i . ? section 19.1 prog r ammed i/o timing and section 19.2 dma timing : added conditions to tables. ? t ab le 152 dynamic char acter istics: host controller prog r ammed interf ace timing : updated description for t ah .
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 145 of 152 nxp semiconductors ISP1362 single-chip usb otg controller ISP1362-04 (9397 750 13957) 20041224 product data - ISP1362-03 ISP1362-03 (9397 750 12337) 20040106 product data - ISP1362-02 ISP1362-02 (9397 750 10767) 20030219 product data - ISP1362-01 ISP1362-01 (9397 750 10087) 20021120 preliminary data - - table 163. revision history continued document id release date data sheet status change notice supersedes
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 146 of 152 nxp semiconductors ISP1362 single-chip usb otg controller 25. legal information 25.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 25.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 25.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 25.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. goodlink is a trademark of nxp b.v. softconnect is a trademark of nxp b.v. 26. contact information for additional information, please visit: http://www .nxp.com for sales of?ce addresses, send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 147 of 152 continued >> nxp semiconductors ISP1362 single-chip usb otg controller 27. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .4 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 3. bus access priority table for the ISP1362 . . . .13 table 4. buffer memory areas and their applications . .14 table 5. i/o port addressing . . . . . . . . . . . . . . . . . . . . .20 table 6. registers used in addressing modes . . . . . . . .25 table 7. recommended capacitor values . . . . . . . . . . .38 table 8. port 1 function . . . . . . . . . . . . . . . . . . . . . . . . .40 table 9. generic ptd structure: bit allocation . . . . . . . .42 table 10. special ?elds for atl, interrupt and iso . . . . .42 table 11. generic ptd structure: bit description . . . . . . .43 table 12. atl buffer area . . . . . . . . . . . . . . . . . . . . . . . .45 table 13. interrupt polling . . . . . . . . . . . . . . . . . . . . . . . .46 table 14. endpoint access and programmability . . . . . . .52 table 15. programmable buffer memory size . . . . . . . . .53 table 16. memory con?guration example . . . . . . . . . . . .53 table 17. endpoint selection for the dma transfer . . . . .55 table 18. 8237 compatible mode: pin functions . . . . . . .55 table 19. summary of eot conditions for a bulk endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 20. recommended eot usage for isochronous endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 21. otg control registers overview . . . . . . . . . . . .60 table 22. otgcontrol register: bit allocation . . . . . . . . . .60 table 23. otgcontrol register: bit description . . . . . . . . .61 table 24. otgstatus register: bit allocation . . . . . . . . . . .62 table 25. otgstatus register: bit description . . . . . . . . . .62 table 26. otginterrupt register: bit allocation . . . . . . . . .63 table 27. otginterrupt register: bit description . . . . . . . .64 table 28. otginterruptenable register: bit allocation . . . .65 table 29. otginterruptenable register: bit description . . .65 table 30. otgtimer register: bit allocation . . . . . . . . . . . .66 table 31. otgtimer register: bit description . . . . . . . . . .67 table 32. otgalttimer register: bit allocation . . . . . . . . .67 table 33. otgalttimer register: bit description . . . . . . . .68 table 34. host controller registers overview . . . . . . . . . .68 table 35. hcrevision register: bit allocation . . . . . . . . . .70 table 36. hcrevision register: bit description . . . . . . . . .70 table 37. hccontrol register: bit allocation . . . . . . . . . . .70 table 38. hccontrol register: bit description . . . . . . . . . .71 table 39. hccommandstatus register: bit allocation . . .72 table 40. hccommandstatus register: bit description . .73 table 41. hcinterruptstatus register: bit allocation . . . . .73 table 42. hcinterruptstatus register: bit description . . . .74 table 43. hcinterruptenable register: bit allocation . . . . .74 table 44. hcinterruptenable register: bit description . . .75 table 45. hcinterruptdisable register: bit allocation . . . .76 table 46. hcinterruptdisable register: bit description . . .76 table 47. hcfminterval register: bit allocation . . . . . . . . 77 table 48. hcfminterval register: bit description . . . . . . . 77 table 49. hcfmremaining register: bit allocation . . . . . 78 table 50. hcfmremaining register: bit description . . . . 78 table 51. hcfmnumber register: bit allocation . . . . . . . . 79 table 52. hcfmnumber register: bit description . . . . . . 79 table 53. hclsthreshold register: bit allocation . . . . . . 79 table 54. hclsthreshold register: bit description . . . . . 80 table 55. hcrhdescriptora register: bit description . . . . 81 table 56. hcrhdescriptora register: bit description . . . . 81 table 57. hcrhdescriptorb register: bit allocation . . . . . 82 table 58. hcrhdescriptorb register: bit description . . . . 83 table 59. hcrhstatus register: bit allocation . . . . . . . . . 83 table 60. hcrhstatus register: bit description . . . . . . . . 84 table 61. hcrhportstatus[1:2] register: bit allocation . . 84 table 62. hcrhportstatus[1:2] register: bit description . 85 table 63. hchardwarecon?guration register: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 64. hchardwarecon?guration register: bit description . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 65. hcdmacon?guration register: bit allocation . . 90 table 66. hcdmacon?guration register: bit description . 90 table 67. buffer_type_select[2:0]: bit description . . . . . 91 table 68. hctransfercounter register: bit description . . . 91 table 69. hcmpinterrupt register: bit allocation . . . . . . . 92 table 70. hcmpinterrupt register: bit description . . . . . . 92 table 71. hcmpinterruptenable register: bit allocation . . 93 table 72. hcmpinterruptenable register: bit description 94 table 73. hcchipid register: bit description . . . . . . . . . . 94 table 74. hcscratch register: bit description . . . . . . . . . 95 table 75. hcsoftwarereset register: bit description . . . . 95 table 76. hcbufferstatus register: bit allocation . . . . . . . 95 table 77. hcbufferstatus register: bit description . . . . . . 95 table 78. hcdirectaddresslength register: bit allocation 96 table 79. hcdirectaddresslength register: bit description . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 80. hcdirectaddressdata register: bit description 97 table 81. hcistlbuffersize register: bit description . . . 97 table 82. hcistl0bufferport register: bit description . . . 98 table 83. hcistl1bufferport register: bit description . . . 98 table 84. hcistltogglerate register: bit allocation . . . . 98 table 85. hcistltogglerate register: bit description . . . 99 table 86. hcintlbuffersize register: bit description . . . 99 table 87. hcintlbufferport register: bit description . . . . 99 table 88. hcintlblksize register: bit allocation . . . . . . 100 table 89. hcintlblksize register: bit description . . . . . 100 table 90. hcintlptddonemap register: bit description . . . . . . . . . . . . . . . . . . . . . . . . 100
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 148 of 152 continued >> nxp semiconductors ISP1362 single-chip usb otg controller table 91. hcintlptdskipmap register: bit description 101 table 92. hcintllastptd register: bit description . . . .101 table 93. hcintlcurrentactiveptd register: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .101 table 94. hcintlcurrentactiveptd register: bit description . . . . . . . . . . . . . . . . . . . . . . . .102 table 95. hcatlbuffersize register: bit description . . .102 table 96. hcatlbufferport register: bit description . . . .102 table 97. hcatlblksize register: bit allocation . . . . . . .103 table 98. hcatlblksize register: bit description . . . . . .103 table 99. hcatlptddonemap register: bit description 103 table 100.hcatlptdskipmap register: bit description .104 table 101.hcatllastptd register: bit description . . . . .104 table 102.hcatlcurrentactiveptd register: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .104 table 103.hcatlcurrentactiveptd register: bit description . . . . . . . . . . . . . . . . . . . . . . . .104 table 104.hcatlptddonethresholdcount register: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .105 table 105.hcatlptddonethresholdcount register: bit description . . . . . . . . . . . . . . . . . . . . . . . .105 table 106.hcatlptddonethresholdtimeout register: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .105 table 107.hcatlptddonethresholdtimeout register: bit description . . . . . . . . . . . . . . . . . . . . . . . .106 table 108.peripheral controller command and register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 table 109.dcendpointcon?guration register: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .109 table 110.dcendpointcon?guration register: bit description . . . . . . . . . . . . . . . . . . . . . . . .109 table 111.dcaddress register: bit allocation . . . . . . . . .109 table 112.dcaddress register: bit description . . . . . . . .109 table 113.dcmode register: bit allocation . . . . . . . . . . .110 table 114.dcmode register: bit description . . . . . . . . . .110 table 115.dchardwarecon?guration register: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .110 table 116.dchardwarecon?guration register: bit description . . . . . . . . . . . . . . . . . . . . . . . .111 table 117.dcinterruptenable register: bit allocation . . . .112 table 118.dcinterruptenable register: bit description . .112 table 119.dcdmacon?guration register: bit allocation .113 table 120.dcdmacon?guration register: bit description 113 table 121.dcdmacounter register: bit allocation . . . . . .114 table 122.dcdmacounter register: bit description . . . .114 table 123.endpoint buffer memory organization . . . . . .115 table 124.example of endpoint buffer memory access .116 table 125.dcendpointstatus register: bit allocation . . . .116 table 126.dcendpointstatus register: bit description . . .116 table 127.dcendpointstatusimage register: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .118 table 128.dcendpointstatusimage register: bit description . . . . . . . . . . . . . . . . . . . . . . . . 118 table 129.dcerrorcode register: bit allocation . . . . . . . 119 table 130.dcerrorcode register: bit description . . . . . . 119 table 131.transaction error codes . . . . . . . . . . . . . . . . . 119 table 132.dclock register: bit allocation . . . . . . . . . . . . 120 table 133.dclock register: bit description . . . . . . . . . . . 120 table 134.dcscratch information register: bit allocation 120 table 135.dcscratch information register: bit description . . . . . . . . . . . . . . . . . . . . . . . . 121 table 136.dcframenumber register: bit allocation . . . . 121 table 137.dcframenumber register: bit description . . . 121 table 138.example of the dcframenumber register access . . . . . . . . . . . . . . . . . . . . . . . 121 table 139.dcchipid register: bit allocation . . . . . . . . . . 122 table 140.dcchipid register: bit description . . . . . . . . . 122 table 141.dcinterrupt register: bit allocation . . . . . . . . . 122 table 142.dcinterrupt register: bit description . . . . . . . . 123 table 143.limiting values . . . . . . . . . . . . . . . . . . . . . . . . 124 table 144.recommended operating conditions . . . . . . . 124 table 145.static characteristics: supply pins . . . . . . . . . 125 table 146.static characteristics: digital pins . . . . . . . . . 125 table 147.static characteristics: analog i/o pins (d+, d - ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 148.static characteristics: charge pump . . . . . . . 126 table 149.dynamic characteristics . . . . . . . . . . . . . . . . 129 table 150.dynamic characteristics: analog i/o lines (d+, d - ) . . . . . . . . . . . . . . . . . . . . . . . . 129 table 151.dynamic characteristics: charge pump . . . . . 129 table 152.dynamic characteristics: host controller programmed interface timing . . . . . . . . . . . . . 130 table 153.dynamic characteristics: peripheral controller programmed interface timing . . . . 131 table 154.dynamic characteristics: host controller single-cycle dma timing . . . . . . . . . . . . . . . . 133 table 155.dynamic characteristics: host controller burst mode dma timing . . . . . . . . . . . . . . . . . . . . . 134 table 156.dynamic characteristics: peripheral controller single-cycle dma timing (8237 mode) . . . . . 135 table 157.dynamic characteristics: peripheral controller single-cycle dma read timing in dack-only mode . . . . . . . . . . . . . . . . . . . . . . 135 table 158.dynamic characteristics: peripheral controller single-cycle dma write timing in dack-only mode . . . . . . . . . . . . . . . . . . . . . . 136 table 159.dynamic characteristics: peripheral controller burst mode dma timing . . . . . . . . 137 table 160.snpb eutectic process (from j-std-020c) . . 141 table 161.lead-free process (from j-std-020c) . . . . . 141 table 162.abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 163.revision history . . . . . . . . . . . . . . . . . . . . . . . 144
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 149 of 152 continued >> nxp semiconductors ISP1362 single-chip usb otg controller 28. figures fig 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 fig 2. pin con?guration lqfp64 . . . . . . . . . . . . . . . . . . .6 fig 3. pin con?guration tfbga64 . . . . . . . . . . . . . . . . . .6 fig 4. recommended values of the ISP1362 buffer memory allocation . . . . . . . . . . . . . . . . . . . . . . . .15 fig 5. a sample snapshot of the atl or intl memory management scheme . . . . . . . . . . . . . . . . . . . . .16 fig 6. a sample snapshot of the istl memory management scheme . . . . . . . . . . . . . . . . . . . . .17 fig 7. peripheral controller buffer memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 fig 8. pio interface between a microprocessor and the ISP1362 . . . . . . . . . . . . . . . . . . . . . . . . .19 fig 9. dma interface between a microprocessor and the ISP1362 . . . . . . . . . . . . . . . . . . . . . . . . .19 fig 10. microprocessor access to the host controller or the peripheral controller . . . . . . . . . . . . . . . . .20 fig 11. access to internal control registers . . . . . . . . . . .21 fig 12. pio register access . . . . . . . . . . . . . . . . . . . . . . .21 fig 13. pio access for a 16-bit or 32-bit register . . . . . . .22 fig 14. hc and otg interrupt logic . . . . . . . . . . . . . . . . .27 fig 15. internal power-on reset timing . . . . . . . . . . . . . . .30 fig 16. clock with respect to the external power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . .30 fig 17. hnp sequence of events . . . . . . . . . . . . . . . . . . .33 fig 18. dual-role a-device state diagram. . . . . . . . . . . . .35 fig 19. dual-role b-device state diagram. . . . . . . . . . . . .36 fig 20. external capacitors connection . . . . . . . . . . . . . .38 fig 21. usb host controller states of the ISP1362 . . . . .39 fig 22. ptd data stored in the buffer memory. . . . . . . . .41 fig 23. using internal overcurrent detection circuit . . . . .47 fig 24. using external overcurrent detection circuit . . . . .48 fig 25. using internal charge pump. . . . . . . . . . . . . . . . .48 fig 26. peripheral controller in 8327 compatible dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 fig 27. suspend and resume timing . . . . . . . . . . . . . . . .59 fig 28. ef?ciency as a function of load current . . . . . . .127 fig 29. output voltage as a function of load current . . .128 fig 30. host controller programmed interface timing . .131 fig 31. peripheral controller programmed interface read timing (i/o and 8237 compatible dma) . . .132 fig 32. peripheral controller programmed interface write timing (i/o and 8237 compatible dma) . . .133 fig 33. host controller single-cycle dma timing . . . . . .134 fig 34. host controller burst mode dma timing . . . . . .135 fig 35. peripheral controller single-cycle dma timing (8237 mode). . . . . . . . . . . . . . . . . . . . . . . . . . . .135 fig 36. peripheral controller single-cycle dma read timing in dack-only mode . . . . . . . . . . . . . . . . 136 fig 37. peripheral controller single-cycle dma write timing in dack-only mode . . . . . . . . . . . . 136 fig 38. peripheral controller burst mode dma timing . . 137 fig 39. package outline sot314-2 (lqfp64). . . . . . . . 138 fig 40. package outline sot543-1 (tfbga64) . . . . . . 139 fig 41. temperature pro?les for large and small components. . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 150 of 152 continued >> nxp semiconductors ISP1362 single-chip usb otg controller 29. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.1 host/peripheral roles. . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 4 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 functional description . . . . . . . . . . . . . . . . . . 12 7.1 on-the-go (otg) controller. . . . . . . . . . . . . . 12 7.2 advanced nxp slave host controller. . . . . . . 12 7.3 nxp peripheral controller. . . . . . . . . . . . . . . . 12 7.4 phase-locked loop (pll) clock multiplier . . . 12 7.5 usb and otg transceivers . . . . . . . . . . . . . . 12 7.6 overcurrent protection . . . . . . . . . . . . . . . . . . 12 7.7 bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.8 peripheral controller and host controller buffer memory. . . . . . . . . . . . . . . . . . . . . . . . . 12 7.9 goodlink . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.10 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 host and device bus interface . . . . . . . . . . . . 13 8.1 memory organization . . . . . . . . . . . . . . . . . . . 14 8.1.1 memory organization for the host controller . 14 8.1.2 memory organization for the peripheral controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.2 pio access mode . . . . . . . . . . . . . . . . . . . . . . 18 8.3 dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.4 pio access to internal control registers . . . . . 20 8.5 pio access to the buffer memory . . . . . . . . . . 23 8.5.1 pio access to the buffer memory by using direct addressing . . . . . . . . . . . . . . . . . . . . . . 23 8.5.2 pio access to the buffer memory by using indirect addressing . . . . . . . . . . . . . . . . . . . . . 24 8.6 setting up a dma transfer . . . . . . . . . . . . . . . 25 8.6.1 con?guring registers for a dma transfer . . . . 25 8.6.2 combining the two dma channels . . . . . . . . . 26 8.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.7.1 interrupt in the host controller and the otg controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.7.2 interrupt in the peripheral controller. . . . . . . . 28 8.7.3 combining int1 and int2 . . . . . . . . . . . . . . . 29 8.7.4 behavior difference between level-triggered and edge-triggered interrupts . . . . . . . . . . . . . 29 8.7.4.1 level-triggered interrupt . . . . . . . . . . . . . . . . . 29 8.7.4.2 edge-triggered interrupt . . . . . . . . . . . . . . . . . 29 9 power-on reset (por) . . . . . . . . . . . . . . . . . . 30 10 on-the-go (otg) controller . . . . . . . . . . . . . 31 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.2 dual-role device . . . . . . . . . . . . . . . . . . . . . . . 31 10.3 session request protocol (srp) . . . . . . . . . . 32 10.3.1 b-device initiating srp. . . . . . . . . . . . . . . . . . 32 10.3.2 a-device responding to srp . . . . . . . . . . . . . 32 10.4 host negotiation protocol (hnp) . . . . . . . . . . 33 10.4.1 sequence of hnp events . . . . . . . . . . . . . . . . 33 10.4.2 otg state diagrams . . . . . . . . . . . . . . . . . . . . 34 10.4.3 hnp implementation and otg state machine 36 10.5 power saving in the idle state and during wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.6 current capacity of the otg charge pump . . 37 11 usb host controller (hc) . . . . . . . . . . . . . . . . 38 11.1 usb states of the host controller . . . . . . . . . 38 11.2 usb traf?c generation . . . . . . . . . . . . . . . . . . 39 11.3 usb ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.4 philips transfer descriptor (ptd). . . . . . . . . . 40 11.5 features of the control and bulk transfer (aperiodic transfer) . . . . . . . . . . . . . . . . . . . . . 44 11.5.1 sending a usb device request (get descriptor) . . . . . . . . . . . . . . . . . . . . . . . 45 11.5.1.1 step 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.5.1.2 step 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.5.1.3 step 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.5.1.4 step 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.5.1.5 step 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.6 features of the interrupt transfer . . . . . . . . . . 46 11.7 features of the isochronous (iso) transfer . . 46 11.8 overcurrent protection circuit . . . . . . . . . . . . . 46 11.8.1 using internal overcurrent detection circuit . . 46 11.8.2 using external overcurrent detection circuit . . 47 11.8.3 overcurrent detection circuit using internal charge pump in otg mode . . . . . . . . . . . . . . 48 11.8.4 overcurrent detection circuit using external 5 v power source in otg mode . . . . . . . . . . . 49 11.9 ISP1362 host controller power management 49 12 usb peripheral controller . . . . . . . . . . . . . . . 49 12.1 peripheral controller data transfer operation . 50 12.1.1 in data transfer. . . . . . . . . . . . . . . . . . . . . . . . 50 12.1.2 out data transfer. . . . . . . . . . . . . . . . . . . . . . 50 12.2 device dma transfer . . . . . . . . . . . . . . . . . . . 51 12.2.1 dma for an in endpoint (internal peripheral controller to the external usb host) . . . . . . . 51 12.2.2 dma for out endpoint (external usb host to internal peripheral controller) . . . . . . . . . . 51
ISP1362_5 ? nxp b.v. 2007. all rights reserved. product data sheet rev. 05 8 may 2007 151 of 152 continued >> nxp semiconductors ISP1362 single-chip usb otg controller 12.3 endpoint description . . . . . . . . . . . . . . . . . . . . 52 12.3.1 endpoints with programmable buffer memory size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.3.2 endpoint access . . . . . . . . . . . . . . . . . . . . . . . 52 12.3.3 endpoint buffer memory size . . . . . . . . . . . . . 52 12.3.4 endpoint initialization . . . . . . . . . . . . . . . . . . . 53 12.3.5 endpoint i/o mode access . . . . . . . . . . . . . . . 54 12.3.6 special actions on control endpoints . . . . . . . 54 12.4 peripheral controller dma transfer . . . . . . . . . 54 12.4.1 selecting an endpoint for the dma transfer . . 55 12.4.2 8237 compatible mode . . . . . . . . . . . . . . . . . . 55 12.4.3 end-of-transfer conditions . . . . . . . . . . . . . . . 57 12.4.3.1 bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . . 57 12.4.3.2 isochronous endpoints . . . . . . . . . . . . . . . . . . 58 12.5 ISP1362 peripheral controller suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.5.1 suspend conditions . . . . . . . . . . . . . . . . . . . . 58 12.5.2 resume conditions . . . . . . . . . . . . . . . . . . . . . 59 13 otg registers . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.1 otgcontrol register (r/w: 62h/e2h) . . . . . . . . 60 13.2 otgstatus register (r: 67h). . . . . . . . . . . . . . . 62 13.3 otginterrupt register (r/w: 68h/e8h) . . . . . . . 63 13.4 otginterruptenable register (r/w: 69h/e9h). . 65 13.5 otgtimer register (r/w: 6ah/eah) . . . . . . . . . 66 13.6 otgalttimer register (r/w: 6ch/ech). . . . . . . 67 14 host controller registers. . . . . . . . . . . . . . . . . 68 14.1 hc control and status registers . . . . . . . . . . . 70 14.1.1 hcrevision register (r: 00h). . . . . . . . . . . . . . 70 14.1.2 hccontrol register (r/w: 01h/81h) . . . . . . . . . 70 14.1.3 hccommandstatus register (r/w: 02h/82h) . 72 14.1.4 hcinterruptstatus register (r/w: 03h/83h) . . . 73 14.1.5 hcinterruptenable register (r/w: 04h/84h) . . 74 14.1.6 hcinterruptdisable register (r/w: 05h/85h) . . 75 14.2 hc frame counter registers. . . . . . . . . . . . . . . 76 14.2.1 hcfminterval register (r/w: 0dh/8dh). . . . . . 76 14.2.2 hcfmremaining register (r/w: 0eh/8eh) . . . 77 14.2.3 hcfmnumber register (r/w: 0fh/8fh). . . . . . 78 14.2.4 hclsthreshold register (r/w: 11h/91h). . . . . 79 14.3 hc root hub registers . . . . . . . . . . . . . . . . . . . 80 14.3.1 hcrhdescriptora register (r/w: 12h/92h) . . . 80 14.3.2 hcrhdescriptorb register (r/w: 13h/93h) . . . 82 14.3.3 hcrhstatus register (r/w: 14h/94h) . . . . . . . 83 14.3.4 hcrhportstatus[1:2] register (r/w [1]: 15h/95h; [2]: 16h/96h). . . . . . . . . . . . . . . . . . . 84 14.4 hc dma and interrupt control registers . . . . . 88 14.4.1 hchardwarecon?guration register (r/w: 20h/a0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.4.2 hcdmacon?guration register (r/w: 21h/a1h) 90 14.4.3 hctransfercounter register (r/w: 22h/a2h) . . 91 14.4.4 hcmpinterrupt register (r/w: 24h/a4h) . . . . . 91 14.4.5 hcmpinterruptenable register (r/w: 25h/a5h) 93 14.5 hc miscellaneous registers . . . . . . . . . . . . . . 94 14.5.1 hcchipid register (r: 27h). . . . . . . . . . . . . . . 94 14.5.2 hcscratch register (r/w: 28h/a8h) . . . . . . . . 94 14.5.3 hcsoftwarereset register (w: a9h) . . . . . . . . 95 14.6 hc buffer ram control registers . . . . . . . . . . 95 14.6.1 hcbufferstatus register (r/w: 2ch/ach) . . . . 95 14.6.2 hcdirectaddresslength register (r/w: 32h/b2h) . . . . . . . . . . . . . . . . . . . . . . . 96 14.6.3 hcdirectaddressdata register (r/w: 45h/c5h) 97 14.7 isochronous (iso) transfer registers . . . . . . . 97 14.7.1 hcistlbuffersize register (r/w: 30h/b0h) . . 97 14.7.2 hcistl0bufferport register (r/w: 40h/c0h) . 97 14.7.3 hcistl1bufferport register (r/w: 42h/c2h) . 98 14.7.4 hcistltogglerate register (r/w: 47h/c7h) . 98 14.8 interrupt transfer registers . . . . . . . . . . . . . . . 99 14.8.1 hcintlbuffersize register (r/w: 33h/b3h) . . 99 14.8.2 hcintlbufferport register (r/w: 43h/c3h) . . 99 14.8.3 hcintlblksize register (r/w: 53h/d3h) . . . 100 14.8.4 hcintlptddonemap register (r: 17h) . . . . 100 14.8.5 hcintlptdskipmap register (r/w: 18h/98h) 100 14.8.6 hcintllastptd register (r/w: 19h/99h). . . 101 14.8.7 hcintlcurrentactiveptd register (r: 1ah). 101 14.9 control and bulk transfer (aperiodic transfer) registers . . . . . . . . . . . . 102 14.9.1 hcatlbuffersize register (r/w: 34h/b4h) . . 102 14.9.2 hcatlbufferport register (r/w: 44h/c4h) . . 102 14.9.3 hcatlblksize register (r/w: 54h/d4h) . . . . 102 14.9.4 hcatlptddonemap register (r: 1bh) . . . . 103 14.9.5 hcatlptdskipmap register (r/w: 1ch/9ch) 103 14.9.6 hcatllastptd register (r/w: 1dh/9dh) . . . 104 14.9.7 hcatlcurrentactiveptd register (r: 1eh) . 104 14.9.8 hcatlptddonethresholdcount register (r/w: 51h/d1h) . . . . . . . . . . . . . . . . . . . . . . 105 14.9.9 hcatlptddonethresholdtimeout register (r/w: 52h/d2h) . . . . . . . . . . . . . . . . . . . . . . 105 15 peripheral controller registers. . . . . . . . . . . 106 15.1 initialization commands . . . . . . . . . . . . . . . . 108 15.1.1 dcendpointcon?guration register (r/w: 30h to 3fh/20h to 2fh). . . . . . . . . . . . . . . . . 108 15.1.2 dcaddress register (r/w: b7h/b6h) . . . . . . 109 15.1.3 dcmode register (r/w: b9h/b8h). . . . . . . . . 109 15.1.4 dchardwarecon?guration register (r/w: bbh/bah) . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 15.1.5 dcinterruptenable register (r/w: c3h/c2h). 111 15.1.6 dcdmacon?guration (r/w: f1h/f0h) . . . . . 113 15.1.7 dcdmacounter register (r/w: f3h/f2h) . . . 114 15.1.8 reset device (f6h) . . . . . . . . . . . . . . . . . . . . 114 15.2 data ?ow commands . . . . . . . . . . . . . . . . . . 115
nxp semiconductors ISP1362 single-chip usb otg controller ? nxp b.v. 2007. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 8 may 2007 document identifier: ISP1362_5 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 15.2.1 write or read endpoint buffer (r/w: 10h,12h to 1fh/01h to 0fh) . . . . . . . . . . . . . 115 15.2.2 read endpoint status (r: 50h to 5fh). . . . . . 116 15.2.3 stall endpoint or unstall endpoint (40h to 4fh/80h to 8fh) . . . . . . . . . . . . . . . . 117 15.2.4 validate endpoint buffer (61h to 6fh) . . . . . . 117 15.2.5 clear endpoint buffer (70h, 72h to 7fh) . . . . 117 15.2.6 dcendpointstatusimage register (d0h to dfh) . . . . . . . . . . . . . . . . . . . . . . . . . 118 15.2.7 acknowledge set up (f4h) . . . . . . . . . . . . . . 118 15.3 general commands . . . . . . . . . . . . . . . . . . . 119 15.3.1 read endpoint error code (r: a0h to afh) . . 119 15.3.2 unlock device (b0h) . . . . . . . . . . . . . . . . . . . 120 15.3.3 dcscratch register (r/w: b3h/b2h) . . . . . . . 120 15.3.4 dcframenumber register (r: b4h) . . . . . . . . 121 15.3.5 dcchipid (r: b5h) . . . . . . . . . . . . . . . . . . . . 121 15.3.6 dcinterrupt register (r: c0h) . . . . . . . . . . . . 122 16 limiting values. . . . . . . . . . . . . . . . . . . . . . . . 124 17 recommended operating conditions. . . . . . 124 18 static characteristics. . . . . . . . . . . . . . . . . . . 125 19 dynamic characteristics . . . . . . . . . . . . . . . . 129 19.1 programmed i/o timing. . . . . . . . . . . . . . . . . 130 19.1.1 host controller programmed i/o timing . . . . 130 19.1.2 peripheral controller programmed i/o timing 131 19.2 dma timing . . . . . . . . . . . . . . . . . . . . . . . . . . 133 19.2.1 host controller single-cycle dma timing . . . 133 19.2.2 host controller burst mode dma timing . . . . 134 19.2.3 peripheral controller single-cycle dma timing (8237 mode). . . . . . . . . . . . . . . . . . . . 135 19.2.4 peripheral controller single-cycle dma read timing in dack-only mode . . . . . . . . . . 135 19.2.5 peripheral controller single-cycle dma write timing in dack-only mode . . . . . . . . . . 136 19.2.6 peripheral controller burst mode dma timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 20 package outline . . . . . . . . . . . . . . . . . . . . . . . 138 21 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 21.1 introduction to soldering . . . . . . . . . . . . . . . . 140 21.2 wave and re?ow soldering . . . . . . . . . . . . . . 140 21.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 140 21.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . 141 22 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 142 23 references . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 24 revision history . . . . . . . . . . . . . . . . . . . . . . . 144 25 legal information. . . . . . . . . . . . . . . . . . . . . . 146 25.1 data sheet status . . . . . . . . . . . . . . . . . . . . . 146 25.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 25.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 146 25.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 146 26 contact information . . . . . . . . . . . . . . . . . . . 146 27 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 28 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 29 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

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Price & Availability of ISP1362

Part #	Manufacturer	Description	Price	BuyNow Qty.
ISP1362BD	NXP Semiconductors	BUS Controller Circuit, 64 Pin, QFP	3: USD10.978 2: USD12.475 1: USD14.97	4
ISP1362BD	NXP Semiconductors	BUS Controller Circuit, 64 Pin, QFP	1: USD33.34	4
ISP1362BD	NXP Semiconductors	BUS Controller Circuit, 64 Pin, QFP	522: USD3.4875 233: USD3.8363 1: USD6.975	2016
ISP1362BDFA	ST-Ericsson	USB BUS CONTROLLER, CMOS, PQFP64	4: USD7.5 2: USD10 1: USD15	10
ISP1362BDFA	Ericsson	USB BUS CONTROLLER, CMOS, PQFP64	243: USD7.5 109: USD8.25 1: USD15	256

Part #	Manufacturer	Description	Price	BuyNow Qty.
ISP1362BD	Ericsson	Bus Controller, PQFP64		42

Part #	Manufacturer	Description	Price	BuyNow Qty.
ISP1362EE	NXP Semiconductors			3

Part #	Manufacturer	Description	Price	BuyNow Qty.
ISP1362BDTM	ST-Ericsson	INSTOCK		600
ISP1362BDTM	NXP Semiconductors	INSTOCK		70

Part #	Manufacturer	Description	Price	BuyNow Qty.
ISP1362EE/01	MFG UPON REQUEST			377
ISP1362BDTM	MFG UPON REQUEST			1382
ISP1362BDTM	NXP Semiconductors			95
ISP1362BDS	MFG UPON REQUEST			560
ISP1362BD-T	NXP Semiconductors			11

Part #	Manufacturer	Description	Price	BuyNow Qty.
ISP1362BDTM	ST-ERICSSON	ISP1362BDTM		0
ISP1362BDFA	ST-ERICSSON	ISP1362BDFA		0

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