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? 2004 microchip technology inc. ds21760e-page 1 ps700 features ? measures, maintains and reports all critical rechargeable battery parameters with high accuracy supports lithium (1-cell and 2-cell) battery packs current measurement with 16-bit integrating a/d accurate to less than 0.5% error temperature measurement accurate to within 2 c absolute, using on-chip temperature sensor or external thermistor accumulation of charge current, discharge current, temperature and voltage in independent 32-bit registers 512-byte nonvolatile eeprom stores factory programmed, measured and user-defined parameters in-system offset calibration compensates for offset error in current measurement industry standard smbus/i 2 c? compatible 2-wire communications interface 8-pin tssop package -20 c to +85 c operating temperature range ntc pin can be configured as a thermistor input or gpio vc2 pin can be configured as a cell input or a gpio flexible power operating modes allow low-power monitoring of battery conditions during system full operating and standby conditions: - run: continuous conversion; 80 a typ. - sample: sample interval from 0.5-64s @ 45 a typ. - sample-sleep: sample interval from 0.5-138s min. @ 20 a typ. shelf-sleep mode reduces power consumption to pack storage conditions to 300 na typ., with automatic wake-up upon pack insertion pin description pin summary pin name description vc2/io1 cell voltage input for cell 2 in a 2-series li ion pack or general purpose i/o #1 vc1 cell voltage input for cell 1 scl smbus clock line sda smbus data l/o r osc oscillator bias resistor ntc/io0 external thermistor connection or general purpose i/o #0 gnd power supply ground sr sense resistor input r osc ps700 1 scl 2 3 gnd 4 8 7 6 5 vc1 vc2/io1 ntc/io0 sr sda 8-pin 150 mil tssop package battery monitor
ps700 ds21760e-page 2 ? 2004 microchip technology inc. 1.0 product overview the ps700 is a cost-effective, highly accurate ic that measures, stores and reports all of the critical parameters required for rechargeable battery monitor- ing with a minimum of external components. it precisely measures charge/discharge current as well as voltage and temperature of a battery pack. in addition, the ps700 accurately accumulates both charge and discharge current as independent parameters. temperature history can also be maintained for calculating self-discharge effects. the ps700 integrates a highly accurate 16-bit integrat- ing a/d converter that performs current measurement to within 0.5% error. on-chip counters precisely track battery charge/discharge and temperature history. also included are an on-chip voltage regulation circuit, non- crystal time base and on-chip temperature sensor. the operating voltage range of the ps700 is optimized to allow a direct interface to 1 or 2-series li ion/li poly battery packs. 512 bytes of general purpose nonvolatile eeprom storage are provided to store factory programmed, measured and user defined parameters. efficient communication is provided through an industry standard smbus/i 2 c? compatible 2-wire communications interface. this interface allows the host to determine accurate battery status for effective system power management and for communication to the end user. a battery management solution utilizing the ps700 delivers both space and total system component cost savings for a wide variety of battery operated applications. figure 1-1: ps700 in ternal block diagram 512 eeprom 512 eeprom 32-bit accumulators / timers 32-bit accumulators/ timers voltage reference and temp sensor voltage reference and temp sensor voltage regulator voltage regulator comm interface comm interface registers registers 16-bit sigma-delta integrating a/d converter 16-bit sigma-delta integrating a/d converter analog input mux analog input mux run oscillator run oscillator vc1 r osc gnd digital section analog section control and status control and status scl sr sda sleep oscillator sleep oscillator vc2/io1 ntc/io0
? 2004 microchip technology inc. ds21760e-page 3 ps700 figure 1-2: application schematic ? ps700-based battery pack table 1-1: pin descriptions r15 1.0k r3 221k r4 680 r5 680 v cell 1 2 v cell 2 1 ntc 6 sr 8 gnd 7 smb-clk 3 smb-dta 4 r osc 5 u1 ps700 r11 470 vr v1 ntc1 ntc2 pack connection cell positive (+) cell negative (-) thermistor connections b+ c d b- r8 0.020 c11 100 nf c1 100 nf r7 6.49k 3 1 2 d1 cmszda5v6 connection ground plane c3 1.0 nf 3 4 2 1 5 6 8 7 q1 si6880edq v dd 2 v ss 3 vm 1 co 5 do 4 u2 s8241a pin no. pin name description 1 vc2/io1 cell input connection for lowest cell in a 2-cell series li ion pack. can also be configured as an open-drain general purpose input/output. 2 vc1 cell input connection for highest cell in a 2-cell series li ion pack. connects to the positive terminal of 1-cell series packs. vc1 serves as the power supply input for the ps700. 3 scl smbus/i 2 c clock line connection. 4 sda smbus/i 2 c data line connection. 5r osc external bias resistor. 6 ntc/io0 input for an external temperature sensor using a 103etb-type thermistor. can also be configured as a general purpose input/output pin. 7 gnd analog and digital ground. 8 sr current measurement a/d input from positive side of the current sense resistor.
ps700 ds21760e-page 4 ? 2004 microchip technology inc. 2.0 architectural overview the ps700 contains a complete analog ?front-end? for battery monitoring as well as digital logic for control, mea- surement accumulation, timing and communications. major functions within the ps700 include: voltage regulator precision time base temperature sensor 512-byte eeprom memory 32-byte ram memory analog-to-digital (a/d) converter 32-bit accumulators/timers smbus/i 2 c communications interface figure 1-1 is a block diagram of the internal circuitry of the ps700. figure 1-2 is a schematic diagram that depicts the ps700 in a typical single cell lithium ion application. the function of each of the blocks listed above is summarized in the following sections. 2.1 internal voltage regulator the ps700 incorporates an internal voltage regulator that supports 1 or 2-cell series lithium pack configura- tions. the internal regulator draws power directly from the vc1 input. no other external components are required to regulate internal supply voltage. 2.2 precision time base the integrated precision time base is a highly accurate rc oscillator that provides precise timing for the sigma- delta a/d and for the on-chip elapsed time counters without the need for an external crystal. this time base is trimmed during manufacturing to a nominal frequency of 131,072 hz. 2.3 temperature sensor an integrated temperature sensor is provided that can eliminate the need for an external thermistor. as an option, a connection is provided for an external thermistor for applications where the battery pack is physically located at a distance away from the ps700. 2.4 eeprom memory 512 bytes of eeprom memory are incorporated for storage of nonvolatile parameters, such as powersmart ? 3d cell models for use with host driver firmware. an initialization block is reserved within the eeprom array for values that are loaded into ps700 registers following a power-on condition. 2.5 ram memory 32 bytes of general purpose ram memory are provided for storage of temporary parameters. 2.6 a/d converter the ps700 incorporates an integrating sigma-delta a/d converter together with an analog mux that has inputs for charge and discharge current, cell and pack voltages, the on-chip temperature sensor and an off- chip thermistor. the converter can be programmed to perform a conversion with resolutions of 9 to 16 bits while utilizing either a 340 mv or a 170 mv reference. 2.7 32-bit accumulators/timers the ps700 incorporates four 32-bit accumulators and four 32-bit elapsed time counters. the discharge current accumulator (dca) and the charge current accumulator (cca) are intended to record discharge and charge capacity values. the discharge time counter (dtc) and the charge time counter (ctc) are intended to maintain the total discharge time and charge time. accumulated charge and discharge values can be used to determine state of charge of the battery as well as cycle count information. with information provided by the elapsed time counters, average charge and discharge currents over an extended period of time can be calculated. 2.8 smbus/i 2 c communications interface the communications port for the ps700 is a 2-wire industry standard smbus/i 2 c interface. all commands, status and data are read or written from the host system via this interface.
? 2004 microchip technology inc. ds21760e-page 5 ps700 3.0 operational description 3.1 a/d and accumulator/timer operation 3.1.1 a/d conversion cycle when the a/d converter is enabled and active, it repeatedly performs a cycle of 1 to 8 conversions as programmed by the user through 8 a/d control registers. these registers determine the input source, resolution, reference voltage source and sequence of conversions during an a/d converter cycle. during the cycle, the a/d logic accesses each register in sequence and performs the conversion specified by the bits within the register. this register contains an enable bit, a resolution field, a select bit for a single-ended or differential reference and a select field for the analog input mux. the results from each conversion are stored in one of eight corresponding16-bit result registers. if the ?enable? bit is set within a control register, a conversion will be performed. if it is disabled, that conversion will be skipped and the logic will move on to the next register. in this manner, the user can specify a sequence of conversions that will be performed during each a/d cycle. as stated above, the input source for each of the registers is programmable. the 3-bit mux field within each control register selects one of seven possible input sources for the a/d conversion. the list of input sources is as follows: charge/discharge current (voltage from sr pin to gnd) internal temperature sensor external thermistor (constant current source on ntc pin) battery pack voltage vc1 voltage vc2 voltage a/d offset (conversion performed with input shorted internally to determine offset error associated with the converter) however, the accumulator/timer functions are ?hard wired? to specific a/d result registers. for this reason, the control/result registers are given names which indicate their primary intended usage (see table 3-1). table 3-1: a/d control/result registers the 3-bit ?resolution? field in each a/d control register determines the resolution of the conversion, from a minimum of 10 bits (9 bits plus sign bit) to a maximum of 16 bits (15 bits plus sign bit). the time required to complete the conversion is a function of the number of bits of resolution (n) selected. the conversion time can be calculated as follows: t adc = 30.52 s * 2 n where: ?n? is the number of bits of resolution selected the ?ref? bit selects the magnitude of the reference voltage. either a 340 mv or a 170 mv reference is available. the 170 mv reference is typically used for current readings and the 340 mv reference for all other measurements. the value of the lsb can be expressed as a function of the resolution selected as follows: a/d lsb = 680/340 mv/2 n where: ?n? is the number of bits of resolution selected the result value is given in sign/magnitude format (i.e., a sign bit with a 15-bit magnitude). a/d register # control register result register intended input source 0 ictrl ires battery pack current (via sense resistor) 1 itctrl itres internal temperature sensor 2 etctrl etres external temperature sensor 3 vpctrl vpres battery pack voltage (vc1 to gnd) 4 vc1ctrl vc1res battery cell voltage (vc1 to vc2) 5 vc2ctrl vc2res battery cell voltage (vc2 to gnd) 6 offsctrl offsres internal a/d offset voltage (a/d input automatically internally shorted to gnd) 7 auxctrl auxres any 15 0 s magnitude
ps700 ds21760e-page 6 ? 2004 microchip technology inc. 3.1.2 current measurement charge and discharge currents are measured using a 5 to 600 m ? sense resistor that is connected between the sr and gnd pins. the maximum input voltage at sr is 150 mv. the sense resistor should be properly sized to accommodate the systems lowest and highest expected charge and discharge currents including suspend and/or standby currents. in order to perform charge and discharge current measurements, the ictrl register must be programmed with the sr pin as the analog input source. if charge and discharge accumulation is desired, the ictrl and corresponding ires registers should be used to select current measurement since the dca, dtc, cca and dca registers are updated by the measurement results from the ires register. ictrl programming in a typical application is as follows. table 3-2: ictrl programming using the maximum resolution of 16 bits, the voltage value of the lsb is: a/d lsb = 340 mv/2 16 = 5.19 v using a sense resistor value of 20 m ? , the value of the lsb in units of current is: 5.19 v/20 m ? = 259 a 3.1.3 voltage measurements analog mux inputs are provided to support measure- ment of individual cell and battery pack voltages. a/d control registers vpctrl, vc1ctrl and vc2ctrl are used to specify the measurement to be made. in typical applications, voltage measurement at the cell or pack level is done using the +340 mv reference and a resolution of 10 bits plus sign bit. the value of the lsb in a pack voltage measurement using a 340 mv reference voltage is given by the formula: v pack lsb = 10.2v/2 n where ?n? is the resolution selected. for typical applications where n = 10: v pack lsb = 10.2v/2 10 = 10.2v/1024 = 9.96 mv the value of the lsb in a cell voltage measurement using a 340 mv reference voltage is given by the formula: v cell lsb = 6.23v/2 n where ?n? is the resolution selected. for typical applications where n = 10: v cell lsb = 6.23v/2 10 = 6.23v/1024 = 6.08 mv the following table shows lsb values for 9-bit plus sign resolution, so n = 9. table 3-3: lsb values for 10-bit resolution vpctrl programming in a typical application is as follows. table 3-4: vpctrl programming the input source fields for the vpctrl, vc1ctrl and vc2ctrl registers must be programmed to select pack voltage (on vc1), vc1 cell voltage and vc2 cell voltage in order for these registers to control their intended measurements. 3.1.4 temperature measurements a/d input channels are provided for temperature mea- surement using either the internal temperature sensor or an external thermistor. 3.1.4.1 internal temperature the output of the internal temperature sensor is a volt- age range with limits that correspond to operating temperature limits as follows: -20c 239 mv +70c 312 mv the output voltage of the internal sensor as a function of temperature can be given as: v it (mv) = 239 + 0.82 * (t + 20) defined within the itctrl registers are the settings for the reference utilized and the resolution desired for measurement of temperature using the internal tem- perature sensor. because of input voltage range described above, the 340 mv reference should be selected. typically, 10-bit plus sign of resolution are selected which results in the following temperature resolution: lsb (voltage) = full scale range/# of steps = 340 mv/2 10 = 332 v/lsb lsb (c) = 332 v/lsb * (1 / 820) c/ v = 0.404c/lsb bit(s) name value function 7en 1 enables a/d conversion 6-4 res 111 selects 16-bit resolution 3ref 0 selects 170 mv reference 2-0 sel 000 selects v sr as converter input measurement vr divider bits lsb v pack 340 1/30 9 + sign 19.92 v cell 340 1/18.33 9 + sign 12.17 bit(s) name value function 7en 1 enables a/d conversion 6-4 res 001 selects 10-bit resolution 3ref 1 selects 340 mv reference 2-0 sel 011 selects v sr as converter input
? 2004 microchip technology inc. ds21760e-page 7 ps700 3.1.4.2 external temperature for temperature measurement using an external sensor, the ntc pin supplies a constant current source of 12.5 a. for proper operation, an industry standard 10 kohm at 25c negative temperature coefficient (ntc) device of the 103etbtype, should be connected between ntc and gnd. the ntc reference output is only enabled during an external temperature measurement in order to minimize power consumption. the output of the current source, connected to the external thermistor, produces a voltage range with limits that correspond to operating temperature limits, as follows: -20c 263 mv +70c 317 mv the output voltage of the external sensor as a function of temperature can be given as: v ex (mv) = 263 + 0.6 * (t + 20) defined within the etctrl registers are the settings for the reference utilized and the resolution desired for mea- surement of temperature usi ng the external temperature sensor. again, the 340 mv reference should be selected. the following temperature results in a 10-bit conversion: lsb (voltage) = full scale range/# of steps = 340 mv/2 10 = 332 v/lsb lsb (c) = 332 v/lsb * (1/600)c/ v = 0.553c/lsb 3.1.5 offset compensation the host software can perform offset compensation by using an offset measurement value read from the ps700. when the offset calibration is enabled within the offsctrl register, the converter inputs are internally shorted together and an a/d conversion is performed at the specified resolution. the offset value is stored in the offsres register. 3.1.6 accumulation/timing the ps700 incorporates four 32-bit accumulators and four 32-bit elapsed time counters. the discharge current accumulator (dca) and the charge current accumula- tor (cca) are intended to record discharge and charge capacity values. the discharge time counter (dtc) and the charge time counter (ctc) are intended to maintain the total discharge time and charge time. accumulated charge and discharge values can be used to determine state of charge of the battery as well as cycle count infor- mation. with information provided by the elapsed time counters, average charge and discharge currents over an extended period of time can be calculated. each of the four 32-bit accu mulator registers is assigned a fixed ?source? a/d result register. when the accumu- lator is enabled, it is updated every 500 ms by adding the contents of the assigned result register value to the previous accumulator value. the accumulators are listed in table 3-5 with their assigned source registers. table 3-5: accumulator registers the resolution of the accumulated value is equal to the resolution selected for the associated conversion, up to a converter resolution of 15-bit plus sign. if a 15-bit plus sign a/d value is being accumulated, then the accumulator resolution in microvolt seconds is: accumulator lsb ( vs) = (full scale range/# of steps) * 0.5s = (340 mv/215) * 0.5s = 2.59 vs 3.1.7 charge/discharge accumulators the dca register is intended to accumulate discharge current and the cca register is intended to accumulate charge current. both use the ires register as its source. for this reason, in most applications, current measure- ment defined in the a/d control registers should be programmed to measure current by reading the voltage across the sense resistor pin (sr). during charging, a negative voltage will exist across the sr pin to ground. following a conversion, a positive voltage measurement results in the sign bit = 0 in the ires register. when the sign bit = 0 , the measured result will be added to the cca register contents and the sum is returned to cca. in this way, the total charge current will be accumulated in cca. similarly, during discharge, a positive voltage will exist between the sr pin and ground. in this case, the conversion will result with sign bit = 1 in the ires regis- ter, indicating a negative value or discharge current condition. under this condition, the dca register will be updated with the discharge current measured during that conversion. the value stored in the dca or cca register can be interpreted as illustrated in the following example. using a 16-bit signed conversion for current measure- ment and a 20 m ? sense resistor, the lsb can be expressed in units of capacity in micro amp seconds as follows: accumulator lsb ( as) = voltage lsb/r sense = (2.59 vs)/20 m ? = 130 as the ?accum? bit in the accumctrl register must be enabled for accumulation to occur in both the cca and dca registers. abbr. accumulator name source dca discharge current accumulator ires (sign bit = 1 ) cca charge current accumulator ires (sign bit = 0 ) ta temperature accumulator itres or etres vc2a vc2 accumulator vc2res
ps700 ds21760e-page 8 ? 2004 microchip technology inc. 3.1.8 charge/discharge time counters the charge time counter (ctc) will increment at the rate of 2 counts every second as long as a negative voltage is measured at the sr pin. the ctc can thereby maintain a time count representing the total time that charge current has flowed into the battery. the discharge time counter (dtc) will increment at the rate of 2 counts every second as long as a positive voltage is measured at the sr pin. the dtc can thereby maintain a time count representing the total time that discharge current has flowed from the battery. 3.1.9 general purpose accumulators there are two general purpose accumulators, ta and vc2a. for typical applications, these accumulators have been assigned specific functions. the user can redefine the use of these accumulators to fit the design requirements. ta can be used to accumulate results from the itres or etres registers. accumulation to ta must be enabled in the accumctrl register bit ?acct?. the selection for accumulation of the values represented by the internal or external thermistor is also determined in the accumctrl register bit ?tsel?. vc2a can be used to accumulate results from vc2res. accumulation in vc2a must be enabled in the accumctrl register bit ?accv?. the value stored in vc2res corresponds to the measurement as defined in the a/d control register vc2ctrl. this function is utilized if the vc2 pin is configured as an independent a/d input and not connected to the cell stack. the ?accum? bit in the accumctrl register must be enabled for accumulation to occur in ta and vc2a. 3.1.10 general purpose timers there are two general purpose timers that are enabled by accumulation in the ta and vc2a accumulators. tat is used to maintain a time count during accumula- tion in the ta register. this timer increments at a frequency of 2 counts every second. vc2t is used to maintain a time count during accumulation in the vc2a register. this timer increments at a frequency of 2 counts every second. 3.2 power modes the ps700 has four operational power modes: run, sample, sample-sleep and shelf-sleep. each con- sumes power according to the configuration settings as described in the following sections. 3.2.1 run mode during run mode, the ps700 performs continuous a/d conversion cycles per the programming of the a/d conversion cycle documented in section 3.1.1 ?a/d conversion cycle? . as described above, during each cycle, between 1 and 8 conversions are performed and the accumulators/time counters are updated as programmed by the user. run mode is entered following a power-on reset when the pack voltage (v pack ) applied on the vc1 pin rises above the v por threshold. run mode can also be entered from the sample, sample-sleep and shelf-sleep modes as described below. the ps700 will remain in run mode as long as the pack voltage is above the v por threshold and the sample, sample-sleep and shelf-sleep modes are not active. 3.2.2 sample mode in sample mode, a/d measurements are not continu- ously performed as in run mode. instead, they are performed at a user selectable rate. the purpose of sample mode is to reduce power consumption during periods of low rate charge or discharge. the power advantage of sample mode comes from the reduction in frequency of a/d measurements. sample mode is entered by programming the ?samp? bit = 1 in the a/d configuration register. the ps700 will remain in sample mode as long as ?samp? bit = 1 and the vc1 voltage is above the v por threshold and the sample-sleep and shelf-sleep modes are not active. run mode will be resumed when the samp bit is cleared to ? 0 ?. the sample mode rate is selected using the ?sampdiv? bits within the a/d configuration register. the sample interval is 2**(sampdiv) * 0.5 sec. the possible sample rate intervals are as follows. table 3-6: sample rate intervals in sample mode, much of the analog circuitry remains on. therefore, the power savings are not as great as in sample-sleep mode (described below). refer to section 6.0 ?electrical characteristics? for a specifi- cation of the amount of current consumed in sample mode. ?sampdiv? sample interval value = 0 0.5s value = 1 1.0s value = 2 2.0s value = 3 4.0s value = 4 8.0s value = 5 16.0s value = 6 32.0s value = 7 64.0s
? 2004 microchip technology inc. ds21760e-page 9 ps700 3.2.3 sample-sleep mode in sample-sleep mode, the ps700 goes into the sleep state and wakes up at user-programmed intervals to perform a set of conversions as programmed for the a/d cycle. the purpose of sample-sleep is to achieve the minimum power consumption possible while periodically measuring specified parameters. while the ps700 is in the sleep portion of sample- sleep interval, all of the analog circuitry is shut off. the sleep interval time is driven by an independent low- power on-chip rc oscillator that is separate from the primary oscillator. the sleep oscillator consumes much less power than the primary oscillator, but is less accurate. while in sample-sleep mode, the device consumes average current in the range of 20 a. during the active portion of sample-sleep mode, a single set of conversions is performed and a run mode current in the range of 85 a will be consumed for the duration of the measurements. sample-sleep mode is invoked by one of the following actions: 1. cell voltage on vc1 or vc2 drops below the trip point programmed in the vctrip register with the corresponding ?vc1ent? or ?vc2ent? bit set in the tripctrl register. this action can be used to prevent excessive battery discharge in the event of a dangerously low cell voltage. be aware that sample-sleep will not be entered if the ?lex? bit is set, enabling wake-up based on charge current and the measured current is above the threshold set in the i+trip register. 2. setting the sslp bit in the opmode register. the host can take this action when the system is entering a low-power standby condition and it is desired to periodically measure and accumulate current, voltage, or temperature. 3. current less than the i-trip register value when ?ient? bit is set in the tripctrl register. the sample-sleep interval is determined by the programming of the ?sampdiv? bits within the a/d con- figuration register, together with the ?sslpdiv? bits within the opmode register. the sample interval is 2**(sampdiv) * 2**(sslpdiv) * 0.5 sec. the possible sample-sleep interval time, therefore, ranges from a minimum of 0.5 sec to over 136 minutes. exit from sample-sleep mode to run mode can be accomplished by clearing the ?sslp? bit or by program- ming a wake-up based on pack voltage or current. wake-up based on charge current will occur when the ?iex? bit is set in the tripctrl register and the charging current value is above the threshold programmed in the i+trip register. wake-up based on pack voltage will occur when the ?vpex? bit is set in the tripctrl register and the pack voltage rises above the threshold programmed in the sstrip register. 3.2.4 shelf-sleep mode shelf-sleep mode is the lowest power mode and is intended to preserve battery capacity when the battery pack is shipped or stored or if the battery voltage drops below a specified threshold. while in shelf-sleep mode, no measurements occur, no accumulation is performed and no smbus communications are recognized. in addition, volatile memory is not maintained. entry to shelf-sleep mode is enabled by programming the ?shent? bit = 1 or if v pack is less than vptrip. the shelf-sleep mode will then be entered when the smbus pins (both sda and scl) drop from a high to a low level for a minimum time period specified by t shelf . this action will also occur if the battery pack is physically disconnected from the system. exit from the shelf-sleep mode back to run mode will occur when the smbus pins (both sda and scl) are both pulled from a low to high condition and remain high for a minimum time of t wake , signifying system activity or the connection of the pack to the host. 3.3 general purpose input/outputs the ntc and vc2 pins have alternate functions of general purpose i/o; io0 and io1, respectively. these pins can be configured as digital general purpose inputs/outputs if their normal application functions of temperature and cell monitoring are not needed. their configuration is controlled in the gpioctrl register. the io0 (ntc) pin may be configured as a push-pull output, an open-drain driver with internal pull-up, or as a tri-stated pin. when configured as a push-pull or open-drain output, the output high voltage is the 3.0v internally regulated supply. when the output function is disabled, an external circuit may drive the pin as an input with a voltage range of 0-3.0v. the input function may be used whether or not the pin is driven by the ps700. in addition, the input function may be disabled, in which case the input buffer is powered down, preventing current drain if the ntc pin rests at an intermediate level. the io1 (vc2) pin is similar to that of ntc except it is an open-drain output only. io1 has no explicit output enable control; therefore, if the output is set to a logic ? 1 ?, the internal pull-down is turned off which tri-states the pin. the input function is the same as io0. note: if the io0 and/or io1 pins are being used for their analog functions, their respective gpio output and input functions must be disabled. the gpio function may be totally disabled by clearing the appropriate gpioctrl bit.
ps700 ds21760e-page 10 ? 2004 microchip technology inc. 3.4 smbus/i 2 c interface the ps700 supports a 2-wire bidirectional bus and data transmission protocol that is fully compatible with the industry standard smbus v1.1 based on the i 2 c interface. this interface is used to read and write data from/to the on-chip registers and eeprom. the device responds to the same smbus slave address for access to all functions. the following is a brief overview of the smbus/i 2 c operational implementation in the ps700. please refer to the smbus v1.1 specification for complete operational details of this industry standard interface. this specification can be obtained at the smbus implementer?s forum web site at www.smbus.org. 3.4.1 smbus overview smbus is a two-wire multi-master bus, meaning that more than one device capable of controlling the bus can be connected to it. a master device initiates a bus transfer and provides the clock signals. a slave device can receive data provided by the master or can in return provide data to the master. since more than one device may attempt to take control of the bus as a master, smbus provides an arbitration mechanism based on i 2 c and relying on the wired-and connection of all smbus devices residing on the bus. if two or more masters try to place informa- tion on the bus, the first to produce a ?one? when the other(s) produce a ?zero? loses arbitration and has to release the bus. the clock signals during arbitration are a wired-and combination of all the clocks provided by smbus masters. bus clock signals from a master can only be altered by clock stretching or by other masters and only during a bus arbitration situation. in addition to bus arbitration, smbus implements the i 2 c method of clock low extending in order to accommodate devices of different speeds on the same bus. smbus version 1.1 can be implemented at any voltage between 3 and 5 volts 10%. devices can be powered by the bus v dd or by their own power source (such as smart batteries) and they will interoperate flawlessly as long as they adhere to the smbus electrical specifications. 3.4.2 smbus data transfers a device that sends data onto the smbus is defined as a transmitter and a device receiving data as a receiver. the device that controls the message is called a ?master?. the devices that are controlled by the master are ?slaves?. the smbus must be controlled by a master device that generates the serial clock (scl), controls the bus access and generates start and stop conditions. the ps700 operates as a slave on the two- wire bus. connections to the bus are made via the open-drain i/o lines sda and scl. smbus operates according to the following bus protocol: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. the smbus specification defines the following bus conditions: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line from high to low, while the clock is high, defines a start condition. stop data transfer: a change in the state of the data line from low to high, while the clock line is high, defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge bit after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generat- ing an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition.
? 2004 microchip technology inc. ds21760e-page 11 ps700 figure 3-1: smbus data transfer figure 3-1 details how data transfer is accomplished on the smbus. depending upon the state of the r/w bit, two types of data transfer are possible: 1. data transfer from a master transmitter to a slave receiver: the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. 2. data transfer from a slave transmitter to a master receiver: the first byte (slave address) is transmitted by the master. the slave then returns an acknowledge bit. next follows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a ?not acknowledge? is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. the ps700 may operate in the following two modes: 1. slave receiver mode: serial data and clock are received through sda and scl. after each byte is received, an acknowledge bit is transmit- ted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit. 2. slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit will indicate that the transfer direction is reversed. serial data is transmitted on sda by the ps700 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer.
ps700 ds21760e-page 12 ? 2004 microchip technology inc. figure 3-2: ps700 sm bus write transaction smbus address 0 710 s bt ah a 710 x 64 bank 32 address low 70 # of bytes (only if bt = 1 ) 70 a a a master controls sda ps700 controls sda legend: s - start p - stop rs - repeated start a - acknowledge a - negative acknowledge (terminates transaction) bt - block mode indicator bit bank - controls selection of bank: 00 : eeprom 01 : ram/registers 10 : reserved 11 : reserved ah - high-order address bits (2) address low - low-order address bits (8) (additional data bytes if bt = 1 ) last write data byte 70 a p
? 2004 microchip technology inc. ds21760e-page 13 ps700 figure 3-3: ps700 smbus read transaction smbus address 0 710 s bt ah a 710 x 64 bank 32 address low 70 # of bytes (only if bt = 1 ) 70 smbus address 1 710 rs a a a a last read data byte 70 a/a master controls sda ps700 controls sda legend: s- start p - stop rs - repeated start a - acknowledge a - negative acknowledge (terminates transaction) bt - block mode indicator bit bank - controls selection of bank: 00 : eeprom 01 : ram/registers 10 : test mode registers 11 : reserved ah - high-order address bits (2) address low - low-order address bits (8) (additional data bytes if bt = 1 ) p
ps700 ds21760e-page 14 ? 2004 microchip technology inc. 4.0 memory/operational register description 4.1 memory/register map the ps700 internal structure is accessible on a strict memory mapped basis. the only action directly taken by the ps700 in response to an smbus command is to read or write registers, ram or eeprom. any actions taken by ps700 happen as a result of values written to internal control registers. addressing in ps700 consists of 10 bits plus two bank select bits. therefore, there are a total of 4 kbyte loca- tions that are addressable within the ps700, organized as 4 banks of 1024 locations each. bank 0 is dedicated to eeprom, bank 1 contains ram/registers, bank 2 contains test registers and bank 3 is reserved. table 4-1 describes the ps700 memory map. the notation is y:0xzzz, where ?y? is the bank and ?zzz? is the address in hex. 4.2 eeprom the 512-byte eeprom is located in bank 0 and occupies addresses 0:0x000 to 0:0x1ff. all critical ps700 parameters, calibration factors and learned data are stored in the ps700 integrated eeprom. see table 4-2 for the ps700 eeprom map. the eeprom can be read using byte or block transfer modes, but can only be written a byte at a time. writing the eeprom takes approximately 4 ms/byte. an eeprom write cycle command from the smbus is immediately acknowledged by the ps700 if no other eeprom write cycles are in progress. if a eeprom write cycle is attempted while a previous request to write is in progress, a negative acknowledge will be returned until the previous write cycle is completed. a eeprom read cycle also results in a negative acknowledge or an acknowledge depending on whether or not a eeprom write cycle is in progress the data eeprom does not write reliably at tempera- tures less than 0c and supply voltages less than 3.3v. a read or write to a register or ram location will not be affected by an eeprom write cycle in progress. 4.3 general purpose ram 32 bytes of general purpose ram are provided as tem- porary storage and are located in bank 1 at 1:0x000 through 1:0x01f. the ram may be read or written using either the byte or block transfer modes. 4.4 operational registers the following is a detailed description of all operational registers within the ps700 and all control, status, result bits and fields that are contained therein. 4.4.1 dca ? discharge count accumulator the dca is a 32-bit register that holds the total accumulated capacity discharged from the battery. each time a conversion is performed with the sign bit of ires = 1 and current accumulation is enabled, the measured value is added to dca. as a result, the register is updated whenever a current measurement is performed with a negative voltage across the sense resistor (v sr < gnd). the dca register will rollover if it is allowed be updated beyond 0xffffffff, so proper register maintenance by the host system is necessary. the dca register may be cleared using the accclr register bit, clr0, described in register 4-6. 4.4.2 dtc ? discharge time count register the dtc records the length of accumulated time that the battery is in a discharge condition as indicated by a negative voltage on the sr pin. this register is incremented using a 2 hz internal clock rate; therefore, the dtc is incremented at the rate of 2 counts per second or 7200 counts per hour so long as current accumulation is enabled and the ires register returns a ? 1 ? in the sign bit following a current conversion. the dtc register will rollover if it is allowed to count beyond 0xffffffff; therefore, proper register main- tenance by the host system is necessary. the dtc reg- ister may be cleared using the accclr register bit, clr1, described in register 4-6. 4.4.3 cca ? charge count accumulator the cca is a 32-bit register that holds the total accu- mulated current delivered as charge into the battery. each time a current conversion is performed with the sign bit of ires = 0 and current accumulation is enabled, the measured value is added to cca. as a result, the register is updated whenever a current measurement is performed with a positive voltage across the sense resistor (v sr > gnd). the cca register will rollover if it is allowed to be updated beyond 0xffffffff; therefore, proper regis- ter maintenance by the host system is necessary. the cca register may be cleared using the accclr register bit, clr2, described below.
? 2004 microchip technology inc. ds21760e-page 15 ps700 table 4-1: ps700 memory map function byte 3 byte 2 byte 1 byte 0 bank:address (byte 0) eeprom 0:0x000 0:0x004 0:0x00c register initialization values (res erved locations must = 0x00) 0:0x020 register initialization values (res erved locations must = 0x00) 0:0x084 0:0x088 0:0x1f8 0:0x1fc reserved reserved 0:0x201 reserved 0:0x3fc general purpose ram 1:0x000 1:0x004 1:0x008 1:0x018 1:0x01c operational registers: accumulators/ timers, a/d registers, mode control dca 1:0x020 dtc 1:0x024 cca 1:0x028 ctc 1:0x02c ta 1:0x030 tat 1:0x034 vc2a 1:0x038 vc2t 1:0x03c adconfig ictrl (adc0) ires (adr0) 1:0x040 reserved itctrl (adc1) itres (adr1) 1:0x044 etctrl (adc2) etres (adr2) 1:0x048 vpctrl (adc3) vpres (adr3) 1:0x04c gpioctrl vc1ctrl (adc4) vc1res (adr4) 1:0x050 reserved vc2ctrl (adc5) vc2res (adr5) 1:0x054 offsctrl (adc6) offsres (adr6) 1:0x058 auxctrl (adc7) auxres (adr7) 1:0x05c acccontrol accclr i+trip 1:0x060 reserved reserved i-trip 1:0x064 vptrip 1:0x068 vctrip 1:0x06c sstrip 1:0x070 tripctrl reserved 1:0x074 opmode 1:0x078 reserved 1:0x07c reserved reserved 2:0x004 reserved 2:0x0fc cal/setup registers mosct v reft v bgt smbadd 2:0x080 reserved aosct reserved reserved 2:0x084 reserved reserved 2:0x088 reserved 2:0x3fc reserved reserved 3:0x000 reserved 3:0x3fc
ps700 ds21760e-page 16 ? 2004 microchip technology inc. table 4-2: p7 eeprom adr name len units dflt description unused 0x00 (available) (32) ? (not used) factory 0x88 pattern 2 ? eeprom pattern id 0x8a tester_id 2 ? tester program id/version 0x8c cal_status 1 ? 0 bit flags ? calibration status 0x8d cf_curr 2 ? calibration factor ? gain ? current 0x8f co_curr 1 a/d calibration factor ? offset ? current 0x90 cf_pack 2 ? calibration factor ? gain ? pack 0x92 cf_vcell1 2 ? calibration factor ? gain ? v cell 1 0x94 cf_vcell2 2 ? calibration factor ? gain ? v cell 2 0x96 co_pack 1 a/d calibration factor ? offset ? pack 0x97 co_vcell1 1 a/d calibration factor ? offset ? v cell 1 0x98 co_vcell2 1 a/d calibration factor ? offset ? v cell 2 0x99 cf_tempi 2 ? calibration factor ? gain ? internal temperature 0x9b co_tempi 2 ? calibration factor ? offset ? internal temperature 0x9d cf_tempe 2 ? calibration factor ? gain ? external temperature 0x9f co_tempe 2 ? calibration factor ? offset ? external temperature 0xa1 reserved 4 ? reserved total 29 fuel gauge 0xa5 version 2 n/a 0x0101 fuel gauge version number 0xa7 veod 2 mv eod voltage threshold 0xa9 veoc 2 mv eoc voltage threshold 0xab ieoc 2 ma eoc current threshold 0xad eod_cap 2 mah eod capacity 0xaf mode 1 bits fuel gauge mode bits 0xb0 serial_no 2 n/a serial number ? battery id 0xb2 cap_full 2 mah full charge capacity 0xb4 cycles 2 cycles cycle count 0xb6 veod_c 3 xma veod lut current axis 0xb9 veod_t 7 xdegc veod lut temperature axis 0xc0 veod 32 xmv veod voltage threshold(s) 0xe0 rcap_t 7 xdegc rcap lut ? residual capacity temperature axis 0xe7 rcap 8 xmah residual capacity total 74 unused 0xef (available) (17) (not used)
? 2004 microchip technology inc. ds21760e-page 17 ps700 4.4.4 ctc ? charge time count register ctc records the length of accumulated time that the battery is in a charge condition as indicated by a posi- tive voltage on the sr pin. this register is incremented using a 2 hz internal clock rate; therefore, the ctc is incremented at the rate of 2 counts per second or 7200 counts per hour so long as current accumulation is enabled and the ires register returns a ? 0 ? in the sign bit following a current conversion. the ctc register will rollover if it is allowed to count beyond 0xffffffff; therefore, proper register maintenance by the host system is necessary. the ctc register may be cleared using the accclr register bit, clr3, described below. 4.4.5 ta ? temperature accumulator ta is the accumulated 32-bit value of temperature measurements from the internal or external tempera- ture sensor. ta is updated by the itres or etres registers. selection of the internal temperature sensor, or external thermistor connected to the ntc pin, is made in the accumctrl register, bit tsel. the ta register will rollover if it is allowed be updated beyond 0xffffffff; therefore, proper register maintenance by the host system is necessary. the ta register may be cleared using the accclr register bit, clr4, described below. 4.4.6 tat ? temperature time count register the tat register records the length of accumulated time that the ps700 is sensing temperature and accu- mulating the value in register ta. tat is incremented using a 2 hz internal clock rate and is incremented at the rate of 2 counts per second, or 7200 counts per hour, as long as temperature accumulation is enabled. the tat register will rollover if it is allowed to count beyond 0xffffffff; therefore, proper register maintenance by the host system is necessary. the tat register may be cleared using the accclr register bit, clr5, described below. 4.4.7 vc2a ? vc2 accumulator vc2a is a 32-bit register that holds the total accumulated value measured on the vc2 pin. at the completion of each measurement, vc2a is incremented by the value of vc2res. this function is enabled when the accumctrl register, bit accv is a ? 1 ?. the vc2a register will rollover if it is allowed to count beyond 0xffffffff; therefore, proper register main- tenance by the host system is necessary. the vc2a register may be cleared using the accclr register bit, clr6, described below. 4.4.8 vc2t ? vc2 time count register vc2t records accumulated time for which measurements are taken on the vc2 pin. this register is incremented using a 2 hz internal clock rate; there- fore, vc2t is incremented at the rate of 2 counts per second or 7200 counts per hour. the vc2t register will rollover if it is allowed to count beyond 0xffffffff; therefore, proper register main- tenance by the host system is necessary. the vc2t register may be cleared using the accclr register bit, clr7, described below.
ps700 ds21760e-page 18 ? 2004 microchip technology inc. 4.4.9 adconfig ? a/d configuration register register 4-1: adconfig: a/d configuration register (address 43 hex/67 decimal) aden samp reserved sampdiv<2:0> bit 7 bit 0 bit 7 aden: master a/d enable bit if no conversions are desired, the a/d converter must be disabled using this bit. 1 = a/d conversions enabled 0 = a/d conversions disabled bit 6 samp: sample mode enable bit this bit controls the enabling of sample mode when the ps700 is not in a power-on reset, sample-sleep or shelf-sleep mode. when set to ? 1 ?, sample mode is enabled and conversions will be performed at a periodic rate determined by the programming of the sampdiv bits. when cleared, sample mode is disabled and the ps700 will operate in run mode. 1 = sample mode enabled 0 = sample mode disabled bit 5-3 reserved: reserved bit location bit 2-0 sampdiv: sample period interval bits the sampdiv bits determine the interval between sample periods when the ps700 is operating in sample mode. the programmed interval will be 2**(sampdiv) * 0.5 sec. legend: ?1? = bit is set ?0? = bit is cleared r = reserved bit
? 2004 microchip technology inc. ds21760e-page 19 ps700 4.4.10 accumctrl ? accumulator control register register 4-2: accumctrl: accumulator control register (address 63 hex/99 decimal) accum accl acct accv tsel reserved bit 7 bit 0 bit 7 accum: accumulator master enable bit ?accum? is a master enable for accl, acct and accv. if any combination of ?accl?, ?acct? and ?accv? are enabled, accum must also be enabled to permit accumulation. if ?accum? is ? 0 ?, no accumulation will occur regardless of the settings in ?accl?, ?acct? and ?accv?. 1 = accumulation enabled 0 = accumulation disabled bit 6 accl: current accumulation enable bit when ?acci? is set to a ? 1 ?, current accumulation is enabled. the dca and cca registers will periodically add the value of the ires register. also, the dct and cct elapsed time counter registers will count during discharge and charge, respectively. when ?acci? is cleared to ? 0 ?, current accumulation is disabled. 1 = current accumulation enabled 0 = current accumulation disabled bit 5 acct: accumulate temperature enable bit when ?acct? is set to a ? 1 ?, accumulation will be enabled in ta. ta will accumulate results from the ad5 result register and the tat elapsed time counter will increment. when ?acct? is cleared to ? 0 ?, ta accumulation will be disabled. 1 = accumulate temperature enabled 0 = accumulate temperature disabled bit 4 accv: accumulate voltage from vc2 enable bit when ?accv? is ? 0 ?, accumulation in ta will be updated by the vc1res register. when ?accv? is ? 1 ?, accumulation in ta will be updated by the vc2res register. bit 3 tsel: temperature selection bit when ?tsel? is ? 0 ?, the internal temperature sensor is used for accumulation. when ?tsel? is ? 1 ?, the external temperature sensor is used for accumulation. 1 = external temperature sensor selected 0 = internal temperature sensor selected bit 2-0 reserved: reserved bit location legend: ?1? = bit is set ?0? = bit is cleared r = reserved bit
ps700 ds21760e-page 20 ? 2004 microchip technology inc. 4.4.11 a/d control registers the eight a/d control registers are defined as follows. table 4-3: a/d control registers the following register defines the bits contained in the eight a/d control registers. register 4-3: a/d control registers a/d reg. # name function location (hex) adc0 ictrl current measurement control 42 adc1 itctrl internal temperature measurement control 46 adc2 etctrl external temperature measurement control 4a adc3 vpctrl pack voltage measurement control 4e adc4 vc1ctrl vc1 voltage measurement control 52 adc5 vc2ctrl vc2 voltage measurement control 56 adc6 offsctrl offset measurement control 5a adc7 auxctrl auxiliary measurement control 5e enable resolution reference select bit 7 bit 0 bit 7 enable: a/d measurement enable bit a ? 1 ? in this bit enables the measurement defined by bits 0-6. bit 6-4 resolution: a/d resolution selection bits these three bits control the resolution of the conversion performed for the corresponding a/d result register as follows: resolution = 0: 8-bit + sign conversion resolution = 1: 9-bit + sign conversion resolution = 2: 10-bit + sign conversion resolution = 3: 11-bit + sign conversion resolution = 4: 12-bit + sign conversion resolution = 5: 13-bit + sign conversion resolution = 6: 14-bit + sign conversion resolution = 7: 15-bit + sign conversion bit 3 reference: a/d reference selection bit reference = 0: vr = 170 mv reference = 1: vr = 340 mv bit 2-0 select: a/d input selection bits selects the analog mux input for the pending conversion as follows: select = 0: current (sr pin voltage) select = 1: internal temperature sensor select = 2: external temperature sensor (ntc pin voltage) select = 3: v pack (pack voltage) select = 4: vc1 voltage select = 5: vc2 voltage select = 6: offset voltage select = 7: offset voltage legend: ?1? = bit is set ?0? = bit is cleared r = reserved bit
? 2004 microchip technology inc. ds21760e-page 21 ps700 in order for the a/d control registers to function according to their names, their select fields should be programmed as follows. table 4-4: a/d control register functions 4.4.12 a/d result registers the eight 16-bit adres registers are defined as follows. table 4-5: a/d result registers the following register defines the bits contained in the eight 16-bit adres registers. register 4-4: adres registers a/d reg. # name select value adc0 ictrl 0 adc1 itctrl 1 adc2 etctrl 2 adc3 vpctrl 3 adc4 vc1ctrl 4 adc5 vc2ctrl 5 adc6 offsctrl 6 adc7 auxctrl x a/d reg. # name function location (hex) adr0 ictrl current measurement result 40 adr1 itctrl internal temperature measurement result 44 adr2 etctrl external temperature measurement result 48 adr3 vpctrl pack voltage measurement result 4c adr4 vc1ctrl vc1 voltage measurement result 50 adr5 vc2ctrl vc2 voltage measurement result 54 adr6 offsctrl offset measurement result 58 adr7 auxctrl auxiliary measurement result 5c sign magnitude bit 15 bit 0 bit 15 sign: polarity of the a/d measurement bit the sign bit shows the polarity of the given result where: 1 = the value is negative 0 = the value is positive bit 14-0 magnitude: magnitude of a/d output bits magnitude reports the value of the a/d measurement, with all ? 0 ?s representing a 0 value and all ? 1 ?s representing full scale. legend: ?1? = bit is set ?0? = bit is cleared r = reserved bit note: the resolution bits, as defined in the adctrl register, specify the measurement resolution and therefore, number of bits stored in the adres registers. the value stored in the adres registers is left justified. bits beyond the selected resolution should be ignored.
ps700 ds21760e-page 22 ? 2004 microchip technology inc. 4.4.13 gpioctrl ? gpio control register register 4-5: gpioctrl: gpio co ntrol register (address 53 hex/83 decimal) pp0oe0ie1ie0out1out0in1in0 bit 7 bit 0 bit 7 pp0: push-pull output io0 bit setting this bit to a ? 1 ?, with bit oe0 set to a ? 1 ?, will configure the io0 (ntc) pin as a push-pull digital output. if pp0 is a ? 0 ?, with oe0 set to ? 1 ?, the ie0 is an open-drain output with a 300 kohm pull-up to internal v dd . bit 6 oe0: output enable io0 bit setting this bit to a ? 1 ? will allow the ps700 to control ntc as either a push-pull (pp0 = 1 ) or open-drain (pp0 = 0 ) output. if oe0 is a ? 0 ?, the ntc pin is tri-state (pp0 = 1 ) or pulled up to internal v dd with a 300 kohm resistor (pp0 = 0 ). bit 5 ie1: input enable io1 bit setting this bit to a ? 1 ? will enable io1 (vc2) as a digital input. if ie1 is a ? 0 ?, the digital input buffer on io1 is powered down and in1 will always read logic ? 0 ?. bit 4 ie0: input enable io0 bit setting this bit to a ? 1 ? will enable io0 (ntc) as a digital input. if ie0 is a ? 0 ? the digital input buffer on io0 is powered down and in0 will always read logic ? 0 ?. bit 3 out1: output data gpio1 bit setting this bit to a ? 0 ? turns on the open-drain pull-down on io1 (vc2) (forcing a logic ? 0 ? on the output). setting this bit to a ? 1 ? turns off the pull-down resistor. bit 2 out0: output data gpio0 bit if oe0 is a ? 1 ?, the logic value of out0 is driven onto the io0 (ntc) pin by the ps700. bit 1 in1: input data gpio1 bit current logic state of the io1 (vc2) pin (read-only). bit 0 in0: input data gpio0 bit current logic state of the io0 (ntc) (read-only). legend: ?1? = bit is set ?0? = bit is cleared r = reserved bit
? 2004 microchip technology inc. ds21760e-page 23 ps700 4.4.14 accclr ? accumulator clear register a ? 1 ? in any accclr bits will clear the associated accumulator. following the clear operation, all of the bits in accclr will be cleared to ? 0 ?. register 4-6: accclr: accumulator clear register (address 62 hex/98 decimal) clr7 clr6 clr5 clr4 clr3 clr2 clr1 clr0 bit 7 bit 0 bit 7 clr7: clear accumulator 7 bit a ? 1 ? in this register will clear the vc2t accumulator. bit 6 clr6: clear accumulator 6 bit a ? 1 ? in this register will clear the vc2a accumulator. bit 5 clr5: clear accumulator 5 bit a ? 1 ? in this register will clear the tat accumulator. bit 4 clr4: clear accumulator 4 bit a ? 1 ? in this register will clear the ta accumulator. bit 3 clr3: clear accumulator 3 bit a ? 1 ? in this register will clear the ctc accumulator. bit 2 clr2: clear accumulator 2 bit a ? 1 ? in this register will clear the cca accumulator. bit 1 clr1: clear accumulator 1 bit a ? 1 ? in this register will clear the dtc accumulator. bit 0 clr0: clear accumulator 0 bit a ? 1 ? in this register will clear the dca accumulator. legend: ?1? = bit is set ?0? = bit is cleared r = reserved bit
ps700 ds21760e-page 24 ? 2004 microchip technology inc. 4.4.15 tpv ? trip point value registers there are 5 registers that are utilized to set up trip point values. these registers are used when enabled by the tripctrl register to enter or exit various power modes. three of these trip point value registers con- tain voltage values and two contain current values. the trip point value registers, their corresponding com- pare registers and their enable locations are listed below: vptrip, vctrip and shtrip are used as voltage values to be compared to vpres, vc1res or vc2res and vpres, respectively, for transition in and out of various power modes. i+trip and i-trip are used as current values to be compared to ires for transition in and out of various power modes. the format for data in these registers is left justified. for the purpose of this trip point, only magnitude is compared, the sign is ignored. register 4-7: tpv: trip point value registers tpv register location (hex) comparison register enable bit i+trip 60 ires iex i-trip 64 ires ient vptrip 68 vpres vpex vctrip 6c vc1res or vc2res vc1ent or vc2ent shtrip 70 vpres shent sign magnitude bit 15 bit 0
? 2004 microchip technology inc. ds21760e-page 25 ps700 4.4.16 opmode ? operation mode control register register 4-8: opmode: operation mode control register (address 7a hex/decimal 122) sslp reserved sslpdiv shelf por spor bit 7 bit 0 bit 7 sslp: sample-sleep enable bit setting this bit to a ? 1 ? immediately enables sample-sleep mode. the low-power oscillator is enabled and the a/d sampling rate is reduced. clearing this bit to ? 0 ? disables sample-sleep mode. 1 = sample-sleep mode enabled 0 = sample-sleep mode disabled bit 6 reserved: reserved bit location bit 5-3 sslpdiv: sample-sleep divider bits these bits set the interval between sampling of the a/d during sample-sleep. the timing is set as: sampling interval = (.5 sec * 2 ** sampdiv * 2 ** sslpdiv) bit 2 shelf: shelf-sleep enable bit writing a ? 1 ? to this register will place the device in shelf-sleep mode. volatile memory will not be maintained. the shelf-sleep mode will not actually be entered until a smbus stop condition occurs and then sda and scl go low. bit 1 por: power-on reset bit a ? 1 ? in this register indicates that a power-on reset has occurred. write this register to ? 0 ? to clear this indicator. bit 0 spor: soft power-on reset bit writing a ? 1 ? to this register will cause the device to re-initialize by writing the contents of the eeprom into all working registers. legend: ?1? = bit is set ?0? = bit is cleared r = reserved bit
ps700 ds21760e-page 26 ? 2004 microchip technology inc. 4.4.17 tripctrl ? trip control registers register 4-9: tripctrl: trip control register s (address 76 hex/118 decimal) lex lent vpex vc1ent vc2ent shent reserved ov bit 7 bit 0 bit 7 iex: current exit from sample-sleep mode bit a ? 1 ? in this register will enable an exit from sample-sleep mode upon the following condition: | current | > i+trip. bit 6 ient: enter sample-sleep mode on current bit a ? 1 ? in this register will enable entry to sample-sleep mode under the following condition: | current | < i-trip. bit 5 vpex: pack voltage exit from sample-sleep mode bit a ? 1 ? in this register will enable an exit from sample-sleep mode upon the following condition: pack voltage > vptrip. bit 4 vc1ent: enter sample-sleep mode on vc1 voltage bit a ? 1 ? in this register will enable entry to sample-sleep mode upon the following condition: vc1 < vctrip. bit 3 vc2ent: enter sample-sleep mode on vc2 voltage bit a ? 1 ? in this register will enable entry to sample-sleep mode upon the following condition: vc2 < vctrip. bit 2 shent: enter shelf-sleep mode on pack voltage bit a ? 1 ? in this register will enable entry to shelf-sleep mode upon the following condition: v pack < vsh ent bit 1 reserved: reserved bit location bit 0 ov: overflow bit ps700 sets this bit when the input voltage is greater than the maximum value of the voltage range for an a/d conversion. legend: ?1? = bit is set ?0? = bit is cleared r = reserved bit
? 2004 microchip technology inc. ds21760e-page 27 ps700 4.5 power-on reset when power is first applied to the vc1 input, the ps700 automatically executes a power-on reset sequence. the device is held in a reset state while the voltage is below the minimum operating threshold, v por . when the voltage on the vc1 input rises above the v por threshold, the ps700 will initialize itself as described below. when initialization is complete, the ps700 will enter run mode. during the power-on reset sequence, the registers are loaded with initial values from eeprom locations 0x020-0x087. these locations are reserved to contain register initialization values. in a battery pack applica- tion, a power-on reset typically happens only at the time of pack manufacture, when the cells are first con- nected to the battery monitoring pcb containing the ps700. data in the eeprom locations, (bank 0) 0:0x020- 0:0x07f, will be loaded into the corresponding register locations in (bank 1) 1:0x020-1:0x07f. data in the eeprom locations, (bank 1) 0:0x080-0:0x084, will be loaded into the corresponding cal/setup register loca- tions in (bank 2) 2:0x080-2:0x084. in all cases, eeprom register initialization locations corre- sponding to ?reserved? register locations must contain the value of 0x00h in order to insure proper operation following a power-on reset. 4.6 factory register initialization the eeprom register initialization locations are pro- grammed with a set of default values at the time that the ps700 is manufactured. this programming results in the following general operational state of a ps700 following a power-on reset: all accumulators and time counters disabled and reset to ? 0 ? all a/d conversion disabled a/d registers programmed with their anticipated input source, resolution and input reference sample and shelf-sleep modes disabled all sample-sleep mode entry methods disabled and trip point values zeroed gpio inputs on vc2 and ntc disabled smbus address = 0x16 factory calibrated trim values for band gap, voltage reference, auxiliary oscillator and main oscillator table 4-6 lists in detail the values that are programmed into the eeprom register initialization locations. note: do not overwrite the factory trimmed values.
ps700 ds21760e-page 28 ? 2004 microchip technology inc. table 4-6: ps700 factory register initialization function byte 3 byte 2 byte 1 byte 0 bank:address (byte 0) operational registers: accumulators/ timers a/d registers mode control dca: 0x00000000 1:0x020 dtc: 0x00000000 1:0x024 cca: 0x00000000 1:0x028 ctc: 0x00000000 1:0x02c ta: 0x00000000 1:0x030 tat: 0x00000000 1:0x034 vc2a: 0x00000000 1:0x038 vc2t: 0x00000000 1:0x03c adconfig: 00000000b = 0x00 ictrl (adc0): 01110000b = 0x70 ires (adr0): 0x0000 1:0x040 reserved 0x00 itctrl (adc1): 00101001b = 0x29 itres (adr1): 0x0000 1:0x044 etctrl (adc2): 00101010b = 0x2a etres (adr2): 0x0000 1:0x048 vpctrl (adc3): 00101011b = 0x2b vpres (adr3): 0x0000 1:0x04c gpioctrl vc1ctrl (adc4): 00100100b = 0x24 vc1res (adr4): 0x0000 1:0x050 reserved: 0x00 vc2ctrl (adc5): 00100101b = 0x25 vc2res (adr5): 0x0000 1:0x054 offsctrl (adc6): 01110110b = 0x76 offsres (adr6): 0x0000 1:0x058 auxctrl (adc7): 00000110b = 0x06 auxres (adr7): 0x0000 1:0x05c accumctrl: 00000000b = 0x00 accclr: 00000000b = 0x00 i+trip: 0x0000 1:0x060 reserved: 0x00 reserved: 0x00 i-trip: 0x0000 1:0x064 vptrip: 0x0000 1:0x068 vctrip: 0x0000 1:0x06c sstrip: 0x0000 1:0x070 tripctrl: 00000000b = 0x00 reserved: 0x00 1:0x074 opmode: 00000000b = 0x00 1:0x078 reserved: 00000000b = 0x00 1:0x07c cal/setup registers mosct: 0xxxxxxxb (?xxxxxxx? = factory trim value) v reft : 0xxxxxxxb (?xxxxxxx? = factory trim value) v bgt : 0000xxxxb (?xxxx? = factory trim value) smbadd: 00010110b 2:0x080 reserved: 0x00 aosct: 000xxxxxb (?xxxxxxx? = factory trim value) reserved: 0x00 reserved: 0x00 2:0x084
? 2004 microchip technology inc. ds21760e-page 29 ps700 5.0 cal/setup mode and registers cal/setup mode allows the designer to reprogram the default smbus address and/or change the calibration parameters programmed at the factory for band gap, voltage reference and main oscillator trim values. entering cal/setup mode requires the host to request three consecutive and specific incorrect smbus addresses with no interruptions between requests. these addresses are: addr1 hex 50 addr2 hex 52 addr3 hex 74 after each address is sent, the ps700 will nack the address. once the sequence is complete, the ps700 will enter cal/setup mode and allow access to the cal/setup registers located in memory bank 2. to exit cal/setup mode, re-enter the same address sequence or power-down the part. the ps700 will always power-up with cal/setup mode disabled. the following registers are only available in cal/setup mode. 5.1 cal/setup mode registers register 5-1: smbadd: smbus address registers (address 80 hex/128 decimal) register 5-2: v bgt : band gap trim register (address 81 hex/129 decimal) smbadd reserved bit 7 bit 0 bit 7-1 smbadd: smbus address register bits the value placed in bits <7:1> of this register defines the smbus address for this device. bit 0 reserved: reserved bit location legend: ?1? = bit is set ?0? = bit is cleared r = reserved bit reserved v bgt bit 7 bit 0 bit 7-4 reserved: reserved bit location bit 3-0 v bgt : band gap voltage trim bits this value is set by the factory. legend: ?1? = bit is set ?0? = bit is cleared r = reserved bit
ps700 ds21760e-page 30 ? 2004 microchip technology inc. register 5-3: v reft : voltage reference trim register (address 82 hex/130 decimal) register 5-4: mosct: main oscillator trim regist er (address 83 hex/131 decimal) register 5-5: aosct: auxiliary oscillator trim register (address 86 hex/134 decimal) gpioen1 gpioen0 v reft bit 7 bit 0 bit 7 gpioen1: enable v cell 2 as gpio bit writing this bit to a ? 1 ? will configure the v cell 2 pin as a gpio. if enabled as gpio, the accumulation function in the accumctrl register and the trip function in the tripctrl register should be disabled. bit 6 gpioen0: enable ntc as gpio bit writing this register to a ? 1 ? will configure the ntc pin as a gpio. if enabled as gpio, the accumulation function in the accumctrl register should be disabled. bit 5-0 v reft : voltage reference trim bits bits 5-0 of this register store the trim value for both the +340 mv and + 170 mv references. this value is factory programmed. legend: ?1? = bit is set ?0? = bit is cleared r = reserved bit r osc _sel mosct bit 7 bit 0 bit 7 r osc _sel: resistor oscillator select bit writing this register to a ? 1 ? requires the use of a low temperature coefficient 221 k ? resistor on the r osc pin. writing this register to a ? 0 ? will allow the use of an internal 221 k ? resistor. (the precision of the internal time base will be affected by the selection of the resistor with the lowest variance of resistance over the systems operating range.) bit 6-0 mosct: main oscillator trim bits bits 0-6 of this register are used to trim the internal time base. this value is factory programmed. legend: ?1? = bit is set ?0? = bit is cleared r = reserved bit reserved aosct bit 7 bit 0 bit 7-5 reserved: reserved bit location bit 4-0 aosct: auxiliary oscillator trim bits trim bits for the secondary oscillator used in low-power modes. legend: ?1? = bit is set ?0? = bit is cleared r = reserved bit
? 2004 microchip technology inc. ds21760e-page 31 ps700 6.0 electrical characteristics table 6-1: absolute maximum ratings note: these are stress ratings only. stress greater than the listed ratings may cause permanent damage to the device. exposure to absolute maximum ratings for an extended period may affect device reliability. functional operation is implied only at the listed operating conditions below. table 6-2: dc characteristics (t a = -20c to +85c; v dd (internal) = +3.3v 10%) note 1: does not include current consumption due to external loading on pins. 2: sample mode current is specified during an a/d inactive cycle. sample mode average current can be calculated using the formula: average sample mode supply current = (i ddrun + (n ? 1) * i ddins )/n; where ?n? is the programmed sample rate. symbol description min max units vcx voltage at any vc(x) pin -0.5 10.0 v v pin voltage directly at any pin (except v cellx )-0.57.0v t bias temperature under bias -20 85 c t storage storage temperature (package dependent) -35 120 c symbol description min typ. max units condition vc1 supply voltage 2.7 ? 9.0 v v dd internal regulated supply voltage ? 3.3 ? v i dd supply current ? run mode ? 80 190 a a/d active (note 1) i ddins supply current ? sample mode ? 45 ? a a/d inactive (note 1, 2) i ddslp supply current ? sample-sleep mode ? 20 ? a sample-sleep mode (note 1) i ddsslp supply current ? shelf-sleep mode ? 300 ? na shelf-sleep mode (note 1) v il input low voltage ? io0, io1 ? ? 0.2 * v dd v v ih input high voltage ? io0, io1 0.8 * v dd ??v i il - iopu gpio input low current ? pull-up mode ? 7 ? a i l - io leakage current ? io pins programmed as outputs or inputs without pull-up ?1 2 a v ol - io output low voltage for io1, io0 ? ? 0.4 v i ol = 0.5 ma v oh - io output high voltage for io1 configured as push-pull 2.0 ? ? v i oh = 100 a v sr sense resistor input voltage range -152 ? 152 mv vr = 170 mv i ntc thermistor output current ? 12.5 ? a v il - smb input low voltage for smbus pins -0.5 ? 0.8 v v ih - smb input high voltage for smbus pins 2.0 ? 5.5 v v ol - smb output low voltage for smbus pins ? ? 0.4 v i pullup = 350 a v oh - smb output high voltage for smbus pins 2.1 ? 5.5 v i pullup - smb current through pull-up resistor or current source for smbus pins 100 ? 350 a i leak - smb input leakage current ? smbus pins ? ? 8 a
ps700 ds21760e-page 32 ? 2004 microchip technology inc. table 6-3: ac characteristics (t a = -20c to +85c; v dd (internal) = +3.3v 10%) table 6-4: ac characteristics ? smbus (t a = -20c to +85c; v dd (internal) = +3.3v 10%) note 1: t high max. provides a simple, ensured method for devices to detect bus idle conditions. 2: t low : sext is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop. 3: t low : mext is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack or ack-to-stop. 4: rise and fall time is defined as follows: t r = (v ilmax ? 0.15) to (v ihmin + 0.15) t f = 0.9v dd to (v ilmax ? 0.15) table 6-5: a/d converter characteristics (t a = -20c to +85c; v reg (internal) = +3.3v 10% ) note 1: voltage is internal at a/d converter inputs. v sr and v ntc are measured directly. vc(x) inputs are measured using internal level translation circuitry that scales the input voltage range appropriately for the converter. symbol description min typ. max units condition f rc internal rc oscillator frequency 130,613 131,072 131,530 hz f a / d internal a/d operating clock ? f rc /4 ? hz t por power-on reset delay ? 2 10 ms delay from time when vc1 voltage exceeds 2.7v t shelf delay to entry of shelf-sleep mode 1 ? ? ms (shent = 1 or v pack < vptrip) and (sda and scl go low) t wake delay to exit of shelf-sleep mode 1 ? ? ms sda and scl go high symbol description min typ. max units condition f smb smbus clock operating frequency 10 ? 100 khz slave mode t buf bus free time between start and stop 4.7 ? ? s t shld bus hold time after repeated start 4.0 ? ? s t su : sta setup time before repeated start 4.7 ? ? s t su : stop stop setup time 4.0 ? ? s t hld data hold time 0 ? ? ns t setup data setup time 250 ? ? ns t low clock low period 4.7 ? ? s t high clock high period 4.0 ? 50 s (note 1) t low : sext message buffering time ? ? 10 ms (note 2) t high : mext message buffering time ? ? 10 ms (note 3) t f clock/data fall time ? ? 300 ns (note 4) t r clock/data rise time ? ? 1000 ns (note 4) symbol description min typ. max units condition ad res a/d converter resolution 9 ? 16 bits (note 1) t conv a/d conversion measurement time, n-bit ? 2 (n + 1) /f a / d ?s v adin a/d converter input voltage range (internal) -152 ? 152 mv vr = 170 mv 0 ? 309 mv vr = 340 mv e vgain supply voltage gain error ? ? 0.100 % e voffset compensated offset error ? ? 0.100 % e temp temperature gain error ? ? 0.100 % e inl integrated nonlinearity error ? ? 0.004 %
? 2004 microchip technology inc. ds21760e-page 33 ps700 figure 6-1: smbus ac timing diagrams table 6-6: silicon time base characteristics (t a = -20c to +85c; v reg (internal) = +3.3v 10% ) table 6-7: temperature measurement accuracy ( t a = -20c to +85c; v reg (internal) = +3.3v 10% ) t hd:sta t buf t low t r t hd:sta t high t su:dat t f t su:sta t su:sto ps s p scl sda scl sda t low:mext scl ack note: scl ack is the acknowledge related clock pulse generated by the master. scl ack t low:mext t low:mext t low:sext t su:sta symbol description min typ. max units condition e time silicon time base error 0.35 % bias resistor r osc tolerance = 1%, t l = 25 ppm symbol description min typ. max units condition t res reported temperature resolution ? 1 ? k t acc reported temperature accuracy -3 ? 3 k t drift reported temperature drift ? -2 ? k/v
ps700 ds21760e-page 34 ? 2004 microchip technology inc. 7.0 packaging information 8-lead plastic thin shrink small outline (st) ? 4.4 mm (tssop) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 3.10 3.00 2.90 .122 .118 .114 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 .043 a overall height 0.65 .026 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters* inches units a2 a a1 l c 1 2 d n p b e e1 foot angle 048048 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005? (0.127mm) per side. jedec equivalent: mo-153 drawing no. c04-086 significant characteristic
? 2004 microchip technology inc. ds21760e-page 35 ps700 appendix a: ps700 data sheet revision history revision a-b (july 2003) removed preliminary condition tag. updated figure 3-3 (page 13). changed format of all operational registers in section 4.4 ?operational registers? . revision b-c (april 2004) removed pec ? pages 1, 10, 12 (figure 3-2) and 13 (figure 3-3). removed nimh 3-6 cell ? pages 1, 2 and 4. updated figure 1-2 ? page 3. removed independent a/d input on pin 1 ? page 3. changed resolution nomen- clature to bit + sign ? pages 5 and 20 (register 4-3). added table 3-3 ? page 6. added section 3.1.4.1 ?internal temperature? and section 3.1.4.2 ?external temperature? . in section 3.2.2 ?sample mode? , added sample-sleep entry exception ? page 9. updated memory map, table 4-1 ? page 15. added table 4-2: ps700 eeprom map ? page 16. changed smbus address factory default from 0x06 to 0x16 ? pages 27 and 28. revision c-d (may 2004) operating temperature typo correction, 70c to 85c ? pages 32 and 33. revision d-e (july 2004) corrected errors in section 3.1.4.2 ?external temperature? . changed internal to external and corrected v ex equation. added appendix a ?revision history? . changed value of bits column in table 3-3 from ?10? to ?9 + sign?. changed reference to ?10 bits of resolution? in section 3.1.4.1 ?internal temperature? to ?10-bit plus sign of resolution?. changed references to ?16 bits of resolution? in section 3.1.6 ?accumulation/ timing? to ?15-bit plus sign?. added information to section 4.2 ?eeprom? about temperature and voltage limits for data eeprom writes.
ps700 ds21760e-page 36 ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. ds21760e-page 37 ps700 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microc hip?s products as critical com- ponents in life support systems is not authorized except with express written approval by mi crochip. no licenses are con- veyed, implicitly or otherwis e, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, pic, picmicro, powersmart and smartshunt are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. smartsensor is a registered trademark of microchip technology incorporated in the u.s.a. powercal, powerinfo, powermate, powertool and smarttel are trademarks of microchip technology incorporated in the u.s.a. and other countries. all other trademarks mentioned he rein are property of their respective companies. ? 2004, microchip technology incorporated. printed in the u.s.a., all rights reserved. printed on recycled paper.
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