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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD9870 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 if digitizing subsystem functional block diagram ifin fref AD9870 lna ?6db lo synth ioutl lop lon ioutc clkp clkn vrefp vcm vrefn pc pd pe syncb lo vco and loop filter clk vco and loop filter samp clock synthesizer mxop mxon if2p if2n gcp gcn decimation filter control logic f clk = 18mhz - adc dac agc spi vo ltag e reference formatting/ssi douta doutb fs clkout vga / aaf features 10 mhzC300 mhz input frequency baseband (i/q) digital output 10 khzC150 khz output signal bandwidth 12 db ssb nf > C1 dbm iip3 (high iip3 mode) 25 db continuous agc range + 16 db gain step support for lo and sampling clock synthesis programmable decimation rate, output format, aaf cutoff, agc and synthesizer settings 360 input impedance 2.7 vC3.6 v supply voltage low current: 42 ma typ (high iip3 mode), 30 ma typ (low iip3, fixed gain mode) 48-lead lqfp package (1.4 mm thick) applications portable and mobile radio products digital uhf/vhf fdma products tetra product description the AD9870 is a general-purpose if subsystem that digitizes a low-level 10 mhzC300 mhz if input with a bandwidth of up to 150 khz. the signal chain of the AD9870 consists of a low-noise amplifier, a mixer, a variable gain amplifier with integral antialias filter, a bandpass sigma-delta analog-to-digital converter, and a decimation filter with programmable decimation factor. an auto- matic gain control (agc) circuit provides the AD9870 with 25 db of continuous gain adjustment. the high dynamic range of the bandpass sigma-delta converter allows the AD9870 to cope with blocking signals that are as much as 70 db stronger than the desired signal. auxiliary blocks include clock and lo synthesizers as well as a serial peripheral interface (spi) port. the spi port programs numerous parameters of the AD9870, including the synthesizer divide ratios, the agc attack and decay times, the agc target signal level, the decimation factor, the output data format, the 16 db attenuator, and the bias currents of several blocks. reducing bias currents allows the user to reduce power consumption at the expense of reduced performance.
rev. 0 C2C AD9870?pecifications parameter conditions 1 min typ max unit overall analog supply voltage (vdda, vddf, vddi) 2.7 3.0 3.6 v digital supply voltage (vddd, vddc, vddl) 2.7 3.0 3.6 v interface supply voltage (vddh) 1.8 3.6 v charge pump supply voltage (vddp, vddq) 2.7 3.0 5.5 v total current high iip3 setting 42 50.6 ma ssb noise figure @ max vga gain high iip3 setting 12 db low iip3 setting 12 db input third-order intercept (iip3) high iip3 setting C5 C1 dbm low iip3 setting C10 dbm input impedance 360 ? gain variation over temperature 0.6 db preamp + mixer maximum input and lo frequencies 300 mhz lo synthesizer lo input frequency 7.75 300 mhz lo input amplitude 0.3 1.0 v p-p fref (reference) frequency 0.1 25 mhz fref input amplitude 0.3 3 v p-p minimum charge pump output current programmable in 0.625 ma steps 0.625 ma maximum charge pump output current programmable in 0.625 ma steps 5.000 ma charge pump output compliance voltage 2 0.25 vddp C 0.25 v synthesizer resolution 6.25 khz clock synthesizer clk input frequency 13 18 mhz clk input amplitude clock vco off 0.3 v p-p minimum charge pump output current programmable in 0.625 ma steps 0.625 ma maximum charge pump output current programmable in 0.625 ma steps 5.000 ma charge pump output compliance voltage 2 0.25 vddq C 0.25 v synthesizer resolution 2.2 khz sigma-delta adc resolution 16 bits clock frequency (f clk ) 13 18 mhz center frequency f clk /8 mhz dynamic range bw = 10 khz 88 db passband gain variation 0.5 db decimator decimation factor programmable in steps of 60 60 960 passband width 50 % passband gain variation 1db alias attenuation 85 db gain control programmable gain step 16 db agc gain range (continuous) 18 25 60 db agc attack time programmable 40 7000 s spi pc clock frequency 10 mhz pd hold time 10 ns ssi clkout frequency 1 18 mhz output rise/fall time cmos output mode, drive strength = 0 120 ns cmos output mode, drive strength = 1 45 ns cmos output mode, drive strength = 2 16 ns cmos output mode, drive strength = 3 10 ns operating temperature range basic functions C40 +95 c meets all specifications C40 +85 c notes 1 standard operating mode: high iip3 setting, synthesizers in normal (not fast acquire) mode, f clk = 18 mhz, 25 pf load on ssi output pins: vddx = 3.0 v. 2 voltage span in which lo (or clk) charge pump output current is maintained within 5% of nominal value of vddp/2 (or vddq/2). specifications subject to change without notice. (vddi = vddf = vdda = 3.3 v, vddc = vddl = 3.3 v, vddd = vddh = 3.3 v, vddq = vddp = 5.0 v, clk = 18 msps, f if = 73.35 mhz, f lo = 71.1 mhz, unless otherwise noted.)
rev. 0 AD9870 C3C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9870 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings * parameter with respect to min max unit vddf, vdda, vddc, vddd, vddh, gndf, gnda, gndc, gndd, gndh C0.3 +4.0 v vddl, vddi gndl, gndi, gnds vddf, vdda, vddc, vddd, vddh, vddr, vdda, vddc, vddd, vddh, C4.0 +4.0 v vddl, vddi vddl, vddi vddp, vddq gndp, gndq C0.3 +6.0 v gndf, gnda, gndc, gndd, gndh gndf, gnda, gndc, gndd, gndh C0.3 +0.3 v gndl, gndi, gndq, gndp, gnds gndl, gndi, gndq, gndp, gnds mxop, mxon, lop, lon, ifin, gndi C0.3 vddi + 0.3 v cxif, cxvl, cxvm pc, pd, pe, clkout, douta, gndh C0.3 vddh + 0.3 v doutb, fs, syncb if2n, if2p, gcp, gcn gndf C0.3 vddf + 0.3 v vrefp, vrefn, vcm gnda C0.3 vdda + 0.3 v ioutc gndq C0.3 vddq + 0.3 v ioutl gndp C0.3 vddp + 0.3 v clkp, clkn gndc C0.3 vddc + 0.3 v fref gndl C0.3 vddl + 0.3 v junction temperature 150 c storage temperature C65 +150 c lead temperature (10 sec) 300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposu re to absolute maximum ratings for extended periods may affect device reliability. thermal characteristics thermal resistance 48-lead lqfp ja = 91 c/w jc = 28 c/w ordering guide model temperature range package description package option AD9870 C40 c to +85 c 48-lead thin plastic quad flatpack (lqfp) st-48 AD9870eb evaluation board
rev. 0 AD9870 C4C pin function descriptions pin mnemonic description pin mnemonic description 1 mxop mixer output, positive 25 pe enable input for spi port 2 mxon mixer output, negative 26 vddd positive power supply for internal digital func tions 3 gndf ground for vga 27 vddh positive power supply for digital interface 4 if2n second if input (to vga), negative 28 clkout clock output for ssi port 5 if2p second if input (to vga), positive 29 douta data output for ssi port 6 vddf positive power supply for antialias filter/vga 30 doutb data output for ssi port, unused 7 gcp filter capacitor for vga gain control, positive 31 fs frame sync for ssi port 8 gcn filter capacitor for vga gain control, negative 32 gndh ground for digital interface 9 vdda positive power supply for adc 33 syncb resets the ssi and decimator counters 10 gnda ground for adc 34 gnds substrate ground 11 vrefp voltage reference, positive 35 fref reference frequency input for both synthesizers 12 vrefn voltage reference, negative 36 gndl ground for lo synthesizer 13 vcm common-mode voltage (requires 20 k ? to gnda) 37 gndp ground for lo synthesizer charge pump 14 vddq pos. power supply for clock synth. charge pump 38 ioutl lo synthesizer charge pump output current 15 ioutc clock synthesizer charge pump output current 39 vddp positive power supply for lo synth. charge pump 16 gndq ground for clock synthesizer charge pump 40 vddl positive power supply for lo synthesizer 17 vddc positive power supply for clock synthesizer 41 cxvm external capacitor for mixer bias 18 gndc ground for clock synthesizer 42 lon lo input to mixer and lo synthesizer, negative 19 clkp sampling clock input/clock vco tank, positive 43 lop lo input to mixer and lo synthesizer, positive 20 clkn sampling clock input/clock vco tank, negative 44 cxvl external capacitor for preamp power supply 21 gnds substrate ground 45 gndi ground for mixer and preamp 22 gndd ground for digital functions 46 cxif external capacitor for preamp bias 23 pc clock input for spi port 47 ifin first if input (to preamp) 24 pd data i/o for spi port 48 vddi positive power supply for mixer and preamp pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) gndl fref gnds syncb gndh fs doutb mxop mxon gndf if2n if2p vddf gcp gcn vdda gnda vrefp douta clkout vddh vddd AD9870 vrefn pe vddi ifin cxif gndi cxvl lop lon cxvm vddl vddp ioutl gndp vcm vddq ioutc gndq vddc gndc clkp clkn gnds gndd pc pd
rev. 0 AD9870 C5C serial peripheral interface (spi) the serial peripheral interface (spi) is a bidirectional serial port. it is used to load configuration information into the reg isters listed below as well as to read back their contents. table i provides a list of the registers that may be programmed through the spi po rt. addresses and default values are given in hexadecimal form. table i. spi address map address bit (hex) breakdown width default value name description power control registers 0x00 (7:0) 8 0xff stby standby control bits (ref, lo, cko, ck, gc, lnamx, vga, adc). 0x01 (7:6) 2 0 lnab lna bias current (0 = 0.5 ma, 1 = 1 ma, 2 = 2 ma, 3 = 3 ma). (5:4) 2 0 mixb mixer bias current (0 = 1 ma, 1 = 2 ma, 2 = 3 ma, 3 = 4 ma). (3:2) 2 0 ckob ck osc illator bias (0 = 0.25 ma, 1 = 0.35 ma, 2 = 0.53 ma, 3 = 0.85 ma). (1:0) 2 1 adcb adc amplifier bias (0 = 2.4 ma, 1 = 3.2 ma, 2 = 4.0 ma, 3 = 4.8 ma). 0x02 (7:0) 8 0x00 test factory test mode. agc 0x03 (7) 1 0 atten apply 16 db attenuation in the front end. (6:0) 7 0x3f agcg(14:8) agc gain setting (7 msbs of a 15-bit twos-complement word). 0x04 (7:0) 8 0xff agcg(7:0) agc gain setting (8 lsbs of a 15-bit twos-complement word). default corresponds to maximum gain. 0x05 (7:4) 4 0 agca agc attack time setting. default yields 50 hz raw loop bandwidth. (3:0) 4 0 agcd agc decay time setting. default is decay time = attack time. 0x06 (7:4) 4 0 agco agc overload update setting. default is slowest update. (3:0) 4 0 agcd fast agc (minimizes resistance seen between gcn and gcp). (2:0) 3 0 agcr agc enable/reference level (disabled, 3 db, 6 db, 9 db, 12 db, 15 db below clip). decimation factor 0x07 (3:0) 4 4 m decimation factor = 60 (m + 1). default is decimate-by-300. lo synthesizer 0x08 (5:0) 6 0x00 lor(13:8) reference frequency divisor (6 msbs of a 14-bit word). 0x09 (7:0) 8 0x38 lor(7:0) reference frequency divisor (8 lsbs of a 14-bit word). default (56) yields 300 khz from f ref = 16.8 mhz. 0x0a (7:5) 3 0x5 loa a counter (prescaler control counter). (4:0) 5 0x00 lob(12:8) b counter msbs (5 msbs of a 13-bit word). default loa and lob values yield 300 khz from 73.35 mhzC2.25 mhz. 0x0b (7:0) 8 0x1d lob(7:0) b counter lsbs (8 lsbs of a 13-bit word). 0x0c (6) 1 0 lof enable fast acquire. (5) 1 0 loinv invert charge pump (0 = pump_up ? ioutl sources current). (4:2) 3 0 loi charge pump current in normal operation. i pump = (loi + 1) 0.625 ma. (1:0) 2 0 lotm ma nual control of lo charge pump (3 = off, 2 = down, 1 = up, 0 = nor mal). 0x0d (3:0) 4 0x0 lofa(13:8) lo fast acquire time unit (4 msbs of a 14-bit word). 0x0e (7:0) 8 0x04 lofa(7:0) lo fast acquire time unit (8 lsbs of a 14-bit word). clock synthesizer 0x10 (5:0) 6 00 ckr(13:8) reference frequency divisor (6 msbs of a 14-bit word). 0x11 (7:0) 8 0x38 ckr(7:0) reference frequency divisor (8 lsbs of a 14-bit word). default yields 300 khz from f ref =16.8 mhz. min = 3, max = 16383. 0x12 (4:0) 5 0x00 ckn(12:8) synthesized frequency divisor (5 msbs of a 13-bit word).
rev. 0 AD9870 C6C address bit (hex) breakdown width default value name description clock synthesizer (continued) 0x13 (7:0) 8 0x3c ckn(7:0) synthesized frequency divisor (8 lsbs of a 13-bit word). default yields 300 khz from f clk = 18 mhz. min = 3, max = 8191. 0x14 (6) 1 0 ckf enable fast acquire. (5) 1 0 ckinv invert charge pump (0 = pump_up ? ioutc sources current). (4:2) 3 0 cki charge pump current in normal operation. i pump = (cki + 1) 0.625 ma. (1:0) 2 0 cktm manual control of clk charge pump (0 = o ff, 1 = down, 2 = up, 3 = normal). 0x15 (3:0) 4 0x0 ckfa(13:8) ck fast acquire time unit (4 msbs of a 14-bit word). 0x16 (7:0) 8 0x04 ckfa(7:0) ck fast acquire time unit (8 lsbs of a 14-bit word). ssi control 0x18 (7:0) 8 0x12 ssicra ssi control register a. see table iii. (default is fs and clkout three-stated.) 0x19 (1:0) 2 0x0 ssicrb ssi control register b. see table iii. 0x1a (3:0) 4 1 ssiord output rate divisor. f clkout = f clk /ssiord. aaf capacitor setting/calibration 0x1c (7:0) 8 0x00 aar antialias response selector. 0x60 is recommended. 0x1d 5 1 0 errn error flag. (4:0) 5 0x0 capn aaf n-well capacitor setting. 0x1e 5 1 0 errp error flag. (4:0) 15 0x0 capp aaf poly-poly capacitor setting. test registers and spi port read enable 0x38 (7:0) 8 0x00 test factory test mode. 0x39 0 1 0 test factory test mode. 0x3a (7:4, 2:0) 7 0x0 test factory test mode. (3) 1 0 spiren enable read from spi port. 0x3bC (7:0) 1 0x00 test factory test mode. 0x3f
rev. 0 AD9870 C7C pc pe pd pd write operation: read operation: a5 a5 a0 a0 d7 d7 d6 d6 d0 d0 figure 1. spi timing figure 1 illustrates the timing for the spi port. after the periph- eral enable (pe) signal goes low, data (pd) is read on the rising edges of the clock (pc). the first bit is a read/not-write indica- tor; the next six bits are address bits; the eighth bit is ignored; the last eight bits are data. address and data are given msb first. if the read/not-write indicator is a zero, a write operation occurs and the data bits are shifted in. if the read/not-write indicator is a one and if the read-back enable bit (reg. 3a, bit 3) has been set, a read opera tion occurs and data is shifted out the data pin on the falling edges of the clock. pe stays low during the operation and goes high at the end of the transfer. if pe rises before an addi- tional eight clock cycles have passed, the operation is aborted. if pe stays low for an additional eight clock cycles, the destina- tion address is increm ented and another eight bits of data are shifted in. again, should pe rise early, the current byte is ignored. by using this implicit addressing mode, the entire chip can be configured with a single write operati on. registers identified as being subject to frequent updates, namely those associated with power control and agc operation, have been assigned a djacent addresses to minimize the time required to update them. the auto- increment mode is not supported for read operations. multibyte registers are big-endian (the most significant byte has the lower address) and are updated when a write to the least significant byte occurs. synchronous serial interface (ssi) the primary output of the AD9870 is the converted signal, which is available from the ssi port as a serial bit stream. the bit stream consists of a 16-bit i word followed by a 16-bit q word, where each word is given msb first and is in twos-complement form. agc, signal strength, and synchronization information may also be embedded in the data stream. the output bit rate ( f clkout ) is equal to the modulator clock frequency ( f clk ) divided by the contents of the ssiord register. users must verify that the output bit rate is sufficient to accommodate the required num- ber of bits per frame (see table ii) and that the chosen output rate does not introduce harmful spurs. idle (high) bits are used to fill out each frame; the frame lengths listed in table ii assume that with embedded frame sync (efs = 1), at least 10 idle bits are desired. table ii. max legal ssiord values for 16-bit i/o data and decimation by 60 n bits per sample (min no. of bits per frame) eagc = 0 eagc = 1 efs =1 efs = 0 efs = 0 efs = 1 32 49 48/40 * 69/59 * output sample rate max ssiord setting (decimal) dec? (ksps, for eagc = 0 eagc = 1 m factor f clk = 18 mhz) efs = 0 efs = 1 efs = 0 efs = 1 0 60 300 1 1 1 1 1 120 150 3 2 2 1 2 180 100 5 3 3 2 3 240 75 7 4 5 3 4 300 60 9 5 6 4 5 360 50 11 7 7 5 6 420 42.857 13 8 8 5 7 480 37.5 14 9 10 6 8 540 33.333 15 10 11 7 9 600 30 15 11 12 8 10 660 27.272 15 13 13 9 11 720 25 15 14 14 10 12 780 23.077 15 15 15 11 13 840 21.428 15 15 15 11 14 900 20 15 15 15 12 15 960 18.75 15 15 15 13 * if the aagc bit of ssicra is set. figure 2 illustrates the output timing of the ssi port for several ssi control register settings. in the default mode of operation, data is shifted out on rising edges of clkout after a pulse is output from the frame sync (fs) pin. as described above, the output data consists of a 16-bit i sample followed by a 16-bit q sample plus two optional bytes containing agc and status information.
rev. 0 AD9870 C8C the two optional bytes are output if the eagc bit of ssicra is set. the first byte contains the eight most significant bits of the agc dac setting while the second byte contains a 2-bit overload field, a 2-bit reset field, a 2-bit large-signal field, a zero bit, and a trailing high bit. the overload, reset, and large-signal fields contain the number of overload, reset, and large-signal events since the last report, respectively, saturating at three should the number of events equal or exceed this amount. the two optional bytes follow the i and q data as a 16-bit word provided the aagc bit of ssicra is not set. if the aagc bit is set, the two bytes follow the i and q data in an alternating fashion. in this alternate agc data mode, the lsb of the byte containing the agc dac setting is zero; the lsb of the byte containing reset/overload information is always a one. figure 3 illustrates the fields of the ssi data frames. eagc = 0, aagc = x: 32 data bits eagc = 1, aagc = 0: 48 data bits eagc = 1, aagc = 1: 40 data bits i (15:0) q (15:0) i (15:0) q (15:0) agc (7:0) 1 i (15:0) q (15:0) agc (7:1) 0 i (15:0) q (15:0) 1 overload count reset count don t care fgm same figure 3. ssi frame structure fs dout clkout fs dout clkout fs dout scki = 0, sckt = 0, slfs = x, sfsi = x, efs = 1, sfst = 1, eagc = 0 scki = 0, sckt = 0, slfs = x, sfsi = x, efs = 1, sfst = 1, eagc = 0: as above, but fs is low idle (high) bits clkout scki = 0, sckt = 0, slfs = 0, sfsi = 0, efs = 0, sfst = 0, eagc = 1, aagc = 0 i15 i0 q15 q14 q0 g15 g14 g0 clkout fs dout scki = 0, sckt = 0, slfs = 1, sfsi = 0, efs = 0, sfst = 0, eagc = 0 i15 i0 q15 q14 q0 start bit start bit stop bit stop bit start bit hi-z scki = 0, sckt = 0, slfs = 0, sfsi = 0, efs = 0, sfst = 0, eagc = 0 i15 i8 i7 i0 q15 i15 i0 q15 q14 q0 figure 2. ssi timing for several ssicr settings
rev. 0 AD9870 C9C when the embedded frame sync bit (efs) is set, fs is either low or in a high z state (as determined by the sfst bit), and framing information is embedded in the data stream. in this mode, each eight bits of data are surrounded by a start bit (low) and a stop bit (high), and each frame ends with at least 10 high bits. other control bits can be used to invert the frame sync (sfsi), to delay the frame sync pulse by one clock period (slfs), to invert the clock (scki), or to set the clock (sckt) to a high z state. note that if efs is set, slfs is a dont care. the AD9870 also provides the means for controlling the switch- ing characteristics of the digital output signals. with a 25 pf load, the rise and fall times of these signals are no more than 120 ns, 45 ns, 16 ns, or 10 ns if the ds (drive strength) setting is 0, 1, 2, or 3, respectively. table iii. ssi control registers name width description ssicra (addr = 0x18) aagc 1 alternate agc data bytes eagc 1 embed agc data efs 1 embed frame sync sfst 1 three-state frame sync sfsi 1 invert frame sync slfs 1 late frame sync (1 = late, 0 = early) sckt 1 three-state clkout scki 1 invert clkout ssicrb (addr = 0x19) ds 2 fs, clkout, and dout drive strength power control to allow power consumption to be minimized, the AD9870 possesses numerous spi-programmable power-down and bias control bits. each major block may be powered down through the appropri- ate bit of the stby register. this scheme provides the greatest flexibility for configuring the ic to a specific application as well as for tailoring the ics power-down and wake-up characteristics. table iv summarizes the function of each of the stby bits. note, when all the blocks are in standby, the master reference circuit is also put into standby and thus the current is reduced by a further 0.4 ma. the AD9870 also allows control over the bias current in several key blocks. the effects on current consumption and system performance are described in the section dealing with the affected block. table iv. standby control bits wake- current up stby reduction time bit effect (ma) 1 (ms) ref voltage reference off, 1.5 1.0 vrefp, vrefn in (c ref = high z state. 4.7 f) lo lo synthesizer off, 4.8 note 2 ioutl in high z state. cko clock oscillator off. 0.25 note 2 ck clock synthesizer off, 1.4 note 2 ioutc in high z state. clock buffer off if adc is off. gc gain control dac off. 3 depends gcp, gcn in high z state. on c gc lnamx lna and mixer off. 10 i(vddi) = 0, cxvm, cxvl, cxif in high z. vga vga/aaf off. 6 0.1 if2p, if2n in high z state. adc adc off; clock buffer 13.8 0.1 off if ck synth. off; vcm in high z state; clock-to-digital filter suspended; digital outputs static. notes 1 when all blocks are in standby, the master reference circuit is also put into standby and thus the current is reduced by a further 0.4 ma. 2 wake-up time is application-dependent. lo synthesizer the lo synthesizer shown in figure 4 is a fully programmable pll capable of 6.25 khz resolution at input frequencies up to 300 mhz and reference clocks of up to 25 mhz. it consists of a low-noise digital phase-frequency detector (pfd), a variable output current charge pump (cp), a 14-bit reference divider, programmable a and b counters and a dual-modulus 8/9 pres- caler. the a (3-bit) and b (13-bit) counters, in conjunction with the dual 8/9 m odulus prescaler, implement an n divider with n = 8 b + a. in addition, the 14-bit reference cou nter (r counter) allows selectable input reference frequencies, f ref , at the pfd input. a complete pll (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and vco (voltage controlled oscillator).
rev. 0 AD9870 C10C the a, b, and r counters can be programmed via the following registers: loa, lob, and lor. the charge pump output current is programmable via the loi register from 0.625 ma to 5.0 ma using the following equation: i pump = (loi + 1) 0.625 ma. an on-chip lock detect function (enabled by the lof bit) auto- matically increases the output current for faster settling during channel changes. the synthesizer may also be disabled using the lo standby bit located in the stby register. fa s t acquire 8/9 a, b counters lo buffer loa, lob f lo from vco ref buffer f ref lor r f ref phase/ frequency detector to external loop filter f lo charge pump figure 4. lo synthesizer the lo (and clk) synthesizer works in the following manner. the reference frequency, f ref , is buffered and divided by the value held in the r counter. the internal f ref is then compared to a divided version of the vco frequency, f lo . the phase/ frequency detector provides up and down pulses whose width vary depending upon the difference in phase and frequency of its two input signals. the up/down pulses control the charge pump, making current available to charge the external low-pass loop filter when there is a discrepancy between the inputs of the pfd. the output of the low-pass filter feeds an external vco whose output frequency, f lo , is driven such that its divided down version, f lo , matches that of f ref thus closing the feed- back loop. the synthesized frequency is related to the reference frequency and the lo register contents as follows: f lo = (8 lob + loa )/ lor f ref note, the minimum allowable value in the lob register is 3 and its value must always be greater than that loaded into loa. the stability, phase noise, spur performance, and transient response of the AD9870s lo (and clk) synthesizers are determined by the external loop filter, the vco, the n-divide factor, and the reference frequency, f ref . an excellent reference book on pll synthesizers titled pll performance, simulation and design by deen banerjee is available for free at www.national.com. an example may help illustrate how the values of loa, lob, and lor can be selected. consider an application employing a 13 mhz crystal oscillator (i.e. , f ref = 13 mhz) with the re- quire ment that f ref = 100 khz and f lo = 143 mhz (i.e., high-side injection with if = 140.75 mhz and f sample = 18 msps). lor is selected to be 130 such that f ref = 100 khz. the n-divider factor is 1430, which can be realized by select- ing lob = 178 and loa = 6. figure 5 shows the equivalent input structures of the synthesiz- ers lo and ref buffers (excluding the esd structures). the lo input is fed to the lo synthesizers buffer as well as the AD9870s mixers lo port. both inputs are self-biasing and thus tolerate ac-coupled inputs. the lo input can be driven with a single-ended or differential signal. single-ended dc- coupled inputs should ensure sufficient signal swing above and below the common-mode bias of the lo and ref buffers (i.e., 1.38 v and vddl/2). f ref 84k ~vddl/2 lo buffer 500 500 to mixer lo port 1.36v bias lop lon note: esd diode structures omitted for clarity f ref stby switches shown with lo synthesizer on figure 5. equivalent input of lo and ref buffers fast acquire mode the fast acquire circuit attempts to boost the output cu rrent when the phase difference between the divided-down lo (i.e., f lo ) and the divided-down reference frequency (i.e., f ref ) exceeds the threshold determined by the lofa register. the lofa register specifies a divisor for the f ref signal, and it is the period (t) of this divided-down clock that specifies the time interval which controls the fast acquire algorithm. assume for the moment that the nominal charge pump current is at its lowest setting (i.e., loi = 0) and denote this minimum current by i 0 . when the output pulse from the phase compara- tor exceeds t, the output current for the next pulse is 2i 0 ; when the pulse is wider than 2t, the output current for the next pulse is 3i 0 , and so forth, up to eight times the minimum output current. if the nominal charge pump current is more than the minimum value (i.e., loi > 0), the preceding rule is only applied if it results in an increase in the instantaneous charge pump current. if the charge pump current is set to its lowest value (loi = 0) and the fast acquire circuit is enabled, the instantaneous charge pump current will never fall below 2i 0 , even when the pulsewidth is less than t. thus the charge pump current when fast acquire is enabled is given by i pump-fa = i o (1 + max (1, loi , pulsewidth / t )).
rev. 0 AD9870 C11C the recommended setting for lofa is lor/16. choosing a larger value for lofa will increase t. thus, for a given phase difference between the lo input and the f ref input, the instan- taneous charge pump current will be less than that available for a lofa value of lor/16. similarly, a smaller value for lofa will decrease t, making more current available for the same phase difference. in other words, a smaller value of lofa will enable the synthesizer to settle faster in response to a frequency hop than will a large lofa value. care must be taken to choose a value of lofa which is large enough (values greater than four recommended) to prevent the loop from oscillating back and forth in response to a frequency hop. table v. spi registers associated with lo synthesizer a ddress bit (hex) breakdown width default value name 0x00 (7:0) 8 0xff stby 0x08 (5:0) 6 0x00 lor(13:8) 0x09 (7:0) 8 0x38 lor(7:0) 0x0a (7:5) 3 0x5 loa (4:0) 5 0x00 lob(12:8 0x0b (7:0) 8 0x1d lob(7:0) 0x0c (6) 1 0 lof (5) 1 0 loinv (4:2) 3 0 loi (1:0) 2 0 lotm 0x0d (3:0) 4 0x0 lofa(13:8) 0x0e (7:0) 8 0x04 lofa(7:0) clock synthesizer the clock synthesizer is a fully programmable integer- n pll capable of 2.2 khz resolution at clock input frequencies up to 18 mhz and reference frequencies up to 25 mhz. it is similar to the lo synthesizer described previously in figure 4 with the following exceptions: ? it does not include an 8/9 prescaler nor an a counter. ? it includes a negative-resistance core which when used in conjunction with an external varactor serves as the vco. the 14-bit reference counter and 13-bit n-divider counter can be programmed via the following registers: ckr and ckn. the charge pump current is programmable via the cki register from 0.625 ma to 5.0 ma using the following equation: i pump = ( cki + 1) 0.625 ma . the fast acquire subcircuit of the charge pump is controlled by the ckfa register in the same manner as the lo synthesizer is controlled by the lofa register. an on-chip lock detect func- tion (enabled by the ckf bit) automatically increases the output current for faster settling during channel changes. the synthe- sizer may also be disabled using the ckob standby bit located in the stby register. 2 clk osc. bias i bias = 0.25, 0.35, 0.53, or 0.85 ma vddc=3.0 v ioutc l osc 0.1 f r bias c osc loop filter c va r r d AD9870 clkn clkp v cm = vddc r bias i bias > 1.6v f osc > (2 l osc (c varactor //c osc )) 1/2 figure 6. external loop filter, varactor and l-c tank are required to realize a complete clock synthesizer the AD9870 clock synthesizer circuitry includes a negative- resistance core so that only an external l-c tank circuit with a varactor is needed to realize a voltage controlled oscillator (vco). figure 6 shows the external components required to complete the clock synthesizer along with the equivalent input of the clk input. the resonant frequency of the vco is approximately deter- mined by l osc and the series equivalent capacitance of c osc and c var . as a result, l osc , c osc , and c var should be selected to provide sufficient tuning range to ensure proper locking of the clock synthesizer the bias, i bias , of the negative-resistance core has four programmable settings. lower equivalent q of the l-c tank circuit may require a higher bias setting of the negative- resistance core to ensure proper oscillation. r bias should be selected such that the common-mode voltage at clkp and clkn is approximately 1.6 v. the synthesizer may be disabled via the ck standby bit to allow the user to employ an external synthesizer and/or vco in place of those resident on the ic. table vi. spi registers associated with clk synthesizer a ddress bit (hex) breakdown width default value name 0x00 (7:0) 8 0xff stby 0x01 (3:2) 2 0 ckob 0x10 (5:0) 6 00 ckr(13:8) 0x11 (7:0) 8 0x38 ckr(7:0) 0x12 (4:0) 5 0x00 ckn(12:8) 0x13 (7:0) 8 0x3c ckn(7:0) 0x14 (6) 1 0 ckf (5) 1 0 ckinv (4:2) 3 0 cki (1:0) 1 0 cktm 0x15 (3:0) 4 0x0 ckfa(13:8) 0x16 (7:0) 8 0x04 ckfa(7:0)
rev. 0 AD9870 C12C if1 lna/mixer the AD9870 contains a single-ended lna followed by gilbert- type active mixer as shown in figure 7a. the mixers differential lo port is driven by an lo buffer stage which can be driven single-ended or differential. the lo signal level can range from 0.3 v p-p to 1.0 v p-p with negligible effect on performance. the input impedance at the ifin pin is 360 ? 2 pf ( 20%) and has no significant variation with respect to the programmable bias settings. figure 7b. shows the s11 parameters of the AD9870 with the following lna/mixer bias setting: lnab = 3, mixb = 3. r gain r f r in = 360 r bias lna gain = 15 db 180 180 mixer gain = 5 db lo input = 0.3 to 1.0 v p p dc servo loop multi-tanh v i stage vcml figure 7a. simplified schematic of AD9870s lna/mixer 10 25 50 100 200 400 j10 j10 j25 j25 j50 j50 j100 j100 j200 j200 j400 j400 0 323 j105 at 73.35 mhz 255 j163 at 140 mhz 166 j177 at 240 mhz figure 7b. input impedance (i.e. s11) of the AD9870s if1 input both the lna and mixer have four programmable bias settings so that current consumption can be minimized for a given appli- cation. figures 7c, 7d, and 7e show how the lna and mixers noise figure (nf), linearity (iip3), conversion gain, current consumption and frequency response are all affected for a given lna/mixer bias setting. the measurements were taken at an if = 73.35 mhz, an lo = 71.1 mhz, and supplies set to 3.0 v. note, since the current consumption of the lna/mixer portion of the ic can be reduced by only 5 ma at most relative to the nominal current consumption of the entire ic in the high iip3 mode (i.e., 42 ma), most applications will benefit with the AD9870s lna/mixer configured for the high bias mode (i.e., lnab = 3, mixb = 3 for spi port register 1). lna-mixer power bias setting 12 0 0 db 11 10 9 8 7 6 0 10 20 31 01 11 21 32 02 12 22 33 03 13 23 3 conversion gain noise figure figure 7c. lna/mixer noise figure and conversion gain vs. bias setting lna-mixer power bias setting 5 0 0 iip3 db 0 5 10 15 20 25 0 10 20 31 01 11 21 32 02 12 22 33 03 13 23 3 lna mixer current iip3 current ma 9 8 7 6 5 4 3 2 1 0 figure 7d. lna/mixer iip3 and current consumption vs. bias setting
rev. 0 AD9870 C13C frequency mhz 1 10 db 1 2 3 4 5 6 3 3 bias setting 100 1000 0 2 2 bias setting 1 1 bias setting 0 1 bias setting figure 7e. lna/mixer frequency response vs. bias setting table vii. spi registers associated with lna/mixer a ddress bit (hex) breakdown width default value name 0 x01 (7:6) 2 0 lnab 0x01 (5:4) 2 0 mixb 0x03 (7) 1 0 atten antialias filter the AD9870 includes a programmable continuous-time third order antialias filter (aaf) as shown in figure 8. its purpose is to suppress any noise or spectral components occurring at n f clk (f clk /8) from aliasing back into the sigma-delta adcs passband centered at f clk /8. it consists of a programmable capacitor at the mixer output providing a real pole plus a second order programmable filter built into the vga providing a com- plex pole pair. c2 c0 r0 180 g m0 g m1 c1 r1 r2 c0 and c1 consist of 36 nwell capacitors in parallel c3 consist of 36 poly-poly capacitors in parallel mixer (5mhz lowpass) i-v 2nd order lpf figure 8. equivalent circuit of antialias filter the aaf is typically tuned during the start-up phase of the AD9870. the user initiates tuning of the aaf by writing a value to the aar (antialias response) register. the following two consid- erations should be noted when tuning the aaf response. first, the accuracy of the tuning algorithm is sensitive to on-chip digital noise. thus, placing the adc in standby (i.e., register stby) prior to tuning the aaf is recommended . second, although the default setting of the aar register is 0x00, writing 0x00 is not recom- mended since all subsequent writes to this register will be ignored until power to the AD9870 is reapplied to reset this register. the aaf tuning algorithm works in the following manner. the AD9870 measures the oscillation frequency of an on-chip rc oscillator relative to the frequency applied to the clkp, clkn pins. it then uses this measurement in conjunction with the aar setting to program the capacitors of the aaf which sets the filters poles. the on-chip circuitry sets the capacitor -programming registers (capn and capp) to the required values based on the clock frequency and the aar setting. the recommended C3 db cutoff frequency is f clk /3.2 (selected by setting aar = 0x60) since it provides minimal signal attenu- ation in the passband region of f clk /8 and sufficient attenuation of the potential alias components in the transition band region. for this setting the frequency-scaling resolution is sufficient to yield less than 10% tuning error with clock frequencies between 13 mhz and 18 mhz. figure 9a shows the measured response of the antialias filter when it has been tuned with aar = 0x60 at an adc clock frequency of 18 mhz. the multiple curves show the possible tuning error due to the finite resolution of the tun- ing capacitors. in this example, the capacitor across the mixer load resistors yields a pole at 5 mhz, which degrades the mixer gain at 2.25 mhz by approximately 0.8 db. the nominal C3 db cutoff frequency of the antialias filter is 5.6 mhz. the nominal attenuation at the first alias (15.75 mhz) is 28 db and falls at 60 db/decade so that the nominal attenuation at 50 mhz is 60 db. 5 frequency mhz 0.1 aaf frequency response dbfs 5 15 25 35 45 55 65 1 10 100 2.25mhz if @ clk = 18msps figure 9a. antialias filter response with aar = 0x60 and f clk = 18 mhz. note, the curves have been normalized individually to 0 db at f 0 = 2.25 mhz. since the frequency measurements are performed relative to the clock frequency, the aafs normalized frequency response remains relatively independent of the adc clock frequency. there is guaranteed to be sufficient range in the programmable capacitor arrays to support the response of figure 9a for clock frequencies between 13 mhz and 18 mhz with the resolution indicated. also, the normalized frequency response of the aaf remains relatively independent of the programmed C3 db cutoff frequency over a 13 mhz to 18 mhz frequency range as shown in figure 9b. if the user specifies an unattainable response, the on-chip circuitry sets capn and/or capp to the limit of their ranges and also sets the errn and/or errp bit to indicate that the specified response cannot be supported.
C14C ) rev. 0 5 frequency mhz 0.01 aaf frequency response dbfs 5 15 25 35 45 55 65 0.1 1 10 75 85 95 f clk /8 f clk = 15msps f clk = 18msps f clk = 13msps figure 9b. measured normalized aaf frequency response for aar = 0 60 setting with f clk = 13, 15, and 18 mhz 5 frequency mhz 0.1 aaf frequency response dbfs 5 15 25 35 45 55 65 1 10 100 aar = 0 30 aar = 0 60 aar = 0 c0 figure 9c. measured aaf frequency response for differ- ent aar settings with f clk = 18 mhz changing the aar setting from the recommended value of 0 60 scales the frequency axis in an inverse way as shown in figure 9c. for example, to scale the frequency response down by a factor of 1.5 set the aar register to 1.5 times 0 60 (i.e., 0 90). this aar setting will not cause an error flag to be set for f clk = 18 mhz since the 3.7 mhz cutoff is within the guaranteed range. for f clk = 18 mhz, this aar setting would increase the attenuation at the first alias by 10 db, lower the C3 db cutoff from 5.6 mhz to 3.7 mhz, and reduce the mixer gain by 0.8 db due to the reduced mixer pole frequency . however, reducing f clk to 13 mhz while using the same aar setting in many parts may cause a deviation in the normalized frequency response since the C3 db cutoff of 2.7 mhz is well below the 3.5 mhz lower limit. in general, C3 db cutoff frequencies can be approxi- mated by the following equation: f C 3 db = (f clk /3.2) (0 60/ aar ) where aar is the hexadecimal contents of the aar register and 0 60 is its hexadecimal default setting. table viii. spi registers associated with aaf address bit (hex) breakdown width default value name 0x1c (7:0) 8 0x00 aar 0x1d 5 1 0 errn (4:0) 5 0x0 capn 0x1e 5 1 0 errp (4:0) 15 0x0 capp variable gain amplifier operation with automatic gain control the AD9870 contains a variable gain amplifier (vga) as well as all of the necessary signal estimation and control circuitry to implement automatic gain control (agc) as shown in figure 10. the agc control circuitry provides a high degree of pro- grammability to allow the user to optimize the agc response as well as the AD9870s dynamic range for a given application. the vga is programmable over a 25 db (typ) range and imple- mented in the same circuitry as the aaf circuitry previously discussed. since its input is self-biasing and presents a high impedance to the mixer output load, the differential output signal appearing at the mixer output (mxop, mxon) must be ac coupled to the vga input (if2p, if2n) with 0.1 f ceramic chip capacitors. note, an external 20 k ? resistor in parallel with a 0.1 f capacitor from vcm (pin 13) to gnda is required to ensure common-mode compatibility between the adc input and vga output. the purpose of the vga is to extend the usable dynamic range of the AD9870 by allowing the sigma-delta adc to digitize low level signals in the presence of larger unfiltered interferer signals without saturation or clipping the adc. the vga can oper- ate in either a user controlled variable gain control mode or automatic gain control (agc) mode. the vga may also be disabled using the vga standby bit located in the stby register. note, ideally the quiescent current of the vga circuitry should reduced from 6 ma to 0 ma when the standby is invoked. how- ever, it has been found that the standby current increases to 1.3 ma a few seconds (temperature dependent) after placing the vga in standby. hence, the user is recommended to write to the stby register periodically (0.1 ksps) and toggle the vga bit (i.e., write 0 followed by 1) to ensure that the standby current remains at approximately 0 ma. vga dac e j(2 f clk /8)t vga / aaf c dac gcn gcp if2p if2n - adc f clk dec1 20 20 i q a bs (i[n])+a bs (q[n]) agcr ref level agc control adc clip point olw 1 (1 z 1 ) f clk /20 figure 10. functional block diagram of vga and agc
rev. 0 AD9870 C15C variable gain control when in variable gain mode, the gain of the vga can be adjusted by writing to the 16-bit agcr register. note, proper loading of the agcr register requires that address 0x03 always be writ- ten prior to 0x04. the maximum update rate of the agcg register is f clk /100. the msb of this register is the bit which enables 16 db of at tenuation in the preamp. this feature allows the AD9870 to cope with large level signals beyond the vgas range to prevent overloading of the adc. the gain of the vga is set by an 8-bit control dac which provides a differential control signal to the vga appearing at pins gcp and gcn. two external 0.1 f capacitors, c dac , from gcp and gcn to analog ground, are required to smooth or filter the dacs output each time it updates. note, the dif- ferential equivalent value of these two capacitors (i.e., c dac/2 ) in combination with the dacs programmable output resis- tance sets the C3 db bandwidth and time constant associated with this rc network. automatic gain control (agc) the gain of the vga is automatically adjusted when the agc is enabled via the agcr register. in this mode, the gain of the vga is continuously updated in an attempt to ensure that the maximum signal level into the adc does not exceed a fixed analog adc clip level and that the rms output level of the adc is equal to a programmable reference level. this programmable level can be set at 3 db, 6 db, 9 db, 12 db, and 15 db below the adc saturation (clip level) by writing values from 1 to 5 to the 3-bit agcr field. note, the adc clip level is defined to be C2 dbfs of its full-scale (i.e., 0.28 v rms). if agcr is 0, auto- matic gain control is disabled. the agc control loop and estimation circuitry are implemented both in the analog and digital domain to cope with out-of-band interferers and in-band signals which could otherwise overload the adc. if the largest signal into the adc falls outside the passband of the first stage digital filter and exceeds the adc clip level of C2 dbfs, a control loop based on an analog com- parator is used to reduce the vga gain and prevent adc clipping. if the largest signal into the adc is the target signal (and/or interferer) falling within the passband defined by the first deci- mation filter (but below the adc clip level), a control loop based on a digital estimation of the signal power is used to con- trol the vga gain. referring to figure 10, an analog comparator is used to com- pare the vga output (or adc input) to a reference threshold which is close to that of the adc clip level. the output of the comparator will be a digital signal named olw which drives the digital integrator within the agc control loop when an over- load condition is detected. note, the detection of an overload condition via this analog signal estimation path takes precedence over the digital signal estimation path in the agc control loop until the analog overload condition is removed. for signals falling within the passband of the first stage decimate-by-20 digital filter, the rms power of the i and q signal is estimated digitally by the following equation: x est [n] = a bs ( i[n] ) + a bs ( q[n] ) (1) as a result, the vga and other registers involved in the agc algorithm are updated at f clk /20. the number of overload and adc reset occurrences within the final i/q update rate of the AD9870 as well as the agc value (8 msbs) can be read from the ssi data upon proper configuration. a description of the agc control algorithm and the user adjust- able parameters follows. first consider the situation in which the in-band signal is bigger than all out-of-band signals. in this case, the amplitude of the in-band signal will be tracked to the pro- grammed reference level by the agc using the output of the digital estimation block. if the difference is negative (i.e., the signal is too large), the gain is decreased with a proportionality constant determined by the agca setting. large agca values result in large gain changes thus rapid tracking of changes in signal strength. if the difference between the target and estimated signal level is positive (i.e., the signal is too small), the gain is increased but now the proportionality constant is determined by both the agca and agcd settings. agcd is effectively sub- tracted from agca, so large agcd results in smaller gain changes and thus slower tracking of fading signals. the 4-bit code in the agca field sets the raw bandwidth of the agc loop. with agca = 0, the agc loop bandwidth is at its minimum of 50 hz. each increment of agca increases the loop bandwidth by a factor of 2 1/2 ; thus the maximum band- width is 9 khz. a general expression for the attack bandwidth is bw a = 50 ( f clk /18 mhz ) 2 ( agca /2) hz (2) the attack time may be estimated from the loop bandwidth if one assumes that the loop dynamics are essentially that of a single-pole system as described by the following equation. t attack = 2.2/(100 2 agca /2 ) = 0.35/ bw a (3) this approximation is good if the extra pole caused by the rc filter on the dac output is at a sufficiently high frequency. if the rc pole is placed at four times the raw agc pole (i.e., rc = 1/(8 bw)) then equation 3 yields an attack time which is high by about 25%. a more accurate formula for this case is to replace the 2.2 in the numerator of equation 3 by 1.7. the 4-bit code in the agcd field sets the ratio of the attack time to the decay time in the amplitude estimation circuitry. when agcd is zero, this ratio is one. incrementing agcd multiplies the decay time-constant by 2 1/2 , allowing a 180:1 range in the decay time relative to the attack time. the decay time may be computed from t decay = t attack 2 ( agcd /2) (4) the 4-bit code in the agco field sets the weighting applied to gain updates when overload is detected. each increment in agco doubles the weighting factor. at the highest agco setting, each reset event will cause a 6 db reduction in the vga gain. lastly, the agcf bit reduces the dac source resistance by a factor of 8. this facilitates fast acquisition by lowering the rc time constant which is formed with the external capacitors connected from the gcp and gcn pins to ground. for an overshoot-free step response in the agc loop, the capacitors should be chosen such that the rc time constant is less than one quarter that of the raw loop. specifically, rc 1/(8 bw ) (5) where r is the resistance between the gcn and gcp pins and ground (30 k ? 30% if agcf = 0, <3.8 k ? if agcf = 1) and bw is the raw loop bandwidth. note that with c chosen at this upper limit, the loop bandwidth increases by approximately 30%.
rev. 0 AD9870 C16C table ix. spi registers associated with agc a d dress bit default (hex) breakdown width value name 0x03 (7) 1 0 atten (6:0) 7 0x3f agcg(14:8) 0x04 (7:0) 8 0xff agcg(7:0) 0x05 (7:4) 4 0 agca (3:0) 4 0 agcd 0x06 (7:4) 4 0 agco (3:0) 4 0 agcd (2:0) 3 0 agcr system noise figure (nf) vs. vga (or agc) control the AD9870s system nf is a strong function of the gain set- ting of the vga. the noise present at the output of the vga and input of the adc is relatively large and independent of the vga setting. under small signal conditions in which the vga is set to its maximum gain, this noise referred back to the input of the lnas input has less of an effect on raising the AD9870s system nf. however, under large signal conditions in which the gain of the vga must be reduced to prevent adc clipping, this noise quickly becomes a significant contributor in determining the AD9870s overall nf. figure 11 shows how the nf of the AD9870 in agc mode remains relatively constant as an inter- ferer signal input power is increased until its power reaches a programmed reference level (i.e., C3 db) at which point the nf degrades almost 1 db per db as the interferer signal is increased beyond this point, forcing the vga gain to decrease. as a result, it is recommended that the agc referenced level be set to 3 (i.e., agcr = 1) to maintain the best possible nf over the widest input signal range. interferer amplitude dbm 45 24 85 20 80 noise figure db 75 70 65 60 55 50 45 40 35 30 25 42 27 21 18 36 30 39 33 15 12 9 noise figure mean agc value adc clips at 24 dbm mean agc value 150 100 50 0 50 100 150 figure 11. noise figure vs. interferer signal level with an if = 73.35 mhz and clk = 18 msps and agcr = 1 decimation filter the decimation filter consists of a complex mix by f clk /8 and a cascade of three linear phase fir filters: dec1, dec2, and dec3 as shown in figure 12. dec1 downsamples by a factor of 20 using a fourth-order comb filter. dec2 also uses a fourth- order comb filter, but its decimation factor is set by the m control register. dec3 is a decim ate-by-3 fir filter. m dec2 sinc 4 filter m + 1 dec3 fir filter 3 i q complex data to ssi port cos sin data from modulator dec1 sinc 4 filter 20 figure 12. decimation filter architecture figure 13a shows the response of the complete decimation filter on a linear frequency axis for frequencies up to the third alias. as this figure shows, the alias with the least attenuation is located at the lower end of the third alias band and has an attenuation of 83 db. frequency khz 0 40 100 030 10 20 20 60 80 70 40 60 50 db folding point 5khz passband 88db attenuation (min) 83db attenuation (min) >100db attenuation figure 13a. frequency response for f clkout = 20 khz, showing the first three alias bands figure 13b shows the full response of the decimation filter with the decimation factor set to 60 on a logarithmic frequency scale, wh ile figure 13c shows the folded frequency response on a linear frequency scale and figure 13d shows a blowup of the passband. the location of the cutoff frequency shown in figure 13b is inversely proportional to the decimation factor. however, since both dec1 and dec2 are fourth-order comb filters, their combination is also a fourth-order comb filter and thus the shapes of the frequency responses shown in figures 13c and 13d are independent of the decimation factor.
rev. 0 AD9870 C17C 0 20 40 60 80 100 10 4 10 3 10 2 10 1 baseband frequency relative to f clk db figure 13b. decimator frequency response 0 20 40 60 80 100 0.50 0.25 0 normalized frequency relative to f out db figure 13c. folded decimator frequency response as figure 13d shows, the gain variation across the passband is approximately 0.4 db. normalization of full-scale is accurate to within 0.4 db across all decimation modes. normalized frequency relative to f out 40 100 0 20 0 60 80 0.25 db figure 13d. passband frequency response of the decimator evaluation board and software the evaluation board along with its accompanying software provide a simple means to evaluate the AD9870. the block diagram in figure 14 shows the major blocks of the evaluation board. the evaluation board is designed to be flexible allowing the user to configure it for different potential applications. the power supply distribution block provides filtered, adjustable voltages to the various supply pins of the AD9870. in the if input signal path, component pads are available to implement different if impedance matching networks. the lo and clk signals can be externally applied or internally derived from a user-supplied vco module interface daughter board. the refer- ence for the on-chip lo and clk synthesizers can be applied via the external fref input or an on-board crystal oscillator. mixer output if input lo input AD9870 or ad9874 vco module interface crystal oscillator idt fifo (optional) AD9870/ad9874 power supply distribution eprom clk input fref input nidaq 68-pin connector xilinx sparton fpga figure 14. evaluation board platform the evaluation board is designed to interface to a pc via a national instruments pci-dio-32hs digital io card. a xilinx fpga formats the data between the ad987x and digital i/o board. software developed using national instruments labview? and provided as ms windows? executable programs is supplied for the configuration of the spi port registers and evaluation of the AD9870 output data. these programs have a convenient graphical user interface allowing for easy access to the various spi port configuration registers and real time frequency analysis of output data.
rev. 0 AD9870 C18C outline dimensions dimensions shown in inches and (mm). 48-lead lqfp (st-48) top view (pins down) 1 12 13 25 24 36 37 48 0.019 (0.5) bsc 0.276 (7.00) bsc sq 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) bsc sq 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) 0.008 (0.2) 0.004 (0.09) 0 min coplanarity 0.003 (0.08) seating plane 0.006 (0.15) 0.002 ( 0.05 ) 7 0 0.057 (1.45) 0.053 (1.35)
C19C
C20C c01626C4.5C4/01(0) printed in u.s.a.

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