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rev. 0 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 AD9874 * if digitizing subsystem * protected by u.s. patent no. 5,969,657; other patents pending. features 10 mhz?00 mhz input frequency 6.8 khz?70 khz output signal bandwidth 8.1 db ssb nf 0 dbm iip3 agc free range up to ?4 dbm 12 db continuous agc range 16 db front end attenuator baseband i/q 16-bit (or 24-bit) serial digital output lo and sampling clock synthesizers programmable decimation factor, output format, agc, and synthesizer settings 370 input impedance 2.7 v?.6 v supply voltage low current consumption: 20 ma 48?ead lqfp package (1.4 mm thick) applications multimode narrowband radio products analog/digital uhf/vhf fdma receivers tetra, apco25, gsm/edge portable and mobile radio products base station applications general description the AD9874 is a general-purpose if subsystem that digitizes a low level 10 mhz?00 mhz if input with a signal bandwidth ranging from 6.8 khz to 270 khz. the signal chain of the AD9874 consists of a low noise amplifier, a mixer, a band-pass sigma-delta analog-to-digital converter, and a decimation filter with program- mable decimation factor. an automatic gain control (agc) circuit gives the AD9874 12 db of continuous gain adjustment. auxiliary blocks include both clock and lo synthesizers. the AD9874? high dynamic range and inherent antialiasing provided by the band-pass sigma-delta converter allow the AD9874 to cope with blocking signals up to 95 db stronger than the desired signal. this attribute can often reduce the cost of a radio by reducing its if filtering requirements. also, it enables multimode radios of varying channel bandwidths, allowing the if filter to be specified for the largest channel bandwidth. the spi port programs numerous parameters of the AD9874, thus allowing the device to be optimized for any given application. programmable parameters include the following: synthesizer divide ratios; agc attenuation and attack/decay time; the received signal strength level; decimation factor; the output data format; 16 db attenuator; and the selected bias currents. the bias currents of the lna and mixer can be further reduced at the expense of the degraded performance for battery- powered applications. functional block diagram - adc lna dac agc vo ltag e reference spi control logic formatting/ssi decimation filter lo sync sample clock synthesizer lo vco and loop filter ifin fref douta doutb fs clkout syncb pe pd pc vrefn vcm vrefp mxop mxon if2p if2n gcp gcn ?6db AD9874 clkn clkp ioutc lon lop ioutl lo vco and loop filter
rev. 0 e2e parameter temp test level min typ max unit system dynamic performance 2 ssb noise figure @ min vga attenuation 3, 4 full iv 8.1 9.5 db @ max vga attenuation 3, 4 full iv 13 db dynamic range with agc enabled 3, 4 full iv 91 95 db if input clip point @ max vga attenuation 3 full iv e20 e19 dbm @ min vga attenuation 3 full iv e32 e31 dbm input third order intercept (iip3) full iv e5 0 dbm gain variation over temperature full iv 0.7 2 db lna + mixer maximum rf and lo frequency range full iv 300 500 mhz lna input impedance 25 o cv 370//1.4 ? ? () ( ) () ( ) ( ) () ( ) + ( ) = = ( ) ( ) + ( = = = = = = = = = = = = = )
rev. 0 ? AD9874 digital specifications (vddi = vddf = vdda = vddc = vddl = vddd = vddh = 2.7 to 3.6 v, vddq = vddp = 2.7 v to 5.5 v, f clk = 18 msps, f if = 109.65 mhz, f lo = 107.4 mhz, f ref = 16.8 mhz, unless otherwise noted.) 1 parameter temp test level min typ max unit decimator decimation factor 2 full iv 48 960 pass-band width full v 50% f clkout pass-band gain variation full iv 1.2 db alias attenuation full iv 88 db spi-read operation (see figure 1a) pc clock frequency full iv 10 mhz pc clock period (t clk ) full iv 100 ns pc clock hi (t hi ) full iv 45 ns pc clock low (t low ) full iv 45 ns pc to pd setup time (t ds ) full iv 2 ns pc to pd hold time (t dh ) full iv 2 ns pe to pc setup time (t s ) full iv 5 ns pc to pe hold time (t h ) full iv 5 ns spi-write operation 3 (s ee figure 1b) pc clock frequency full iv 10 mhz pc clock period (t clk ) full iv 100 ns pc clock hi (t hi ) full iv 45 ns pc clock low (t low ) full iv 45 ns pc to pd setup time (t ds ) full iv 2 ns pc to pd hold time (t dh ) full iv 2 ns pc to pd (or doubt) data valid time (t dv ) full iv 3 ns pe to pd output valid to hi-z (t ez ) full iv 8 ns ssi 3 (see figure 2b) clkout frequency full iv 0.867 26 mhz clkout period (t clk ) full iv 38.4 1153 ns clkout duty cycle (t hi, t low ) full iv 33 50 67 ns clkout to fs valid time (t v ) full iv ? 1 ns clkout to dout data valid time (t dv ) full iv ? 1 ns cmos logic inputs 4 logic ??voltage (v ih ) full iv vddh?.2 v logic ??voltage (v il ) full iv 0.5 v logic ??current (v ih ) full iv 10 m a logic ??current (v il ) full iv 10 m a input capacitance full iv 3 pf cmos logic outputs 3,4,5 logic ??voltage (v ih ) full iv vddh?.2 v logic ??voltage (v il ) full iv 0.2 v notes 1 standard operating mode: high iip3 setting, synthesizers in normal (not fast acquire) mode, f clk = 18 mhz, decimation factor = 300, 10 pf load on ssi output pins: vddx = 3.0 v. 2 programmable in steps of 48 or 60. 3 cmos output mode with c load = 10 pf and drive strength = 7. 4 absolute max and min input/output levels are vddh +0.3 v and ?.3 v. 5 i ol = 1 ma; specification is also dependent on drive strength setting. specifications subject to change without notice.
rev. 0 e4e AD9874 absolute maximum ratings * parameter with respect to min max unit vddf, vdda, vddc, vddd, vddh, gndf, gnda, gndc, gndd, gndh, e0.3 +4.0 v vddl, vddi gndl, gndi, gnds vddf, vdda, vddc, vddd, vddh, vddr, vdda, vddc, vddd, vddh, e4.0 +4.0 v vddl, vddi vddl, vddi vddp, vddq gndp, gndq e0.3 +6.0 v gndf, gnda, gndc, gndd, gndh, gndf, gnda, gndc, gndd, gndh, e0.3 +0.3 v gndl, gndi, gndq, gndp, gnds gndl, gndi, gndq, gndp, gnds mxop, mxon, lop, lon, ifin, gndi e0.3 vddi + 0.3 v cxif, cxvl, cxvm pc, pd, pe, clkout, douta, gndh e0.3 vddh + 0.3 v doutb, fs, syncb if2n, if2p, gcp, gcn gndf e0.3 vddf + 0.3 v vrefp, vrefn, rref gnda e0.3 vdda + 0.3 v ioutc gndq e0.3 vddq + 0.3 v ioutl gndp e0.3 vddp + 0.3 v clkp, clkn gndc e0.3 vddc + 0.3 v fref gndl e0.3 vddl + 0.3 v junction temperature 150 + ( ) ( ) = = + ()
rev. 0 AD9874 e5e pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 pin 1 identifier top view (not to scale) gndl fref gnds syncb gndh fs doutb mxop mxon gndf if2n if2p vddf gcp gcn vdda gnda vrefp douta clkout vddh vddd AD9874 vrefn pe vddi ifin cxif gndi cxvl lop lon cxvm vddl vddp ioutl gndp rref vddq ioutc gndq vddc gndc clkp clkn gnds gndd pc pd 40 41 42 13 19 18 17 16 15 14 20 21 22 23 24 pin function descriptions pin mnemonic description 1 mxop mixer output, positive 2m xon mixer output, negative 3 gndf ground for front end of adc 4i f2n second if input (to adc), negative 5 if2p second if input (to adc), positive 6 vddf positive power supply for front end of adc 7 gcp filter capacitor for adc full-scale control 8 gcn full-scale control ground 9 vdda positive power supply for adc back end 10 gnda ground for adc back end 11 vrefp voltage reference, positive 12 vrefn voltage reference, negative 13 rref reference resistor: requires 100 k ? () ( )
rev. 0 e6e AD9874 definition of specifications/test methods single-sideband noise figure (ssb nf) noise figure (nf) is defined as the degradation in snr perfor- mance (in db) of an if input signal after it passes through a component or system. it can be expressed with the following equation: noise figure log snr snr in out = ( ) ( ) ssb noise figure is determined by the following equation: ssb nf p log bw dbm hz snr in = ( ) p in is the input power of an unmodulated carrier, bw is the noise measurement bandwidth, ?74 d bm/hz is the thermal noise floor at 293 snr is the measured signal-to-noise ratio in db of the AD9874. note, p in is set to ?5 dbm to minimize any degradation in measured snr due to phase noise from the rf and lo signal generators. the if frequency, clk frequency, and decimation factors are selected to minimize any ?purious?components falling within the measurement bandwidth. note, a bandwidth of 10 khz is used for the data sheet specification on page 2. refer to figures 22a and 22b for an indication of how nf varies with bw. also, refer to the tpcs to see how nf is affected by different operating conditions. all references to noise figures within this data sheet imply single-sideband noise figure. input third order intercept (iip3) iip3 is a figure of merit to determine a component? or system? susceptibility to intermodulation distortion (imd) from its third order nonlinearities. two unmodulated carriers?at a specified frequency relationship ( f 1 and f 2 ) are injected into a nonlinear system exhibiting third order nonlinearities producing imd components at 2 f 1 ? f 2 and 2 f 2 ?f 1 . iip3 graphically represents the extrapolated intersection of the carrier? input power with the third order imd component when plotted in db. the dif- ference in power ( d in dbc) between the two carriers and the resulting third order imd components can be determined from the following equation: d iip p in = () () ( ) ( ) ( ) ( ) ( p target ) is adjusted to achieve an snr target of 6 db. the power of the signal is then increased by 3 db prior to injecting the interferer signal. the offset frequency of the interferer signal is selected so that aliases produced by the decimation filter? response as well as phase noise from the lo (due to reciprocal mixing) do not fall back within the measure- ment bandwidth. for this reason, an offset of 110 khz was selected. the interferer signal (also an unmodulated carrier) is then injected into the input and its power level is increased to the point ( p inter ) where the target signal snr is reduced to 6 db. the dynamic range is determined from the following equation: dr p p snr inter target target =+ below the input power level (p in ), resulting in the ?lipping?of the AD9874? adc. unlike other linear components that typically exhibit a ?oft?compression (characterized by its 1 db compression point), an adc exhibits a ?ard?compression once its input signal exceeds its rated maximum input signal range. in the case of the AD9874, which contains a
rev. 0 AD9874 e7e (vddi = vddf = vdda = vddc = vddl = vddd = vddh = vddx, vddq = vddp = 5.0 v, f clk = 18 msps, f if = 109.56 mhz, f lo = 107.4 mhz, t a = 25 c, lo = e5 dbm, lo and clk synthesizer disabled, 16-bit data with agc and dvga enabled, unless otherwise noted.) 1 noise figure e db percentage e % 100 7.2 7.5 7.8 8.1 8.4 8.7 9.0 80 60 40 20 0 e40 c +25 c +85 c tpc 1a. cdf of ssb noise figure (vddx = 3.0 v, high bias 2 ) iip3 e dbm percentage e % 100 e3 80 60 40 20 0 e2 e1 0 1 2 e40 c +25 c +85 c tpc 2a. cdf of iip3 (vddx = 3.0 v, high bias 2 ) dy namic range e db percentage e % 100 92 80 60 40 20 0 e40 c +85 c +25 c 93 94 95 96 97 98 tpc 3a. cdf of dynamic range (vddx = 3.0 v, high bias 2 ) t ypical performance characteristicse vddx e v nf e db 9.5 2.7 3.0 3.3 3.6 6.0 9.0 8.5 8.0 7.5 7.0 6.5 +85 c +25 c e40 c tpc 1b. ssb noise figure vs. supply (high bias 2 ) vddx e v iip3 e dbm 1.5 2.7 3.0 3.3 3.6 e3.5 +85 c +25 c e40 c 1.0 0.5 0 e0.5 e1.0 e1.5 e2.0 e2.5 e3.0 tpc 2b. iip3 vs. supply (high bias 2 ) vddx e v dr e db 98 2.7 3.0 3.3 3.6 92 97 96 95 94 93 e40 c +85 c +25 c tpc 3b. dynamic range vs. supply (high bias 2 ) vddx e v nf e db 9.5 2.7 3.0 3.3 3.6 6.0 9.0 8.5 8.0 7.5 7.0 6.5 +85 c +25 c e40 c tpc 1c. ssb noise figure vs. supply (low bias 3 ) vddx e v iip3 e dbm 0 2.7 3.0 3.3 3.6 e12 +85 c +25 c e40 c e10 e8 e6 e4 e2 tpc 2c. iiip3 vs. supply (low bias 3 ) vddx e v dr e db 98 2.7 3.0 3.3 3.6 92 97 96 95 94 93 e40 c +85 c +25 c tpc 3c. dynamic range vs. supply (low bias 3 ) 1 data taken with toko fslm series 10
rev. 0 e8e AD9874 (vddi = vddf = vdda = vddc = vddl = vddd = vddh = vddx, vddq = vddp = 5.0 v, f clk = 18 msps, f if = 109.56 mhz, f lo = 107.4 mhz, t a = 25 c, lo = e5 dbm, lo and clk synthesizer disabled, 16-bit data with agc and dvga enabled, unless otherwise noted.) 1 ifin clip point e dbm percentage e % 100 80 60 40 20 0 e19.4 e19.2 e19.0 e18.8 e18.6 e18.4 +25 c +85 c e40 c tpc 4a. cdf of maximum vga attenuation clip point (vddx = 3.0 v, high bias 2 ) ifin clip point e dbm percentage e % 100 80 60 40 20 0 e31.6 +25 c +85 c e40 c e31.4 e31.2 e31.0 e30.8 e30.6 e30.4 tpc 5a. cdf of minimum vga attenuation clip point (vddx = 3.0 v, high bias 2 ) supply current e ma percentage e % 100 80 60 40 20 0 18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0 +85 c +25 c e40 c tpc 6a. cdf of supply current (vddx = 3.0 v, high bias 2 ) vddx e v input clip point e dbm 2.7 3.0 3.3 3.6 e20.5 e20.0 e19.5 e19.0 e18.5 e18.0 e17.5 e40 c +25 c +85 c tpc 4b. maximum vga attenuation clip point vs. supply (high bias 2 ) vddx e v input clip point e dbm e29.5 2.7 3.0 3.3 3.6 +85 c +25 c e30.0 e30.5 e31.0 e31.5 e32.0 e40 c tpc 5b. minimium vga attenuation clip point vs. supply (high bias 2 ) f clk e mhz supply current e ma 16 13 14 10 6 2 0 12 8 4 15 17 19 21 23 25 digital ( iddd, iddc, and iddl) digital interface ( iddh) analog ( idda, iddf, and iddi) tpc 6b. supply current vs. f clk (vddx = 3.0 v, high bias 2 ) vddx e v input clip point e dbm e17.5 2.7 3.0 3.3 3.6 e40 c +85 c +25 c e18.0 e18.5 e19.0 e19.5 e20.0 e20.5 tpc 4c. maximum vga attenuation clip point vs. supply (low bias 3 ) vddx e v input clip point e dbm e29.5 2.7 3.0 3.3 3.6 +85 c +25 c e30.0 e30.5 e31.0 e31.5 e32.0 e40 c tpc 5c. minimium vga attenuation clip point vs. supply (low bias 3 ) vddx e v supply current e ma 18 2.7 3.0 3.3 3.6 16 12 8 4 0 digital interface ( iddh) digital ( iddd, iddc, and iddl) analog ( idda, iddf, and iddi) 14 10 6 2 tpc 6c. supply current vs. supply (high bias 2 ) 1 data taken with toko fslm series 10
rev. 0 AD9874 e9e (vddi = vddf = vdda = vddc = vddl = vddd = vddh = vddx, vddq = vddp = 5.0 v, f clk = 18 msps, f if = 109.56 mhz, f lo = 107.4 mhz, t a = 25 c, lo = e5 dbm, lo and clk synthesizer disabled, 16-bit data with agc and dvga enabled, unless otherwise noted.) 1 lo drive e dbm gain variation e db 0.1 e20 e14 e8 e5 0 e0.2 e0.4 e0.6 e0.8 e0.1 e0.3 e0.5 e0.7 e11 e17 low bias high bias tpc 7a. normalized gain variation vs. lo drive (vddx = 3.0 v) frequency e khz fs 0 e140 e20 e40 e60 e80 e100 e120 e80 e60 e40 e20 0 20 40 60 80 e2.8 dbfs output nbw = 3.66khz f clk = 18mhz max vga atten decebye120 tpc 8a. complex fft of baseband i/q for single-tone (high bias) frequency e khz dbfs 0 e140 e20 e40 e60 e80 e100 e120 e80 e60 e40 e20 0 20 40 60 80 nbw = 3.66khz f clk = 18mhz max vga atten decebye120 imd = 74dbc e18.2dbfs output tpc 9a. complex fft of baseband i/q for dual tone imd (high bias with each ifin tone @ e35 dbm) lo drive e dbm noise figure e dbc 9.0 e20 e10 0 5 8.6 8.2 7.8 7.4 7.0 8.4 8.0 7.6 7.2 e5 e15 nf-high bias imd-high bias nf-low bias imd-low bias 8.8 imd w/ ifin = e36 dbm e dbc 0 e20 e40 e60 e80 e30 e50 e70 e10 tpc 7b. noise figure and imd vs. lo drive (vddx = 3.0 v) ifin e dbm dbfs 0 e30 e14 adc goes into hard compression e28 e26 e24 e22 e20 e18 e16 e2 e4 e6 e8 e10 e12 2.7v 3.0v 3.3v 3.6v tpc 8b. gain compression vs. ifin (high bias 2 ) ifin e dbm imd e dbc e70 e124 e76 e82 e88 e100 e106 e118 e51 e48 e45 e42 e39 e36 e33 e30 pin 2.7v 3.6v 3.0v 3.3v e130 e112 e94 pin e dbfs e15 e42 e18 e21 e24 e30 e33 e39 e45 e36 e27 tpc 9b. imd vs. ifin (high bias 2 ) ifin e dbm dbm e12 e36 e18 e24 e30 e36 e15 e21 e27 e33 e33 e30 e27 e24 e21 e18 e15 e12 e9 e6 e3 0 high bias low bias tpc 7c. gain compression vs. ifin with 16 db lna attenuator enabled ifin e dbm dbfs 0 e30 e14 adc does not go into hard compression e28 e26 e24 e22 e20 e18 e14 e2 e4 e6 e8 e10 e12 2.7v 3.0v 3.3v 3.6v e16 tpc 8c. gain compression vs. ifin (low bias 3 ) ifin e dbm imd e dbc e55 e109 e61 e67 e73 e85 e91 e103 e51 e48 e45 e42 e39 e36 e33 e30 pin 2.7v 3.6v 3.0v 3.3v e115 e97 e79 pin e dbfs e15 e42 e18 e21 e24 e30 e33 e39 e45 e36 e27 tpc 9c. imd vs. ifin (low bias 3 ) 1 data taken with toko fslm series 10
rev. 0 e10e AD9874 (vddi = vddf = vdda = vddc = vddl = vddd = vddh = vddx, vddq = vddp = 5.0 v, f clk = 18 msps, f if = 109.56 mhz, f l o = 107.4 mhz, t a = 25 c, lo = e5 dbm, lo and clk synthesizer disabled, 16-bit data with agc and dvga enabled, unless otherwise noted.) 1 channel bandwidth e khz noise figure e db 10.0 10 7.5 1000 100 9.5 9.0 8.5 8.0 24-bit i/q data 16-bit i/q data 16-bit i/q data w/ dvga enabled tpc 10a. noise figure vs. bw (mini- mum attenuation, f clk = 13 msps) vg a attenuation e db noise figure e db 11.5 0 7.0 12 6 9 3 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 bw = 6.78khz (k = 0, m = 15) bw = 12.04khz (k = 0, m = 8) bw = 27.08khz (k = 0, m = 3) tpc 11a. noise figure vs. vga attenuation (f clk = 13 msps) ifin e dbm imd e dbc e45 e130 e30 e40 e50 e60 e70 e80 e90 e100 e110 e120 e42 e39 e36 e33 e30 e27 e24 low bias pin high bias pout e dbfs e5 e30 e10 e15 e20 e25 e40 e35 e45 tpc 12a. imd vs. ifin (f clk = 13 msps) channel bandwidth e khz noise figure e db 10.0 10 7.5 1000 100 9.5 9.0 8.5 8.0 24-bit data 16-bit data 16-bit data w/ dvga enabled tpc 10b. noise figure vs. bw (mini- mum attenuation, f clk = 18 msps) vg a attenuation e db noise figure e db 14 0 7 12 6 9 3 13 12 11 10 9 8 bw = 15khz (k = 0, m = 9) bw = 50khz (k = 0, m = 2) bw = 75khz (k = 0, m = 1) tpc 11b. noise figure vs. vga attenuation (f clk = 18 msps) ifin e dbm imd e dbc e45 e130 e30 e40 e50 e60 e70 e80 e90 e100 e110 e120 e42 e39 e36 e33 e30 e27 e24 low bias pin high bias pin e dbfs e5 e30 e10 e15 e20 e25 e40 e35 e45 tpc 12b. imd vs. ifin (f clk = 18 msps) channel bandwidth e khz noise figure e db 10.0 10 7.5 1000 100 9.5 9.0 8.5 8.0 24-bit data 16-bit data 16-bit data w/ dvga enabled tpc 10c. noise figure vs. bw (mini- mum attenuation, f clk = 26 msps) vg a attenuation e db noise figure e db 14 0 7 12 6 9 3 13 12 11 10 9 8 bw = 27.08khz (k = 1, m = 9) bw = 90.28khz (k = 1, m = 2) bw = 135.42khz (k = 1, m = 1) tpc 11c. noise figure vs. vga attenuation (f clk = 26 msps) ifin e dbm imd e dbc e45 e130 e30 e40 e50 e60 e70 e80 e90 e100 e110 e120 e42 e39 e36 e33 e30 e27 e24 low bias pin high bias pin e dbfs e5 e30 e10 e15 e20 e25 e40 e35 e45 tpc 12c. imd vs. ifin (f clk = 26 msps) 1 data taken with toko fslm series 10
rev. 0 AD9874 e11e (vddi = vddf = vdda = vddc = vddl = vddd = vddh = vddx, vddq = vddp = 5.0 v, f clk = 18 msps, f if = 109.56 mhz, f lo = 107.4 mhz, t a = 25 c, lo = e5 dbm, lo and clk synthesizer disabled, 16-bit data with agc and dvga enabled, unless otherwise noted.) 1 frequency e mhz noise figure e db 13 0 6 12 11 10 9 8 7 50 500 100 150 200 250 300 350 400 450 24-bit 16-bit w/dvga tpc 13a. noise figure vs. frequency (minimum attenuation, f clk = 18 msps, bw = 10 khz, high bias) frequency e mhz noise figure e db 13 0 6 12 11 10 9 8 7 50 500 100 150 200 250 300 350 400 450 24-bit 16-bit w/dvga tpc 14a. noise figure vs. frequency (minimum attenuation, f clk = 26 msps, bw = 24 khz, high bias) interferer level e dbm noise figure e dbc 20.0 e55 8.0 18.5 15.5 12.5 11.0 9.5 e5 e10 noise figure agc 17.0 14.0 e15 e20 e25 e30 e35 e40 e45 e50 mean agc attn value 128 0 112 80 48 32 16 96 64 tpc 15a. noise figure vs. interferer level (16-bit data, bw = 12.5 khz, agcr = 1, f interferer = f if + 110 khz) frequency e mhz noise figure e db 13 0 6 12 11 10 9 8 7 50 500 100 150 200 250 300 350 400 450 24-bit 16-bit w/dvga tpc 13b. noise figure vs. frequency (m inimum attenuation, f clk = 18 msps, bw = 10 khz, low bias) frequency e mhz noise figure e db 13 0 6 12 11 10 9 8 7 50 500 100 150 200 250 300 350 400 450 24-bit 16-bit w/dvga tpc 14b. noise figure vs. frequency (m inimum attenuation, f clk = 26 msps, bw = 24 khz, low bias) interferer level e dbm noise figure e dbc 16 e50 8 15 13 11 10 9 e10 e15 noise figure agc a ttn 14 12 e20 e25 e30 e35 e40 e45 mean agc attn value 256 0 224 160 96 64 32 192 128 tpc 15b. noise figure vs. interferer level (16-bit data with dvga, bw = 12.5 khz, agcr = 1, f interferer = f if + 110 khz) frequency e mhz iip3 e dbm 4 0 e10 2 0 e2 e4 e6 e8 50 500 100 150 200 250 300 350 400 450 low bias high bias tpc 13c. input ip3 vs. frequency (f clk = 18 msps) frequency e mhz iip3 e dbm 2 0 e10 0 e2 e4 e6 e8 50 500 100 150 200 250 300 350 400 450 low bias high bias tpc 14c. input ip3 vs. frequency (f clk = 26 msps) interferer level e dbm noise figure e dbc 16 e65 8 15 13 11 10 9 e5 e15 noise figure agc a ttn 14 12 e25 e35 e45 e55 mean agc attn value 128 0 32 96 64 tpc 15c. noise figure vs. interferer level (24-bit data, bw = 12.5 khz, agcr = 1, f interferer = f if + 110 khz) 1 data taken with toko fslm series 10
rev. 0 e12e AD9874 serial peripheral interface (spi) the serial peripheral interface (spi) is a bidirectional serial port. it is used to load configuration information into the reg isters listed below as well as to read back their contents. table i provides a list of the registers that may be programmed through the spi po rt. addresses and default values are given in hexadecimal form. table i. spi address map address bit (hex) breakdown width default value name description power control registers 0x00 (7:0) 8 0xff stby standby control bits (ref, lo, cko, ck, gc, lnamx, unused, and adc) 0x01 (7:6) 2 0 lnab lna bias current (0 = 0.5 ma, 1 = 1 ma, 2 = 2 ma, 3 = 3 ma) (5:4) 2 0 mixb mixer bias current (0 = 0.5 ma, 1 = 1.5 ma, 2 = 2.7 ma, 3 = 4 ma) (3:2) 2 0 ckob ck osc illator bias (0 = 0.25 ma, 1 = 0.35 ma, 2 = 0.40 ma, 3 = 0.65 ma) (1:0) 2 0 adcb do not use 0x02 (7:0) 8 0x00 test factory test mode. do not use. agc 0x03 (7) 1 0 atten apply 16 db attenuation in the front end (6:0) 7 0x00 agcg(14:8) agc attenuation setting (7 msbs of a 15-bit unsigned word) 0x04 (7:0) 8 0x00 agcg(7:0) agc attenuation setting (8 lsbs of a 15-bit unsigned word) default corresponds to maximum gain 0x05 (7:4) 4 0 agca agc attack bandwidth setting. default yields 50 hz raw loop bandwidth. (3:0) 4 0 agcd agc decay time setting. default is decay time = attack time. 0x06 (7) 1 0 agcv enable digital vga to increase agc range by 12 db (6:4) 3 0 agco agc overload update setting. default is slowest update (3) 1 0 agcf fast agc (minimizes resistance seen between gcp and gcn) (2:0) 3 0 agcr agc enable/reference level (disabled, 3 db, 6 db, 9 db, 12 db, 15 db below clip) decimation factor 0x07 (7:5) 3 unused (4) 1 0 k decimation factor = 60 ( + ) = ( + ) = () () () ( ) () () ( ) () = () ( ) () () ( ) () () ( ) () () ( = ) () = ( + ) () ( = = = = ) () () ( ) () () ( )
rev. 0 AD9874 e13e address bit (hex) breakdown width default value name description clock synthesizer 0x10 (5:0) 6 00 ckr(13:8) reference frequency divisor (6 msbs of a 14-bit word) 0x11 (7:0) 8 0x38 ckr(7:0) reference frequency divisor (8 lsbs of a 14-bit word) default yields 300 khz from f ref =16.8 mhz; min = 3, max = 16383. 0x12 (4:0) 5 0x00 ckn(12:8) synthesized frequency divisor (5 msbs of a 13-bit word) 0x13 (7:0) 8 0x3c ckn(7:0) synthesized frequency divisor (8 lsbs of a 13-bit word) default yields 300 khz from f clk = 18 mhz; min = 3, max = 8191 0x14 (6) 1 0 ckf enable fast acquire (5) 1 0 ckinv invert charge pump (0 = source current to increase vco frequency) (4:2) 3 0 cki charge pump current in normal operation. i pump = (cki + 1) () ( = = = = ) () () ( ) () () ( ) () ( ) () ( ) () = () ( ) () ( ) () () ( ) () () ( ) () ( ) () ( ) () ( ) () () () () ()
rev. 0 e14e AD9874 serial port interface (spi) the serial port of the AD9874 has 3-wire or 4-wire spi capa- bility, allowing read/write access to all registers that configure the device?s internal parameters. the default 3-wire serial commu- nication port consists of a clock (pc), peripheral enable (pe), and a bidirectional data (pd) signal. the inputs to pc, pe, and pd contain a schmitt trigger with a nominal hysteresis of 0.4 v centered about the digital interface supply (i.e., vddh/2). a 4-wire spi interface can be enabled by setting the msb of the ssicrb register ( reg. 0x19, bit 7) resulting in the output data also appearing on the doutb pin. note, since the default power-up state sets doutb low, bus contention is possible for systems sharing the spi output line. to avoid any bus contention, the doutb pin can be three-stated by setting the fourth control bit in the three-state bit (reg 0x3b, bit 3). this bit can then be toggled to gain access to the shared spi output line. an 8-bit instruction header must accompany each read and write spi operation. only the write operation supports an auto-increment mode allowing the entire chip to be configured in a single write operation. the instruction header is shown in table i. it includes a read/not-write indicator bit, 6 address bits, and a don?t care bit. the data bits immediately follow the instruction header for both read and write operations. note, address and data are always given msb first. table ii. instruction header information msb lsb i7 i6 i5 i4 i3 i2 i1 i0 r/w a5 a4 a3 a2 a1 a0 x figure 1a illustrates the timing requirements for a write opera tion to the spi port. after the peripheral enable (pe) signal goes low, data (pd) pertaining to the instruction header is read on the rising edges of the clock (pc). to initiate a write opera tion, the read/not-write bit is set low. after the instruction header is read, the eight data bits pertaining to the specified register are shifted into the data pin (pd) on the rising edge of the next eight clock cycles. pe stays low during the operation and goes high at the end of the transfer. if pe rises before the eight clock cycles have passed, the operation is aborted. if pe stays low for an additional eight clock cycles, the destination address is incremented and another eight bits of data are shifted in. again, should pe rise early, the current byte is ignored. by using this implicit addressing mode, the entire chip can be configured with a single write operation. registers identified as being subject to frequent updates, namely those associated with power control and agc operation, have been assigned adjacent addresses to minimize the time required to update them. note, multibyte registers are ?ig-endian?(the most significant byte has the lower address) and are updated when a write to the least significant byte occurs. figure 1b illustrates the timing for a read operation to the spi port. although the AD9874 does not require read access for proper operation, it is often useful in the product development phase or for system authentication. note, the readback enable bit (register 0x3a, bit 3) must be set for a read operation with a 3-wire spi interface. after the peripheral enable (pe) signal goes low, data (pd) pertaining to the instruction header is read on the rising edges of the clock (pc). a read operation occurs if the read/not- write indicator is set high. after the address bits of the instruction header are read, the eight data bits pertaining to the specified register are shifted out of the data pin (pd) on the falling edges of the next eight clock cycles. if the 4-wire spi interface is enabled, the eight data bits will also appear on the doutb pin with the same tim ing relationship as those appearing at pd. after the last data bit is shifted out, the user should return pe high, causing pd to become three-stated and return to its normal status as an input pin. since the auto-increment mode is not supported for read operations, an instruction header is required for each register read operation and pe must return high before initiating the next read operation. pc pe pd a5 a4 d7 d6 d0 a0 don? care d1 r/w t ds t dh t clk t hi t low t s t h figure 1b. spi read operation timing pc pe pd a5 a4 d7 d6 d0 a0 don? care d1 r/w t ds t dh t clk t hi t low t s t h figure 1a. spi write operation timing
rev. 0 AD9874 e15e synchronous serial interface (ssi) the AD9874 provides a high degree of programmability of its ssi output data format, control signals, and timing parameters to accommodate various digital interfaces. in a 3-wire digital interface, the AD9874 provides a frame sync signal (fs), a clock output (clkout), and a serial data stream (douta) signal to the host device. in a 2-wire interface, the frame sync information is embedded into the data stream, thus only a clkout and douta output signal are provided to the host device. the ssi control registers are ssicra, ssicrb, and ssiord. table iii shows the different bit fields associated with these registers. the primary output of the AD9874 is the converted i and q demodulated signal available from the ssi port as a serial bit stream contained within a frame. the output frame rate is equal to the modulator clock frequency (f clk ) divided by the digital filter?s decimation factor that is programmed in the decimator register (0x07). the bit stream consists of an i word followed by a q word, where each word is either 24 bits or 16 bits long and is given msb first in two?s complement form. two optional bytes may also be included within the ssi frame following the qw ord. one byte contains the agc attenuation and the other byte contains both a count of modulator reset events and an estimate of the received signal amplitude (relative to full scale of the AD9874?s adc). figure 2 illustrates the structure of the ssi data frames in a number of ssi modes. 16-bit i and q, eagc = 0, aagc = x:32 data bits 16-bit i and q, eagc = 1, aagc = 0:48 data bits 16-bit i and q, eagc = 1, aagc = 1:40 data bits i (15:0) q (15:0) i (15:0) q (15:0) a ttn (7:0) i (15:0) q (15:0) 0 i (15:0) q (15:0) 1 reset count i (24:0) q (24:0) 24-bit i and q, eagc = 0, aagc = x: 48 data bits a ttn (7:1) ssi(5:1) ssi(5:0) i (24:0) q (24:0) ssi(5:0) reset count a ttn (7:0) 24-bit i and q, eagc = 1, aagc = 0:64 data bits figure 2. ssi frame structure the two optional bytes are output if the eagc bit of ssicra is set. the first byte contains the 8-bit attenuation setting (0 = no attenuation, 255 = 24 db of attenuation), while the second byte contains a 2-bit reset field and 6-bit received signal strength signal field. the reset field contains the number of modulator reset events since the last report, saturating at 3. the received signal strength (rssi) field is a linear estimate of the signal strength at the output of the first decimation stage; 60 corre sponds to a full-scale signal. the two optional bytes follow the i and q data as a 16-bit word providing that the aagc bit of ssicra is not set. if the aagc bit is set, the two bytes follow the i and q data in an alternating fashion. in this alternate agc data mode, the lsb of the byte containing the agc attenuation is a 0, while the lsb of the byte containing reset and rssi information is always a 1. in a 2-wire interface, the embedded frame sync bit (efs) within the ssicra register is set to 1. in this mode, the framing infor- mation is embedded in the data stream with each eight bits of data surrounded by a start bit (low) and a stop bit (high), and each frame ends with at least 10 high bits. fs remains either low or three-stated (default) depending on the state of the sfst bit. other control bits can be used to invert the frame sync (sfsi), to delay the frame sync pulse by one clock period (slf s), to invert the clock (scki), or to three-state the clock (sckt). note that if efs is set, slfs is a don?t care. name width default description ssicra (addr = 0x18) aagc eagc efs sfst sfsi slfs sckt scki 1 al ternate agc data bytes embed agc data embed frame sync th ree-state frame sync invert frame sync la te frame sync (1 = late, 0 = early) th ree-state clkout invert clkout 1 1 1 1 1 1 1 ssicrb (addr = 0x19) ds 3 fs , clkout, and dout drive strength 7 dw 1 output bit rate divisor f clkout = f clk / ssiord 0 1 1 0 0 0 0 0 0 aagc eagc efs sfst sfsi slfs sckt scki dw ds_2 ds_1 ds_0 div_3 ssiord (addr = 0x1a) i/q data-word width (0 = 16 bit, 1 bit?4 bit) automatically 16-bit when the agcv=1 4 1 div_2 div_1 div_0 div 4_spi 4_spi 0 enable 4-wire spi interface for spi read operation via doutb 1 the ssiord register controls the output bit rate (f clkout ) of the serial bit stream. f clkout can be set to equal the modulator clock frequency (f clk ) or an integer fraction of it. it is equal to f clk divided by the contents of the ssiord register. note, f clkout should be chosen such that it does not introduce harmful spurs within the pass band of the target signal. users must verify that the output bit rate is sufficient to accommodate the re quired number of bits per frame for a selected word size and decima tion factor. idle (high) bits are used to fill out each frame. table iii. ssi control registers
rev. 0 e16e AD9874 fs dout clkout scki = 0, sckt = 0, slfs = 0, sfsi = 0, efs = 0, sfst = 0, eagc = 0 i15 i0 q15 q14 q0 clkout fs dout scki = 0, sckt = 0, slfs = 0, sfsi = 0, efs = 0, sfst = 0, eagc = 1, aagc = 0 i15 i0 q15 q14 q0 rssi0 a tten6 a ttn7 clkout fs dout scki = 0, sckt = 0, slfs = 1, sfsi = 0, efs = 0, sfst = 0, eagc = 0 i15 i0 q15 q14 q0 clkout fs dout scki = 0, sckt = 0, slfs = x, sfsi = x, efs = 1, sfst = 1, eagc = 0 scki = 0, sckt = 0, slfs = x, sfsi = x, efs = 1, sfst = 0, eagc = 0: as above, but fs is low idle (high) bits start bit start bit stop bit stop bit start bit hi-z i15 i8 i7 i0 q15 figure 3a. ssi timing for several ssicra settings with 16-bit i/q data table iv. number of bits per frame for different ssicr settings number of bits dw eagc efs aagc per frame 0 (16-bit) 0 0 na 32 01na49 * 100 48 101 40 110 69 * 111 59 * 1 (24-bit) 0 0 na 48 01na69 * 100 64 101 56 110 89 * 111 79 * * the number of bits per frame with embedded frame sync (efs = 1) assume at least 10 idle bits are desired. the maximum ssiord setting can be determined by the fol lowing equation: ssiord trunc dec factor of bits per frame ( ) ( ) () trunc is the truncated integer value. table iv lists the number of bits within a frame for 16-bit and 24-bit output data formats for all of the different ssicr settings. the decimation factor is determined by the contents of reg ister 0x07. an example helps illustrate how the maximum ssiord setting is determined. suppose a user selects a decimation factor of 600 (register 0x07, k = 0, m = 9) and prefers a 3-wire interface with a dedicated frame sync (efs = 0) containing 24-bit data (dw = 1) with nonalternating embedded agc data included (eagc = 1, aagc = 0). referring to table iv, each frame will consist of 64 data bits. using equation 1, the maximum ssiord setting is 9 (= trunc (600/64)). thus, the user can select any ssiord setting between 1 and 9. figure 3a illustrates the output timing of the ssi port for several ssi control register settings with 16-bit i/q data, while figure 3b shows the associated timing parameters. note, the same timing relationship holds for 24-bit i/q data, with the exception that i and qw ord lengths now become 24 bits. in the default mode of the operation, data is shifted out on rising edges of clkout after a pulse equal to a clock period is output from the frame sync (fs) pin. as described above, the output data consists of a 16- or 24-bit i sample followed by a 16- or 24-bit q sample, plus two optional bytes containing agc and status information. fs dout i15 i14 clkout t v t clk t hi t low t dv figure 3b. timing parameters for ssi timing * * timing parameters also apply to inverted clkout or fs modes with t dv relative to the falling edge of the clk and/or fs.
rev. 0 AD9874 e17e the AD9874 also provides the means for controlling the switching characteristics of the digital output signals via the ds (drive strength) field of the ssicrb. this feature is useful in limiting switching transients and noise from the digital output that may ultimately couple back into the analog signal path, potentially degrading the AD9874?s sensitivity performance. figures 3c and 3d show how the nf can vary as a function of the ssi setting for an if frequency of 109.65 mhz. the following two observations can be made from these figures: the nf becomes more sensitive to the ssi output drive strength level at higher signal bandwidth settings. the nf is dependent on the number of bits within an ssi frame, becoming more sensitive to the ssi output drive strength level as the number of bits is increased. as a result, one should select the lowest possible ssi drive strength setting that still meets the ssi timing requirements. ssi output drive strength setting 2 10.0 4 noise figure e db 9.6 3 1 8.0 7 6 5 24-bit i/o data 9.8 9.4 9.2 9.0 8.6 8.8 8.4 8.2 16-bit i/o data w/dvga enabled 16-bit i/o data figure 3c. nf vs. ssi output drive strength (vddx = 3.0 v, f clk = 18 msps, bw = 10 khz) ssi output drive strength setting 2 14 4 noise figure e db 12 3 1 7 7 6 5 24-bit i/o data 13 11 9 10 8 16-bit i/o data w/dvga enabled 16-bit i/o data figure 3d. nf vs. ssi output drive strength (vddx = 3.0 v, f clk = 18 msps, bw = 75 khz) table v lists the typical output rise/fall times as a function of ds for a 10 pf load. rise/fall times for other capacitor loads can be determined by multiplying the typical values presented in table v by a scaling factor equal to the desired capacitive load divided by 10 pf. * blackfin is a registered trademark of analog devices, inc. table v. typical rise/fall times ( ) () ( ( ) ) ()
rev. 0 ?8 AD9874 AD9874 clkout rsclk pc sck pe sel pd mosi doutb miso fs rfs douta dr spi ssi adsp-2153x serial port spi-port figure 4b. example of AD9874 and adsp-2153x interface as shown in figure 4b, AD9874? synchronous serial interface (ssi) links the receive data stream to the dsp? serial port (sport). for AD9874 set-up and register programming, the device connects directly to adsp-2153x? spi-port. dedicated select lines (sel) allow the adsp-2153x to program and read back registers of multiple devices using only one spi port. the dsp driver code pertaining to this interface is available on the AD9874 web page (http://products.analog.com/products/info.asp?product=AD9874). power control to allow power consumption to be minimized, the AD9874 possesses numerous spi-programmable power-down and bias control bits. the AD9874 powers up with all of its functional blocks placed into a standby state (i.e., stby register default is 0xff). each major block may then be powered up by writing a 0 to the appropriate bit of the stby register. this scheme provides the greatest flexibility for configuring the ic to a specific appli- cation as well as for tailoring the ic? power-down and wake-up characteristics. table vi summarizes the function of each of the stby bits. note, when all the blocks are in standby, the master reference circuit is also put into standby and thus the current is reduced by a further 0.4 ma. table vi. standby control bits current stby reduction wake-up bit effect (ma) 1 time (ms) 7:ref voltage reference off; 0.6 <0.1 (c ref all biasing shut down. = 4.7 nf) 6:lo lo synthesizer off, 1.2 note 2 ioutl three-state. 5:cko clock oscillator off 1.1 note 2 4:ck clock synthesizer off, 1.3 note 2 ioutc three-state. clock buffer off if adc is off. 3:gc gain control dac off. 0.2 depends gcp and gcn three-state. on c gc 2:lnamx lna and mixer off. cxvm, 8.2 <2.2 cxvl, and cxif three-state. 1:unused 0:adc adc off; clock buffer off 9.2 <0.1 if clk synthesizer off; vcm three-state; clock to the digital filter halted; digital outputs static. notes 1 when all blocks are in standby, the master reference circuit is also put into standby and thus the current is reduced by a further 0.4 ma. 2 wake-up time is dependent on programming and/or external components. the AD9874 also allows control over the bias current in the lna, mixer, and clock oscillator. the effects on current consumption and system performance are described in the section dealing with the affected block. lo synthesizer the lo synthesizer shown in figure 5 is a fully programmable pll capable of 6.25 khz resolution at input frequencies up to 300 mhz and reference clocks of up to 25 mhz. it consists of a low noise digital phase-frequency detector (pfd), a variable output current charge pump (cp), a 14-bit reference divider, programmable a and b counters, and a dual-modulus 8/9 prescaler. the a (3-bit) and b (13-bit) counters, in conjunction with the dual 8/9 modulus prescaler, implement an n divider with n = 8 b + a. in addition, the 14-bit reference counter (r counter) allows selectable input reference frequencies, f ref , at the pfd input. a complete pll (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and vco (voltage controlled oscillator). the a, b, and r counters can be programmed via the following registers: loa, lob, and lor. the charge pump output cur rent is programmable via the loi register from 0.625 ma to 5.0 ma using the following equation: ipump loi ma =+ (). 10 625 (2) an on-chip fast acquire function (enabled by the lof bit) automatically increases the output current for faster settling during channel changes. the synthesizer may also be disabled using the lo standby bit located in the stby register. fa s t ac q uire 8/9 a, b counters lo bu ffer loa, lob f lo from vco ref bu ffer f ref lor r f ref phase/ frequency detector to external loop filter f lo charge pump figure 5. lo synthesizer the lo (and clk) synthesizer works in the following manner. the externally supplied reference frequency, f ref , is buffered and divided by the value held in the r counter. the internal f ref is then compared to a divided version of the vco frequency, f lo . the phase/frequency detector provides up and down pulses whose widths vary depending upon the difference in phase and frequency of its two input signals. the up/down pulses con- trol the charge pump making current available to charge the external low-pass loop filter when there is a discrepancy between the inputs of the pfd. the output of the low-pass filter feeds an external vco whose output frequency, f lo , is driven such that its divided down version, f lo , matches that of f ref , thus closing the feedback loop. the synthesized frequency is related to the reference frequency and the lo register contents as follows: f lob loa lor f lo ref = + ()/ 8 (3) note, the minimum allowable value in the lob register is 3 and its value must always be greater than that loaded into loa .
rev. 0 AD9874 ?9 an example may help illustrate how the values of loa , lob , and lor can be selected. consider an application employing a 13 mhz crystal oscillator (i.e., f ref = 13 mhz) with the requirement that f ref = 100 khz and f lo = 143 mhz (i.e., high side injection with f if = 140.75 mhz and f clk = 18 msps). lor is selected to be 130 such that f ref = 100 khz. the n-divider factor is 1430, which can be realized by selecting lob = 178 and loa = 6. the stability, phase noise, spur performance, and transient response of the AD9874 s lo (and clk) synthesizers are deter- mined by the external loop filter, the vco, the n-divide factor, and the reference frequency, fref. a good overview of the theory and practical implementation of pll synthesizers (fea- tured as a three-part series in analog dialogue ) can be found at: www.analog.com/library/analogdialogue/archives/33-03/phase/ index.html www.analog.com/library/analogdialogue/archives/33-05/ phase_locked/index.html www.analog.com/library/analogdialogue/archives/33-07/ phase3/index.html also, a free software copy of the analog devices adisimpll, a pll synthesizer simulation tool, is available at www.analog.com/ technology/rfcomms/rfif/adisimpll.html. note, the adf4112 model can be used as a close approximation to the AD9874 s lo synthesizer when using this software tool. fref 84k ~ vddl/2 lo bu ffer 500 500 to mixer lo port 1.75v bias lop lon notes 1. esd diode structures omitted for clarity. 2. fref stby switches shown with lo synthesizer on. figure 6. equivalent input of lo and ref buffers figure 6 shows the equivalent input structures of the synthesiz- ers lo and ref buffers (excluding the esd structures). the lo input is fed to the lo synthesizer s buffer as well as the AD9874 s mixer s lo port. both inputs are self-biasing and thus tolerate ac-coupled inputs. the lo input can be driven with a single-ended or differential signal. single-ended dc- coupled inputs should ensure sufficient signal swing above and below the common-mode bias of the lo and ref buffers (i.e., 1.75 v and vddl/2). note, the fref input is slew rate dependent and must be driven with input signals exceeding 6.4 v/ m sec to ensure synthesizer operation. fast acquire mode the fast acquire circuit attempts to boost the output current when the phase difference between the divided-down lo (i.e., f lo ) and the divided-down reference frequency (i.e., f ref ) exceeds the threshold determined by the lofa register. the lofa register specifies a divisor for the f ref signal that determines the period (t) of this divided-down clock. this period defines the time interval used in the fast acquire algorithm to control the charge pump current. assume for the moment that the nominal charge pump current is at its lowest setting (i.e., loi = 0) and denote this minimum current by i 0 . when the output pulse from the phase comparator exceeds t, the output current for the next pulse is 2 i 0 . when the pulse is wider than 2 t, the output current for the next pulse is 3 i 0 , and so forth, up to eight times the minimum output current. if the nominal charge pump current is more than the minimum value (i.e., loi > 0), the preceding rule is only applied if it results in an increase in the instantaneous charge pump current. if the charge pump current is set to its lowest value (loi = 0) and the fast acquire circuit is enabled, the instantaneous charge pump current will never fall below 2 i 0 when the pulsewidth is less than t. thus, the charge pump current when fast acquire is enabled is given by: ii loi pulse width t pump fa - =+ 0 11 { max( , , _ )} (4) the recommended setting for lofa is lor/16. choosing a larger value for lofa will increase t . thus, for a given phase differ- ence between the lo input and the f ref input, the instantaneous charge pump current will be less than that available for a lofa value of lor/16. similarly, a smaller value for lofa will decrease t , making more current available for the same phase difference. in other words, a smaller value of lofa will enable the synthe- sizer to settle faster in response to a frequency hop than will a large lofa value. care must be taken to choose a value for lofa that is large enough (values greater than 4 recommended) to prevent the loop from oscillating back and forth in response to a frequency hop. table vii. spi registers associated with lo synthesizer address bit default (hex) breakdown width value name 0x00 (7:0) 1 0xff stby 0x08 (5:0) 6 0x00 lor(13:8) 0x09 (7:0) 8 0x38 lor(7:0) 0x0a (7:5) 3 0x5 loa (4:0) 5 0x00 lob(12:8) 0x0b (7:0) 8 0x1d lob(7:0) 0x0c (6) 1 0 lof (5) 1 0 loinv (4:2) 3 0 loi (1:0) 2 0 lotm 0x0d (3:0) 4 0x0 lofa(13:8) 0x0e (7:0) 8 0x04 lofa(7:0)
rev. 0 e20e AD9874 the bias, i bias , of the negative-resistance core has four pro- grammable settings. lower equivalent q of the lc tank circuit may require a higher bias setting of the negative-resistance core to ensure proper oscillation. r bias should be selected so the common-mode voltage at clkp and clkn is approximately 1.6 v. the synthesizer may be disabled via the ck standby bit to allow the user to employ an external synthesizer and/or vco in place of those resident on the ic. note, if an external clk source or vco is used, the clock oscillator must be disabled via the cko standby bit. the phase noise performance of the clock synthesizer is depen- dent on several factors, including the clk oscillator i bias setting, the charge pump setting, the loop filter component values, and the internal f ref setting. figures 7b and 7c show how the measured phase noise attributed to the clock synthe- sizer varies (relative to an external f clk ) as a function of the i bias setting and charge pump setting for a e31 dbm ifin signal at 73.35 mhz with an external lo signal at 71.1 mhz. figure 7b shows that the optimum phase noise is achieved with the highest i bias (cko) setting, while figure 7c shows that the higher charge pump values provide the optimum performance for the given loop filter configuration. the AD9874 clock syn- thesizer and oscillator were set up to provide a f clk of 18 mhz from an external f ref of 16.8 mhz. the following external component values were selected for the synthesizer: r f = 390 ? = ? = = = = = = = = () ( = = = = ) n pll capable of 2.2 khz resolution at clock input frequencies up to 18 mhz and reference frequencies up to 25 mhz. it is similar to the lo synthesizer described previously in figure 4 with the following exceptions: it does not include an 8/9 prescaler nor an a counter. it includes a negative-resistance core that when used in conjunc- tion with an external lc tank and varactor, serves as the vco. the 14-bit reference counter and 13-bit n-divider counter can be programmed via the following registers: ckr and ckn. the clock frequency, f clk , is related to the reference frequency by the following equation: f ckn ckr f clk ref = () () i cki ma pump =+ () () ( ) = = ? = ? ? ? ( ? ( )) ()
rev. 0 AD9874 e21e e25 0 e90 e100 e110 e120 dbfs e20 e15 e10 e5 0 5 10 15 20 25 cki = 0 frequency offset e khz e80 e70 e60 e50 e40 e30 e20 e10 cki = 2 cki = 6 ext clk cki = 4 figure 7c. clk phase noise vs. charge pump setting bias (clk syn settings: cko bias = 3, ckr = 56, and ckn = 60 with f ref = 100khz) table viii. spi registers associated with clk synthesizer address bit default (hex) breakdown width value name 0x00 (7:0) 8 0xff stby 0x01 (3:2) 2 0 ckob 0x10 (5:0) 6 00 ckr(13:8) 0x11 (7:0) 8 0x38 ckr(7:0) 0x12 (4:0) 5 0x00 ckn(12:8) 0x13 (7:0) 8 0x3c ckn(7:0) 0x14 (6) 1 0 ckf (5) 1 0 ckinv (4:2) 3 0 cki (1:0) 1 0 cktm 0x15 (3:0) 4 0x0 ckfa(13:8) 0x16 (7:0) 8 0x04 ckfa(7:0) if lna/mixer the AD9874 contains a single-ended lna followed by a gilbert- type active mixer, shown in figure 8 w ith the required external components. the lna uses negative shunt feedback to set its input impedance at the ifin pin, thus making it dependent on the lna bias setting and input frequency. it can be modeled as approximately 370 ? (
rev. 0 e22e AD9874 the mixer?s differential lo port is driven by the lo buffer stage shown in figure 6 that can be driven single-ended or differential. since it is self-biasing, the lo signal level can be ac-coupled and range from 0.3 v p-p to 1.0 v p-p with negligible effect on per- formance. the mixer?s open-collector outputs, mxop and mxon, drive an external resonant tank consisting of a differential lc net- work tuned to the if of the band-pass ? ( = ) ? must be ac-coupled to the input of the band-pass ? ? f clk /8 center frequency of the modulator. the inductors should be chosen such that their impedance at f clk /8 is about 140 ? ( = f clk ). an accuracy of 20% is considered to be adequate. for example, at f clk = 18 mhz, l = 10 f clk /8 = 1/{2 f clk = 18 mhz and l = 10 f clk is increased by a factor of 1.44 mhz to 26 mhz so that f clk /8 becomes 3.25 mhz, reduc- ing l and c by approximately the same factor (i.e., l = 6.9 = ) f clk of 18 mhz varies between toko? fslm series and coilcraft? 1812cs series inductors. the graph also shows the extrapolated point of intersection used to determine the iip3 performance. note, the coilcraft inductor provides a 7 db? db improvement in performance and closely approximates the 3:1 slope associated with a third order linearity compared to the 2.65:1 slope associated with the toko inductor. the coilcraft 1008cs series showed similar performance to the 1812cs series. it is worth noting that the difference in imd performance between these two inductor families with an f clk of 26 mhz is insignificant. ?0 ?4 ?8 ?6 ?8 ?2 ?4 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 input referred power ?dbm to ko inductor p imd = 2.64 p in + 4.6 p in f in = 109.65mhz coilcraft p imd = 2.92 p in + 6.9 figure 10. imd performance between different inductors with lna and mixer at full bias and f clk of 18 mhz both the lna and mixer have four programmable bias settings so that current consumption can be minimized for a given appli- cation. figures 11a, 11b, and 11c show how the lna and mixer? noise figure (nf), linearity (iip3), if clip point, current consumption, and frequency response are all affected for a given lna/mixer bias setting. the measurements were taken at an if = 73.35 mhz and lo = 71.1 mhz with supplies set to 3 v. 1_0 13 12 11 10 9 8 noise figure ?db 1_1 1_2 1_3 2_0 2_1 2_2 2_3 3_0 3_1 3_2 3_3 ?0 ?8 ?6 ?4 ?2 ?0 clip point ?dbm clip point noise figure lna_mixer bias setting figure 11a. lna/mixer noise figure and conversion gain vs. bias setting 1_0 5 0 ? ?0 ?5 ?5 input iip3 ?dbm 1_1 1_2 1_3 2_0 2_1 2_2 2_3 3_0 3_1 3_2 3_3 7.00 8.25 5.75 4.50 3.25 2.00 iddi ?ma 9.50 ?0 lna_mixer current iip3 lna_mixer bias setting figure 11b. lna/mixer iip3 and current consumption vs. bias setting
rev. 0 AD9874 e23e based on these characterization curves, a lna/mixer bias setting of 3_3 is suitable for most applications since it will provide the greatest dynamic range in the presence of multiple unfiltered interferers. however, portable radio applications demanding the lowest possible power may benefit by changing the lna/mixer bias setting based on the received signal strength power (i.e., rssi) available from the ssi output data. for instance, selecting an lna_mixer bias setting of 1_2 for nominal input strength condi- tions (i.e., AD9874?s noise and linearity performance under different operating conditions. 0 0 e1 e2 e3 e5 db 100 200 300 400 500 e4 frequency e mhz e6 e7 e8 lna_mixer 1_2 setting lna_mixer 3_3 setting figure 11c. lna/mixer frequency response vs. bias setting a 16 db step attenuator is also included within the lna/mixer circuitry to prevent large signals (i.e., > e18 dbm) from overdriving the f clk /8 for the adc to function properly. the center frequency of the discrete-time resonator automatically scales with f clk , thus no tuning is required. to digital fi lter sc r eso- nator nine- l evel flas h esl g ain c ontrol mixer ou tput e xternal lc f clk = 13 msps?6 msps mxop mxon if2p if2n rc r eso- nator dac1 figure 12. equivalent circuit of sixth order band-pass f clk /8, is achieved once the lc and rc resonators of the
rev. 0 e24e AD9874 the signal transfer function of the AD9874 possesses inherent antialias filtering by virtue of the continuous-time portions of the loop filter in the band-pass 2f clk . the notches that naturally occur for all frequencies that alias to the f clk /8 pass band are clearly visible. even at the widest bandwidth setting, the notches are deep enough to provide greater than 80 db of alias protection. thus, the wideband if filtering requirements preceding the AD9874 will be mostly determined by the mixer? image band that is offset from the desired if input frequency by f clk /4 (i.e., 2 f clk /8), rather than any aliasing associated with the adc. 0 0 ?0 ?0 ?0 ?0 db ?0 normalized frequency ?relative to f out ?0 ?0 ?0 0.5 1.0 1.5 2.0 notch at all alias frequencies figure 13b. signal transfer function of the band-pass f clk /8 pass band. the width of the pass band determines the transfer function droop, but even at the lowest oversampling ratio (48) where the pass band edges are at f clk /192 ( f clk ), the gain variation is less than 0.5 db. note, the amount of attenuation offered by the signal transfer function near f clk /8 should also be considered when determining the narrow-band if filtering requirements preceding the AD9874. ?.1 0 ? db ?0 normalized frequency ?relative to f clk ?5 ?0 ?.05 0 0.05 0.1 figure 13c. magnitude of the adc? signal transfer function near f clk /8 tuning of the ( ) () () ()
rev. 0 AD9874 e25e once the AD9874 has been tuned, the noise figure degradation attributed solely to the temperature drift of the lc and rc resona- tors is m inimal. since the drift of the rc resonator is actually negligible compared to that of the lc resonator, the external l and c components? temperature drift characteristics tend to dominate. figure 13d shows the degradation in noise figure as the product of the lc value is allowed to vary from e12.5% to +12.5%. note, the noise figure remains relatively constant over a ( ) = = = ( = = ) f clk /8 complex mixer and a cascade of three linear phase fir filters: dec1, dec2, and dec3. dec1 downsamples by a factor of 12 using a fourth order comb filter. dec2 also uses a fourth order comb filter, but its decimation factor is set by the m field of register 0x07. dec3 is either a decimate-by-5 fir filter or a decimate-by-4 fir filter depending on the value of the k bit within register 0x07. thus, the composite decimation factor can be set to either 60 ( ) ( ) + ( = = ) ( f out ) is 20 ksps, with a usable complex signal bandwidth of 10 khz centered around dc. as this figure shows, the first and second alias bands (occurring at even integer multiples of f out /2) have the least attenuation but provide at least 88 db of attenuation. note, signals falling around frequency offsets that are odd integer multiples of f out /2 (i.e., 10 khz, 30 khz, and 50 khz) will fall back into the transition band of the digital filter. frequency ?khz 0 ?0 ?00 030 10 20 ?0 ?0 ?0 40 100 db fold- ing point 5.0khz pass band ?20 70 80 60 50 90 ?8db ?8db ?01db ?03db figure 15a. decimation filter frequency response for f out = 20 ksps (f clk = 18 mhz, osr = 900) figure 15b shows the response of the decimation filter with a decimation factor of 48 and a sampling clock rate of 26 mhz. the alias attenuation is now at least 94 db, and this attenuation occurs for frequencies at the edges of the fourth alias band. the differ- ence between the alias attenuation characteristics of figure 15b and those of figure 15a is due to the fact that the third decimation stage decimates by a factor of 5 for figure 15a versus a factor of 4 for figure 15b. 0 ?0 ?00 ?0 ?0 ?0 db ?20 frequency mhz 0 1.5 0.5 1.0 2.0 2.5 135.466khz pass band ?8db ?15db ?4db figure 15b. decimation filter frequency response for f out = 541.666 ksps (f clk = 26 mhz, osr = 48)
rev. 0 e26e AD9874 figures 16a and 16b show expanded views of the pass band for the two possible configurations of the third decimation filter. when decimating by 60 n (k = 0), the pass-band gain variation is 1.2 db; when decimating by 48 n (k = 1), the pass-band gain variation is 0.9 db. normalization of full scale at band center is accurate to within 0.14 db across all decimation modes. figures 17a and 17b show the folded frequency response of the decimator for k = 0 and k = 1, respectively. normalized frequency ?relative to f out 0 3 0.250 db 0.125 2 1 0 ? ? ? pa ss-band gain frequency = 1.2db figure 16a. pass-band frequency response of the decimator for k = 0 normalized frequency ?relative to f out 0 3 0.250 db 0.125 2 1 0 ? ? ? pa ss-band gain variation = 0.9db figure 16b. pass-band frequency response of the decimator for k = 1 normalized frequency ?relative to f out 0 0 0.50 db 0.25 ?0 ?0 ?0 ?0 ?00 ?20 min alias attn = 87.7db figure 17a. folded decimator frequency response for k = 0 normalized frequency ?relative to f out 0 0 0.50 db 0.25 ?0 ?0 ?0 ?0 ?00 ?20 min alias attn = 97.2db figure 17b. folded decimator frequency response for k = 1
rev. 0 AD9874 ?7 variable gain amplifier operation with automatic gain control the AD9874 contains both a variable gain amplifier (vga) and a digital vga (dvga) along with all of the necessary signal estima- tion and control circuitry to implement automatic gain control (agc), as shown in figure 18. the agc control circuitry provides a high degree of programmability, allowing users to optimize the agc response as well as the AD9874? dynamic range for a given application. the vga is programmable over a 12 db range and implemented within the adc by adjusting its full-scale reference level. increasing the adc? full scale is equivalent to attenuating the signal. an additional 12 db of digital gain range is achieved by scaling the output of the decimation filter in the dvga. note, a slight increase in the supply current (i.e., 0.67 ma) is drawn from vddi and vddf as the vga changes from 0 db to 12 db attenuation. the purpose of the vga is to extend the usable dynamic range of the AD9874 by allowing the adc to digitize a desired signal over a large input power range as well as recover a low level signal in the presence of larger unfiltered interferers without saturating or ?lipping?the adc. the dvga is most useful in extending the dynamic range in narrow-band applications requiring a 16-bit i and q data format. in these applications, quantization noise resulting from internal truncation to 16 bits as well as external 16-bit fixed point post-processing can degrade the AD9874? effective noise figure by 1 or more db. the dvga is enabled by writing a 1 to the agcv field. the vga (and the dvga) can operate in either a user-controlled variable gain mode or auto- matic gain control (agc) mode. it is worth noting that the vga imparts negligible phase error upon the desired signal as its gain is varied over a 12 db range. this is due to the bandwidth of the vga being far greater than the down converted desired signal (centered about f clk /8) and remaining relatively independent of gain setting. as a result, phase modulated signals should experience minimal phase error as the agc varies the vga gain while tracking an interferer or the desired signal under fading conditions. note, the envelope of the signal will still be affected by the agc settings. variable gain control the variable gain control is enabled by setting the agcr field of register 0x06 to 0. in this mode, the gain of the vga (and the dvga) can be adjusted by writing to the 16-bit agcg register. the maximum update rate of the agcg register via the spi port is f clk /240. the msb of this register is the bit that enables 16 db of attenuation in the mixer. this feature allows the AD9874 to cope with large level signals beyond the vga? range (i.e., > ?8 dbm at lna input) to prevent overloading of the adc. the lower 15 bits specify the attenuation in the remainder of the signal path. if the dvga is enabled, the attenuation range is from ?2 db to +12 db since the dvga provides 12 db of digital gain. in this case, all 15 bits are significant. however, with the dvga disabled the attenuation range extends from 0 db to 12 db and only the lower 14 bits are useful. figure 19 shows the relationship between the amount of attenuation and the agc register setting for both cases. agcg setting ? hex ?12 0 12 0000 agc attenuation ? db 1fff 3fff 7fff 5fff 6 ?6 vga r ange dvga r ange only vga enabled dvga and vga enabled figure 19. agc gain range characteristics vs. agcg register setting with and without dvga enabled + vga dac figure 18. functional block diagram of vga and agc
rev. 0 e28e AD9874 referring to figure 18, the gain of the vga is set by an 8-bit control dac that provides a control signal to the vga appearing at the gain control pin (gcp). for applications implementing automatic gain control, the dac?s output resistance can be reduced by a factor of 9 to decrease the attack time of the agc response for faster signal acquisition. an external capacitor, c dac , from gcp to analog ground is required to smooth the dac?s output each time it updates as well as to filter wideband noise. note, c dac , in combination with the dac?s programmable output resistance, sets the e3 db bandwidth and time constant associated with this rc network. a linear estimate of the received signal strength is performed at the output of the first decimation stage (dec1) and output of the dvga (if enabled) as discussed in the agc section. this data is available as a 6-bit rssi field within an ssi frame with 60 corresponding to a full-scale signal for a given agc attenua- tion setting. the rssi field is updated at f clk /60 and can be used with the 8-bit attenuation field (or agcg attenuation setting) to determine the absolute signal strength. the accuracy of the mean rssi reading (relative to the if input power) depends on the input signal? frequency offset relative to the if frequency since both dec1 filter? response as well as the adc? signal transfer function attenuates the mixer? downconverted signal level centered at f clk /8. as a result, the estimated signal strength of input signals falling within proximity to the if is reported accurately, while those signals at increasingly higher frequency offsets incur larger measurement errors. figure 20 shows the normalized error of the rssi reading as a function of the frequency offset from the if frequency. note, the significance of this error becomes apparent when determining the maximum input interferer (or blocker) levels with the agc enabled. 0 0 ? measured rssi error ?db ? normalized frequency offset ?( f in ? f if ) f clk ? ?8 0.03 0.04 0.05 0.02 0.01 ?2 ?5 figure 20. normalized rssi error vs. normalized if frequency offset automatic gain control (agc) the gain of the vga (and dvga) is automatically adjusted when the agc is enabled via the agcr field of register 0x06. in this mode, the gain of the vga is continuously updated at f clk /60 in an attempt to ensure that the maximum analog signal level into the adc does not exceed the adc clip level and that the rms output level of the adc is equal to a programmable reference level. with the dvga enabled, the agc control loop also attempts to minim ize the effects of 16-bit truncation noise prior to the ssi output by continuously adjusting the dvga? gain to ensure maximum digital gain while not exceeding the pr o gra mma bl e reference level. this programmable level can be set at 3 db, 6 db, 9 db, 12 db, and 15 db below the adc saturation (clip) level by writing values from 1 to 5 to the 3-bit agcr field. note, the adc clip level is defined to be 2 db below its full scale (i.e., ?8 dbm at the lna input for a matched input and maximum attenuation). if agcr is 0, automatic gain control is disabled. since clipping of the adc input will degrade the snr performance, the refer- ence level should also take into consideration the peak-to-rms characteristics of the target (or interferer) signals. referring again to figure 18, the majority of the agc loop operates in the discrete time domain. the sample rate of the loop is f clk /60; therefore, registers associated with the agc algorithm are updated at this rate. the number of overload and adc reset occurrences within the final i/q update rate of the AD9874, as well as the agc value (8 msbs), can be read from the ssi data upon proper configuration. the agc performs digital signal estimation at the output of the first decimation stage (dec1) as well as the dvga output that follows the last decimation stage (dec3). the rms power of the i and q signal is estimated by the following equation: xest n abs i n abs q n [] = [] () + [] () () ( ) = =
rev. 0 AD9874 e29e the maximum bandwidth is 9 khz. a general expression for the attack bandwidth is: bw f mhz hz a clk agca = () () () t attack bw agca a = ? ? ? ? = () () t decay t attack agcd = () () = = = = = = = = = = = = f clk = 18 mhz. figure 21b shows the agc attack time response for different agco settings. vga attenuation setting time ?msec 0.1 0.2 0 0.5 0.4 0.3 80 64 0 48 32 16 96 1.0 0.9 0.8 0.7 0.6 112 128 a gco = 7 a gco = 4 a gcd = 0 figure 21b. agc response for different agco settings with f clk = 18 msps, f clkout = 300 ksps, decimate by 60, and agca = agcd = 0 lastly, the agcf bit reduces the dac source resistance by at least a factor of 10. this facilitates fast acquisition by lowering the rc time constant that is formed with the external capacitors connected from the gcp pin-to-ground (gcn pin). for an overshoot-free step response in the agc loop, the capacitor connected from the gcp pin to the gcn ground pin should be chosen so that the rc time constant is less than one quarter that of the raw loop. specifically: rc bw < () () r is the resistance between the gcp pin and ground (64 kw = < = ) bw is the raw loop bandwidth. note that with c chosen at this upper limit, the loop bandwidth increases by approximately 30%. now consider the same case as above but with the dvga enabled to minimize the effects of 16-bit truncation. with the dvga enabled, a control loop based on the larger of the two estimated signal levels (i.e., output of dec1 and dvga) is used to control the dvga gain. the dvga multiplies the output of the deci- mation filter by a factor ranging from 1 to 4 (i.e., 0 db to 12 db). when signals are small, the dvga gain is 4 and the 16-bit output is extracted from the 24-bit data produced by the decimation filter by dropping 2 msbs and taking the next 16-bits. as signals get larger, the dvga gain decreases until the point where the dvga gain is 1 and the 16-bit output data is simply the 16 msbs of the internal 24-bit data. as signals get even larger, attenuation is accomplished by the normal method of increasing the adc? full scale. the extra 12 db of gain range provided by the dvga reduces the input-referred truncation noise by 12 db and makes the data more tolerant of lsb corruption within the dsp. the price paid for this extension to the gain range is that the start of agc action is 12 db lower and that the agc loop will be unstable if its bandwidth is set too wide. the latter difficulty results from the large delay of the decimation filters, dec2 and dec3, when one implements a large decimation factor. as a result, given an option, the use of 24-bit data is preferable to using the dvga.
rev. 0 e30e AD9874 table xii indicates which agca values are reasonable for various decimation factors. the white cells indicate that the (decimation factor/agca) combination works well. the light gray cells indi- cate ringing and an increase in the agc settling time, and the dark gray cells indicate that the combination results in instability or near instability in the agc loop. setting agcf = 1 improves the time-domain behavior at the expense of increased spectral spreading. table xii. agca limits if the dvga is enabled agca m 0 1 4 8 e 60 120 300 540 900 decimation factor 45 6 78 9 10 11 12 13 14 15 lastly, consider the case of a strong out-of-band interferer (i.e., e18 dbm to e32 dbm for matched if input) that is larger than the target signal and large enough to be tracked by the control loop based on the output of the dec1. the ability of the control loop to track this interferer and set the vga attenuation to prevent clipping of the adc is limited by the accuracy of the digital signal estimation occurring at the output of dec1. the accuracy of the digital signal estimation is a function of the frequency offset of the out-of-band interferer relative to the if frequency as shown in figure 20. interferers at increasingly higher frequency offsets incur larger measurement errors, potentially causing the control loop to inadvertently reduce the amount of vga attenuation that may result in clipping of the adc. figure 21c shows the maxi- mum measured interferer signal level versus the normalized if offset frequency (relative to f clk ) tolerated by the AD9874 relative to its maximum target input signal level (0 dbfs = e18 dbm). note, the increase in allowable interferer level occurring beyond 0.04 f clk = 18 mhz. also shown on the plot is the snr that would be observed at the output for a ? dbfs input. the high dynamic range of the adc within the AD9874 ensures that the system nf increases gradually as the agc attenuation is increased. in narrow-band (bw = 20 khz) mode, the system noise figure increases by less than 3 db over a 12 db agc range, while in wideband (bw = 150 khz) mode, the degradation is about 5d b. as a result, the highest instantaneous dynamic range for the AD9874 occurs with 12 db of agc attenuation, since the AD9874 can accommodate an additional 12 db peak signal level with only a moderate increase in its noise floor. as figure 22a shows, the AD9874 can achieve an snr in excess of 100 db in narrow-band applications. to realize the full perfor- mance of the AD9874 in such applications, it is recommended that the i/q data be represented with 24 bits. if 16-bit data is used, the effective system nf will increase because of the quantization noise present in the 16-bit data after truncation. 36 0 15 14 12 13 11 10 9 8 noise figure ?db 912 vg a attenuation ?db snr = 90.1dbfs bw = 50khz bw = 150khz snr = 82.9dbfs bw = 10khz snr = 95.1dbfs snr = 103.2db figure 22a. nominal system noise figure and peak snr vs. agcg setting (f if = 73.35 mhz, f clk = 18 msps, and 24-bit i/q data)
rev. 0 AD9874 e31e figure 22b plots the nominal system nf with 16-bit output data as a function of agc in both narrow-band and wideband mode. in wideband mode, the nf curve is virtually unchanged relative to the 24-bit output data because the output snr before truncation is always less than the 96 db snr that 16-bit data can support. noise figure e db 15 8 14 13 12 11 10 9 snr = 98.8dbfs bw = 50khz bw = 150khz snr = 83dbfs snr = 94.1dbfs bw = 10khz snr = 89.9dbfs 16 17 3 6 0 9 12 vg a attenuation e db figure 22b. nominal system noise figure and peak snr vs. agcg setting (f if = 73.35 mhz, f clk = 18 msps, and 16-bit i/q data) however, in narrow-band mode, where the output snr approaches or exceeds the snr that can be supported with 16-bit data, the degradation in system nf is more severe. furthermore, if the signal processing within the dsp adds noise at the level of an lsb, the system noise figure can be degraded even more than figure 22b shows. for example, this could occur in a fixed 16-bit dsp whose code is not optimized to process the AD9874?s 16-bit data with minimal quantization effects. to limit the quantization effects within the AD9874, the 24-bit data undergoes noise shaping just prior to 16-bit truncation, thus reducing the in-band quantization noise by 5 db (with 2 f clk . thus, the clock frequency ( f clk ) is the most important variable in determining which lo (and therefore if) frequencies are viable. in-band power ?dbfs ?0 ?0 ?0 ?0 ?0 0 250 300 200 150 100 50 lo frequency ?mhz figure 23a. total in-band noise + spur power with no signal applied as a function of the lo frequency (f clk = 18 mhz and output signal bandwidth of 150 khz) in-band power ?dbfs ?0 ?0 ?0 ?0 ?0 0 250 300 lo frequency ?mhz 200 150 100 50 figure 23b. same as figure 23a excluding lo frequencies known to produce large in-band spurs
rev. 0 e32e AD9874 many applications have frequency plans that take advantage of industry-standard if frequencies due to the large selection of low cost crystal or saw filters. if the selected if frequency and adc clock rate result in a problematic spurious component, an alternative adc clock rate should be selected by slightly modi- fying the decimation factor and clk synthesizer settings (if used) such that the output sample rate remains the same. also, applications requiring a certain degree of tuning range should take into consideration the location and magnitude of these spurs when determining the tuning range as well as optimum if and adc clock frequency. figure 23a plots the measured in-band noise power as a function of the lo frequency for f clk = 18 mhz and an output signal band- width of 150 khz when no signal is present. any lo frequency resulting in large spurs should be avoided. as this figure shows, large spurs result when the lo is f clk /8 = 2.25 mhz away from a harmonic of 18 mhz (i.e., n f clk ) ( m f lo ) m ix with harmonics of f clk to f clk /8. this spur mechanism is a result of the mixer being internally driven by a squared-up version of the lo input consisting of the lo frequency and its odd order harmonics. these spur frequencies can be calculated from the following relation: mf n f lo clk = () () m = 1, 3, 5... and n = 1, 2, 3... a second source of spurs is a large block of digital circuitry that is clocked at f clk /3. problematic lo frequencies associated with this spur source are given by: ff nf f lo clk clk clk =+ () n = 1, 2, 3 ... figure 23b shows that omitting the lo frequencies given by equation 12 for m = 1, 3, and 5 and by equation 13 accounts for most of the spurs. some of the remaining low level spurs can be attributed to coupling from the ssi digital output. as a result, users are also advised to optimize the output bit rate ( f clkout via the ssiord register) and the digital output driver strength to achieve the lowest spurious and noise figure performance for a particular lo frequency and f clk setting. this is especially the case for very narrow-band channels in which low level spurs can degrade the AD9874? sensitivity performance. despite the many spurs, sweet spots in the lo frequency are generally wide enough to accommodate the maximum signal bandwidth of the AD9874. as evidence of this property, figure 24 shows that the in-band noise is quite constant for lo frequencies ranging from 70 mhz to 71 mhz. 70.5 70.0 ?0 ?0 ?0 ?0 ?0 71.0 lo frequency ?mhz in-band power ?dbfs figure 24. expanded view from 70 mhz to 71 mhz spurious responses the spectral purity of the lo (including its phase noise) is an important consideration since lo spurs can mix with undesired signals present at the AD9874? ifin input to produce an in-band response. to demonstrate the low lo spur level introduced within the AD9874, figure 25 plots the demodulated output power as a function of the input if frequency for an lo frequency of 71.1 mhz and a clock frequency of 18 mhz. 90 50 0 ?0 ?0 ?0 ?0 100 if frequency ?mhz dbfs ?20 ?00 60 70 80 d = f clk /4 = 4.5mhz desired responses figure 25. response of AD9874 to a ?0 dbm input if input when f lo = 71.1 mhz the two large ?0 dbfs spikes near the center of the plot are the desired responses at f lo f if2_adc where f if2_adc = f clk /8, i.e., at 68.85 mhz and 73.35 mhz. lo spurs at f lo f spur would result in spurious responses at offsets of f spur around the desired responses. close-in spurs of this kind are not visible on the plot, but small spurious responses at f lo f if2_adc f clk , i.e., at 50.85 mhz, 55.35 mhz, 86.85 mhz, and 91.35 mhz, are visible at the ?0 dbfs level. this data indicates that the AD9874 does an excellent job of preserving the purity of the lo signal. figure 25 can also be used to gauge how well the AD9874 rejects undesired signals. for example, the half-if response (at 69.975 mhz and 72.225 mhz) is approximately ?00 dbfs, giving a selectivity of 90 db for this spurious response. the largest spurious response at approximately ?0 dbfs occurs with input frequencies of 70.35 mhz and 71.85 mhz. these s purs result from third order nonlinearity in the signal path (i.e., abs [3 f lo ?3 f if_input ] = f clk /8).
rev. 0 AD9874 e33e external passive component requirements figure 26 shows an example circuit using the AD9874 while table xiv shows the nominal dc bias voltages seen at the different pins. the purpose is to show the various external passive compo- nents required by the AD9874 along with nominal dc voltages for troubleshooting purposes. mxop mxon gndf if2n if2p vddf gcp gcn vdda gnda vrefp vrefn gndl fref gnds syncb gndh fs doutb douta clkout vddh vddd pe vddi ifin cxif gndi cxvl lop lon cxvm vddl vddp ioutl gndp rref vddq ioutc gndq vddc gndc clkp clkn gnds gndd pc pd 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 25 26 27 28 29 30 31 32 33 34 35 36 AD9874 50 180pf 10 h 10 h lc tank 100pf 100 pf 2.2nf 100pf 10nf 100pf 100k 10nf 10nf 1nf 10nf 10nf 100nf 100nf 10nf figure 26. example circuit showing recommended component values table xiv. nominal dc bias voltages pin number pin name (v) nominal dc bias 1 mxop vddi e 0.2 2m xon vddi e 0.2 4i f2n 1.3 e 1.7 5 if2p 1.3 e 1.7 11 vrefp vdda/2 + 0.250 12 vrefn vdda/2 e 0.250 13 rref 1.2 19 clkp vddc e 1.3 20 clkn vddc e 1.3 35 fref vddc/2 41 cxvm 1.6 e 2.0 42 lon 1.65 e 1.9 43 lop 1.65 e 1.9 44 cxvl vddi e 0.05 46 cxif 1.6 e 2.0 47 ifin 0.9 e 1.1 the lo, clk, and ifin signals are coupled to their respective inputs using 10 nf capacitors. the output of the mixer is coupled to the input of the adc using 100 pf. an external 100 k ? f clk = 18 mhz are given on the diagram. for other clock frequencies, the two inductors and the capacitor of the lc tank should be scaled in inverse proportion to the clock. for example, if f clk = 26 mhz, then the two inductors should be = 6.9 ( ) ( ) f clk /8) to simplify the digital quadrature demodulation process.
rev. 0 e34e AD9874 this second if signal is then digitized by the f clk /4 depending on high or low side injection). rf input preselect filter tuner if crystal or saw filter vdda - adc lna vco adf42xx pll syn refin to dsp AD9874 decimation filter sample clock synthesizer ioutc loop filter lop lon vco loop filter vddc ioutc clkp clkn from dsp lo synth. vo ltag e reference spi rref vrefp vrefn syncb pc pd pe crystal oscillator ifin ?6db lna vxop vxon ii-2p ii-2n dac agc formatting/ssi douta doutb fs clkout control logic gcp gcn if2 = f clk /8 figure 27. typical dual conversion superheterodyne application using the AD9874 the selectivity and bandwidth of the if filter will depend on both the magnitude and frequency offset(s) of the adjacent channel blocker(s) that could overdrive the AD9874? input or generate in-band intermodulation components. further suppression is performed within the AD9874 by its inherent band-pass response and digital decimation filters. note, some applications will require additional application-specific filtering performed in the dsp that follows the AD9874 to remove the adjacent channel and/or implement a matched filter for optimum signal detection. the output data rate of the AD9874, f out , should be chosen to be at least twice the bandwidth or symbol rate of the desired signal to ensure that the decimation filters provide a flat pass-band response as well as to allow for post-processing by a dsp. once f out is determined, the decimation factor of the digital filters should be set such that the input clock rate, f clk , falls between the AD9874? rated operating range of 13 mhz?6 mhz and no significant spurious products related to f clk f all within the desired pass band resulting in a reduction in sensitivity perfor- mance. if a spurious component is found to limit the sensitivity performance, the decimation factor can often be modified slightly to find a ?purious free?pass band. in general, selecting
rev. 0 AD9874 e35e vco 25 23 24 pe pc pd 33 syncb 31 fs 29 28 douta clkout 35 f ref 19 20 clkp clkn lop lon 43 42 ifin 47 15 AD9874 master ioutc loop filter 38 15 ioutc 25 23 24 pe pc pd 35 lop lon 43 42 ifin 47 31 fs 29 28 douta clkout 33 syncb to dsp clkp clkn ioutl to dsp from dsp loop filter c va r r d r f c p c z 0.1 f l osc r bias c osc to ot her AD9874s from crystal oscillation vddc to ot her AD9874s AD9874 slave 19 20 f ref figure 28. example of synchronizing multiple AD9874s a higher f clk is typically more desirable given a choice, since the first if? filtering requirements often depend on the transition reg i on b etw een th e if frequency and the image band (i.e., f clk /4 ). lastly, the output ssi clock rate, f clkout , and digital driver strength should be set to their lowest possible settings to mini- mize the potential harm f ul effects of digital induced noise while preserving a reliable data link to the dsp. note, the ssicra, ssicrb, and ssiord registers (i.e., 0x18, 0x19, and 0x1a) provide a large degree of flexibility for optimization of the ssi interface. synchronization of multiple AD9874s some applications such as receiver diversity and beam steering may require two or more AD9874s operating in parallel while maintaining synchronization. figure 28 shows an example of how multiple AD9874s can be cascaded, with one device serving as the master and the other devices serving as the slaves. in this example, all of the devices have the exact same spi register con- figuration since they share the same spi interface to the dsp. since the state of each of the AD9874? internal counters is unknown upon initialization, synchronization of the devices is required via a syncb pulse (see figure 4) to synchronize their digital filters and ensure precise time alignment of the data streams. although all of the devices?synthesizers are enabled, the lo and clk signals for the slaves(s) are derived from the masters?synthe- sizers and are referenced to an external crystal oscillator. all of the necessary external components (i.e., loop filters, varactor, lc, and vco) to ensure proper closed-loop operation of these synthesizers are included. note, while the vco output of the lo synthesizer is ac-coupled to the slave? lo input(s), all of the clk inputs of the devices must be dc-coupled if the AD9874? clk oscillators are enabled. this is due to the dc current required by the clk oscillators in each device. in essence, these negative impedance cores are oper- ating in parallel, increasing the effective q of the lc resonator circuit. note, rbias should be sized such that the sum of the oscillators?dc bias currents maintains a common-mode voltage of around 1.6 v.
rev. 0 e36e AD9874 vco lna x mixer if saw 1 if saw 2 duplexer preselect gain = e2db nf = 2db gain = 22db nf = 1db gain = e3db nf = 3db gain = 5db nf = 12db if amp gain = e9db nf = e9db gain = 15db nf = 2db 13mhz dsp or asic 36db pad 25 23 24 pe pc pd 33 syncb 31 fs 29 28 douta clkout 35 19 20 clkp clkn lop lon 43 42 47 15 AD9874 master loop filter 15 ioutc 25 23 24 pe pc pd 35 lop lon 43 42 ifin 47 AD9874 slave 31 fs 29 28 douta clkout 33 syncb 19 20 clkp clkn ioutl loop filter c var r d r f c p c z 0.1 f l osc r bias c osc vddc ifin 38 ioutc attenuated path with clip point = 7.0dbm direct path with clip point = e17dbm f ref f ref figure 29. example of split path rx architecture to increase receiver dynamic range capabilities
rev. 0 AD9874 ?7 gives a 6d b adjustment of the clip point, allowing the clip point difference to be calibrated to exactly 24 db so that a simple 5-bit shift would make up the gain difference. the attenuated path can handle signal levels up to C 12 db at the antenna before being overdriven. since the saw filters provide sufficient blocker suppression, the digital data from this path need only be selected when the target signal exceeds C 36 dbm. although the sensitivity of the receiver with the attenuated path is 20 db lower than the direct path, the strong target signal ensures a sufficiently high carrier-to-noise ratio. since gsm is based on a tdma scheme, digital data (or path) selection can occur on a slot-by-slot basis. the AD9874 would be configured to provide serial i and q data at a frame rate of 541.67 ksps as well as some additional information including a 2-bit reset field and a 6-bit rssi field. these two fields contain the information needed to decide whether the direct or the attenuated path should be used for the current time slot. hung mixer mode the AD9874 can be operated in the hung mixer mode by tying one of the lo s self-biasing inputs to ground (i.e., gndi) or the positive supply (vddi). in this mode, the AD9874 acts as a narrow-band, band-pass - adc, since its mixer passes the ifin signal without any frequency translation. the ifin signal must be centered about the resonant frequency of the - adc (i.e., f clk /8) and the clock rate, f clk , and decimation factors must be selected to accommodate the bandwidth of the desired input signal. note: the lo synthesizer can be disabled since it is no longer required. since the mixer does not have any losses associated with the mix- ing operation, the conversion gain through the lna and mixer is higher resulting in a nominal input clip point of C 24 dbm. the linearity or iip3 performance of the lna and mixer remains roughly unchanged and similar to that shown in figure 11b. the snr performance is dependent of the vga attenuation setting, i/ q data resolution, and output bandwidth as shown in figure 30. applications requiring the highest instantaneous dynamic range should set the vga for maximum attenuation. also, several extra db in snr performance can be gained at lower signal bandwidths by using 24-bit i/q data. 0 105 snr ?db 95 bw ?khz 85 80 80 120 140 160 40 20 60 100 100 90 min atten w/ 24-bit i/q data max atten w/ 16-bit i/q data min atten w/ 16-bit i/q data max atten w/ 24-bit i/q data f clk = 18msps figure 30. ?ung mixer?snr vs. bw and vga layout example, evaluation board, and software the evaluation board and its accompanying software provide a simple way to evaluate the AD9874. the block diagram in fig- ure 31 shows the major blocks of the evaluation board. the evaluation board is designed to be flexible, allowing the user to configure it for different applications. the power supply distribution block provides filtered, adjustable voltages to the various supply pins of the AD9874. in the if input signal path, component pads are available to implement different if impedance matching networks. the lo and clk signals can be externally applied or internally derived from a user-supplied vco module interface daughter board. the reference for the on-chip lo and clk synthesizers can be applied via the external f ref input or an on-board crystal oscillator. the evaluation board is designed to interface to a pc via a national instruments ni 6533 digital io card. an xilinx fpga formats the data between the AD9874 and digital i/o card. mixer output dut if input lo input vco module interface crystal oscillator (optional) idt fifo (optional) power supply distribution eprom clk input fref input nidaq 68-pin connector xilinx sparton fpga AD9874 figure 31. evaluation board platform software developed using national instruments l abview ? (and provided as microsoft ? w indows ? executable programs) is supplied for the configuration of the spi port registers and evaluation of the AD9874 output data. these programs have a convenient graphical user interface allowing for easy access to the various spi port configuration registers and realtime frequency analysis of the output data. for more information on the AD9874 evaluation board, including an example layout, please refer to the eval-AD9874 ebi data sheet.
rev. 0 e38e AD9874 outline dimensions 48-lead plastic quad flatpack [lqfp] (st-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc seating plane 1.60 max 0.75 0.60 0.45 view a 7 3.5 0 0.20 0.09 1.45 1.40 1.35 0.15 0.05 0.08 max coplanarity view a rotated 90 ccw pin 1 indicator 9.00 bsc compliant to jedec standards ms-026bbc seating plane
e39e
c02639??/02(0) printed in u.s.a. ?0

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