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dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 as4lc4m16 rev. 1.0 7/02 4 meg x 16 dram extended data out (edo) dram features ? single +3.3v 0.3v power supply. ? industry-standard x16 pinout, timing, functions, and package. ? 12 row, 10 column addresses ? high-performance cmos silicon-gate process ? all inputs, outputs and clocks are lvttl-compatible ? extended data-out (edo) page mode access ? 4,096-cycle cas\-before-ras\ (cbr) refresh distributed across 64ms ? optional self refresh (s) for low-power data retention ? level 1 moisture sensitivity rating, jedec j-std-020 options markings ? package(s) 50-pin tsop (400-mil) dg ? timing 50ns access -5 60ns access -6 ? refresh rates standard refresh none self refresh s* ? operating temperature ranges military (-55c to +125c) xt industrial (-40c to +85c) it note: the \ symbol indicates signal is active low. *contact factory for availability. self refresh option available on it version only. for more products and information please visit our web site at www.austinsemiconductor.com pin assignment (top view) 50-pin tsop (dg) configuration 4 meg x 16 refresh 4k row address a0-a11 column addressing a0-a9 speed t rc t rac t pc t aa t cac t cas -5 84ns 50ns 20ns 25ns 13ns 8ns -6 104ns 60ns 25ns 30ns 15ns 10ns key timing parameters
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 as4lc4m16 rev. 1.0 7/02 functional block diagram
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 as4lc4m16 rev. 1.0 7/02 general description the 4 meg x 16 dram is a high-speed cmos, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3v to 3.6v. the device is functionally organized as 4,194,304 locations containing 16 bits each. the 4,194,304 memory locations are arranged in 4,096 rows by 1,024 columns. during read or write cycles, each location is uniquely addresses via the address bits: 12 row-address bits (a0 - a11) and 10 column-address bits (a0 - a9). in addition, both byte and word accesses are supported via the two cas\ pins (casl\ and cash\). the cas\ functionality and timing related to address and control functions (e.g., latching column addresses or selecting cbr refresh) is such that the internal cas\ signal is determined by the first external cas\ signal (casl\ or cash\) to transition low and the last to transition back high. the cas\ functionality and timing related to driving or latching data is such that each cas\ signal independently controls the associated either dq pins. the row address is latched by the ras\ signal, then the column address is latched by cas\. this device provides edo-page-mode operation, allowing for fast successive data operations (read, write or read-modify-write) within a given row. the 4 meg x 16 dram must be refreshed periodically in order to retain stored data. dram access each location in the dram is uniquely addressable, as mentioned in the general description. use of both cas\ signals resulted in a word access via the 16 i/o pins (dq0 - dq15). using only one of the two signals results in a byte access cycle. casl\ transitioning low selects an access cycle for the lower byte (dq0 - dq7), and cash\ transitioning low selects an access cycle for the upper byte (dq8-dq15). general byte and word access timing is shown in figures 1 and 2. figure 1: word and byte write example
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 as4lc4m16 rev. 1.0 7/02 dram access (continued) a logic high on we\ dictates read mode, while a logic low on we\ dictates write mode. during a write cycle, data-in (d) is latched by the falling edge of we or cas\ (casl\ or cash\), whichever occurs last. an early write occurs when we is taken low prior to either cas\ falling. a late write or read-modify-write occurs when we falls after cas\ (casl\ or cash\) is taken low. during early write cycles, the data outputs (q) will remain high-z, regardless of the state of oe\. during late write or read-modify- write cycles, oe\ must be taken high to disable the data outputs prior to applying input data. if a late write or read-modify-write is attempted while keeping oe\ low, no write will occur, and the data outputs will drive read data from the accessed location. additionally, both bytes are active. a cas\ precharge must be satisfied prior to changing modes of operation be- tween the upper and lower bytes. for example, an early write on one byte and a late write on the other byte are not allowed during the same cycle. however, an early write on one byte and a late write on the other byte, after a cas\ precharge has been satisfied, are permissible. edo page mode dram read cycles have traditionally turned the output buffers off (high-z) with the rising edge of cas\. if cas\ went high and oe\ was low (active), the output buffers would be disabled. the 64mb edo dram offers an accelerated page mode cycle by eliminating output disable from cas\ high. this option is called edo, and it allows cas\ precharge time (t cp ) to occur without the output data going invalid (see read and edo-page-mode read waveforms). edo operates like any dram read or fast-page- mode read, except data is held valid after cas\ goes high, as long as ras\ and oe\ are held low and we\ is held high. oe\ can be brought low or high while cas\ and ras\ are low, and the dqs will transition between valid data and high- z. using oe\, there are two methods to disable the outputs and figure 2: word and byte read example
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 as4lc4m16 rev. 1.0 7/02 figure 3: oe\ control of dqs figure 4: we\ control of dqs
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 as4lc4m16 rev. 1.0 7/02 edo page mode (continued) two methods to disable the outputs and keep them disabled during the cas\ high time. the first method is to have oe\ high when cas\ transitions high and keep oe\ high for toehc thereafter. this will disable the dqs, and they will remain disabled (regardless of the state of oe\ after that point) until cas\ falls again. the second method is to have oe\ low when cas\ transitions high and then bring oe\ high for a minimum of t oep anytime during the cas\ high period. this will disable the dqs, and they will remain disabled (regardless of the state of oe\ after that point) until cas\ falls again (see figure 3). during other cycles, the outputs are disabled at t off time after ras\ and cas\ are high or at t whz after we\ transitions low. the t off time is referenced from the rising edge of ras\ or cas\, whichever occurs last. we\ can also perform the function of disabling the output drivers under certain conditions, as shown in figure 4. edo-page-mode operations are always initiated with a row address strobed in by the ras\ signal, followed by a column address strobed in by cas\, just like for single location accesses. however, subsequent column locations within the row may then be accessed at the page mode cycle time. this is accomplished by cycling cas\ while holding ras\ low and entering new column addresses with each cas\ cycle. returning ras\ high terminates the edo-page-mode operation. dram refresh the supply voltage must be maintained at the specified levels, and the refresh requirements must be met in order to retain stored data in the dram. the refresh requirements are met by refreshing all rows in the 4 meg x 16 dram array at least once every 64ms* (4,096 rows). the recommended procedure is to execute 4,096 cbr refresh cycles, either uniformly spaced or grouped in bursts, every 64ms*. the dram refreshes one row for every cbr cycle. for this device, executing 4,096 cbr cycles will refresh the entire device. the cbr refresh will invoke the internal refresh counter for auto- matic ras\ addressing. alternatively, ras\-only re- fresh capability is inherently provided. however, with this method, only one row is refreshed on each cycle. jedec strongly recommends the use of cbr refresh for this device. an optional self refresh mode is also available on the ?s? version. the self refresh feature is initiated by performing a cbr refresh cycle and holding ras\ low for the specified t rass . the ?s? option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 128ms, or 31.25s per cycle, when using a distributed cbr refresh. this refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. the self refresh mode is terminated by driving ras\ high for a minimum time of t rps . this delay allows for the completion of any internal refresh cycles that may be in process at the time of the ras\ low-to-high transition. if the dram controller uses a distributed cbr refresh sequence, a burst refresh is not required upon exiting self refresh, however, if the controller is using ras\ only or burst cbr refresh then a burst refresh using t rc (min) is required. notes: *64ms for it version, 32ms for xt version.
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 as4lc4m16 rev. 1.0 7/02 *stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. absolute maximum ratings* voltage on v cc relative to v ss .......................................-1v to +4.6v voltage on nc, inputs or i/o pins relative to v ss ...................................................-1v to +4.6v power dissipation...........................................................................1w operating temperature range, t a (ambient)..............-55c to 125c storage temperature (plastic)......................................-55c to 150c dc electrical characteristics and operating conditions 1 (v cc = +3.3v 0.3v) parameters sym min max units notes supply voltage v cc 3 3.6 v input high voltage: valid logic 1; all inputs, i/os and any nc v ih 2v cc + 0.3 v 35 input low voltage: valid logic 0; all inputs, i/os and any nc v il -0.3 0.8 v 35 input leakage current: any input at v in (0v < v in < v cc +0.3v); all other pins not under test = 0v i i -2 2 a 36 output leakage current: any input at v out (0v < v out < v cc +0.3v); dq is disabled and in high-z state i oz -5 5 a output high voltage: i out = -2ma v oh 2.4 --- v output low voltage: i out = 2ma v ol --- 0.4 v
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 as4lc4m16 rev. 1.0 7/02 i cc operating conditions and maximum limits 1,2,3,5,6 (v cc = +3.3v 0.3v) -5 -6 parameters sym max max units notes standby current: ttl ras\ = cas\ = v ih i cc1 1.5 1.5 ma standby current: cmos (ras\ = cas\ > v cc - 0.2v; dqs may be left open; other inputs: v in > v cc - 0.2v or v in < 0.2v) i cc2 11ma operating current: random read/write average power supply current (ras\, cas\, address cycling: t rc = t rc [min]) i cc3 165 150 ma 26 operating current: edo page mode average power supply current (ras\ = v il , cas\, address cycling: t pc = t pc [min]) i cc4 125 120 ma 26 refresh current: ras\-only avera g e power supply current (ras\ cycling, cas\ = v ih : t rc = t rc [min]) i cc5 165 150 ma 22 refresh current: cbr average power supply current (ras\, cas\, address cycling: t rc = t rc [min]) i cc6 165 150 ma 4, 7, 23 refresh current: extended ("s" version only) avera g e power supply current: cas\ = 0.2v or cbr cyclin g ; ras\ = t ras (min); we\ = v cc - 0.2v; a0 - a10, oe\ and d in = v cc - 0.2v or 0.2v (d in may be left open); t rc = 125s i cc7 11ma 4, 7, 23, 37 refresh current: self ("s" version only) average power supply current: cbr with ras\ > t rass (min) and cas\ held low; we\ = v cc - 0.2v; a0 - a10, oe\ and d in = v cc - 0.2v or 0.2v (d in may be left open) i cc8 1 1 ma 4, 7, 37
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 as4lc4m16 rev. 1.0 7/02 capacitance 2 parameter sym max unit input capacitance: address pins c i1 5pf input capacitance: ras\, cas\, we\, oe\ c i2 7pf input/output capacitance: dq c i0 7pf ac electrical characteristics 5,6,7,8,9,10,11,12 (v cc = +3.3v 0.3v) symbol min max min max units notes access time from column address t aa 25 30 ns column-address setup to cas\ precharge t ach 12 15 ns column-address hold time (referenced to ras\) t ar 38 45 ns column-address setup time t asc 00ns28 row-address setup time t asr 00ns28 column address to we\ delay time t awd 42 49 ns 18 access time from cas\ t cac 13 15 ns 29 column-address hold time t cah 810ns28 cas\ pulse width t cas 8 10,000 10 10,000 ns 30, 32 cas\ low to "don't care" during self refresh t chd 15 15 ns cas\ hold time (cbr refresh) t chr 810ns4, 31 last cas\ going low to first cas\ to return high t clch 55ns31 cas\ to output in low-z t clz 00ns29 data output hold after cas\ low t coh 33ns cas\ precharge time t cp 8 10 ns 13, 33 access time from cas\ precharge t cpa 28 35 ns 29 cas\ to ras\ precharge time t crp 55ns31 cas\ hold time t csh 38 45 ns 31 cas\ setup time (cbr refresh) t csr 5 5 ns 4, 28 cas\ to we\ delay time t cwd 28 35 ns 18, 28 write command to cas\ lead time t cwl 810ns31 data-in hold time t dh 8 10 ns 19, 29 data-in setup time t ds 0 0 ns 19, 29 output disable t od 0 12 0 15 ns 24, 25 output enable time t oe 12 15 ns 20 oe\ hold time from we\ durin g read-modify-write cycle t oeh 810ns25 oe\ high hold time from cas\ high t oehc 510ns oe\ high pulse width t oep 55ns oe\ low to cas\ high setup time. t oes 45ns output buffer turn-off delay t off 0 12 0 15 ns 17, 24, 29 oe\ setup prior to ras\ during hidden refresh cycle t ord 00ns description -6 -5
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 as4lc4m16 rev. 1.0 7/02 ac electrical characteristics (continued) 5,6,7,8,9,10,11,12 (v cc = +3.3v 0.3v) symbol min max min max units notes edo-page-mode read or write cycle time t pc 20 25 ns 34 edo-page-mode read-write cycle time t prwc 47 56 ns 34 access time from ras\ t rac 50 60 ns ras\ to column-address delay time t rad 912ns15 row address hold time t rah 710ns ras\ pulse width t ras 50 10,000 60 10,000 ns ras\ pulse width (edo page mode) t rasp 50 125,000* 60 125,000* ns ras\ pulse width during self refresh t rass 80 80 s random read or write cycle time t rc 84 104 ns ras\ to cas\ delay time t rcd 11 14 ns 14, 28 read command hold time (referenced to cas\) t rch 0 0 ns 16, 30 read command setup time t rcs 00ns28 refresh period t ref 64/24** 64/24** ms 22, 23 refresh period ("s" version) t ref 100 100 ms 23, 38 ras\ precharge time t rp 30 40 ns ras\ to cas\ precharge time t rpc 55ns ras\ precharge time exiting self refresh t rps 90 105 ns read command hold time (referenced to ras\) t rrh 00ns16 ras\ hold time t rsh 13 15 ns 35 read-write cycle time t rwc 116 140 ns ras\ to we\ delay time t rwd 67 79 ns 18 write command to ras\ lead time t rwl 13 15 ns transitioin time (rise or fall) t t 225225ns write command hold time t wch 810ns35 write command hold time (referenced to ras\) t wcr 38 45 ns we\ command setup time t wcs 0 0 ns 18, 28 we\ to outputs in high-z t whz 12 15 ns write command pulse width t wp 55ns we\ pulse widths to disable outputs t wpz 10 10 ns we\ hold time (cbr refresh) t wrh 810ns we\ setup time (cbr refresh) t wrp 810ns description -6 -5 notes: *for xt temp (-55c to +125c) trasp (max) = 80,000ns for -5 and -6 speed. **64ms refresh for it temp, 24ms refresh for xt temp.
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 11 as4lc4m16 rev. 1.0 7/02 notes: 1. all voltages referenced to v ss . 2. this parameter is sampled. v cc = +3.3v; f = 1 mhz; t a = 25c. 3. i cc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. an initial pause of 100s is required after power-up, followed by eight ras\ refresh cycles (ras\-only or cbr with we\ high), before proper device operation is ensured. the eight ras\ cycle wake-ups should be repeated any time the t ref refresh requirements is exceeded. 7. ac characteristics assume t t = 2.5ns. 8. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih and v il (or between v il and v ih ). 9. in addition to meeting the transition rate specification, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 10. if cas\ and ras\ = v ih , data output is high-z. 11. if cas\ = v il , data output may contain data from the last valid read cycle. 12. measured with a load equivalent to two ttl gates and 100pf; and v ol = 0.8v and v oh = 2v. 13. if cas\ is low at the falling edge of ras\, output data will be maintained from the previous cycle. to initiate a new cycle and clear the data-out buffer, cas\ must be pulsed high for t cp . 14. the t rcd (max) limit is no longer specified. t rcd (max) was specified as a reference point only. if t rcd was greater than the specified t rcd (max) limit, then access time was controlled exclusively by t cac (t rac [min] no longer applied). with our without the t rcd limit, t aa and t cac must always be met. 15. the t rad (max) limit is no longer specified. t rad (max) was specified as a reference point only. if t rad was greater than the specified t rad (max) limit, then access time was controlled exclusively by t aa (t rac and t cac no longer applied). with or without the t rad (max) limit, t aa , t rac , and t cac must always be met. 16. either t rch or t rrh must be satisfied for a read cycle. 17. t off (max) defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . 18. t wcs , t rwd , t awd , and t cwd are not restrictive operating parameters. t wcs applies to early write cycles. if t wcs > t wcs (min), the cycle is an early write cycle and the data output will remain an open circuit throughout the entire cycle. t rwd , t awd , and t cwd define read-modify-write cycles. meeting these limits allows for reading and disabling output data and then applying input data. oe\ held high and we\ taken low after cas\ goes low results in a late write (oe\-controlled) cycle. t wcs , t rwd , t cwd , and t awd are not applicable in a late write cycle. 19. these parameters are referenced to cas\ leading edge in early write cycles and we\ leading edge in late write or read-modify-write operations are not possible. 20. if oe\ is tied permanently low, late write, or read- modify-write operations are not possible. 21. a hidden refresh may also be performed after a write cycle. in this case, we\ is low and oe\ is high. 22. ras\-only refresh that all 4,096 rows of the device be refreshed at least once every 64ms. 23. cbr refresh for the device requires that at least 4,096 cycles be completed every 64ms. 24. the dqs go high-z during read cycles once t od or toff occur. if cas\ stays low while oe\ is brought high, the dqs will go high-z. if oe\ is brought back low (cas\ still low), the dqs will provide the previous read data. 25. late write and read-modify-write cycles must have both t od and t oeh met (oe\ high during write cycle) in order to ensure that the output buffers will be open during the write cycle. if oe\ is taken back low while cas\ remains low, the dqs will remain open. 26. column address changed once each cycle. 27. the first cas\ edge to transition low. 28. output parameter (dqx) is referenced to corresponding cas\ input; dq0 - dq7 by casl\ and dq8 - dq15 by cash\. 29. each casx\ must meet minimum pulse width. 30. the last casx\ edge to transition high. 31. last falling casx\ edge to first rising casx\ edge. 32. last rising casx\ edge to first falling casx\ edge. 33. last rising casx\ edge to next cycles last rising casx\ edge. 34. last casx\ to go low. notes continued on next page. *64ms for it version, 32ms for xt version.
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 12 as4lc4m16 rev. 1.0 7/02 notes (continued): 35. v ih overshoot: v ih (max) - v cc + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 3ns, and the pulse width cannot be greater then one third of the cycle rate. 36. nc pins are assumed to be left floating and are not tested for leakage. 37. self refresh and extended refresh for the device requires that at least 4,096 cycles be completed every 128ms. 38. self refresh version on it temp parts only.
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 13 as4lc4m16 rev. 1.0 7/02 read cycle notes: 1. t off is referenced from rising edge of ras\ or cas\, whichever occurs last.
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 14 as4lc4m16 rev. 1.0 7/02 early write cycle
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 15 as4lc4m16 rev. 1.0 7/02 read-write cycle (late write and read-modify-write cycles)
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 16 as4lc4m16 rev. 1.0 7/02 edo-page-mode read cycle notes: * t rasp (max) = 80,000ns for xt temperature version.
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 17 as4lc4m16 rev. 1.0 7/02 edo-page-mode early write cycle notes: * t rasp (max) = 80,000ns for xt temperature version.
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 18 as4lc4m16 rev. 1.0 7/02 edo-page-mode read-write cycle (late write and read-modify-write cycles) notes: * t rasp (max) = 80,000ns for xt temperature version.
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 19 as4lc4m16 rev. 1.0 7/02 edo-page-mode read early write cycle (pseudo read-modify-write) notes: * t rasp (max) = 80,000ns for xt temperature version.
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 20 as4lc4m16 rev. 1.0 7/02 read cycle (with we\-controlled disable)
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 21 as4lc4m16 rev. 1.0 7/02 ras\-only refresh cycle (oe\ and we\ = don?t care) cbr refresh cycle (addresses and oe\ = don?t care) notes: 1. end of first cbr refresh cycle.
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 22 as4lc4m16 rev. 1.0 7/02 hidden refresh cycle 1 (we\ = high; oe\ = low) notes: 1. a hidden refresh may also be performed after a write cycle. in this case, we\ is low and oe\ is high.
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 23 as4lc4m16 rev. 1.0 7/02 self refresh cycle (addresses and oe\ = don?t care) notes: 1. once t rass (min) is met and ras\ remains low, the dram will enter self refresh mode. 2. once t rps is satisfied, a complete burst of all rows should be executed if ras\-only or burst cbr refresh is used.
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 24 as4lc4m16 rev. 1.0 7/02 mechanical definitions (package designator dg)
dram dram dram dram dram as4lc4m16 austin semiconductor, inc. austin semiconductor, inc. reserves the right to change products or specifications without notice. 25 as4lc4m16 rev. 1.0 7/02 *available processes xt = industrial temperature range -55 o c to +125 o c it = industrial temperature range -40 o c to +85 o c option definitions s = self refresh ordering information device number package t yp e speed ns options process as4lc4m16 dg -5 s /* as4lc4m16 dg -6 s /* example: as4lc4m16dg-6s/xt

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