hanbit h sd2m64b2 url:www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) 1 general description th e hsd2m64b2 is a 2 m x 64 bit synchronous dynamic ram high density memory module. the module consists of two cmos 512k x 32 bit with 4banks synchronous drams in tsop - ii 400mil package s on a 144 - pin glass - epoxy substrate. two 0 . 1 uf decoupling capacitors are mounted on the printed circuit board in parallel for each sdram. the hsd2m64b2 is a so - dimm(small outline dual in line memory module) and is intended for mounting into 144 - pin edge connector sockets. synchronous design allows precise cycle control with the use of system clock. i/o transactions are possible on every clock cycle. range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory sys tem applications a ll module components may be powered from a single 3.3 v dc power supply and all inputs and outputs are lv ttl - compatible. features ? p art identification hsd2m64b2 - f/10 :100 mhz hsd2m64b2 - f/8 : 1 25 mhz * f : auto self - refresh with low power ? burst mode operation ? auto & self refresh capability ( 4096 cycles/64ms) ? lvttl compatible inputs and outputs ? single 3.3v 0.3v power supply ? mrs cycle with address key programs - latency (access from column address) - burst length (1, 2, 4, 8 & full page) - data scramble (sequential & interleave) ? jedec standard 144 - pin so - dimm ? all inputs are sampled at the positive going edge of the system clock ? the used device is 512kx32bitx4banks sdram synchronous dram module 16mbyte (2mx64 - bit), so - dimm, 4banks, 4k ref., 3.3v part no . h sd2m64b2
hanbit h sd2m64b2 url:www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) 2 pin assign pin symb ol pin symbol pin symbol pin symbol pin symbol pin symbol 1 vss 2 vss 49 dq13 50 dq45 97 dq22 98 dq54 3 dq0 4 dq32 51 dq14 52 dq46 99 dq23 100 dq55 5 dq1 6 dq33 53 dq15 54 dq47 101 vdd 102 vdd 7 dq2 8 dq34 55 vss 56 vss 103 a6 104 a7 9 dq3 10 dq35 5 7 nc 58 nc 105 a8 106 ba0 11 vdd 12 vdd 59 nc 60 nc 107 vss 108 vss 13 dq4 14 dq36 61 clk0 62 cke0 109 a9 110 ba1 15 dq5 16 dq37 63 vdd 64 vdd 111 a10_ap 112 a11 17 dq6 18 dq38 65 /ras 66 /cas 113 vdd 114 vdd 19 dq7 20 dq39 67 /we 68 nc 115 dqm2 11 6 dqm6 21 vss 22 vss 69 /cs0 70 nc 117 dqm3 118 dqm7 23 dqm0 24 dqm4 71 nc 72 nc 119 vss 120 vss 25 dqm1 26 dqm5 73 du 74 clk1 121 dq24 122 dq56 27 vdd 28 vdd 75 vss 76 vss 123 dq25 124 dq57 29 a0 30 a3 77 nc 78 nc 125 dq26 126 dq58 31 a1 32 a4 79 nc 80 nc 127 dq27 128 dq59 33 a2 34 a5 81 vdd 82 vdd 129 vdd 130 vdd 35 vss 36 vss 83 dq16 84 dq48 131 dq28 132 dq60 37 dq8 38 dq40 85 dq17 86 dq49 133 dq29 134 dq61 39 dq9 40 dq41 87 dq18 88 dq50 135 dq30 136 dq62 41 dq10 42 dq42 89 dq19 90 dq51 137 dq31 138 dq63 43 dq11 44 dq43 91 vss 92 vss 139 vss 140 vss 45 vdd 46 vdd 93 dq20 94 dq52 141 sda 142 scl 47 dq12 48 dq44 95 dq21 96 dq53 143 vdd 144 vdd
hanbit h sd2m64b2 url:www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) 3 functional block dia gram vcc vss two 0.1uf capacitor s pe r each s dram cke clk cas dq0 - 7,dq32 - 39 ra s dqm 0 c e w e a0 - a1 1 ba0 - 1 dqm4 u 1 /ca /cs0 /ras cke0 dqm0 clk0b clk0a cke clk cas dq 8 - 15,dq40 - 47 ras dqm 1 c e w e a0 - a1 1 ba0 - 1 dqm5 cke clk cas dq 16 - 23,dq48 - 55 ras dqm 2 c e w e a0 - a1 2 ba0 - 1 d qm6 cke clk cas dq 24 - 31,dq56 - 63 ras dqm 3 c e w e a0 - a1 1 ba0 - 1 dqm7 dqm1 dqm3 dqm2 u 2 u 4 u 3 /we a0 C a11 ba0 - 1 dq0 - 63 dqm4 dqm5 d qm6 dqm7
hanbit h sd2m64b2 url:www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) 4 pin f unction description pin name input function clk system clock active on the positive going edge to sample all inputs. / c e chip e nable disables or enables device operation by masking or enabling all inputs except clk, cke and dqm cke clock enable masks s ystem clock to freeze operation from the next clock cycle. cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. cke should be enabled 1clk+ tss prior to valid command. a0 ~ a1 1 address row/column a ddresses are multiplexed on the same pins. row address : ra0 ~ ra1 1 , column address : ca0 ~ ca 8 ba0 ~ ba1 bank select address selects bank to be activated during row address latch time. selects bank for read/write during column address latch time. / ras r ow address strobe latches row addresses on the positive going edge of the clk with ras low. enables row access & precharge. / cas column address strobe latches column addresses on the positive going edge of the clk with cas low. enables column access. / we write enable enables write operation and row precharge. latches data in starting from cas, we active. dqm0 ~ 7 data input/output mask makes data output hi - z, tshz after the clock and masks the output. blocks data input when dqm active. (byte masking) dq 0 ~ 63 data input/output data inputs/outputs are multiplexed on the same pins. vd d/ vss power supply/ground power and ground for the input buffers and the core logic. absolute maximum rat ings parameter symbol rating voltage on any pin relative to v ss v in ,out - 1v to 4.6 v voltage on vcc supply relative to vss vcc - 1v to 4.6 v power dissipation p d 2 w storage temperature t stg - 55 o c to 150 o c short circuit output current i os 100ma notes: permanent device damage may occur if " absolute maximum rating s" are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
hanbit h sd2m64b2 url:www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) 5 dc operating con d itions ( recommended operating conditions (voltage referenced to vss = 0v, ta = 0 to 70 c) ) parameter symbol min typ . max unit note supply voltage vcc 3.0 3 . 3 3 . 6 v input high voltage v ih 2. 0 3.0 vcc+ 0.3 v 1 input low voltage v il - 0 . 3 0 0.8 v 2 out p ut high voltage v oh 2.4 - - v i oh = - 2ma out put low voltage v o l - - 0. 4 v i ol = 2ma input leakage current i l i - 1 0 - 1 0 ua 3 notes: 1. v ih (max) = 5.6v ac. the overshoot voltage duration is 3ns. 2. v il (min) = - 2.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v v in v dd q . input leakage currents include hi - z output leakage for all bi - directional buffers with tri - state outputs. capacitance ( v cc = 3.3v, ta = 23 c, f = 1mhz, vref =1.4v 200 mv) description symbol min max units clock c clk 2.5 4.0 pf / ras, / cas ,/we,/cs, cke, dqm c in 2.5 4.5 pf address c add 2.5 4.5 pf dq (dq0 ~ dq31) c out 4.0 6.5 pf d c characteristics (recommended operating condition unless otherwise noted, ta = 0 to 70 c) version parameter symbol test condition - 8 - 10 unit note operating current (one bank active) i cc1 burst length = 1 t rc 3 t r c (min) i o = 0ma 130 115 ma 2 i cc 2 p cke v i l (max) t cc =10ns 2 ma precharge standby current in power - down mode i cc 2 ps cke & clk v i l (max) t cc = 2 ma precharg e standby current in non power - down mode i cc 2 n cke 3 v i h (min) cs * 3 v i h (min), t cc =10ns input signals are changed one time during 20ns 20 ma
hanbit h sd2m64b2 url:www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) 6 i cc 2 ns cke 3 v i h (min) clk v i l (max), t cc = input signals are stable 10 i cc 3 p cke v i l (max), t cc =10ns 3 active standby current in power - do wn mode i cc 3 ps cke&clk v i l (max) t cc = 3 ma i cc 3 n cke 3 v i h (min), cs * 3 v i h (min), t cc =10ns input signals are changed one time during 20ns 30 active standby current in non power - down mode (one bank active) i cc 3 ns cke 3 vi h(min) clk vi l(max), t cc = input signals are stable 20 ma operating current (burst mode) i cc4 i o = 0 ma page burst 4banks activated t ccd = 2clks 150 130 ma 2 refresh current i cc5 t rc 3 t r c (min) 160 150 ma 3 2 ma self refresh current i cc6 cke 0.2 v 450 ma 5 notes : 1. measured with outputs open. 2. refresh period is 64ms. 3 . unless otherwise noticed, input swing level is cmos( v i h / v i l = v dd q / v ss q ). ac operating test conditions (vcc = 3.3v 0.3v, ta = 0 to 70 c) parameter value unit ac in put levels (vih/vil) 2.4/0.4 v input timing measurement reference level 1.4 v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 1.4 v output load condition see fig. 2
hanbit h sd2m64b2 url:www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) 7 operating ac parameter ( ac operating conditions unless otherwise noted) version parameter symbol - 8 - 10 unit note row active to row active delay t rr d (min) 2 2 ns 1 ras to cas delay t r p (min) 3 2 ns 1 row precharge time t r p (min) 3 2 ns 1 t ra s (min) 6 5 ns 1 row active time t ra s (max) 100 ns row cycle time tr c (min) 9 7 ns 1 last data in to row precharge t rd l (min) 2 clk 2.5 last data in to new col. address delay t cd l (min) 1 clk 2 last data in to burst stop t bd l (min) 1 clk 2 col. address to col. address delay t cc d (min) 1 clk 3 cas latency=3 2 number of valid output data cas latency=2 1 ea 4 notes : 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interrupt, auto precharge and read burst stop. . + 3.3 v 1200 w 870 w 5 0 pf* d out v tt = 1.4 v 5 0 w 50pf d out z0=50 w v oh (dc) = 2.4v, i oh = - 2ma v ol (dc) = 0.4v, i ol = 2ma (fig. 1) dc output load circuit (fig. 2) ac output load circuit
hanbit h sd2m64b2 url:www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) 8 a c c haracteristics (ac oper ating conditions unless otherwise noted ) - 8 - 10 parameter symbol min max min max min max min max unit note cas latency=3 8 10 clk cycle time cas latency=2 t cc 10 1000 12 1000 ns 1 cas latency=3 6 6 clk to valid output delay cas latency=2 t sac 6 8 ns 1,2 output data hold time t oh 2.5 2.5 ns 2 clk high pulse width t ch 3 3.5 ns 3 clk low pulse width t cl 3 3.5 ns 3 input setup time t ss 2 2.5 ns 3 input hold time t sh 1 1 ns 3 clk to ou tput in low - z t slz 1 1 ns 3 cas latency=3 6 6 ns 2 clk to output in hi - z cas latency=2 t shz - 6 8 ns notes : 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2 - 0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, transient time compensation should be considered, i e., [(tr + tf)/2 - 1]ns should be added to the parameter.
hanbit h sd2m64b2 url:www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) 9 simplified truth tab le command cke n - 1 cke n /c s /r a s /c a s /w e d q m ba 0,1 a10/ ap a9~a0 note register mode register set h x l l l l x op code 1,2 auto refresh h 3 entry h l l l l h x x 3 l h h h 3 refresh self refres h exit l h h x x x x x 3 bank active & row ad dr. h x l l h h x v row address auto precharge disable l 4 read & column address auto precharge disable h x l h l h x v h column address ( a0 ~ a 9) 4,5 auto precharge disable l column address ( a0 ~ a 9) 4 write & column address auto precharge disable h x l h l l x v h 4,5 burst stop h x l l h l x x 6 bank selection v l precharg e all banks h x l l h l x x h x h x x x entry h l l v v v x clock suspend or active power down exit l h x x x x x x h x x x entry h l l h h h x h x x x precharge power down mode exit l h l v v v x x dqm h x v x 7 h x x x no operation command h x l h h h x x (v=valid, x=don't care, h=logic high, l=log ic low) notes : 1. op code : operand code a0 ~ a1 1 & b a0 ~ b a1 : program keys. (@ mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are as same as cbr refresh of dr am. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. b a0 ~ b a1 : bank select addresses. if both b a0 and b a1 are "low" at read, write, row active and precharge, bank a is selected. if both b a0 is "low" and b a1 is "high" at read, write, row active and precharge, bank b is selected. if both b a0 is "high" and b a1 is "low" at read, write, row active and precharge, bank c is selected. if both b a0 and b a1 are "high" at read, write, row active and precharge, bank d is selected. if a1 0/ap is "high" at row precharge, b a0 and b a1 is ignored and all banks are selected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank r ead/write command can be issued after the end of burst. new row active of the associated bank can be issued at trp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at positive going edge of a clk and masks the da ta - in at the very clk (write dqm latency is 0), but makes hi - z state the data - out of 2 clk cycles after. (read dqm latency is 2 )
hanbit h sd2m64b2 url:www.hbe.co.kr hanbit electronics co.,ltd. rev.1.0 ( august.2002 ) 10 timing diagrams please refer to attached timing diagram chart (ii) p ackaging information unit : mm o r dering inf ormation part number density org. package ref. vcc feature max.frq hmd2m64b2 - 10 16mbyte 2mx 64 144 pin so - dimm 4k 3.3v 100mhz hmd2m64b2 - f10 16mbyte 2mx 64 144 pin so - dimm 4k 3.3v low power 100mhz hmd2m64b2 - 8 16mbyte 2mx 64 144 pin so - dimm 4k 3.3v 125 mhz hmd2m64b2 - f8 16mbyte 2mx 64 144 pin so - dimm 4k 3.3v low power 125mhz * f : auto self - refresh with low power 1. 0 + 0.1 mm 0 .25 mm max min 2.54 mm 1.27 mm (solder & gold plating) gold: 1.04 0. 10 mm solder: 0.914 0. 10 mm
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