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1 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram 9mb qdr? sram 2-word burst features ? 9mb density (512k x 18) ? separate independent read and write data ports with concurrent transactions ? 100% bus utilization ddr read and write operation ? high frequency operation with future migration to higher clock frequencies ? fast clock to valid data times ? full data coherency, providing most current data ? two-tick burst counter for low ddr transaction size ? double data rate operation on read and write ports ? two input clocks (k and k#) for precise ddr timing at clock rising edges only ? two output clocks (c and c#) for precise flight time and clock skew matchingclock and data delivered together to receiving device ? single address bus ? simple control logic for easy depth expansion ? internally self-timed, registered writes ? +2.5v core and hstl i/o ? clock-stop capability ? 13x15mm, 1mm pitch, 11 x 15 grid fbga package ? user programmable impedence output ? jtag boundary scan options marking ? clock cycle timing 6ns (167 mhz) -6 7.5ns (133 mhz) -7.5 10ns (100 mhz) -10 ? configuration 512k x 18 MT54V512H18A ? package 165-pin, 13mm x 15mm fbga f 165-pin fbga MT54V512H18A general description the micron ? qdr? (quad data rate?) synchro- nous pipelined burst sram employs high-speed, low- power cmos designs using an advanced 6t cmos process. the qdr architecture consists of two separate ddr (double data rate) ports to access the memory array. the read port has dedicated data outputs to support read operations. the write port has dedicated data inputs to support write operations. this architec- ture eliminates the need for high-speed bus turnaround. access to each port is accomplished using a common address bus. addresses for reads and writes are latched on rising edges of the k and k# input clocks, respec- tively. each address location is associated with two 18- bit words that burst sequentially into or out of the device. since data can be transferred into and out of the device on every rising edge of both clocks (k, k#, c and c#) memory bandwidth is maximized while sim- plifying system design by eliminating bus turnarounds. depth expansion is accomplished with port selects for each port (read r#, write w#) which are received at k rising edge. port selects permit independent port operation. all synchronous inputs pass through regis- ters controlled by the k or k# input clock rising edges. active low byte writes (bw0#, bw1#) permit byte write selection. write data and byte writes are regis- tered on the rising edges of both k and k#. the addressing within each burst of two is fixed and sequential, beginning with the lowest and ending with valid part numbers part number description MT54V512H18Af-xx 512k x 18, qdrb2 fbga
2 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram note: 1. the functional block diagram illustrates simplified device operation. see truth table, pin descriptions and timing diagrams for detailed information. 2. n = 18 the highest address. all synchronous data outputs pass through output registers controlled by the rising edges of the output clocks (c and c# if provided, otherwise k and k#). four pins are used to implement jtag test capabili- ties: test mode select (tms), test data-in (tdi), test clock (tck) and test data-out (tdo). jtag circuitry is used to serially shift data to and from the sram. jtag inputs use jedec-standard 2.5v i/o levels to shift data during this testing mode of operation. the sram operates from a +2.5v power supply, and all inputs and outputs are hstl-compatible. the device is ideally suited for applications that benefit from a high-speed fully-utilized ddr data bus. please refer to microns web site (www.micron.com/ mti/msp/html/sramprod.html) for the latest data sheet. read/write operations all bus transactions operate on an uninterruptable burst of two data, requiring one full clock cycle of bus utilization.the resulting benefit is that short data trans- actions can remain in operation on both buses pro- vided that the address rate can be maintained by the system (2x the clock frequency). read cycles are pipelined. the request is initiated by asserting r# low at k rising edge. data is delivered after the next rising edge of k using c and c# as the output timing references, or using k and k# if c and c# general description (continued) are tied high. if c and c# are tied high, they may not be toggled during device operation. output tri-stating is automatically controlled such that the bus is released if no data is being delivered. this permits banked sram systems with no complex oe timing generation. back- to-back read cycles are initiated every k rising edge. write cycles are initiated by w# low at k rising edge. the address for the write cycle is provided at the following k# rising edge. data is expected at the rising edge of k and k# beginning at the same k which initiated the cycle. write registers are incorporated to facilitate pipelined self-timed write cycles and pro- vide fully coherent data for all combinations of reads and writes. a read can immediately follow a write even if they are to the same address. although the write data has not been written to the memory array, the sram will deliver the data from the write register instead of using the older data from the memory array. the latest data is always utilized for all bus transactions. write cycles can be initiated on every k rising edge. byte write operations byte write operations are supported. the active low byte write controls, bw0# and bw1#, are regis- tered coincident with their corresponding data. this feature can eliminate the need for some read/ modify/write cycles, collapsing it to a single byte write operation in some instances. functional block diagram 512k x 18 address d (data in) n n r# w# k k# 18 36 36 36 k# k r# w# bw0# bw1# k n 2 x 36 memory array c address registry & logic data registry & logic c,c# 18 q (data out) r e g w r i t e mux d r i v e r w r i t e o u t p u t o u t p u t r e g b u f f e r a m p s s e n s e o u t p u t s e l e c t
3 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram programmable impedance output buffer the qdr sram is equipped with programmable impedance output buffers. this allows a user to match the driver impedance to the system. to adjust the impedance, an external precision resistor (rq) is con- nected between the zq pin and v ss . the value of the resistor must be five times the desired impedance. for example, a 350 w resistor is required for an output impedance of 70 w . to ensure that output impedance is one fifth the value of rq (within 10 percent), the range of rq is 175 w to 350 w . alternately, the zq pin can be connected directly to v dd , which will place the device in a minimum impedance mode. output impedance updates may be required because variations may occur in supply voltage and tempera- ture over time. the device samples the value of rq. an update of the impedance is transparent to the system. impedance updates do not affect device operation, and all data sheet timing and current specifications are met during an update. the device will power up with an output impedance set at 50 w . to guarantee optimum output driver imped- ance after power-up, the sram needs 1,024 cycles to update the impedance. the user can operate the part with fewer than 1,024 clock cycles, but optimal output impedance is not guaranteed. vt vt = v ref vt cc# zq q0-17 k# d0-17 sa k cc# zq q0-17 k# d0-17 sa k bus master (cpu or asic) sram #1 sram #4 data in 0-71 data out 0-71 address 0-17 read# write# bw0-7# return clk source clk return clk# source clk# r=50 w r=250 w r=250 w r # w # b w 0 # b w 1 # r # w # b w 0 # b w 1 # vt vt vt r r application example clock considerations the device does not utilize internal phase-locked loops and can therefore be placed into a stopped-clock state to minimize power without lengthy restart times. it is strongly recommended that the clocks operate for a number of cycles prior to initiating commands to the sram. this delay permits transmission line charging effects to be overcome and allows the clock timing to be nearer to its steady-state value. single clock mode the sram can be used with the single k, k# clock pair by tying c and c# high. in this mode the sram will use k and k# in place of c and c#. this mode provides the most rapid data output but does not compensate for system clock skew and flight times. depth expansion port select inputs are provided for the read and write ports. this allows for easy depth expansion. both port selects are sampled on the rising edge of k only. each port can be independently selected and deselected and do not affect the operation of the opposite port. all pending transactions are completed prior to a port deselecting.
4 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram 1234567891011 a dnu v ss / sa * nc/ sa * w# bw1# k# nc r# nc/ sa *v ss / sa * dnu b nc q9 d9 sa nc k bw0# sa nc nc q8 c nc nc d10 v ss sa sa sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v dd qv ss v ss v ss v dd qnc d6 q6 f nc q12 d12 v dd qv dd v ss v dd v dd qnc nc q5 g nc d13 q13 v dd qv dd v ss v dd v dd qnc nc d5 h nc v ref v dd qv dd qv dd v ss v dd v dd qv dd qv ref zq j nc nc d14 v dd qv dd v ss v dd v dd qnc q4 d4 k nc nc q14 v dd qv dd v ss v dd v dd qnc d3 q3 l nc q15 d15 v dd qv ss v ss v ss v dd qnc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa c sa sa nc d0 q0 r tdo tck sa sa sa c# sa sa sa tms tdi pin assignment (top view) 165-pin fbga *expansion addresses: 9a for 18mb, 3a for 36mb, 10a for 72mb, 2a for 144mb
5 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram pin descriptions pins (x18) symbol type description 6c sa input synchronous address inputs: these inputs are registered and must meet 7c the setup and hold times around the rising edge of k for read cycles and 4b, 8b, must meet the setup and hold times around the rising edge of k# for 5c, 5n-7n, write cycles. pins 9a, 3a, 10a, and 2a are reserved for the next higher 4p, 5p, 7p, -order address inputs on 18, 36, 72, and 144mb devices, respectively. all 8p, 3r-5r, transactions operate on a burst of two 18-bit data (one clock period of 7r-9r bus activity). these inputs are ignored when both ports are deselected. 8a r# input synchronous read: when low this input causes the address inputs to be registered and a read cycle to be initiated. this input must meet setup and hold times around the rising edge of k. 4a w# input synchronous write: when low this input causes the address inputs to be registered and a write cycle to be initiated. this input must meet setup and hold times around the rising edge of k. 7b bw0# input synchronous byte writes: when low these inputs cause their respective 5a bw1# byte to be registered and written if w# had initiated a write cycle. bw0# and bw1# must meet setup and hold times around the rising edges of k and k# for each of the two rising edges comprising the write cycle. bw0# controls d0-d8. bw1# controls d9-d17. 6b k input input clock: this input clock pair registers address and 6a k# control inputs on the rising edge of k, and registers data on the rising edge of k and the rising edge of k#. k# is ideally 180 degrees out of phase with k. all synchronous inputs must meet setup and hold times around the clock rising edges. 6p c input output clock: this clock pair provides a user controlled means of 6r c# tuning device output data. the rising edge of c is used as the output timing reference for first output data. the rising edge of c# is used as the output reference for second output data. ideally, c# is 180 degrees out of phase with c. c and c# may be tied high to force the use of k and k# as the output reference clocks instead of having to provide c and c# clocks. if tied high, these inputs may not be allowed to toggle during device operation. 10r tms input ieee 1149.1 test inputs: jedec-standard 2.5v i/o levels. these pins may be 11r tdi left not connected if the jtag function is not used in the circuit. 2r tck input ieee 1149.1 clock input: jedec-standard 2.5v i/o levels. this pin must be tied to v ss if the jtag function is not used in the circuit. 2h, 10h v ref input hstl input reference voltage: nominally v dd q/2 but may be adjusted to improve system noise margin. provides a reference voltage for the hstl input buffer trip point. 11h zq input output impedance matching input: this input is used to tune the device outputs to the system data bus impedance. dq output impedance is set to 0.2 x rq, where rq is a resistor from this pin to ground. alternately, this pin can be connected directly to v dd , which enables the minimum impedance mode. this pin cannot be connected directly to gnd or left unconnected.
6 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram 10p d0 input synchronous data inputs: input data must meet setup and hold times 11n d1 around the rising edges of k and k# during write operations. 11m d2 10k d3 11j d4 11g d5 10e d6 11d d7 11c d8 3b d9 3c d10 2d d11 3f d12 2g d13 3j d14 3l d15 3m d16 2n d17 1a, 11a dnu output do not use. these pins should not be used. 1r tdo output ieee 1149.1 test output: jedec-standard 2.5v i/o level. 11p q0 output synchronous data outputs: output data is synchronized to the 10m q1 respective c and c# or to k and k# rising edges if c and c# are tied 11l q2 high. this bus operates in response to r# commands. 11k q3 10j q4 11f q5 11e q6 10c q7 11b q8 2b q9 3d q10 3e q11 2f q12 3g q13 3k q14 2l q15 3n q16 3p q17 5f, 7f, 5g, v dd supply power supply: 2.5v nominal. see dc electrical characteristics and 7g, 5h, 7h, operating conditions for range. 5j,7j, 5k, 7k 4e, 8e, 4f, v dd q supply power supply: isolated output buffer supply. nominally 1.5v. see dc 8f, 4g, 8g, electrical characteristics and operating conditions for range. 3h, 4h, 8h, 9h, 4j, 8j, 4k, 8k, 4l, 8l pin descriptions (continued) pins (x18) symbol type description
7 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram 2a, 10a, 4c, v ss supply power supply: gnd. 8c, 4d-8d, 5e-7e, 6f, 6g, 6h, 6j, 6k, 5l-7l, 4m-8m, 4n, 8n 3a, 7a, 9a, nc C no connect: these signals are not internally connected and may be 1b, 5b, 9b, connected to ground to improve package heat dissipation. 10b, 1c, 2c, 9c, 1d, 9d, 10d, 1e, 2e, 9e, 1f, 9f, 10f, 1g, 9g, 10g, 1h, 1j, 2j, 9j, 1k, 2k, 9k, 1l, 2k, 10l, 1m, 2m, 9m, 1n, 9n, 10n, 1p, 2p, 9p pin descriptions (continued) pins (x18) symbol type description
8 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram bus cycle state diagram load new read address read double power-up supply voltage provided read port nop r_init=0 rd rd always /rd /rd load new write address at k# - write double at k# - supply voltage provided write port nop wt wt always /wt /wt note: 1. the address is concatenated with 1 additional internal lsb to facilitate burst operation. the address order is always fixed as: xxx...xxx+0, xxx...xxx+1. bus cycle is terminated at the end of this sequence (burst count = 2). 2. state transitions: rd = (r# = low); wt = (w# = low). 3. read and write state machines can be active simultaneously. 4. state machine control timing sequence is controlled by k.
9 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram note: 1. x means dont care. h means logic high. l means logic low. - means rising edge; means falling edge. 2. data inputs are registered at k and k# rising edges. data outputs are delivered at c and c# rising edges except if c and c# are high then data outputs are delivered at k and k# rising edges. 3. r# and w# must meet setup/hold times around the rising edge (low to high) of k and are registered at the rising edge of k. 4. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 5. refer to state diagram and timing diagrams for clarification. 6. it is recommended that k = /k# = c = /c# when clock is stopped. this is not essential but permits most rapid restart by overcoming transmission line charging symmetrically. 7. assumes a write cycle was initiated. bw0# and bw1# can be altered for any portion of the burst write operation provided that the setup and hold requirements are satisfied. byte write operation 7 operation k k# bw0# bw1# write d0-17 at k rising edge l ? h00 write d0-17 at k# rising edge l ? h0 0 write d0-8 at k rising edge l ? h01 write d0-8 at k# rising edge l ? h0 1 write d9-17 at k rising edge l ? h10 write d9-17 at k# rising edge l ? h1 0 write nothing at k rising edge l ? h11 write nothing at k# rising edge l ? h1 1 truth table (notes 1-6) operation k r# w# d or q d or q write cycle: l ? hx ld a (a+0) d a (a+1) load address, input write data on at at consecutive k and k# rising edges k(t) - k#(t) - read cycle: l ? hl xq a (a+0) q a (a+1) load address, output data on at at consecutive c and c# rising edges c(t+1) - c#(t+1) - nop: no operation l ? hh hd = xd = x q = high-z q = high-z standby: clock stopped stopped x x previous previous state state
10 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram absolute maximum ratings* voltage on v dd supply relative to v ss .................................. -0.5v to +3.6v voltage on v dd q supply relative to v ss ..................................... -0.5v to v dd v in ................................................. -0.5v to v dd + 0.5v storage temperature .......................... -55c to +125c junction temperature** .................................... +125c short circuit output current ........................... 70ma *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. ** junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. see micron technical note tn-05-14 for more information. dc electrical characteristics and operating conditions (+20c t j +110c; +2.4v v dd +2.6v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage v ih v ref + 0.1 v dd q + 0.3 v 3, 4 input low (logic 0) voltage v il -0.3 v ref - 0.1 v 3, 4 clock input signal voltage v in -0.3 v dd q + 0.3 v 3, 4 input leakage current 0v v in v dd qil i -5 5 a output leakage current output(s) disabled, il o -5 5 a 0v v in v dd q (q) output high voltage |i oh | 0.1ma v oh ( low )v dd q - 0.2 v dd q v 3, 5, 7 note 1 v oh v dd q/2 - 0.08 v dd q/2 + 0.08 v 3, 5, 7 output low voltage i ol 0.1ma v ol ( low )v ss 0.2 v 3, 5, 7 note 2 v ol v dd q/2 - 0.08 v dd q/2 + 0.08 v 3, 5, 7 supply voltage v dd 2.4 2.6 v 3 isolated output buffer supply v dd q 1.4 1.6 v 3, 6 reference voltage v ref 0.68 0.9 v 3 note: 1. outputs are impedance-controlled. | i oh | = (v dd q/2)/(rq/5) for values of 175 w rq 350 w . 2. outputs are impedance-controlled. i ol = (v dd q/2)/(rq/5) for values of 175 w rq 350 w . 3. all voltages referenced to v ss (gnd). 4. overshoot: v ih (ac) v dd + 0.7v for t t khkh/2 undershoot: v il (ac) 3 -0.5v for t t khkh/2 power-up: v ih v dd q + 0.3v and v dd 2.4v and v dd q 1.4v for t 200ms during normal operation, v dd q must not exceed v dd . r# and w# signals may not have pulse widths less than t khkl (min) or operate at cycle rates less than t khkh (min). 5. ac load current is higher than the shown dc values. ac i/o curves are available upon request. 6. for higher v dd q voltages, contact factory for product information. 7. hstl outputs meet jedec hstl class i and class ii standards.
11 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram max i dd operating conditions and maximum limits (+20c t j +110c; v dd = max unless otherwise noted) description conditions symbol typ -6 -7.5 -10 units notes operating supply all inputs v il or 3 v ih ; current: ddr cycle time 3 t khkh (min); i dd tbd 500 400 300 ma 1, 2, outputs open 3 standby supply t khkh = t khkh (min); i sb 1 tbd 170 140 110 ma 2, 4 current: nop device in nop state; all addresses/data static output supply c l = 15pf i dd q 342720 ma 5 current: ddr (for information only) note: 1. i dd is specified with no output current and increases with faster cycle times. i dd q increases with faster cycle times and greater output loading. typical value is measured at 6ns cycle time. 2. typical values are measured at v dd = 2.5v, v dd q = 1.5v and temperature = 25c. 3. operating supply currents and burst mode currents are calculated with 50 percent read cycles and 50 percent write cycles. 4. nop currents are valid when entering nop after all pending read and write cycles are completed. 5. average i/o current and power is provided for information purposes only and is not tested. calculation assumes that all outputs are loaded with c l (in farads), f = input clock frequency, half of outputs toggle at each transition (n=18), v dd q=1.5v and uses the equations: average i/o power as dissipated by the sram is: p = 0.5 * n * f * c l * v dd q 2 . average i dd q = n * f * c l * v dd q. 6. this parameter is sampled. 7. average thermal resistance between the die and the case top surface per mil spec 883 method 1012.1. 8. junction temperature is a function of total device power dissipation and device mounting environment. measured per semi g38-87. thermal resistance description conditions symbol typ units notes junction to ambient (airflow of 1m/s) soldered on a 4.25 x 1.125 inch, q ja 25 c/w 6, 7 junction to case (top) 4-layer printed circuit board q jc 10 c/w 6 junction to pins (bottom) q jb 12 c/w 6, 8 capacitance description conditions symbol typ max units notes address/control input capacitance c i 45pf6 input, output capacitance (d, q) t a = 25c; f = 1 mhz c o 67pf6 clock capacitance c ck 56pf6
12 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram description note: 1. this parameter is sampled. 2. transition is measured 100mv from steady state voltage. 3. this is a synchronous device. all addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. 4. test conditions as specified with the output loading as shown in figure 1 unless otherwise noted. 5. control input signals may not be operated with pulse widths less than t khkl (min). 6. t chqx1 is greater than t chqz at any given voltage and temperature. 7. if c, c# are tied high, k, k# become the references for c, c# timing parameters. ac electrical characteristics (notes 1, 4, 5, 7); (+20c t j +110c; +2.4v v dd +2.6v) -6 -7.5 -10 symbol min max min max min max units notes clock clock cycle time (k, k#, c, c#) t khkh 6.0 7.5 10 ns clock high time (k, k#, c, c#) t khkl 2.4 3.0 3.5 ns clock low time (k, k#, c, c#) t klkh 2.4 3.0 3.5 ns clock to clock# (k - ? k# - , c - ? c# - ) t khk#h 2.7 3.3 3.4 4.1 4.6 5.4 ns clock to data clock (k - ? c - , k# - ? c# - ) t khch 0.0 2.0 0.0 2.5 0.0 3.0 ns output times c, c# high to output valid t chqv 2.5 3.0 3.0 ns c, c# high to output hold t chqx 1.2 1.2 1.2 ns c high to output high-z t chqz 2.5 3.0 3.0 ns 2,6 c high to output low-z t chqx1 1.2 1.2 1.2 ns 2,6 setup times address valid to k rising edge t avkh 0.7 0.8 1.0 ns 3 control inputs valid to k rising edge t ivkh 0.7 0.8 1.0 ns 3 data-in valid to k, k# rising edge t dvkh 0.7 0.8 1.0 ns 3 hold times k rising edge to address hold t khax 0.7 0.8 1.0 ns 3 k rising edge to control inputs hold t khix 0.7 0.8 1.0 ns 3 k, k# rising edge to data-in hold t khdx 0.7 0.8 1.0 ns 3
13 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram ac test conditions input pulse levels ................................. 0.25v to 1.25v input rise and fall times ...................................... 0.3ns input timing reference levels ............................ 0.75v output reference levels .................................. v dd q/2 zq for 50 w impedance ....................................... 250 w output load ............................................. see figure 1 50 w v dd q/2 250 w z = 50 w o zq sram 0.75v v ref figure 1 output load equivalent
14 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram read/write timing note: 1. q00 refers to output from address a0+0. q01 refers to output from the next internal burst address following a0, i.e., a0+1. 2. outputs are disabled (high-z) one clock cycle after a nop. 3. in this example, if address a0 = a1, data q00 = d10, q01 = d11. write data is forwarded immediately as read results. read read write write write nop read write nop k 12345 8 10 6 7 k# r# w# a q d c c# a1 a0 d10 t khkl t khk#h t khch t chqv t klkh t khkh tt khix t avkh t khax t dvkh t khdx t khch dont care undefined t chqx1 t chqz ivkh t khkl t klkh a2 t a3 a4 a5 a6 t avkh t khax d11 d30 d31 d50 d51 d60 d61 t dvkh t khdx q00 q21 q01 q20 q40 q41 t chqv t chqx t chqx t khk#h t khkh 9 read/write timing parameters -6 -7.5 -10 symbol min max min max min max units t khkh 6.0 7.5 10 ns t khkl 2.4 3.0 3.5 ns t klkh 2.4 3.0 3.5 ns t khk#h 2.7 3.3 3.4 4.1 4.6 5.4 ns t khch 0.0 2.0 0.0 2.5 0.0 3.0 ns t chqv 2.5 3.0 3.0 ns t chqx 1.2 1.2 1.2 ns t chqz 2.5 3.0 3.0 ns -6 -7.5 -10 symbol min max min max min max units t chqx1 1.2 1.2 1.2 ns t avkh 0.7 0.8 1.0 ns t ivkh 0.7 0.8 1.0 ns t dvkh 0.7 0.8 1.0 ns t khax 0.7 0.8 1.0 ns t khix 0.7 0.8 1.0 ns t khdx 0.7 0.8 1.0 ns
15 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram ieee 1149.1 serial boundary scan (jtag) the qdr sram incorporates a serial boundary scan test access port (tap). this port operates in accordance with ieee standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specification are ex- cluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec-stan- dard 2.5v i/o logic levels. the sram contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be uncon- nected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left uncon- nected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see figure 2. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signifi- cant bit (msb) of any register. (see figure 3.) figure 2 tap controller state diagram note: the 0/1 next to each state represents the value of tms at the rising edge of tck. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . selection circuitry selection circuitry tck tms tap controller tdi tdo x = 69 for the x18 configuration. figure 3 tap controller block diagram
16 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram test data-out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine. (see figure 2.) the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see figure 3.) performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in figure 2. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board- level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins. the x18 configuration has a 69-bit-long register. the boundary scan register is loaded with the con- tents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload, and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order table shows the order in which the bits are connected. each bit corresponds to one of the pins on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32- bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other informa- tion described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction codes table. three of these instruc- tions are listed as reserved and should not be used. the other five instructions are described in detail be- low. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully imple- mented. the tap controller cannot be used to load address, data or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather it performs a capture of the i/o ring when these instruc- tions are executed. instructions are loaded into the tap controller dur- ing the shift-ir state when the instruction register is placed between tdi and tdo. during this state, in- structions are shifted through the instruction register through the tdi and tdo pins. to execute the instruc- tion once it is shifted in, the tap controller needs to be moved into the update-ir state.
17 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. extest is not implemented in the tap controller, hence this device is not ieee 1149.1 compliant. the tap controller does recognize an all-0 instruc- tion. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/ preload instruction has been loaded. extest does not place the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the in- struction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruc- tion. the preload portion of this instruction is not implemented, so the device tap controller is not fully 1149.1-compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bi-directional pins is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controllers capture setup plus hold time ( t cs plus t ch). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the in- struction register and the tap is placed in a shift-dr state, the bypass register is placed between tdi and tdo. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instruction are not implemented but are re- served for future use. do not use these instructions.
18 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram t tlth test clock (tck) 123456 test mode select (tms) t thtl test data-out (tdo) t thth test data-in (tdi) t thmx t mvth t thdx t dvth t tlox t tlov dont care undefined tap timing tap ac electrical characteristics (notes 1, 2) (+20c t j +100c, +2.4v v dd +2.6v) description symbol min max units clock clock cycle time t thth 100 ns clock frequency f tf 10 mhz clock high time t thtl 40 ns clock low time t tlth 40 ns output times tck low to tdo unknown t tlox 0 ns tck low to tdo valid t tlov 20 ns tdi valid to tck high t dvth 10 ns tck high to tdi invalid t thdx 10 ns setup times tms setup t mvth 10 ns capture setup t cs 10 ns hold times tms hold t thmx 10 ns capture hold t ch 10 ns note: 1. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 2. test conditions are specified using the load in figure 4.
19 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram tap ac test conditions input pulse levels ...................................... v ss to 2.5v input rise and fall times ....................................... 1ns input timing reference levels ........................... 1.25v output reference levels .................................... 1.25v test load termination supply voltage .............. 1.25v tdo 1.25v 20pf z = 50 w o 50 w figure 4 tap ac output load equivalent tap dc electrical characteristics and operating conditions (+20c t j +110c, +2.4v v dd +2.6v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage v ih 1.7 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.7 v 1, 2 input leakage current 0v v in v dd il i -5.0 5.0 a output leakage current output(s) disabled, il o -5.0 5.0 a 0v v in v dd q output low voltage i olc = 100a v ol 1 0.2 v 1 output low voltage i olt = 2ma v ol 2 0.7 v 1 output high voltage |i ohc | = 100a v oh 1 2.1 v 1 output high voltage |i oht | = 2ma v oh 2 1.7 v 1 note: 1. all voltages referenced to v ss (gnd). 2. overshoot: v ih (ac) v dd + 0.7v for t t khkh/2 undershoot: v il (ac) 3 -0.5v for t t khkh/2 power-up: v ih +2.6v and v dd 2.4v and v dd q 1.4v for t 200ms during normal operation, v dd q must not exceed v dd . control input signals (such as ld#, r/w#, etc.) may not have pulse widths less than t khkl (min) or operate at frequencies exceeding f kf (max).
20 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram identification register definitions instruction field 512k x 18 description revision number 000 version number. (31:29) device id 00011000010000000 512k x 18 qdr 2-word burst. (28:12) micron jedec id 00000101100 allows unique identification of sram vendor. code (11:1) id register presence 1 indicates the presence of an id register. indicator (0) scan register sizes register name bit size (x18) instruction 3 bypass 1 id 32 boundary scan 69 instruction codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. this operation does not affect sram operations. this instruction is not 1149.1-compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruction is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations.
21 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram 36 bw0# 7b 37 k 6b 38 k# 6a 39 bw1# 5a 40 w# 4a 41 sa 5c 42 sa 4b 43 nc/ sa19 3a; reads as 1 44 gnd/ sa21 2a; reads as 0 45 reserved 1a; reads as x 46 d9 3b 47 q9 2b 48 d10 3c 49 q10 3d 50 d11 2d 51 q11 3e 52 d12 3f 53 q12 2f 54 d13 2g 55 q13 3g 56 d14 3j 57 q14 3k 58 d15 3l 59 q15 2l 60 d16 3m 61 q16 3n 62 d17 2n 63 q17 3p 64 sa 3r 65 sa 4r 66 sa 4p 67 sa 5p 68 sa 5n 69 sa 5r bit# signal name pin id 1c# 6r 2c 6p 3sa 6n 4sa 7p 5sa 7n 6sa 7r 7sa 8r 8sa 8p 9sa 9r 10 d0 10p 11 q0 11p 12 d1 11n 13 q1 10m 14 d2 11m 15 q2 11l 16 d3 10k 17 q3 11k 18 d4 11j 19 zq 11h 20 q4 10j 21 d5 11g 22 q5 11f 23 d6 10e 24 q6 11e 25 d7 11d 26 q7 10c 27 d8 11c 28 q8 11b 29 reserved 11a; reads as x 30 gnd/ sa20 10a; reads as 0 31 nc/ sa18 9a; reads as 1 32 sa 8b 33 sa 7c 34 sa 6c 35 r# 8a boundary scan (exit) order bit# signal name pin id
22 512k x 18 2.5v v dd , hstl, qdrb2 sram micron technology, inc., reserves the right to change products or specifications without notice. MT54V512H18A.p65 C rev. 3/00 ?2000, micron technology, inc. advance 512k x 18 2.5v v dd , hstl, qdrb2 sram a w b p top view side view bottom view pin 1a identifier scribe mark g g ? d d pin 1a identifier s r f e 0.08 (0.003) c t 165-pin fbga note: 1. controlling dimensions are metric. 2. molding dimensions do not include protrusion; allowable mold protrusion is 0.25mm per side. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 qdr rams and quad data rate rams comprise a new family of products developed by cypress semiconductor, idt, and micron technol ogy, inc. micron is a registered trademark of micron technology, inc. dimensions dimension mm inches note a 13.0 0.1 b 15.0 0.1 c 1.20 max d 0.45 0.05 e 0.45 max f 0.850 0.075 g 1.00 typical p 1.00 typical r 10.00 typical s 14.00 typical t 6.50 typical w 4.40 max

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