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918 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 hs-82c37arh radiation hardened cmos high performance programmable dma controller description the intersil hs-82c37arh is an enhanced, radiation hardened cmos version of the industry standard 8237a direct memory access (dma) controller, fabricated using the intersil hardened ?eld, self-aligned silicon gate cmos process. the hs-82c37arh offers increased functionality, improved performance, and dramatically reduced power consumption for the radiation environment. the high speed, radiation hardness, and industry standard con?guration of the hs-82c37arh make it compatible with radiation hardened microprocessors such as the hs-80c85rh and the hs-80c86rh. the hs-82c37arh can improve system performance by allowing external devices to transfer data directly to or from system memory. memory-to-memory transfer capability is also provided, along with a memory block initialization feature. dma requests may be generated by either hardware or software, and each channel is independently programmable with a variety of features for ?exible operation. static cmos circuit design insures low operating power and allows gated clock operation for an even further reduction of power. multimode programmability allows the user to select from three basic types of dma services, and recon?guration under program control is possible even with the clock to the controller stopped. each channel has a full 64k address and word count range, and may be programmed to autoinitialize these registers following dma termination (end of process). the intersil hardened ?eld cmos process results in performance equal to or greater than existing radiation resis- tant products at a fraction of the power. features ? radiation hardened - total dose >10 5 rad (si) - transient upset > 10 8 rad (si)/s - latch up free epi-cmos ? low power consumption - iddsb = 50 m a maximum - iddop = 4.0ma/mhz maximum ? pin compatible with nmos 8237a and the intersil 82c37a ? high speed data transfers up to 2.5 mbps with 5mhz clock ? four independent maskable channels with autoinitializa- tion capability ? expandable to any number of channels ? memory-to-memory transfer capability ? cmos compatible ? hardened field, self-aligned, junction isolated cmos process ? single 5v supply ? military temperature range -55 o c to +125 o c august 1995 spec number 518058 file number 3042.1 db na ordering information part number temperature range package hs1-82c37arh-q -55 o c to +125 o c 40 lead sbdip hs1-82c37arh-8 -55 o c to +125 o c 40 lead sbdip hs1-82c37arh-sample +25 o c 40 lead sbdip hs9-82c37arh-q -55 o c to +125 o c 42 lead ceramic flatpack HS9-82C37ARH-8 -55 o c to +125 o c 42 lead ceramic flatpack hs9-82c37arh/sample +25 o c 42 lead ceramic flatpack
919 hs-82c37arh functional diagram pinouts 40 lead ceramic dual-in-line metal seal package (sbdip) mil-std-1835 cdip2-t40 top view 42 lead ceramic metal seal flatpack package (flatpack) intersil outline k42.a top view 33 34 35 36 37 38 39 40 32 31 30 29 24 25 26 27 28 21 22 23 a5 a7 a6 a4 eop a3 dack1 db6 db7 dack0 db5 a1 a2 a0 db0 db1 db2 db3 db4 vdd 1 13 12 14 15 16 17 18 19 20 2 3 4 5 6 7 8 9 10 11 hrq cs ior clk reset dack2 iow memr memw nc ready hlda adstb aen dack3 dreq3 dreq2 dreq1 dreq0 (gnd) vss a5 a6 a3 db0 vdd a7 a1 db1 db2 db3 db4 nc dack0 dack1 db5 db6 a4 db7 hrq cs memw nc ready hlda adstb aen ior iow clk reset dack2 dack3 nc dreq1 dreq0 gnd memr dreq3 dreq2 a0 a2 eop 33 32 39 38 37 36 35 34 42 41 31 30 29 28 27 24 23 22 40 26 25 10 11 4 5 6 7 8 9 1 2 12 13 14 15 16 19 20 21 3 17 18 timing and control command (8) decrementor inc decrementor i/o buffer mask (4) request (4) priority encoder and rotating priority logic temp word count reg (16) 16 bit bus temp address reg (16) 16 bit bus internal data bus mode (4 x 6) temporary (8) status (8) write buffer read buffer read buffer base address (16) (16) base address (16) base word count (16) base word count output buffer command control i/o buffer d0-d1 db0-db7 a4-a7 a0-a3 eop reset cs ready clock aen adstb memr memw ior iow dreq0- dreq3 hlda hdq dack0- dack3 4 4 a8-a15 spec number 518058
920 hs-82c37arh pin descriptions symbol pin number type description vdd 31 vdd: is the +5v power supply pin. a 0.1 m f capacitor between pins 31 and 20 is recommended for de- coupling. gnd 20 ground clk 12 i clock input: the clock input is used to generate the timing signals which control hs-82c37arh operations. this input may be driven from dc to 5mhz and may be stopped in either high or low state for standby operation. cs 11 i chip select: chip select is an active low input used to enable the controller onto the data bus for cpu communications. reset 13 i reset: this is an active high input which clears the command, status, request and temporary reg- isters, the first/last flip-flop, and the mode register counter. the mask register is set to ignore re- quests. following a reset, the controller is in an idle cycle. ready 6 i ready: this signal can be sued to extend the memory read and write pulses from the hs-82c37arh to accommodate slow memories or i/o devices. ready must not make transitions during its specified set-up and hold times. ready is ignored in verify transfer mode. hlda 7 i hold acknowledge: the active high hold acknowledge from the cpu indicates that is has relin- quished control of the system busses. dreq0- dreq3 16-19 i dma request: the dma request (dreq) lines are individual asynchronous channel request inputs used by peripheral circuits to obtain dma service. in fixed priority, dreq0 has the highest priority and dreq3 has the lowest priority. a request is generated by activating the dreq line of a channel. dack will acknowledge the recognition of dreq signal. polarity of dreq is programmable. reset initializes these lines to active. dreq will not be recognized while the clock is stopped. unused dreq inputs should be pulled high or low (inactive) and the corresponding mask bit set. db0- db7 21-23 26-30 i/o data bus: the data bus lines are bidirectional three-state signals connected to the system data bus. the outputs are enabled in the program condition during the i/o read to output the contents of a reg- ister to the cpu. the outputs are disabled and the inputs are read during an i/o write cycle when the cpu is programming the hs-82c37arh control registers. during dma cycles, the most significant 8 bits of the address are output onto the data bus to be strobed into an external latch by adstb. in mem- ory-to-memory operations, data from the memory enters the hs-82c37arh on the data bus during the read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write the data into the new memory location. ior 1 i/o i/o read: i/o read is a bidirectional active low three-state line. in the idle cycle, it is an input control signal used by the cpu to read the internal registers. in the active cycle, it is an output control signal used by the hs-82c37arh to access data from a peripheral during a dma write transfer. iow 2 i/o i/o write: i/o write is a bidirectional active low three-state line. in the idle cycle, it is an input control signal used by the cpu to load information into the hs-82c37arh. in the active cycle, it is an output control signal used by the hs-82c37arh to load data to the peripheral during a dma read transfer. eop 36 i/o end of process: end of process ( eop) is an active low bidirectional signal. information concerning the completion of dma services is available at the bidirectional eop pin. the hs-82c37arh allows an external signal to terminate an active dma service by pulling the eop pin low. a pulse is generated by the hs-82c37arh when terminal count (tc) for any channel is reached, except for channel 0 in memory-to-memory mode. during memory-to-memory transfers, eop will be output when the tc for channel 1 occurs. the eop pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor. when an eop pulse occurs, whether internally or externally generated, the hs-82c37arh will termi- nate the service, and if autoinitialize is enabled, the base registers will be written to the current registers of that channel. the mask bit and tc bit in the status register will be set for the currently active channel by eop unless the channel is programmed for autoinitialize. in that case, the mask bit remains clear. a0-a3 32-35 i/o address: the four least signi?cant address lines are bidirectional three-state signals. in the idle cycle, they are inputs and are used by the hs-80c86rh to address the internal registers to be loaded or read. in the active cycle, they are outputs and provide the lower 4 bits of the output address. spec number 518058
921 hs-82c37arh a4-a7 37-40 o address: the four most signi?cant address lines are three-state outputs and provide 4 bits of address. these lines are enabled only during the active cycle. hrq 10 o hold request: the hold request (hrq) output is used to request control of the system bus. when a dreq occurs and the corresponding mask bit is clear, or a software dma request is made, the hs- 82c37arh issues hrq. the hlda signal then informs the controller when access to the system bus- ses is permitted. for stand-alone operation where the hs-82c37arh always controls the busses, hrq may be tied to hlda. this will result in one s0 state before the transfer. dack0- dack3 14,15, 24, 25 o dma acknowledge: dma acknowledge is used to notify the individual peripherals when one has been granted a dma cycle. the sense of these lines is programmable. reset initializes them to active low. aen 9 o address enable: address enable enables the 8-bit latch containing the upper 8 address bits onto the system address bus. aen can also be used to disable other system bus drivers during dma transfers. aen is active high. adstb 8 o address strobe: this is an active high signal used to control latching of the upper address byte. it will drive directly the strobe input of external transparent octal latches, such as the 82c82. during block op- erations, adstb will only be issued when the upper address byte must be updated, thus speeding op- eration through elimination of s1 states. (see note 2). memr 3 o memory read: the memory read signal is an active low three-state output used to access data from the selected memory location during a dma read or a memory-to-memory transfer. memw 4 o memory write: the memory write is an active low three-state output used to write data to the selected memory location during a dma write or a memory-to-memory transfer. nc 5 no connect. pin 5 is open and should not be tested for continuity. pin descriptions (continued) symbol pin number type description spec number 518058
922 speci?cations hs-82c37arh absolute maximum ratings reliability information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5v input or output voltage applied . . . . . . . .vss - 0.3v to vdd + 0.3v for all grades storage temperature range . . . . . . . . . . . . . . . . . -65 o c to +150 o c lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . +300 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c typical derating factor. . . . . . . . . . . . 4ma/mhz increase in iddop esd classi?cation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 thermal resistance q ja q jc sbdip package. . . . . . . . . . . . . . . . . . . . 38 o c/w 5 o c/w ceramic flatpack package . . . . . . . . . . . 72 o c/w 10 o c/w maximum package power dissipation at +125 o c ambient sbdip package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.32w ceramic flatpack package . . . . . . . . . . . . . . . . . . . . . . . . . 0.69w if device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: sbdip package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26.3mw/c ceramic flatpack package . . . . . . . . . . . . . . . . . . . . . .13.9mw/c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. operating conditions operating supply voltage range (vdd) . . . . . . . . . +4.5v to +5.5v operating temperature range (t a ) . . . . . . . . . . . . -55 o c to +125 o c input low voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0v to +0.8v input high voltage. . . . . . . . . . . . . . . . . . . . . . . . vdd -1.5v to vdd table 1. dc electrical performance characteristics parameter symbol conditions group a subgroup temperature limits units min max ttl output high voltage voh1 vdd = 4.5v, io = -2.5ma, vin = 0v or 4.0v 1, 2, 3 +25 o c, +125 o c, -55 o c 3.0 - v cmos output high volt- age voh2 vdd = 4.5v, io = -100 m a, vin = 0v or 4.0v 1, 2, 3 +25 o c, +125 o c, -55 o c vdd- 0.4 -v output low voltage vol1 vdd = 4.5v, io = +2.5ma, vin = 0v or 4.0v 1, 2, 3 +25 o c, +125 o c, -55 o c - 0.4 v input leakage current iil or iih vdd = 5.5v, vin = 0v or 5.5v pins: 6, 7, 11-13, 16-19 1, 2, 3 +25 o c, +125 o c, -55 o c -1.0 1.0 m a output leakage current iozl or iozh vdd = 5.5v, vin = 0v or 5.5v pins: 1-4, 21-23, 26- 30, 32-40 1, 2, 3 +25 o c, +125 o c, -55 o c -10 10 m a standby power supply current iddsb vdd = 5.5v, io = 0ma, vin = gnd or vdd 1, 2, 3 +25 o c, +125 o c, -55 o c - +50 m a operating power supply current iddop vdd = 5.5v, io = 0ma, vin = gnd or vdd, f = 5mhz 1, 2, 3 +25 o c, +125 o c, -55 o c -20ma functional tests ft vdd = 4.5v and 5.5v, vin = gnd or vdd, f = 1mhz 7, 8a, 8b +25 o c, +125 o c, -55 o c -- - noise immunity functional test fn vdd = 4.5v and 5.5v, vin = gnd or vdd - 1.5v and vdd = 4.5v, vin = 0.8v or vdd 7, 8a, 8b +25 o c, +125 o c, -55 o c -- - spec number 518058
923 speci?cations hs-82c37arh table 2. ac electrical performance characteristics vcc = +5v 10%, gnd = 0v, acs tested at worst case vdd, guaranteed over full operating range. parameter symbol (notes 1, 2) conditions temperature subgroup limits units min max dma (master) mode aen high from clk low (s1) delay time tclaeh vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 175 ns dma (master) mode (continued) aen low from clk high (si) delay time tchael vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 - 130 ns adr from read high hold time trhax vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 tclcl- 100 -ns db from adstb low hold time tsldz vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 tclch- 18 -ns adr from write high hold time twhax vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 tclcl- 50 -ns dack valid from clk low delay time tcldav vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 - 170 ns eop high from clk high delay time tchiph vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 - 170 ns eop low from clk high delay time tchipl vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 - 100 ns adr stable from clk high tchav vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 - 110 ns db to adstb low setup time tdvsl vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 tchcl +10 -ns clock high time (transitions 10ns) tchcl vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 70 - ns clock low time (transitions 10ns) tclch vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 50 - ns clk cycle time tclcl vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 200 - ns clk high to read or write low delay tchrwl vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 - 190 ns read high from clk high (s4) delay time tchrh vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 - 190 ns write high from clk high (s4) delay time tchwh vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 - 130 ns hrq valid from clk high delay time tchrqv vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 - 120 ns eop low to clk low setup time teplcl vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 40 - ns eop pulse width tepleph vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 220 - ns read or write active from clk high tchrwv vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 - 150 ns spec number 518058
924 speci?cations hs-82c37arh dma (master) mode (continued) db float to active delay from clk high tchdv vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 - 110 ns hlda valid to clk high setup time travch vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 75 - ns input data from memr high hold time tmrhdx vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 0 ns input data to memr high setup time tdvmrh vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 155 ns output data from memw high hold time tmwhdz vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 15 ns output data valid to memw high tdvmwh vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 tclcl- 35 -ns dreq to clk low (si, s4) setup time tdqvcl vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 0 - ns clk low to ready hold time tclryx vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 20 - ns ready to clk low setup time tryvcl vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 60 - ns adstb high from clk low delay time tclsh vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 - 80 ns adstb low from clk low delay time tclsl vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 - 120 ns read high delay from write high twhrh vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 0 - ns read pulse width, normal timing trlrh1 vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 2tclcl -50 -ns adstb pulse width tshsl vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 tclcl - 80 -ns extended write pulse width twlwh1 vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 2tclcl -100 -ns write pulse width twlwh2 vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 tclcl - 100 -ns read pulse width, compressed trlrh2 vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 tclcl - 50 -ns peripheral (slave) mode adr valid or cs low to ior low tavirl vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 10 - ns adr valid or cs low to iow low setup time 0 taviwl vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 0 - ns data valid to iow high setup time tdviwh vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 150 - ns table 2. ac electrical performance characteristics (continued) vcc = +5v 10%, gnd = 0v, acs tested at worst case vdd, guaranteed over full operating range. parameter symbol (notes 1, 2) conditions temperature subgroup limits units min max spec number 518058
925 speci?cations hs-82c37arh peripheral (slave) mode (continued) adr or cs hold from ior high tirhax vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 0 - ns data access from ior tirldv vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 - 150 ns reset to first iow or ior trslirwl vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 2tclcl - ns reset pulse width trshrsl vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 300 - ior width tirlirh vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 200 - ns adr or cs high from iow high hold time tiwhax vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 0 - ns data from iow high hold time tiwhdx vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 10 - ns iow width tiwliwh vdd = 4.5v +25 o c, +125 o c, -55 o c 9, 10, 11 150 - ns notes: 1. read refers to both ior and memr, and write refers to both iow and memw, during memory to i/o and i/o to memory transfers 2. acs tested at worst case vdd but guaranteed over full operating range table 3. electrical performance characteristics parameter symbol conditions temperature limits units min max input capacitance cin vdd = open, f = 1mhz, all measurements refer- enced to device ground. t a = +25 o c - 15 pf output capacitance cout vdd = open, f = 1mhz, all measurements refer- enced to device ground. t a = +25 o c - 15 pf i/o capacitance ci/o vdd = open, f = 1mhz, all measurements refer- enced to device ground. t a = +25 o c - 20 pf adr active to float delay from clk high tchaz vdd = 4.5v and 5.5v -55 o c < t a < +125 o c - 90 ns read or write float delay from clk high tchrwz vdd = 4.5v and 5.5v -55 o c < t a < +125 o c - 120 ns db active to float delay from clk high tchdz vdd = 4.5v and 5.5v -55 o c < t a < +125 o c - 170 ns db float delay from ior high tirhdz vdd = 4.5v and 5.5v -55 o c < t a < +125 o c10 85 ns power supply high to reset low setup time tphrsl vdd = 4.5v and 5.5v -55 o c < t a < +125 o c 500 - ns note: the parameters listed in table 3 are controlled via design or process parameters and are not directly tested. these parame ters are characterized upon initial design release and upon design changes which would affect these characteristics. table 2. ac electrical performance characteristics (continued) vcc = +5v 10%, gnd = 0v, acs tested at worst case vdd, guaranteed over full operating range. parameter symbol (notes 1, 2) conditions temperature subgroup limits units min max spec number 518058
926 speci?cations hs-82c37arh table 4. post 100k rad electrical performance characteristics note: see +25 o c limits in table 1 and table 2 for post rad limits (subgroups 1, 7 and 9). table 5. burn-in delta parameters (+25 o c) parameter symbol delta limits standby power supply current iddsb 20 m a output leakage current iozl, iozh 2 m a input leakage current iih, iil 200na output low voltage vol 80mv ttl output high voltage voh1 600mv cmos output high voltage voh2 150mv table 6. applicable subgroups conformance group mil-std-883 method group a subgroups tested for -q recorded for -q tested for -8 recorded for -8 initial test 100% 5004 1, 7, 9 1 (note 2) 1, 7, 9 interim test 100% 5004 1, 7, 9, d 1, d (note 2) 1, 7, 9 pda 100% 5004 1, 7, d - 1, 7 final test 100% 5004 2, 3, 8a, 8b, 10, 11 - 2, 3, 8a, 8b, 10, 11 group a (note 1) sample 5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11 - 1, 2, 3, 7, 8a, 8b, 9, 10, 11 subgroup b5 sample 5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11, d 1, 2, 3, d (note 2) n/a subgroup b6 sample 5005 1, 7, 9 - n/a group c sample 5005 n/a n/a 1, 2, 3, 7, 8a, 8b, 9, 10, 11 group d sample 5005 1, 7, 9 - 1, 7, 9 group e, subgroup 2 sample 5005 1, 7, 9 - 1, 7, 9 notes: 1. alternate group a testing in accordance with mil-std-883 method 5005 may be exercised. 2. table 5 parameters only spec number 518058
927 hs-82c37arh intersil space level product flow -q wafer lot acceptance (all lots) method 5007 (includes sem) gamma radiation veri?cation (each wafer) method 1019, 2 samples/wafer, 0 rejects 100% die attach 100% nondestructive bond pull, method 2023 sample - wire bond pull monitor, method 2011 sample - die shear monitor, method 2019 or 2027 100% internal visual inspection, method 2010, condition a csi and/or gsi precap (note 6) 100% temperature cycle, method 1010, condition c, 10 cycles 100% constant acceleration, method 2001, condition per method 5004 100% pind, method 2020, condition a 100% external visual 100% serialization 100% initial electrical test (t0) 100% static burn-in 1, condition a or b, 72 hours min, +125 o c min, method 1015 100% interim electrical test 1 (t1) 100% delta calculation (t0-t1) 100% pda 1, method 5004 (note 1) 100% dynamic burn-in, condition d, 240 hours, +125 o c or equivalent, method 1015 100% interim electrical test 2(t2) 100% delta calculation (t0-t2) 100% pda 2, method 5004 (note 1) 100% final electrical test 100% fine/gross leak, method 1014 100% radiographic (x-ray), method 2012 (note 2) 100% external visual, method 2009 sample - group a, method 5005 (note 3) sample - group b, method 5005 (note 4) sample - group d, method 5005 (notes 4 and 5) 100% data package generation (note 7) csi and/or gsi final (note 6) notes: 1. failures from subgroup 1, 7 and deltas are used for calculating pda. the maximum allowable pda = 5% with no more than 3% of t he failures from subgroup 7. 2. radiographic (x-ray) inspection may be performed at any point after serialization as allowed by method 5004. 3. alternate group a testing may be performed as allowed by mil-std-883, method 5005. 4. group b and d inspections are optional and will not be performed unless required by the p.o. when required, the p.o. should i nclude separate line items for group b test, group b samples, group d test and group d samples. 5. group d generic data, as de?ned by mil-i-38535, is optional and will not be supplied unless required by the p.o. when require d, the p.o. should include a separate line item for group d generic data. generic data is not guaranteed to be available and is theref ore not available in all cases. 6. csi and/or gsi inspections are optional and will not be performed unless required by thep.o. when required, the p.o. should i nclude separate line items for csi precap inspection, csi ?nal inspection, gsi precap inspection, and/or gsi ?nal inspection. 7. data package contents: ? cover sheet (intersil name and/or logo, p.o. number, customer part number, lot date code, intersil part number, lot number, qu an- tity). ? wafer lot acceptance report (method 5007). includes reproductions of sem photos with percent of step coverage. ? gamma radiation report. contains cover page, disposition, rad dose, lot number, test package used, speci?cation numbers, test equipment, etc. radiation read and record data on ?le at intersil. ? x-ray report and ?lm. includes penetrometer measurements. ? screening, electrical, and group a attributes (screening attributes begin after package seal). ? lot serial number sheet (good units serial number and lot number). ? variables data (all delta operations). data is identi?ed by serial number. data header includes lot number and date of test. ? group b and d attributes and/or generic data is included when required by the p.o. ? the certi?cate of conformance is a part of the shipping invoice and is not part of the data book. the certi?cate of conformanc e is signed by an authorized quality representative. spec number 518058
928 hs-82c37arh intersil space level product flow -8 gamma radiation veri?cation (each wafer) method 1019, 2 samples/wafer, 0 rejects 100% die attach periodic- wire bond pull monitor, method 2011 periodic- die shear monitor, method 2019 or 2027 100% internal visual inspection, method 2010, condition b csi an/or gsi precap (note 5) 100% temperature cycle, method 1010, condition c, 10 cycles 100% constant acceleration, method 2001, condition per method 5004 100% external visual 100% initial electrical test 100% dynamic burn-in, condition d, 160 hours, +125 o c or equivalent, method 1015 100% interim electrical test 100% pda, method 5004 (note 1) 100% final electrical test 100% fine/gross leak, method 1014 100% external visual, method 2009 sample - group a, method 5005 (note 2) sample - group b, method 5005 (note 3) sample - group c, method 5005 (notes 3 and 4) sample - group d, method 5005 (notes 3 and 4) 100% data package generation (note 6) csi and/or gsi final (note 5) notes: 1. failures from subgroup 1, 7 are used for calculating pda. the maximum allowable pda = 5%. 2. alternate group a testing may be performed as allowed by mil-std-883, method 5005. 3. group b, c and d inspections are optional and will not be performed unless required by the p.o. when required, the p.o. shoul d include separate line items for group b test, group c test, group c samples, group d test and group d samples. 4. group c and/or group d generic data, as de?ned by mil-i-38535, is optional and will not be supplied unless required by the p. o. when required, the p.o. should include a separate line item for group c generic data and/or group d generic data. generic data is no t guar- anteed to be available and is therefore not available in all cases. 5. csi and/or gsi inspections are optional and will not be performed unless required by thep.o. when required, the p.o. should i nclude separate line items for csi precap inspection, csi ?nal inspection, gsi precap inspection, and/or gsi ?nal inspection. 6. data package contents: ? cover sheet (intersil name and/or logo, p.o. number, customer part number, lot date code, intersil part number, lot number, qu an- tity). ? gamma radiation report. contains cover page, disposition, rad dose, lot number, test package used, speci?cation numbers, test equipment, etc. radiation read and record data on ?le at intersil. ? screening, electrical, and group a attributes (screening attributes begin after package seal). ? group b, c and d attributes and/or generic data is included when required by the p.o. ? the certi?cate of conformance is a part of the shipping invoice and is not part of the data book. the certi?cate of conformanc e is signed by an authorized quality representative. spec number 518058 ac test circuit test condition definition table pins v1 r1 c1 all output except eop 1.7v 510 w 100pf eop vdd 1.6k w 50pf v1 output from device under test r1 test point c1 * * includes stray and jig capacitance ac testing input, output waveforms vdd -1.5v vil -0.4v input 1.5v voh vol output output z l or h voh vol 2.0v 0.8v voh - 0.45v 0.45 l or h z voh
929 hs-82c37arh spec number 518058 waveforms figure 1. slave mode timing note: host system must allow at least tclcl as recovery time between successive write accesses figure 2. slave mode read note: host system must allow at least tclcl as recovery time between successive write accesses figure 3. ready * read refers to both ior and memr outputs. write refers to both iow and memw outputs cs iow taviwl a0-a3 db0-db7 tiwliwh input valid tdviwh input valid tiwhax tiwhax tiwhdx cs a0-a3 ior db0-db7 tavirl address must be valid tirlirh tirldv tirhax tirhdz data out valid clk ready s2 s3 sw sw s4 tchrwl tchrwl extended write tchrwl tclryx tryvcl tchrh tchwh tclryx tryvcl write * read *
930 hs-82c37arh figure 4. dma transfer * read refers to both ior and memr outputs. write refers to both iow and memw outputs waveforms (continued) si si s0 s0 clk dreq hrq tchrqv hlda aen s1 s2 s3 s4 s2 s3 s4 s1 si si tclch tclcl tchcl adstb db0-db7 a0-a7 dack tclsh tchael tchdv tsldz tcldav tchaz trhaz tchav read * write * int eop ext eop tchrwv twhrh tchrwl tchrh trlrh1 tchrwz tchrwl tchwh twlwh1 tchrwl tchiph (for extended write) tepleph tchipl tchwh twlwh2 tchrh trhax tcldav tchdz tdvsl tshsl tclsl a8-a15 tchrwl tclaeh travch tdqvcl tdqvcl tchrqv tchav twhaz twhax address valid teplcl address valid spec number 518058
931 hs-82c37arh figure 5. memory-to-memory transfer figure 6. reset waveforms (continued) s0 s11 s12 s13 s14 s21 s22 s23 s24 si tclsl tclsh tclsl tclsh tchav tchdv tchdz a8 - a15 tchrwl tchrvw tchrh tmrhdx tdvmrh tchdv tchrwl extended write teplcl tepleph tchipl tchiph tchwh tdvmwh tmwhdz tchaz tchav tsldz tchrwl tchrwz clk adstb a0 - a7 db0 - db7 memr int eop tsldz a8 - a15 out address valid address valid in vdd reset ior or iow tphrsl trshrsl trslirwl spec number 518058
932 hs-82c37arh figure 7. compressed transfer * read refers to both ior and memr outputs. write refers to both iow and memw outputs waveforms (continued) clk a0 - a7 read * write * ready s2 s4 s2 s4 tchav tchrwl trlrh2 tchrh tchwh tchrwl tchwh tclryx tryvcl tclryx tryvcl tchav valid valid tchrh spec number 518058
933 hs-82c37arh burn-in circuits hs-82c37arh 40 lead sbdip hs-82c37arh 40 lead sbdip static configuration notes: 1. vdd = +6.0v 5% part is static sensitive 2. t a = +125 o c minimum voltage must be ramped 3. resistors: r1 = 10k w 10% (pins 6, 7, 11-13, 17 - 20) r2 = 2.7k w 5% (pins 1, 2, 21-23, 24, 28-32, 34-39) start-up timing notes: 1. f0 is 50% duty cycle square wave pulse burst. 2. 1.0khz f0 100khz f0 is left high after pulse burst 3. 10 cycles f0 pulse burst 1.0s 4. f1 = single pulse with width equal to 2 cycles of f0 5. f1 is left low after pulse burst 6. f1 pulse occurs after start of f0 and ends before f0. input levels: 0.9vdd vih vdd, -0.3v vil 0.7v dynamic configuration notes: 1. vdd = 6.5v 5% (burn-in) 2. vdd = 6.0v 5% (life test) 3. t a = +125 o c minimum 4. part is static sensitive, voltage must be ramped 5. resistors: r1 = 10k w 10% (pins 6, 7, 11-13, 17 - 20) r2 = 2.7k w 10% (pins 1, 2, 22-24, 28-32, 34-37, and loads) 33 34 35 36 37 38 39 40 32 31 30 29 24 25 26 27 28 21 22 23 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 f1 f0 vdd load 2.7k w 2.7k w vdd 33 34 35 36 37 38 39 40 32 31 30 29 24 25 26 27 28 21 22 23 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 vdd load load load load load load nc load load load load load load load f0 f0 f5 f2 f1 f0 f5 f4 f3 f1 f2 f3 f4 f0 f1 spec number 518058
934 hs-82c37arh hs-82c37arh 42 lead ceramic flatpack hs-82c37arh 42 lead ceramic flatpack static configuration notes: 1. vdd = +6.0v 5% part is static sensitive 2. t a = +125 o c minimum voltage must be ramped 3. resistors: r1 = 10k w 10% (pins 6, 7, 11-13, 16-19) r2 = 2.7k w 5% (pins 1, 2, 21-23, 26-30, 32-36) start-up timing notes: 1. f0 is 50% duty cycle square wave pulse burst. 2. 1.0khz f0 100khz f0 is left high after pulse burst 3. 10 cycles f0 pulse burst 1.0s 4. f1 = single pulse with width equal to 2 cycles of f0 5. f1 is left low after pulse burst 6. f1 pulse occurs after start of f0 and ends before f0. input levels: 0.9vdd vih vdd, -0.3v vil 0.7v dynamic configuration notes: 1. vdd = 6.5v 5% (burn-in) 2. vdd = 6.0v 5% (life test) 3. t a = +125 o c minimum 4. part is static sensitive, voltage must be ramped 5. resistors: r1 = 10k w 10% (pins 6, 7, 11-13, 16-19) r2 = 2.7k w 10% (pins 1, 2, 21-23, 26-30, 32-36, and loads) burn-in circuits (continued) vdd 1 2 3 4 5 6 7 8 9 21 13 10 11 12 14 15 16 17 18 19 20 37 38 39 40 41 42 35 34 33 32 31 28 29 30 36 26 23 24 25 22 27 f0 f1 load 2.7k w 2.7k w vdd 1 2 3 4 5 6 7 8 9 21 13 10 11 12 14 15 16 17 18 19 20 37 38 39 40 41 42 35 34 33 32 31 28 29 30 36 26 23 24 25 22 27 f0 load f0 f5 f1 f2 f3 f4 load load load load load load open open open vdd load load load load load load f5 f4 f3 f2 f1 f0 f0 f1 spec number 518058
935 hs-82c37arh irradiation circuit notes: 1. r = 47k w 2. pins with load: 3, 4, 8, 9, 10, 37-40 pins with load2: 14, 15, 21-30 pins brought out: 12 (clock), 13 (reset) 3. vdd = 5.5v 0.5v 33 34 35 36 37 38 39 40 32 31 30 29 24 25 26 27 28 21 22 23 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 vcc clock reset load 2 load 2 load load load load nc load vss r r r r r r r r r r r load load load load load 2 load 2 load 2 load 2 load 2 load 2 load 2 load 2 load 2 load 2 r r r r r toggle toggle 5.5v vss vcc out load 2.7k w 2.7k w vss out load 2 2.7k w spec number 518058
936 hs-82c37arh functional description the hs-82c37arh direct memory access controller is designed to improve the data transfer rate in systems which must transfer data from an i/o device to memory, or move a block of memory to an i/o device. it will also perform mem- ory-to-memory block moves, or ?ll a block of memory with data from a single location. operating modes are provided to handle single byte transfers as well as discontinuous data streams, which allows the hs-82c37arh to control data movement with software transparency. the dma controller is a state-driven address and control sig- nal generator, which permits data to be transferred directly from an i/o device to memory or vice versa without ever being stored in a temporary register. this can greatly increase the data transfer rate for sequential operations, compared with processor moves or repeated string instruc- tions. memory-to-memory operations require temporary internal storage of the data byte between generation of the source and destination addresses, so memory-to-memory transfers take place at less than half the rate of i/o opera- tions, but still much faster than with central processor tech- niques. the maximum data transfer rate obtainable with the hs-82c37arh is approximately 2.5 mbytes/second, for an i/o operation using the compressed timing option and 5mhz clock. the block diagram of the hs-82c37arh is shown on page 2. the timing and control block, priority block, and internal registers are the main components. figure 8 lists the name and size of the internal registers. the timing and control block derives internal timing from the clock input, and generates external control signals. the priority encoder block resolves priority contention between dma channels requesting service simultaneously. figure 8 . hs-82c37arh internal registers dma operation in a system, the hs-82c37arh address and control outputs and data bus pins are basically connected in parallel with the system busses. an external latch is required for the upper name size number base address registers 16 bits 4 base word count registers 16 bits 4 current address registers 16 bits 4 current word count registers 16 bits 4 temporary address register 16 bits 1 temporary word count register 16 bits 1 status register 8 bits 1 command register 8 bits 1 temporary register 8 bits 1 mode registers 6 bits 4 mask registers 4 bits 1 request register 4 bits 1 address byte. while inactive, the controllers outputs are in a high impedance state. when activated by a dma request and bus control is relinquished by the host, the hs- 82c37arh drives the busses and generates the control sig- nals to perform the data transfer. the operation performed by activating one of the four dma request inputs has previ- ously been programmed into the controller via the com- mand, mode, address, and word count registers. for example, if a block of data is to be transferred from ram to an i/o device, the starting address of the data is loaded into the hs-82c37arh current and base address registers for a particular channel, and the length of the block is loaded into that channels word count register. the corresponding mode register is programmed for a memory-to-i/o opera- tion (read transfer), and various options are selected by the command register and other mode register bits. the chan- nels mask bit is cleared to enable recognition of a dma request (dreq). the dreq can either be a hardware signal or a software command. once initiated, the block dma transfer will proceed as the controller outputs the data address, simultaneous memr and iow pulses, and selects an i/o device via the dma acknowledge (dack) outputs. the data byte ?ows directly from the ram to the i/o device. after each byte is trans- ferred, the address is automatically incremented (or decre- mented) and the word count is decremented. the operation is then repeated for the next byte. the controller stops trans- ferring data when the word count register under?ows, or an external eop is applied. to further understand hs-82c37arh operation, the states generated by each clock cycle must be considered. the dma controller operates in two major cycles, active and idle. after being programmed, the controller is normally idle until a dma request occurs on an unmasked channel, or a soft- ware request is given. the hs-82c37arh will then request control of the system busses and enter the active cycle. the active cycle is composed of several internal states, depend- ing on what options have been selected and what type of operation has been requested. the hs-82c37arh can assume seven separate states, each composed of one full clock period. state i (si) is the idle state. it is entered when the hs-82c37arh has no valid dma requests pending, at the end of a transfer sequence, or when a reset or master clear has occurred. while in si, the dma controller is inactive but may be in the program condi- tion (being programmed by the processor.) state 0 (s0) is the ?rst state of a dma service. the hs- 82c37arh has requested a hold but the processor has not yet returned an acknowledge. the hs-82c37arh may still be programmed until it has received hlda from the cpu. an acknowledge from the cpu will signal that dma transfers may begin. s1, s2, s3 and s4 are the working states of the dma service. if more time is needed to complete a transfer than is available with normal timing, wait states (sw) can be inserted between s2 or s3 and s4 by the use of the ready line on the hs-82c37arh. spec number 518058
937 hs-82c37arh note that the data is transferred directly from the i/o device to memory (or vice versa) with ior and memw (or memr and iow) being active at the same time. the data is not read into or driven out of the hs-82c37arh in i/o-to-memory or memory-to-i/o dma transfers. memory-to-memory transfers require a read-from and a write-to-memory to complete each transfer. the states, which resemble the normal working states, use two-digit numbers for identi?cation. eight states are required for a sin- gle transfer. the ?rst four states (s11, s12, s13, s14 are used for the read-from-memory half and the last four states (s21, s22, s23, s24) for the write-to-memory half of the transfer. idle cycle when no channel is requesting service, the hs-82c37arh will enter the idle cycle and perform si states. in this cycle, the hs-82c37arh will sample the dreq lines on the falling edge of every clock cycle to determine if any channel is requesting a dma service. note that for standby operation where the clock has been stopped, dma requests will be ignored. the device will respond to cs (chip select), in case of an attempt by the microprocessor to write or read the internal registers of the hs-82c37arh. when cs is low and hlda is low, the hs- 82c37arh enters the program condition. the cpu can now establish, change or inspect the internal de?nition of the part by reading from or writing to the internal registers. the hs-82c37arh may be programmed with the clock stopped, provided that hlda is low and at least one rising clock edge has occurred after hlda was driven low, so the controller is in an si state. address lines a0-a3 are inputs to the device and select which registers will be read or written. the ior and iow lines are used to select and time the read or write operations. due to the number and size of the inter- nal registers, an internal ?ip-?op is used to generate an addi- tional bit of address. the bit is used to determine the upper or lower byte of the 16-bit address and word count regis- ters. the ?ip-?op is reset by master clear or reset. separate software commands can also set or reset this ?ip-?op. special software commands can be executed by the hs- 82c37arh in the program condition. these commands are decoded as sets of addresses with cs, ior, and iow. the commands do not make use of the data bus. instructions include set and clear first/last flip-flop, master clear, clear mode register counter, and clear mask register. active cycle when the hs-82c37arh is in the idle cycle, and a software request or an unmasked channel requests a dma service, the device will output an hrq to the microprocessor and enter the active cycle. it is in this cycle that the dma service will take place, in one of four modes: single transfer mode - in single transfer mode, the device is programmed to make one transfer only. the word count will be decremented and the address decremented or incre- mented following each transfer. when the word count rolls over from zero to ffffh, a terminal count (tc) bit in the status register is set, an eop pulse is generated, and the channel will autoinitialize if this option has been selected. if not programmed to autoinitialize, the mask bit will be set, along with the tc bit and eop pulse. dreq must be held active until dack becomes active. if dreq is held active throughout the single transfer (there-by triggering a second transfer), hrq will still go inactive and release the bus to the system. then it will again go active and, upon receipt of a new hlda, another single transfer will be performed, unless a higher priority channel takes over. in hs-80c85rh or hs-80c86rh systems, this will ensure one full machine cycle execution between dma transfers. details of timing between the hs-82c37arh and other bus control protocols will depend upon the characteristics of the micro- processor involved. block transfer mode - in block transfer mode, the device is activated by dreq or software request and continues making transfers during the service until a tc, caused by word count going to ffffh, or an external end of process ( eop) is encountered. dreq need only beheld active until dack becomes active. again, an autoinitialization will occur at the end of the service if the channel has been pro- grammed for that option. demand transfer mode - in demand transfer mode the device continues making transfers until a tc or external eop is encountered, or until dreq goes inactive. thus, transfers may continue until the i/o device has exhaust edits data capacity. after the i/o device has had a chance to catch up, the dma service is reestablished by means of a dreq. during the time between services when the micro-processor is allowed to operate, the intermediate values of address and word count are stored in the hs-82c37arh current address and current word count registers. higher priority channels may intervene in the demand process, once dreq has gone inactive. only an eop can cause an autoinitializa- tion at the end of the service. eop is generated either by tc or by an external signal. cascade mode - this mode is used to cascade more than one hs-82c37arh for simple system expansion. the hrq and hlda signals from the additional hs-82c37arh are connected to the dreq and dack signals respectively of a channel for the initial hs-82c37arh. this allows the dma requests of the additional device to propagate through the priority network circuitry of the preceding device. the priority chain is preserved and the new device must wait for its turn to acknowledge requests. since the cascade channel of the initial hs-82c37arh is used only for prioritizing the addi- tional device, it does not output an address or control signals of its own so that there is no con?ict with the cascaded device. the hs-82c37arh will respond to dreq and gen- erate dack but all other outputs except hrq will be dis- abled. an external eop will be ignored by the initial device, but will have the usual effect on the added device. figure 9 shows two additional devices cascaded with an ini- tial device using two of the previous channels. this forms a two-level dma system. more hs-82c37arhs could be added at the second level by using the remaining channels of the ?rst level. additional devices can also be added by cascading into the channels of the second level devices, forming a third level. spec number 518058
938 hs-82c37arh figure 9. cascaded hs-82c37arhs when programming cascaded controllers, start with the ?rst level (closest to the microprocessor). after reset, the dack outputs are programmed to be active low and are held in the high state. if they are used to drive hlda directly, the second level device(s) cannot be programmed until dack polarity is selected as active high on the initial device. also, the initial devices mask bits function normally on cas- caded channels, so they may be used to inhibit second-level services. transfer types each of the three active transfer modes can perform three different types of transfers. these are read, write and ver- ify. write transfers move data from an i/o device to the mem- ory by activating memw and ior. read transfers move data from memory to an i/o device by activating memr and iow. verify transfers are pseudo-transfers. the hs-82c37arh operates as in read or write transfers generating addresses and responding to eop, etc., however the memory and i/o control lines all remain inactive. verify mode is not permitted for memory-to-memory operation. ready is ignored during verify transfers. autoinitialize - by programming a bit in the mode register, a channel may be set up as an autoinitialize channel. during autoinitialization, the original values of the current address and current word count registers are automatically restored from the base address and base word count reg- isters of that channel following eop. the base registers are loaded simultaneously with the current registers by the microprocessor and remain unchanged throughout the dma service. the mask bit is not set when the channel is in auto- initialize. following autoinitialization, the channel is ready to perform another dma service, without cpu intervention, as soon as a valid dreq is detected, or software request made. memory-to-memory - to perform block moves of data from one memory address space to another with minimum of pro- hs-80c86rh micro- processor 1st level hrq hlda dreq dack hs-82c37arh dreq dack initial device 2nd level hrq hlda hs-82c37arh hrq hlda hs-82c37arh additional devices gram effort and time, the hs-82c37arh includes a mem- ory-to-memory transfer feature. programming a bit in the command register selects channels 0 and 1 to operate as memory-to-memory transfer channels. the transfer is initiated by setting the software or hardware dreq for channel 0. the hs-82c37arh requests a dma service in the normal manner. after hlda is true, the device, using four-state transfers in block transfer mode, reads data from the memory. the channel 0 current address register is the source for the address used and is decremented or incremented in the normal manner. the data byte read from the memory is stored in the hs-82c37arh internal tempo- rary register. another four-state transfer moves the data to memory using the address in channel 1s current address register and incrementing or decrementing it in the normal manner. the channel 1 current word count register is dec- remented. when the word count of channel 1 goes to ffffh, a tc is generated causing an eop output terminating the service. channel 0 word count decrementing to ffffh will not set the channel 0 tc bit in the status register or generate an eop in this mode. it will cause an autoinitialization of chan- nel 0, if that option has been selected. if full autoinitialization for a memory-to-memory operation is desired, the channel 0 and channel 1 word counts must be set equal before the transfer begins. otherwise, if channel 0 under?ows before channel 1, it will autoinitialize and set the data source address back to the beginning of the block. if the channel 1 word count under?ows before channel 0, the memory-to-memory dma service will terminate, and channel 1 will autoinitialize but channel 0 will not. in memory-to-memory mode, channel 0 may be pro- grammed to retain the same address for all transfers. this allows a single byte to be written to a block of memory. this channel 0 address hold feature is selected by bit 1 in the command register. the hs-82c37arh will respond to external eop signals during memory-to-memory transfers, but will only relinquish the system busses after the transfer is complete (i.e., after an s24 state). data comparators in block search schemes may use this input to terminate the service when a match is found. the timing of memory-to-memory transfers is found in figure 5. memory-to-memory operations can be detected as an active aen with no dack outputs. priority - the hs-82c37arh has two types of priority encoding available as software selectable options. the ?rst is fixed priority which ?xes the channels in priority order based upon the descending value of their numbers. the channel with the lowest priority is 3 followed by 2, 1 and the highest priority channel, 0. after the recognition of any one channel for service, the other channels are prevented from interfering with the service until it is completed. the second scheme is rotating priority. the last channel to get service becomes the lowest priority channel with the oth- ers rotating accordingly. the next lower channel from the channel serviced has highest priority on the following request: priority rotates every time control of the system busses is returned to the processor. spec number 518058
939 hs-82c37arh rotating priority with rotating priority in a single chip dma system, any device requesting service is guaranteed to be recognized after no more than three higher priority services have occurred. this prevents any one channel from monopolizing the system. regardless of which priority scheme is chosen, priority is evaluated every time a hlda is returned to the hs-82c37arh. compressed timing - in order to achieve even greater throughput where system characteristics permit, the hs- 82c37arh can compress the transfer time to two clock cycles. from figure 4 it can be seen that state s3 is used to extend the access time of the read pulse. by removing state s3, the read pulse width is made equal to the write pulse width and a transfer consists only of state s2 to change the address and state s4 to perform the read/write. s1 states will still occur when a8-a15 need updating (see address generation). timing for compressed transfers is found in figure 7. eop will be output in s2 if compressed timing is selected. compressed timing is not allowed for memory-to- memory transfers. address generation - in order to reduce pin count, the hs- 82c37arh multiplexes the eight higher order address bits on the data lines. state s1 is used to output the higher order address bits to an external latch from which they may be placed on the address bus. the falling edge of address strobe (adstb) is used to load these bits from the data lines to the latch. address enable (aen) is used to enable the bits onto the address bus through a three-state enable. the lower order address bits are output by the hs- 82c37arh directly. lines a0-a7 should be connected to the address bus. figure 4 shows the time relationships between clk, aen, adstb, db0-db7 and a0-a7. during block and demand transfer mode service, which include multiple transfers, the addresses generated will be sequential. for many transfers the data held in the external address latch will remain the same. this data need only change when a carry or borrow from a7 to a8 takes place in the normal sequence of addresses. to save time and speed transfers, the hs-82c37arh executes s1 states only when updating of a8-a15 in the latch is necessary. this means for long services, s1 states and address strobes may occur only once every 256 transfers, a savings of 255 clock cycles for each 256 transfers. 1sr service 2nd service 3rd service highest 0 1 2 lowest 3 2 3 0 1 3 0 1 2 service request service service programming the hs-82c37arh will accept programming from the host processor anytime that hlda is inactive, and at least one rising clock edge has occurred after hlda went low. it is the responsibility of the host to assure that programming and hlda are mutually exclusive. note that a problem can occur if a dma request occurs on an unmasked channel while the hs-82c37arh is being pro- grammed. for instance, the cpu may be starting to repro- gram the two byte address register of channel 1 when channel 1 receives a dma request. if the hs-82c37arh is enabled (bit 2 in the command register is 0), and channel 1 is unmasked, a dma service will occur after only one byte of the address register has been reprogrammed. this condi- tion can be avoided by disabling the controller (setting bit 2 in the command register) or masking the channel before programming any of its registers. once the programming is complete, the controller can be enabled/unmasked. after power-up it is suggested that all internal locations be loaded with some known value, even if some channels are unused. this will aid in debugging. register description current address register - each channel has a 16-bit cur- rent address register. this register holds the value of the address used during dma transfers. the address is auto- matically incremented or decremented after each transfer and the values of the address are stored in the current address register during the transfer. this register is written or read by the microprocessor in successive 8-bit bytes. it may also be reinitialized by an autoinitialize back to its origi- nal value. autoinitialize takes place only after an eop. in memory-to-memory mode, the channel 0 current address register can be prevented from incrementing or decrement- ing by setting the address hold bit in the command register. current word register - each channel has a 16-bit current word count register. this register determines the number of transfers to be performed. the actual number of transfers will be one more than the number programmed in the cur- rent word count register (i.e., programming a count of 100 will result in 101 transfers). the word count is decremented after each transfer. when the value in the register goes from zero to ffffh, a tc will be generated. this register is loaded or read in successive 8-bit bytes by the microproces- sor in the program condition. following the end of a dma service it may also be reinitialized by an autoinitialization back to its original value. autoinitialization can occur only when an eop occurs. if it is not autoinitialized, this register will have a count of ffffh after tc. base address and base word count registers - each channel has a pair of base address and base word count registers. these 16-bit registers store the original value of their associated current registers. during autoinitialization, these values are used to restore the current registers to their original values. the base registers are written simulta- neously with their corresponding current register in 8-bit bytes in the program condition by the microprocessor. these registers cannot be read by the microprocessor. spec number 518058
940 hs-82c37arh mask register - each channel has associated with it a mask bit which can be set to disable an incoming dreq. each mask bit is set when its associated channel produces an eop if the channel is not programmed to autoinitialize. each bit of the 4-bit mask register may also be set or cleared separately or simultaneously under soft-ware con- trol. the entire register is also set by a reset or master clear. this disables all hardware dma requests until a clear mask register instruction allows them to occur. the instruc- tion to separately set or clear the mask bits is similar in form to that used with the request register. refer to the following table and figure 10 for details. when reading the mask reg- ister, bits 4-7 will always read as logical ones, and bits 0-3 will display the mask bits of channel 0-3, respectively. the 4 bits of the mask register may be cleared simultaneously by using the clear mask register command (see software com- mands section). mask register all four bits of the mask register may also be written with a single command. 76543210 00 01 10 11 0 1 bit number select channel 0 mask bit select channel 1 mask bit select channel 2 mask bit select channel 3 mask bit clear mask bit set mask bit dont care 76543210 0 1 0 1 0 1 bit number clear channel 0 mask bit set channel 0 mask bit clear channel 1 mask bit set channel 1 mask bit clear channel 2 mask bit set channel 2 mask bit dont care, write all ones, read 0 1 clear channel 3 mask bit set channel 3 mask bit mode register - each channel has a 6-bit mode register associated with it. when the register is being written to by the microprocessor in the program condition, bits 0 and 1 determine which channel mode register is to be written. when the processor reads a mode register, bits 0 and 1 will both be ones. see the adjacent table and figure 10 for mode register functions and addresses. mode register request register - the hs-82c37arh can respond to requests for dma service which are initiated by software as well as by a dreq. each channel has a request bit associ- ated with it in the 4-bit request register. these are non- maskable and subject to prioritization by the priority encoder network. each register bit is set or reset separately under software control. the entire register is cleared by a reset. to set or reset a bit, the software loads the proper form of the data word. see figure 10 for register address coding, and the following table for request register format. a software request for dma operation can be made in block or single modes. for memory-to-memory transfers, the software request for channel 0 should be set. when reading the request register, bits 4-7 will always read as ones, and bits 0-3 will display the request bits of channels 0-3 respectively. request register 76543210 00 01 10 11 bit number channel 0 select channel 1 selectt channel 2 select channel 3 select 00 01 10 11 verify transfer write transfer read transfer illegal 0 1 autoinitialization disable autoinitialization enable 00 01 10 11 demand mode select single mode select block mode select cascade mode select 0 1 address increment select address decrement select xx readback xx if bits 6 and 7 = 11 76543210 00 01 10 11 0 1 bit number select channel 0 select channel 1 select channel 2 select channel 3 reset request bit set request bit dont care, write bits 4-7 all ones, read spec number 518058
941 hs-82c37arh command register - this 8-bit register controls the operation of the hs-82c37arh. it is programmed by the microprocessor and is cleared by reset or a master clear instruction. the adjacent table lists the function of the command bits. see figure 10 for read and write addresses. command registe r 76543210 0 1 0 1 bit number mem-to-mem disable mem-to-mem enable ch. 0 addr. hold disable ch. 0 addr. hold enable if bit 0 = 0 x 0 1 controller enable controller disable 0 1 normal timing compressed timing if bit 0 = 1 x 0 1 fixed priority rotating priority 0 1 late write selection extended write sel. if bit 3 = 1 x 0 1 dreq sense active high dreq sense active low 0 1 dack sense active low dack sense active high status register - the status register contains information about the present status of the hs-82c37arh and can be read by the microprocessor. this information includes which channels have reached a terminal count and which channels have pending dma requests. bits 0-3 are set every time a tc is reached by that channel or an external eop is applied. these bits are cleared upon reset, master clear, and on each status read. bits 4-7 are set whenever their corre- sponding channel is requesting service, regardless of the mask bit state. if the mask bits are set, software can poll the status register to determine which channels have dreqs, and selectively clear a mask bit, thus allowing user de?ned service priority. status bits 4-7 are updated while the clock is high, and latched on the falling edge. status bits 4-7 are cleared upon reset or master clear. status registe r temporary register - the temporary register is used to hold data during memory-to-memory transfers. following the completion of the transfer, the last word moved can be read by the microprocessor by accessing this register. the tem- porary register always contains the last byte transferred in the previous memory-to-memory operation, unless cleared by a reset or master clear. 76543210 1 1 1 1 1 1 bit number channel 0 has reached tc channel 1 has reached tc channel 2 has reached tc channel 3 has reached tc channel 0 request channel 1 request 1 1 channel 2 request channel 3 request operation a3 a2 a1 a0 ior iow read status register 100001 write command register 100010 read request register 100101 write request register 100110 read command register 101001 write single mask bit 101010 read mode register 101101 write mode register 101110 set byte pointer f/f 110001 clear byte pointer f/f 110010 read temporary register 110101 master clear 110110 clear mode reg. counter 111001 clear mask register 111010 read all mask bits 111101 write all mask bits 111110 figure 10. software command codes and register codes spec number 518058
942 hs-82c37arh software commands there are special software commands which can be exe- cuted by reading or writing to the hs-82c37arh. these commands do not depend on the speci?c data pattern on the data bus, but are activated by the i/o operation itself. on read type commands, the data value is not guaranteed. these commands are: clear first/last flip-flop: this command is executed prior to writing or reading new address or word count information to the hs-82c37arh. this initializes the ?ip-?op to a known state so that subsequent accesses to register contents by the microprocessor will address upper and lower bytes in the correct sequence. set first/last flip-flop : this command will set the ?ip-?op to select the high byte ?rst on read and write operations to address and word count registers. master clear : this software instruction has the same effect as the hardware reset. the command, status, request, and temporary registers, and internal first/last flip-flop and mode register counter are cleared and the mask reg- ister is set. the hs-82c37arh will enter the idle cycle. clear mask register : this command clears the mask bits of all four channels, enabling them to accept dma requests. clear mode register counter : since only one address location is available for reading the mode registers, an inter- nal two-bit counter has been included to select mode regis- ters during read operations. to read the mode registers, ?rst execute the clear mode register counter command, then do consecutive reads until the desired channel is read. read order is channel 0 ?rst, channel 3 last. the lower two bits on all mode registers will read as ones. external eop operation the eop pin is a bidirectional, open drain pin which may be driven by external signals to terminate dma operation. because eop is an open drain pin an external pull-up resis- tor is required. the value of the external pull-up resistor used should guarantee a rise time of less than 125ns. it is impor- tant to note that the hs-82c37arh will not accept external eop signals when it is in an si (idle)state. the controller must be active to latch ext eop. once latched, the ext eop will be acted upon during the next s2 state, unless the hs-82c37arh enters an idle state ?rst. in the latter case the latched eop is cleared. external eop pulses occurring between active dma transfers in demand mode will not be recognized, since the hs-82c37arh is in an si state. channel register opera tion signals internal flip-flop data bus db0-db7 cs ior iow a3 a2 a1 a0 0 base and current address write 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 a0-a7 a8-a15 current address read 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 a0-a7 a8-a15 base and current word count write 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 w0-w7 w8-w15 current word count read 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 w0-w7 w8-w15 1 base and current address write 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 a0-a7 a8-a15 current address read 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 a0-a7 a8-a15 base and current word count write 0 0 1 1 0 0 0 0 0 0 1 1 1 1 0 1 w0-w7 w8-w15 current word count read 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 w0-w7 w8-w15 2 base and current address write 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 1 a0-a7 a8-a15 current address read 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 a0-a7 a8-a15 base and current word count write 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 1 w0-w7 w8-w15 current word count read 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 w0-w7 w8-w15 3 base and current address write 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 1 a0-a7 a8-a15 current address read 0 0 0 0 1 1 0 0 1 1 1 1 0 0 0 1 a0-a7 a8-a15 base and current word count write 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 1 w0-w7 w8-w15 current word count read 0 0 0 0 1 1 0 0 1 1 1 1 1 1 0 1 w0-w7 w8-w15 figure 11. word count and address register command codes spec number 518058
943 hs-82c37arh application information figure 12 shows an application for a dma system utilizing the hs-82c37arh dma controller and the hs-80c86rh microprocessor. in this application, the hs-82c37arh dma controller is used to improve system performance by allow- ing an i/o device to transfer data directly to or from system memory. components the system clock is generated by the hs-82c85rh clock controllers generator and is inverted to meet the clock high and low times required by the hs-82c37arh dma control- ler. the four or gates are used to support the hs-80c86rh microprocessor in minimum mode by producing the control signals used by the processor to access memory or i/o. a decoder is used to generate chip select for the dma control- ler and memory. the hs-82c37arh multiplexes the most signi?cant bits of the address on its data outputs (db0 - 7), so the 82c82 octal latch is used to demultiplex the address. a three-state inverter is used to generate the bhe signal using the a0 output of the hs-82c37arh. hold acknowl- edge (hlda) and address enable (aen) are ored together and used to deactivate the microprocessors 82c82 transceiver to insure that the dma controller does not have bus contention with the microprocessor. operation a dma request (dreq) is generated by the i/o device. after receiving the dma request, the dma controller will issue a hold request (hrq) to the processor. the system busses are not released to the dma controller until a hold acknowl- edge (hlda) signal is returned to the dma controller from the hs-80c86rh processor. after the hold acknowledge has been received, addresses and control signals are gener- ated by the dma controller to accomplish the dma transfers. data is transferred directly from the i/o device to memory (or vice versa) with ior and memw (or memr and iow) being active. note that data is not read into or driven out of the dma controller in i/o-to-memory or memory-to-i/o data transfers. figure 12. application for dma system stb oe 82c82 clk cs adstb aen a0-7 db0-7 eop iow memr memw hrq dreq0 dack0 ior hlda decoder memcs clk hs-82c85rh hlda hlda hrq ale ad0 ad15 vdd mn/ mx m/ 10 rd wr bhe memw ior iow memr memr memw memcs memory hs-80c86rh data bus address bus data bus stb oe 82c82 address bus bhe a0 vdd cs dreq i/o device ior iow hs-82c37arh spec number 518058
944 hs-82c37arh metallization topology die dimensions: 215 x 232 mils x 19 1 mil metallization: type: al/si thickness: 11k ? 2k ? glassivation: thickness: 8k ? 1k ? worst case current density: 7.9 x 10 4 a/cm 2 metallization mask layout hs-82c37arh dack3 (15) dreq3 (16) vss (20) dreq2 (17) dreq1 (18) dreq0 (19) db7 (21) db6 (22) db5 (23) dack1 (24) dack0 (25) (32) a0 (30) db0 (31) vdd (33) a1 (29) db1 (28) db2 (27) db3 (26) db4 (34) a2 (1) ior (2) iow (3) memr (4) memw (6) ready (38) a5 (39) a6 (40) a7 (37) a4 (5) nc (35) a3 hrq (10) cs (11) hlda (7) adstb (8) aen (9) clk (12) reset (13) dack2 (14) (36) eop spec number 518058
945 hs-82c37arh spec number 518058 notes: 1. index area: a notch or a pin one identi?cation mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturers identi?cation shall not be used as a pin one identi?cation mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identi?cation mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. this dimension allows for off-center lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and ?nish thickness. the maximum lim- its of lead dimensions b and c or m shall be measured at the cen- troid of the ?nished lead surfaces, when solder dip or tin plate lead ?nish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead ?nish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. 11. the basic lead spacing is 0.050 inch (1.27mm) between center lines. each lead centerline shall be located within 0.005 inch (0.13mm) of its exact longitudinal position relative to lead 1 and the highest numbered (n) lead. e e1 d s1 b q e2 a c 1 a a m c1 b1 (c) (b) section a-a base lead finish metal m e n l k42.a top brazed 42 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a - 0.100 - 2.54 - b 0.017 0.025 0.43 0.64 - b1 0.017 0.023 0.43 0.58 - c 0.007 0.013 0.18 0.33 - c1 0.007 0.010 0.18 0.25 - d 1.045 1.075 26.54 27.31 3 e 0.630 0.650 16.00 16.51 - e1 - 0.680 - 17.27 3 e2 0.530 0.550 13.46 13.97 - e 0.050 bsc 1.27 bsc 11 k----- l 0.320 0.350 8.13 8.89 - q 0.045 0.065 1.14 1.65 8 s1 0.000 - 0.00 - 6 m - 0.0015 - 0.04 - n42 42- rev. 0 6/17/94 packaging
946 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?ce headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. taiwan limited 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 hs-82c37arh spec number

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