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rev. 1.0 11/10 copyright ? 2010 by silicon laboratories si5317 si5317 p in -c ontrolled 1?710 mh z j itter c leaning c lock features applications description the si5317 is a flexible 1:1 jitter cleaning clock for high-performance applications that require jitter attenuation without cl ock multiplication. th e si5317 accepts a single clock input ranging from 1 to 710 mhz and generates two low jitter clock outputs at the same frequency. the clock frequency range and loop bandwidth are selectable from a simple look-up table. the si5317 is based on silicon laboratories' 3rd-generation dspll ? technology, which provides jitter attenuation on any frequency in a highly integrated pl l solution that eliminates the need for external vcxo and loop filter components. the dspll loop bandwidth is user selectable, providing jitter performance optimization at the application level. functional block diagram ? provides jitter attenuation on any frequency ? one clock input / two clock outputs ? input/output frequency range: 1?710 mhz ? ultra low jitter: 300 fs (12 khz?20 mhz) typical ? simple pin control interface ? selectable loop bandwidth for jitter attenuation: 60 hz?8.4 khz ? selectable output clock signal format: lvpecl, lvds, cml or cmos ? single supply: 1.8, 2.5, or 3.3 v ? loss of lock and loss of signal alarms ? vco freeze during los/lol ? on-chip voltage regulator with high psrr ? small size: 6 x 6 mm, 36-qfn ? wide temperature range: ?40 to +85 oc ? data converter clocking ? wireless infrastructure ? networking, sonet/sdh ? switches and routers ? medical instrumentation ? test and measurement dspll ? clock in clock out1 signal format [1:0] status/control loss of lock loss of signal bandwidth select [1:0] xtal/clock rate [1:0] frequency table high psrr regulator frequency select [3:0] clock out2 xtal/clock phase skew inc/dec vdd (1.8, 2.5, 3.3 v) gnd ordering information: see page 41. pin assignments 1 2 3 29 30 31 32 33 34 35 36 20 21 22 23 24 25 26 27 10 11 12 13 14 15 16 17 4 5 6 7 8 frqtbl nc rst nc los gnd vdd xa vdd rate0 nc nc dbl2_by rate1 ckin+ ckin? nc bwsel0 bwsel1 frqsel1 frqsel2 frqsel3 ckout1? sfout1 gnd vdd sfout0 ckout2- ckout2+ nc gnd pad frqsel0 inc 9 18 19 28 xb lol dec ckout1+
si5317 2 rev. 1.0
si5317 rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1. three-level (3l) input pins (no external resistors) . . . . . . . . . . . . . . . . . . . . . . . . .9 1.2. three-level input pins (example with external resistors) . . . . . . . . . . . . . . . . . . . . .9 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3. frequency plan tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1. frequency range plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2. output skew adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3. pll self-calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4. alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5. vco freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 3.6. pll bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4. high-speed i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1. input clock buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 4.2. output clock driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5. crystal/reference cl ock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.1. crystal/reference clock se lection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 6. power supply filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 7. typical phase noise plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 5 7.1. example: sonet oc-192 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8. typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9. pin descriptions: si5317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11. package outline: 36-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 12. recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 13. si5317 device top mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
si5317 4 rev. 1.0 1. electrical specifications table 1. recommended operating conditions (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit temperature range t a ?40 25 85 oc supply voltage v dd 3.3 v nominal 2.97 3.3 3.63 v 2.5 v nominal 2.25 2.5 2.75 v 1.8 v nominal 1.71 1.8 1.89 v note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise noted. table 2. dc characteristics (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max units supply current (supply current is independent of v dd ) i dd lvpecl format 622.08 mhz out all ckouts enabled 1 ? 251 279 ma lvpecl format 622.08 mhz out only 1 ckout enabled 1 ? 217 243 ma cmos format 19.44 mhz out all ckouts enabled 2 ? 204 234 ma cmos format 19.44 mhz out only ckout1 enabled 2 ? 194 220 ma ckin input pin input common mode voltage (input threshold voltage) v icm 1.8 v 5% 0.9 ? 1.4 v 2.5 v 10% 1.0 ? 1.7 v 3.3 v 10% 1.1 ? 1.95 v input resistance ckn rin single-ended 20 40 60 k ? input voltage level limits ckn vin see note 3 0?v dd v single-ended input voltage swing v ise f ckin < 212.5 mhz see figure 2. 0.2 ? ? v pp f ckin > 212.5 mhz see figure 2. 0.25 ? ? v pp notes: 1. lvpecl outputs require vdd > 2.25 v. 2. this is the amount of leakage that the 3l inputs can tolerate from an external driver. see figure 3 on page 9. in most designs, an external resistor voltage divider is recommended. 3. no overshoot or undershoot.
si5317 rev. 1.0 5 differential input voltage swing v id f ckin < 212.5 mhz see figure 2. 0.2 ? ? v pp f ckin > 212.5 mhz see figure 2. 0.25 ? ? v pp ckout output clock 1 common mode v ocm lvpecl 100 ? load line-to-line v dd ? 1.42 ?v dd ? 1.25 v differential ou tput swing v od lvpecl 100 ? load line-to-line 1.1 ? 1.9 v pp single-ended output swing v se lvpecl 100 ? load line-to-line 0.5 ? 0.93 v pp differential output voltage cko vd cml 100 ? load line-to-line 350 425 500 mv pp common mode output voltage cko vcm cml 100 ? load line-to-line ?v dd ? 0.36 ?v differential output voltage cko vd lvds 100 ? load line-to-line 500 700 900 mv pp low swing lvds 100 ? load line-to-line 350 425 500 mv pp common mode output voltage cko vcm lvds 100 ? load line-to-line 1.125 1.2 1.275 v output voltage low cko vollh cmos ? ? 0.4 v output voltage high cko vohlh v dd = 1.71 v cmos 0.8 x v dd ?? v output drive current cko io cmos driving into cko vol for out- put low or cko voh for output high. ckout+ and ckout? shorted externally. v dd = 1.8 v ? 7.5 ? ma v dd = 3.3 v ? 32 ? ma 2-level lvcmos input pins input voltage low v il v dd =1.71v ? ? 0.5 v v dd =2.25v ? ? 0.7 v v dd =2.97v ? ? 0.8 v table 2. dc characteristics (continued) (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max units notes: 1. lvpecl outputs require vdd > 2.25 v. 2. this is the amount of leakage that the 3l inputs can tolerate from an external driver. see figure 3 on page 9. in most designs, an external resistor voltage divider is recommended. 3. no overshoot or undershoot.
si5317 6 rev. 1.0 input voltage high v ih v dd =1.89v 1.4 ? ? v v dd =2.25v 1.8 ? ? v v dd =3.63v 2.5 ? ? v input low current i il ??50 a input high current i ih ??50 a weak internal input pull-up resistor r pup ?75? k ? weak internal input pull-down resistor r pdn ?75? k ? 3-level input pins input voltage low v ill ?? 0.15 x v dd v input voltage mid v imm 0.45 x v dd ? 0.55 x v dd v input voltage high v ihh 0.85 x v dd ?? v input low current i ill 2 ?20 ? ? a input mid current i imm 2 ?2 ? 2 a input high current i ihh 2 ??20 a table 2. dc characteristics (continued) (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max units notes: 1. lvpecl outputs require vdd > 2.25 v. 2. this is the amount of leakage that the 3l inputs can tolerate from an external driver. see figure 3 on page 9. in most designs, an external resistor voltage divider is recommended. 3. no overshoot or undershoot.
si5317 rev. 1.0 7 figure 1. voltage characteristics lvcmos output pins output voltage low v ol i o =2ma v dd =1.62v ??0.4 v i o =2ma v dd =2.97v ??0.4 v output voltage high v oh i o =?2ma v dd =1.62v v dd ?0.4 ? ? v i o =?2ma v dd =2.97v v dd ?0.4 ? ? v single-ended reference clock input pin xa (xb with cap to gnd) input resistance xa rin xtal/refclk rate[1:0] = lm, ml, mh, or hm ?12? k ? input voltage level limits xa vin 0?1.2 v input voltage swing xa vpp 0.5 ? 1.2 v pp differential reference cl ock input pins (xa/xb) input resistance xa/xb rin xtal/refclk rate[1:0] = lm, ml, mh, or hm ?12? k ? differential input voltage level limits xa/xb vin 0?1.2 v input voltage swing xa vpp /xb vpp 0.5 ? 1.2 v pp, each table 2. dc characteristics (continued) (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max units notes: 1. lvpecl outputs require vdd > 2.25 v. 2. this is the amount of leakage that the 3l inputs can tolerate from an external driver. see figure 3 on page 9. in most designs, an external resistor voltage divider is recommended. 3. no overshoot or undershoot. v ise , v ose v id ,v od differential i/os v icm , v ocm single-ended peak-to-peak voltage differential peak-to-peak voltage signal + signal ? (signal +) ? (signal ?) v t signal + signal ? v id = (signal+) ? (signal?) v icm , v ocm
si5317 8 rev. 1.0 figure 2. rise/fall time characteristics t f t r 80% 20% dout, clout
si5317 rev. 1.0 9 1.1. three-level (3 l) input pins (no external resistors) figure 3. three-level input pins 1.2. three-level i nput pins (example with external resistors) figure 4. three-level input pins table 3. three-level input pins 1,2,3,4 parameter min max input low current ?30 a ? input mid current ?11 a ?11 a input high current ? ?30 a notes: 1. the current parameters are the amount of leakage that the 3l inputs can tolerate from an external driver using the external resistor values indicated in this example. in most designs, an external resistor voltage divider is recommended. 2. resistor packs are only needed if the leakage current of the external driver exceeds the current specified in table 2 , iimm. any resistor pack may be used (e.g. panasonic exb-d10c183j). pcb layout is not critical. 3. if a pin is tied to ground or v dd , no resistors are needed. 4. if a pin is left open (no connect), no resistors are needed. external driver si5317 i imm 75 k ? v dd 75 k ? ? v dd 18 k ? 75 k ? v dd 75 k ? one of eight resistors from a panasonic exb-d10c183j (or similar) resistor pack
si5317 10 rev. 1.0 table 4. ac characteristics (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max units input frequency ckn f 1?710mhz ckin input pins input duty cycle (minimum pulse width) ckn dc whichever is smaller 40 ? 60 % 2??ns input capacitance ckn cin ?? 3pf input rise/fall time ckn trf 20?80% see figure 2 ?? 11ns ckout output pins output frequency (output not configured for cmos or disable) ck of 1?710mhz maximum output frequency in cmos format cko fmc 1 ? 212.5 mhz single-ended output rise/fall (20?80%) cko trf cmos output v dd =1.62 cload = 5 pf ?? 8ns cmos output v dd =2.97 cload = 5 pf ?? 2ns differential output rise/fall time cko trf 20 to 80 %, f out = 622.08 ? 230 350 ps output duty cycle differential uncertainty cko dc 100 ? load line to line measured at 50% point (not for cmos) ??40ps lvcmos pins input capacitance c in ?? 3pf
si5317 rev. 1.0 11 lvcmos output pins rise/fall times t rf cload = 20 pf see figure 2 ?25 ?ns losn trigger window los trig from l vst ckin ? to los ? ?750s time to clear lol after los cleared t clrlol f in unchanged and xa/xb stable. ?? los to ? lol ?10 ?ms pll performance lock time t lockhw whenever rst , frqtbl, rate, bwsel, or frqsel are changed, with valid ckin to ?? lol; bw = 100 hz ? 1.2 sec closed loop jitter peaking j pk ? 0.05 0.1 db jitter tolerance j tol bw determined by bwsel[1:0] 5000/ bw ? ? ns pk- pk minimum reset pulse width t rstmin 1??s spurious noise sp spur max spur @ n x f3 (n > 1, n x f3 < 100 mhz) ? ?93 ?70 dbc phase change due to temperature variation t temp max phase changes from ? 40 to +85 oc ? 300 500 ps table 4. ac characteristics (continued) (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max units
si5317 12 rev. 1.0 table 5. performance specifications 1, 2, 3, 4, 5 (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit jitter generation f in =f out =622.08mhz, lvpecl output format bw = 120 hz j gen 50 khz?80 mhz ? 0.32 0.42 ps rms 12 khz?20 mhz ? 0.31 0.41 ps rms 800 hz?80 mhz ? 0.4 0.45 ps rms phase noise f in =f out = 622.08 mhz lvpecl output format cko pn 1 khz offset ? ?106 ?87 dbc/hz 10 khz offset ? ?121 ?100 dbc/hz 100 khz offset ? ?132 ?104 dbc/hz 1 mhz offset ? ?132 ?119 dbc/hz notes: 1. bwsel [1:0] loop bandwidth settings provided in table 9 on page 22. 2. 114.285 mhz 3rd ot crystal used as xa/xb input. 3. v dd =2.5v 4. t a =85c 5. test condition: f in =622.08mhz, f out = 622.08 mhz, lvpecl clock input: 1.19 vppd with 0.5 ns rise/fall time (20-80%), lvpecl clock output.
si5317 rev. 1.0 13 table 6. thermal characteristics (v dd = 1.8 5%, 2.5 10%, or 3.3 v 10%, t a = ?40 to 85 oc) parameter symbol test condition min typ max unit thermal resistance junction to ambient ? ja still air ? 32 ? oc/w thermal resistance junction to case ? jc ?14?oc/w table 7. absolute maximum ratings parameter symbol value unit dc supply voltage v dd ?0.5 to 3.8 v lvcmos input voltage v dig ?0.3 to (v dd + 0.3) v ckinn voltage level limits ckn vin 0 to v dd v xa/xb voltage level limits xa vin 0 to 1.2 v operating junction temperature t jct ?55 to 150 c storage temperature range t stg ?55 to 150 c esd hbm tolerance (100 pf, 1.5 k ? ); all pins except ckin+/ckin? 2kv esd mm tolerance; all pins except ckin+/ckin? 150 v esd hbm tolerance (100 pf, 1.5 k ? ); ckin+/ckin? 750 v esd mm tolerance; ckin+/ckin? 100 v latch-up tolerance jesd78 compliant note: permanent device damage may occur if the absolute maximu m ratings are exceeded. functional operation should be restricted to the conditions as specified in the operation se ctions of this data sheet. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
si5317 14 rev. 1.0 2. functional description figure 5. detailed block diagram 2.1. overview the si5317 is a 1:1 jitter-atte nuating precision clock for applications requiring sub 1 ps jitter performance. the si5317 accepts one clock input ranging from 1 to 710 mhz and generates two clock outputs at the same frequency ranging from 1 to 710 mhz. the si531 7 is based on silicon laboratories' 3r d-generation dspll? technology, which provides jitter attenuation on any frequency in a highly integrated pll solution that eliminates the need for external vcxo and loop filter components. the nominal operating frequency is selectable from a look-up table. the si5317 pll loop bandwidth (bw) is selectable via the bwsel[1:0] pins and supports a range from 60 hz to 8.4 khz. the si5317 monitors the input clock for loss-of-signal (l os) and provides a los alarm when it detects missing pulses on the input clock. the device monitors the lock status of the dspll. the lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. the si5317 provides a vco freeze capab ility that allows the device to contin ue generation of a stable output clock when the selected input cloc k is lost. during vco freeze, the dspll latches its vco settings and uses its xa/xb clock as its frequency reference. the si5317 has two output clock drivers and can be config ured as four single-ended or two differential outputs. the signal format of the clock output is selectable to support lvpecl, lvds, cml, or cmos loads. the device operates from a single 1.8, 2.5, or 3.3 v supply. th e use of lvpecl requires a vdd > 2.25 v. dspll ? los lol bwsel[1:0] ckin+ ckin? ckout+ ckout? vdd (1.8, 2.5, or 3.3 v) gnd 2 frqsel[3:0] rst rate[1:0] xa xb f osc 2 f 3 frequency control bandwidth control alarms control external crystal or reference clock frqtbl voltage regulator with high psrr sfout[1:0] 2 ckout+ ckout? skew control inc dec dbl2_by
si5317 rev. 1.0 15 3. frequency plan tables for ease of use, the si5317 is pin-controlled to enable si mple device configuration of the frequency range plan and pll loop bandwidth via a predefined look-up table. the dspll has been optimized for jitter performance and tunability for each fr equency range and pll loop bandwid th provided in table 9 on page 22. many of the control inputs are three levels: high, low, and medium. high and low are standard voltage levels determined by the supply pins: v dd and ground. if the input pin is left floatin g, it is driven to nominally half of v dd . effectively, this creates three logic leve ls for these controls. see section 6. "pow er supply filtering" on page 34 and section 1.2. "three-level input pins (example with exte rnal resistors)" on page 9 for additional information. 3.1. frequency range plan the input to output clock frequency range is set by the 3-level frqsel[3:0] and frqtbl pins. the ckin and ckout is the same frequenc y range as specified in table 8. due to the wide tunability of the si5317, each frequency plan provides overlap between adjacent se ttings. to select a frequency plan, the desired frequency should be selected as close to the defined center fr equency. in certain cases where the desired frequency is exactly between two overlapping plans, eith er frqtbl and frqsel setting can be used. 3.1.1. pll loop bandwidth plan the si5317's loop bandwidth ranges from 60 hz to 8.4 k hz. for each frequency range, the corresponding loop bandwidth is provided in a simple look-up table (see table 9 on page 22). the loop bandwidth is digitally programmable using the three-level bwsel [1:0] input pins. 3.2. output skew adjustment the overall device skew (ckin to ckoutn phase delay) is adjustable via the inc and dec input pins. a positive edge triggered pulse applied to the inc pin increases the device skew defined by tabl e 8, inc/dec step size, for each given frequency plan. the identical operation on the dec pin decreases the skew by the same amount. using the inc and dec pins, there is no limit to the ra nge of skew adjustment that can be made. following a powerup or reset, the overall device skew will revert to the reset value, although the input- to-output skew is effectively random. the rate of change for each inc/de c operation is defined by the selected loop bandwidth, bwsel[1:0].
si5317 16 rev. 1.0 table 8. look-up tables for fin = fout frequency range and loop bandwidth settings frequency range (mhz) bwsel [1:0] (bw in hz) inc/dec phase change (ns) plan no frqtbl frqsel [3:0] min center max lh ml mm mh hl hm 0 l llll .95 1.00 1.05 ? 3814 927 230 114 57 0.21 1 l lllm 1.00 1.05 1.10 ? 3814 927 230 114 57 0.21 2 l lllh 1.05 1.10 1.15 ? 3834 931 231 115 57 0.21 3 l llml 1.10 1.15 1.20 ? 4052 983 244 121 60 0.21 4 l llmm 1.15 1.20 1.25 ? 4251 1030 255 127 63 0.21 5 l llmh 1.20 1.25 1.30 ? 4451 1078 267 133 66 0.21 6 l llhl 1.25 1.30 1.35 ? 4652 1125 279 139 69 0.21 7 l llhm 1.30 1.35 1.40 ? 4852 1172 290 145 72 0.21 8 l llhh 1.35 1.40 1.45 ? 5054 1219 302 150 75 0.21 9 l lmll 1.40 1.45 1.50 ? 5256 1267 314 156 78 0.21 10 l lmlm 1.45 1.50 1.55 ? 5256 1267 314 156 78 0.21 11 l lmlh 1.50 1.55 1.60 ? 5459 1314 325 162 81 0.21 12 l lmml 1.55 1.60 1.65 ? 5866 1409 349 174 87 0.21 13 l lmmm 1.60 1.65 1.70 ? 5866 1409 349 174 87 0.21 14 l lmmh 1.65 1.70 1.75 ? 6071 1457 360 180 89 0.21 15 l lmhl 1.70 1.75 1.80 ? 6276 1504 372 185 92 0.21 16 l lmhm 1.75 1.80 1.85 ? 6483 1552 384 191 95 0.21 17 l lmhh 1.80 1.85 1.90 ? 6688 1599 395 197 98 0.21 18 l lhll 1.85 1.90 1.95 ? 6895 1647 407 203 101 0.21 19 l lhlm 1.90 1.95 2.00 4696 2285 560 139 69 ? 0.21 20 l lhlh 1.95 2.00 2.10 4832 2350 575 143 71 ? 0.21 21 l lhml 2.00 2.10 2.20 4967 2415 591 147 73 ? 0.21 22 l lhmm 2.10 2.20 2.30 5239 2544 622 154 77 ? 0.21 23 l lhmh 2.20 2.30 2.40 ? 4052 983 244 121 60 0.21 24 l lhhl 2.30 2.40 2.50 ? 4251 1030 255 127 63 0.21 25 l lhhm 2.40 2.50 2.60 ? 4451 1078 267 133 66 0.21 26 l lhhh 2.50 2.60 2.70 ? 4651 1125 279 139 69 0.21 27 l mlll 2.60 2.70 2.80 ? 4852 1172 290 145 72 0.20 28 l mllm 2.70 2.80 2.90 ? 5054 1219 302 150 75 0.21 29 l mllh 2.80 2.90 3.00 ? 5255 1267 314 156 78 0.20 30 l mlml 2.90 3.00 3.10 ? 5458 1314 325 162 81 0.20 31 l mlmm 3.00 3.10 3.20 ? 5859 1409 349 174 87 0.20 32 l mlmh 3.10 3.20 3.30 ? 5859 1409 349 174 87 0.20 33 l mlhl 3.20 3.30 3.40 ? 6071 1457 360 180 89 0.21 note: for bwsel[1:0] settings ll, lm, hh are reserved.
si5317 rev. 1.0 17 34 l mlhm 3.30 3.40 3.50 ? 6071 1457 360 180 89 0.21 35 l mlhh 3.40 3.50 3.60 ? 6276 1504 372 185 92 0.21 36 l mmll 3.50 3.60 3.70 ? 6483 1552 384 191 95 0.21 37 l mmlm 3.60 3.70 3.80 ? 6895 1647 407 203 101 0.21 38 l mmlh 3.70 3.80 3.90 ? 6895 1647 407 203 101 0.21 39 l mmml 3.80 3.90 4.00 ? 4650 1125 279 139 69 0.20 40 l mmmm 3.90 4.00 4.20 ? 4786 1156 286 143 71 0.21 41 l mmmh 4.00 4.20 4.40 ? 4919 1188 294 147 73 0.21 42 l mmhl 4.20 4.40 4.60 ? 5457 1314 325 162 81 0.20 43 l mmhm 4.40 4.60 4.80 ? 5457 1314 325 162 81 0.20 44 l mmhh 4.60 4.80 5.00 ? 5730 1378 341 170 85 0.21 45 l mhll 4.80 5.00 5.20 ? 6268 1504 372 185 92 0.20 46 l mhlm 5.00 5.20 5.40 ? 6273 1504 372 185 92 0.20 47 l mhlh 5.20 5.40 5.60 ? 6550 1568 387 193 96 0.20 48 l mhml 5.40 5.60 5.80 ? 6823 1631 403 201 100 0.20 49 l mhmm 5.60 5.80 6.00 ? 6823 1631 403 201 100 0.20 50 l mhmh 5.80 6.00 6.20 ? 6333 3064 748 185 92 0.20 51 l mhhl 6.00 6.20 6.40 ? 6571 3176 774 192 96 0.20 52 l mhhm 6.20 6.40 6.60 ? 6811 3289 801 199 99 0.20 53 l mhhh 6.40 6.60 6.80 ? 6071 1457 360 180 89 0.21 54 l hlll 6.60 6.80 7.00 ? 6534 1567 387 193 96 0.20 55 l hllm 6.80 7.00 7.20 ? 6534 1567 387 193 96 0.20 56 l hllh 7.00 7.20 7.40 ? 6483 1552 384 191 95 0.21 57 l hlml 7.20 7.40 7.60 ? 6686 1599 395 197 98 0.20 58 l hlmm 7.40 7.60 7.80 ? 6891 1647 407 203 101 0.20 59 l hlmh 7.60 7.80 8.00 ? 4648 1125 279 139 69 0.20 60 l hlhl 7.80 8.00 8.40 ? 4786 1156 286 143 71 0.21 61 l hlhm 8.00 8.40 8.80 ? 4919 1188 294 147 73 0.21 62 l hlhh 8.40 8.80 9.00 ? 6599 1580 391 195 97 0.20 63 l hmll 8.80 9.00 9.20 ? 7080 1693 418 209 104 0.19 64 l hmlm 9.00 9.20 9.60 ? 7080 1693 418 209 104 0.19 65 l hmlh 9.20 9.60 10.00 ? 5727 1377 341 170 85 0.20 66 l hmml 9.60 10.00 10.50 ? 6003 1441 356 178 88 0.21 67 l hmmm 10.00 10.50 11.00 ? 6273 1504 372 185 92 0.20 table 8. look-up tables for fin = fout frequency range and loop bandwidth settings (continued) frequency range (mhz) bwsel [1:0] (bw in hz) inc/dec phase change (ns) plan no frqtbl frqsel [3:0] min center max lh ml mm mh hl hm note: for bwsel[1:0] settings ll, lm, hh are reserved.
si5317 18 rev. 1.0 68 l hmmh 10.50 11.00 11.50 ? 6992 1672 413 206 103 0.20 69 l hmhl 11.00 11.50 12.00 ? 5866 1409 349 174 87 0.21 70 l hmhm 11.50 12.00 12.50 ? 6155 1477 365 182 91 0.20 71 l hmhh 12.00 12.50 13.00 ? 6446 1545 382 190 95 0.20 72 l hhll 12.50 13.00 13.50 ? 7034 1680 415 207 103 0.20 73 l hhlm 13.00 13.50 14.00 ? 5408 1303 323 161 80 0.20 74 l hhlh 13.50 14.00 14.50 ? 5633 1356 336 167 83 0.20 75 l hhml 14.00 14.50 15.00 ? 5861 1409 349 174 87 0.20 76 l hhmm 14.50 15.00 15.50 ? 7383 1764 436 217 108 0.19 77 l hhmh 15.00 15.50 16.00 ? 6321 1515 374 187 93 0.21 78 l hhhl 15.50 16.00 16.50 ? 6321 1515 374 187 93 0.21 79 l hhhm 16.00 16.50 17.00 ? 6774 1620 400 200 99 0.20 80 l hhhh 16.50 17.00 17.50 ? 7230 1726 426 213 106 0.20 81 m llll 17.00 17.50 18.00 ? 4422 1071 265 132 66 0.21 82 m lllm 17.50 18.00 18.50 ? 7342 1756 434 216 108 0.19 83 m lllh 18.00 18.50 19.00 ? 7342 1756 434 216 108 0.19 84 m llml 18.50 19.00 19.50 ? 7298 1742 430 214 107 0.20 85 m llmm 19.00 19.50 20.00 ? 4995 1206 299 149 74 0.20 86 m llmh 19.50 20.00 21.00 ? 7518 1796 444 221 110 0.19 87 m llhl 20.00 21.00 22.00 ? 6208 1488 368 183 91 0.21 88 m llhm 21.00 22.00 23.00 ? 7429 1777 439 219 109 0.18 89 m llhh 22.00 23.00 24.00 ? 6155 1477 365 182 91 0.20 90 m lmll 23.00 24.00 25.00 ? 6155 1477 365 182 91 0.20 91 m lmlm 24.00 25.00 26.00 ? 6739 1612 399 199 99 0.20 92 m lmlh 25.26 26.00 27.00 ? 7613 1816 449 224 111 0.19 93 m lmml 26.00 27.00 28.00 ? 6817 1631 403 201 100 0.20 94 m lmmm 27.00 28.00 29.00 ? 6817 1631 403 201 100 0.20 95 m lmmh 28.00 29.00 30.00 ? 7640 1821 450 224 112 0.20 96 m lmhl 29.00 30.00 31.00 ? 4941 1194 296 147 73 0.20 97 m lmhm 30.31 31.00 32.00 ? 7658 1827 451 225 112 0.19 98 m lmhh 31.00 32.00 33.00 ? 7658 1827 451 225 112 0.19 99 m lhll 32.00 33.00 34.00 ? 6774 1620 400 200 99 0.20 100 m lhlm 33.00 34.00 35.00 ? 6774 1620 400 200 99 0.20 101 m lhlh 34.00 35.00 36.00 ? 7692 1832 452 225 112 0.20 table 8. look-up tables for fin = fout frequency range and loop bandwidth settings (continued) frequency range (mhz) bwsel [1:0] (bw in hz) inc/dec phase change (ns) plan no frqtbl frqsel [3:0] min center max lh ml mm mh hl hm note: for bwsel[1:0] settings ll, lm, hh are reserved.
si5317 rev. 1.0 19 102 m lhml 35.00 36.00 37.00 ? 7680 1833 453 226 113 0.19 103 m lhmm 36.00 37.00 38.00 ? 7539 1803 446 222 111 0.18 104 m lhmh 37.00 38.00 39.00 ? 7658 1827 451 225 112 0.19 105 m lhhl 38.00 39.00 40.00 ? 7607 1818 449 224 112 0.18 106 m lhhm 39.00 40.00 42.00 ? 7607 1818 449 224 112 0.18 107 m lhhh 40.00 42.00 44.00 ? 5709 1373 340 169 84 0.21 108 m mlll 43.30 44.00 46.00 ? 7653 1828 452 225 112 0.18 109 m mllm 44.00 46.00 48.00 ? 7653 1828 452 225 112 0.18 110 m mllh 46.00 48.00 50.00 ? 6155 1477 365 182 91 0.20 111 m mlml 48.00 50.00 52.00 ? 7630 1823 450 225 112 0.18 112 m mlmm 50.52 52.00 54.00 ? 7692 1832 452 225 112 0.20 113 m mlmh 52.00 54.00 56.00 ? 7880 1882 465 232 116 0.18 114 m mlhl 54.00 56.00 58.00 ? 6169 1481 366 183 91 0.20 115 m mlhm 56.00 58.00 60.00 ? 7664 1826 451 225 112 0.20 116 m mlhh 58.00 60.00 60.00 ? 7664 1826 451 225 112 0.20 117 m mmll 60.00 62.00 64.00 ? 7882 1882 465 232 116 0.18 118 m mmlm 62.00 64.00 66.00 ? 7890 1883 465 232 116 0.18 119 m mmlh 64.00 66.00 68.00 ? 7878 1882 465 232 116 0.18 120 m mmml 66.00 68.00 70.00 ? 7878 1882 465 232 116 0.18 121 m mmmm 68.00 70.00 70.88 ? 6228 1494 369 184 92 0.20 122 m mmmh 70.00 72.00 74.00 ? 7888 1883 465 232 116 0.18 123 m mmhl 72.00 74.00 76.00 ? 7889 1883 465 232 116 0.18 124 m mmhm 75.78 76.00 78.00 ? 7917 1884 465 232 116 0.20 125 m mmhh 76.00 78.00 80.00 ? 7895 1883 465 232 116 0.19 126 m mhll 78.00 80.00 84.00 ? 7895 1883 465 232 116 0.19 127 m mhlm 80.00 84.00 88.00 ? 6010 1445 357 178 89 0.20 128 m mhlh 84.00 88.00 88.59 ? 6010 1445 357 178 89 0.20 129 m mhml 88.00 90.00 92.00 ? 6329 1518 375 187 93 0.20 130 m mhmm 90.00 92.00 96.00 ? 7878 1882 465 232 116 0.18 131 m mhmh 92.00 96.00 100.00 ? 7795 1864 461 230 114 0.18 132 m mhhl 96.00 100.00 105.00 ? 7795 1864 461 230 114 0.18 133 m mhhm 101.04 105.00 110.00 ? 7903 1884 465 232 116 0.19 134 m mhhh 105.00 110.00 115.00 ? 7812 1866 461 230 115 0.18 135 m hlll 110.00 115.00 118.13 ? 6329 1518 375 187 93 0.20 table 8. look-up tables for fin = fout frequency range and loop bandwidth settings (continued) frequency range (mhz) bwsel [1:0] (bw in hz) inc/dec phase change (ns) plan no frqtbl frqsel [3:0] min center max lh ml mm mh hl hm note: for bwsel[1:0] settings ll, lm, hh are reserved.
si5317 20 rev. 1.0 136 m hllm 115.00 120.00 125.00 ? 7820 1867 461 230 115 0.18 137 m hllh 120.00 125.00 130.00 ? 7812 1868 462 230 115 0.18 138 m hlml 125.00 130.00 135.00 ? 7878 1882 465 232 116 0.18 139 m hlmm 130.00 135.00 140.00 ? 6873 1648 408 203 101 0.19 140 m hlmh 135.00 140.00 145.00 ? 7851 1871 462 230 115 0.19 141 m hlhl 140.00 145.00 150.00 ? 7826 1870 462 230 115 0.18 142 m hlhm 145.00 150.00 155.00 ? 7240 1735 429 214 107 0.18 143 m hlhh 151.56 155.00 160.00 ? 7853 1872 462 230 115 0.19 144 m hmll 155.00 160.00 165.00 ? 7890 1883 465 232 116 0.18 145 m hmlm 160.00 165.00 170.00 ? 7831 1871 462 231 115 0.18 146 m hmlh 165.00 170.00 175.00 ? 7831 1871 462 231 115 0.18 147 m hmml 170.00 175.00 177.19 ? 6912 1654 409 204 102 0.20 148 m hmmm 175.00 180.00 185.00 ? 7140 1710 423 211 105 0.19 149 m hmmh 180.00 185.00 190.00 ? 7846 1873 463 231 115 0.18 150 m hmhl 185.00 190.00 195.00 ? 7878 1882 465 232 116 0.18 151 m hmhm 190.00 195.00 200.00 ? 7878 1882 465 232 116 0.18 152 m hmhh 195.00 200.00 202.50 ? 6993 1673 414 206 103 0.19 153 m hhll 202.08 210.00 220.00 ? 7903 1884 465 232 116 0.19 154 m hhlm 210.00 220.00 230.00 ? 7069 1689 417 208 104 0.20 155 m hhlh 220.45 230.00 240.00 ? 7903 1884 465 232 116 0.19 156 m hhml 230.00 240.00 250.00 ? 7507 1793 443 221 110 0.19 157 m hhmm 242.50 250.00 260.00 ? 7910 1884 465 232 116 0.19 158 m hhmh 250.00 260.00 270.00 ? 7878 1882 465 232 116 0.18 159 m hhhl 260.00 270.00 280.00 ? 7429 1776 439 219 109 0.19 160 m hhhm 270.00 280.00 290.00 ? 7908 1884 465 232 116 0.19 161 m hhhh 280.00 290.00 300.00 ? 7879 1882 465 232 116 0.18 162 h llll 290.00 300.00 310.00 ? 7571 1811 448 223 111 0.18 163 h lllm 303.13 310.00 320.00 ? 7903 1884 465 232 116 0.19 164 h lllh 310.00 320.00 330.00 ? 7890 1883 465 232 116 0.18 165 h llml 320.00 330.00 340.00 ? 7878 1882 465 232 116 0.18 166 h llmm 330.00 340.00 350.00 ? 7878 1882 465 232 116 0.18 167 h llmh 340.00 350.00 354.38 ? 7344 1757 434 217 108 0.18 168 h llhl 350.00 360.00 370.00 ? 7900 1883 465 232 116 0.19 table 8. look-up tables for fin = fout frequency range and loop bandwidth settings (continued) frequency range (mhz) bwsel [1:0] (bw in hz) inc/dec phase change (ns) plan no frqtbl frqsel [3:0] min center max lh ml mm mh hl hm note: for bwsel[1:0] settings ll, lm, hh are reserved.
si5317 rev. 1.0 21 169 h llhm 360.00 370.00 380.00 ? 7889 1883 465 232 116 0.18 170 h llhh 370.00 380.00 390.00 ? 7878 1882 465 232 116 0.18 171 h lmll 380.00 390.00 400.00 ? 7878 1882 465 232 116 0.18 172 h lmlm 390.00 400.00 405.00 ? 7755 1854 458 228 114 0.18 173 h lmlh 404.17 420.00 440.00 ? 7903 1884 465 232 116 0.19 174 h lmml 420.00 440.00 460.00 ? 7848 1874 463 231 115 0.18 175 h lmmm 440.91 460.00 480.00 ? 7903 1884 465 232 116 0.19 176 h lmmh 460.00 480.00 500.00 ? 7507 1793 443 221 110 0.19 177 h lmhl 485.00 500.00 520.00 ? 7910 1884 465 232 116 0.19 178 h lmhm 500.00 520.00 540.00 ? 7878 1882 465 232 116 0.18 179 h lmhh 520.00 540.00 560.00 ? 7704 1842 455 227 113 0.18 180 h lhll 540.00 560.00 580.00 ? 7908 1884 465 232 116 0.19 181 h lhlm 560.00 580.00 600.00 ? 7879 1882 465 232 116 0.18 182 h lhlh 580.00 600.00 620.00 ? 7571 1811 448 223 111 0.18 183 h lhml 606.25 620.00 640.00 ? 7903 1884 465 232 116 0.19 184 h lhmm 620.00 640.00 660.00 ? 7890 1883 465 232 116 0.18 185 h lhmh 640.00 660.00 680.00 ? 7878 1882 465 232 116 0.18 186 h lhhl 660.00 680.00 700.00 ? 7878 1882 465 232 116 0.18 187 h lhhm 680.00 700.00 704.00 ? 7831 1871 462 231 115 0.18 188 h lhhh 700.00 7.05 710.00 ? 7908 1880 464 231 115 0.20 table 8. look-up tables for fin = fout frequency range and loop bandwidth settings (continued) frequency range (mhz) bwsel [1:0] (bw in hz) inc/dec phase change (ns) plan no frqtbl frqsel [3:0] min center max lh ml mm mh hl hm note: for bwsel[1:0] settings ll, lm, hh are reserved.
si5317 22 rev. 1.0 3.3. pll self-calibration an internal self-calibration (ical) is performed before operation to optimize loop parameters and jitter performance. while the self-calibration is being performed, the dspll is being internally controlled by the self- calibration state machine. the lo l alarm will be active during ic al. the self-calibration time t lockhw is given in table 4, ?ac characteristics?. any of the following events will trigger a self -calibration: ? power-on-reset (por) ? release of the external reset pin rst (transition of rst from 0 to 1) ? change in frqsel, frqtbl , bwsel, or rate[1:0] pins ? internal dspll registers out-of-range, indicating the need to relock the dspll in any of the above cases, an ical will be initiated if a valid input clock ex ists with no input alarm. the external crystal or reference clock must also be present for the self-c alibration to begin. if no valid input clock is present, the self-calibration state machine will wait until it app ears, at which time the calibration will start. after a successful ical has been performed with a valid in put clock, no subsequent self -calibrations are performed unless one of the above conditions are met. if the input cl ock is lost following self-calibration, the device enters vco freeze mode. when the input clock returns, the device relocks to the input clock without performing a self- calibration. 3.3.1. input clock stability during internal self-calibration an exit from reset must occur when the selected ckin clock is stable in frequency with a frequency value that is within the device operating range. 3.3.2. self-calibration caused by changes in input frequency if the selected ckin frequency varies by 500 ppm or more within the frequency range defined by frqsel and frqtbl since the last calibration, the device may initiate a self-calibration. 3.3.3. device reset upon powerup, the device internally executes a power-on-r eset (por) which resets the internal device logic. the pin rst can also be used to initiate a re set. the device stays in this state until a valid ckinn is present, when it then performs a pll self-calibration (refer to section 3.3. "pll self-calibration?). 3.3.4. recommended reset guidelines follow the recommended reset guidelines in table 9 that describe when reset should be applied to a device. table 9. si5317 pins and reset pin # si5317 pin name must reset after changing 2frqtbl yes 11 rate0 yes 15 rate1 yes 22 bwsel0 yes 23 bwsel1 yes 24 frqsel0 yes 25 frqsel1 yes 26 frqsel2 yes 27 frqsel3 yes
si5317 rev. 1.0 23 3.4. alarms summary alarms are available to indicate the overall status of the input signals. alarm outputs stay high until all the alarm conditions for that alarm output are cleared. 3.4.1. loss-of-signal the device has loss-of-signal circuitry that continuously monitors ckin for missing pulses. an los condition on ckin causes the los alarm to become active. once a los alarm is asserted, it remains asserted until the input clock is validated over a designated time period. the time to clear los after a valid input clock appears is listed in table 4, ?a c characteristics?. if another error condition on the same input clock is detected during the validation time, then the alarm remains asserted and the validation time starts over. 3.4.1.1. los algorithm the los circuitry divides down each input clock to produce an 8 khz to 2 mhz signal. the los circuitry oversamples this divided down input clock using a 40 mhz clock to search for extended periods of time without input clock transitions. if the los monitor detects twic e the normal number of samples without a clock edge, a los alarm is declared. table 4, ?ac characteristics? gi ves the minimum and maximum amount of time for the los monitor to trigger. 3.4.1.2. lock detect the pll lock detection algorithm indicates the lock st atus on the lol output pin. the algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. if the time between two consecutive phase cycle slips is greater than the retrigger time, the pll is in lock. the lol output has a guaranteed minimum pulse width as shown in table 4 , ?ac characteristics?. the lol pin is also held in the active state during an internal pll calibration. the retrigger time is automatically set based on the pll closed loop bandwidth (see table 10). 3.5. vco freeze the si5317 device features a vco freeze mode wh ereby the dspll is locked to a frequency value. if an los condition exists on the selected input clock, the device freezes the vco. in this mode, the device provides a stable output frequency until the input cloc k returns and is validated. when the device enters vco freeze, the internal oscilla tor is initially held to its last frequency value. 3.5.1. recovery from vco freeze when the input clock signal returns, the device tran sitions from vco freeze to the selected input clock. table 10. lock detect retrigger time pll bandwidth setting (bw) retrigger time (ms) 60?120 hz 53 120?240 hz 26.5 240?480 hz 13.3 480?960 hz 6.6 960?1920 hz 3.3 1920?3840 hz 1.66 3840?7680 hz 0.833
si5317 24 rev. 1.0 3.6. pll bypass mode the si5317 supports a pll bypass mode in which the sele cted input clock is fed directly to both enabled output buffers, bypassing the dspll. internally, the bypass path is implemented with high-speed signaling; however, this path is not a low jitter path and will resu lt in significantly higher jitter on ck out. in pll bypass mode, the input and output clocks will be at the same freq uency. pll bypass mode is useful as a debug tool. the dsbl2_by pin is used to select the pll bypass mode according to t able 11. bypass mode is not supported for cmos clock outputs. figure 6. bypass signal table 11. dsbl2/bypass pin settings dsbl2/bypass function l ckout2 enabled m ckout2 disabled h pll bypass mode w/ ckout2 enabled dspll ? ckin+ ckin? ckout+ ckout? vdd (1.8, 2.5, or 3.3 v) gnd rate[1:0] xa xb f osc f 3 external crystal or reference clock voltage regulator with high psrr ckout+ ckout? dbl2_by sfout[1:0] 2 2 0 1 0 1 pll bypass 2 los lol bwsel[1:0] frqsel[3:0] rst frequency control bandwidth control alarms control frqtbl skew control inc dec
si5317 rev. 1.0 25 4. high-speed i/o 4.1. input clock buffer the si5317 provides differential inputs fo r the ckin clock input. this input is internally biased to a common mode voltage (see table 2, ?dc characteristics?) and can be driv en by either a single-ended or differential source. no additional external bias is required. figure 7 th rough figure 10 show typical inte rface circuits for lvpecl, cml, lvds, or cmos input clocks. note that the jitter generation improves fo r higher levels on ckinn within the limits in table 4, ?ac characteristics?. ac coupling the input clocks is recommended because it removes any issue with common mode input voltages. dc coupling is acceptable if the device driving the si5317 meets all of the in put clock requirements, including the input common mode range and the peak-to-peak swing specifications. figure 7 and figure 8 shows various examples of different input termination arrangem ents. unused inputs can be left unconnected. figure 7. differential lvpecl termination figure 8. single-ended lvpecl termination 40 k c c ckin _ ckin + v icm 300 130 130 3.3 v 82 82 si5317 lvpecl driver ? ? ? ? ? ? 40 k ? 40 k c c ckin _ ckin + v icm 300 130 3.3 v 82 si5317 driver ? ? ? ? 40 k ?
si5317 26 rev. 1.0 figure 9. cml/lvds termination (1.8, 2.5, 3.3 v) figure 10. cmos termination with attenuation and ac-coupling (1.8, 2.5, 3.3 v) 40 k c c ckin _ ckin + v icm 300 100 si5317 cml/ lvds driver ? ? ? 40 k ? cmos driver r1 33 ohms 50 r2 see table r3 150 ohms c1 100 nf r4 150 ohms c2 100 nf v icm ckin+ ckin? r5 40 kohm r6 40 kohm si5317 v dd r2 notes 3.3 v 100 ohm locate r1 near cmos driver 2.5 v 49.9 ohm locate other components near si5317 1.8 v 14.7 ohm recalculate resistor values for other drive strengths additional notes: 1. attenuation circuit limits overshoot and undershoot. 2. not to be used with non-square wave input clocks.
si5317 rev. 1.0 27 4.2. output clock driver the si5317 has a flexible output driv er structure that can dr ive a variety of loads, including lvpecl, lvds, cml, and cmos formats. the signal format is selected for ckou t output using the sfout [1:0] pins. this modifies the output common mode and differential signal swing. see table 2, ?dc characteristics? for output driver specifications. the sfout [1:0] pins are three-level input pins with the states designated as l (ground), m (v dd /2), and h (v dd ). table 12 shows the signal formats based on the supply voltage and the type of load being driven. when sfout = lh for cmos, bypass mode is not supported. figure 11. typical differential output circuit figure 12. typical cmos output circuit (tie ckoutn+ and ckoutn? together) for the cmos setting (sfout = lh), both output pins drive single-ended in-phase signals and should be externally shorted together to obtain the drive st rength specified in table 2, ?dc characteristics?. table 12. output signal format selection (sfout) sfout[1:0] signal format hl cml hm lvds lh cmos lm disabled mh lvpecl ml low-swing lvds all others reserved si5317 rcvr 100 ? z0 = 50 ? z0 = 50 ? ckoutn cmos logic ckoutn optionally tie ckoutn outputs together for greater strength si5317
si5317 28 rev. 1.0 figure 13. disable ckout structure the sfout [1:0] pins can also be used to disable bo th outputs. disabling the output puts the ckout+ and ckout? pins in a high-impedance state relative to v dd (common mode tri-state) while the two outputs remain connected to each other through a 200 ? on-chip resistance (differential impedance of 200 ? ). the maximum amount of internal circuitry is powered down, minimizi ng power consumption and nois e generation (see figure 13). recovery from the disable mode requires additional time as specified in tabl e 4, ?ac characteristics?. sfout[1:0] = ml (output disable) 100 100 + ? ? ckout output from dspll
si5317 rev. 1.0 29 5. crystal/reference clock input the device can use an external crystal or external clock as a reference. if an external clock is used, it must be ac coupled. with appropriate buffers, the same external reference clock can be applied to ckin. although the reference clock input can be driven single ended (see figure 14), the best performance is with a crystal or differential clock source. figure 14. cmos external reference circuit figure 15. sinewave external reference clock input example figure 16. differential external reference clock input example 3.3 v cmos buffer, 8 ma output current 3.3 v 130 ? 150 ? 150 ? xa 10 k ? 0.1 ? f 0.6 v 0.1 ? f xb si5317 for 2.5 v operation, change 130 ? to 82 ? . external clock source 50 ? 0.01 ? f 1.2 v 0.6 v 10 pf si5317 10 k ? xa 0 dbm into 50 ? 0.01 ? f xb 0.1 f lvpecl, cml, etc. 0.01 ? f 1.2 v 0.6 v si5317 xa ? xb 10 k ? 100 0.01 ? f 10 k ?
si5317 30 rev. 1.0 5.1. crystal/reference clock selection an external low-jitter clock or a low-cost crystal is used as part of a fixed-frequency oscillator within the dspll. this external clock is required for the device to perfo rm jitter attenuation. silicon laboratories reco mmends using a high-quality crystal. in vco freeze, the dspll remains locked to this external clock. any changes in the frequency of this clock when the dspll is in vco freeze will be tracked by the output of the device. note that cr ystals can have temperature sensitivities. table 13 shows the recommended crystals. table 13. approved crystals manufacturer part number web address stability initial accuracy txc 7ma1400014 http://www.txc.com.tw 100 ppm 100 ppm connor winfield cs-018-114.285m http://www.conwin.com 100 ppm 100 ppm connor winfield cs-023-114.285m h ttp://www.conwin.com 20 ppm 20 ppm ndk nx3225sa exs00a-cs00871 http://www.ndk.com/en/ 100 ppm 100 ppm ndk nx3225sa exs00a-cs00997 http://www.ndk.com/en/ 20 ppm 20 ppm siward xtl573200nlg- 114.285 mhz-or http://www.siward.com 20 ppm 20 ppm saronix/ecera flb420001 http://www.pericom.com/saronix 100 ppm 100 ppm mtron m1253s071 http://www.mtronpti.com 100 ppm 100 ppm note: while these crystals meet the preceding criteria according to their data sheets, silicon laboratories, inc. does not guarantee operation with the si5317, nor does silicon labo ratories endorse one supplier of crystals over another. contact silicon labs for details and a current list of crystal vendors and recommended part numbers.
si5317 rev. 1.0 31 because the crystal is used as a jitter reference, rapid ch anges of the crystal temperature can temporarily disturb the output phase and frequency. for exam ple, it is recommended that the crystal not be placed close to a fan that is being turned off and on. if a situation such as this is unavoidable, the crystal should be thermally isolated with an insulating cover. 5.1.1. xa/xb clock drift during vco freeze, long-term and temperature-related drift of the xa/xb clock input results in a one-to-one drift of the output frequency. t he stability of the any frequency ou tput is identical to the drif t of the xa/xb frequency. this means that for the most demanding applications where the drift of a crystal is not acceptable, an external temperature-compensated or ovenized oscillator will be required. drift is not an issue unless th e part is in vco freeze. also, the initial accuracy of the xa/ xb oscillator (or crystal ) is not relevant. 5.1.2. xa/xb jitter jitter on the xa/xb input has a roughly one-to-one transfer function to the output jitte r over the bandwidth ranging from 100 hz up to 30 khz. if a crystal is used on the xa/xb pins, this will have low jitter if a suitable crystal is in use. if the xa/xb pins are connected to an external osc illator, the jitter of the exte rnal oscillator may contribute significantly to the output jitter. table 14. xa/xb reference sources and frequencies rate[1:0] type recommended lower limit upper limit hh reserved ? ? ? hm reserved ? ? ? hl reserved ? ? ? mh external clock 114.285 mhz 109 mhz 125.5 mhz mm 3rd overtone crystal 114.285 mhz ? ? ml reserved ? ? ? lh reserved ? ? ? lm external clock 38.88 mhz 37 mhz 41 mhz ll reserved ? ? ?
si5317 32 rev. 1.0 5.1.3. jitter attenuation performance the internal vco uses the xa/xb clock on the xa/xb pins as its reference for jitter attenuation. the xa/xb pins support either a crystal input or an input buffer single-ended or differential clock input, such that an external oscillator can become the reference sour ce. in either case, the device accept s a wide margin in absolute frequency of the xa/xb input (refer to section 3.5.1. "recovery from vco freeze" on page 23). in vco freeze, the si5317's output clock stability matches the cloc k supplied on the xa/xb pins. the extern al crystal or clock must be selected based on the stability requirements of the application if vc o freeze is a key requiremen t. however, care must be exercised in certain areas for optimum performance. fo r examples of connections to the xa/xb pins, refer to section 5. figure 22, ?si5317 typica l application circuit,? on page 36. figure 17. typical xa-xb jitter transfer function -30 -25 -20 -15 -10 -5 0 5 1 10 100 1000 10000 100000 1000000 jitter transfer xa/xb reference to ckout 38.88 mhz clock on xa/xb, rate[1:0]=lm jitter transfer (db) jitter frequency (hz)
si5317 rev. 1.0 33 5.1.4. reference clock frequency based on the application and desired output frequency, care should be exercised in selecting the frequency on the reference used for xa/xb. when the ckout operating frequen cy is close to having a simple integer relationship, significant spurs can occur. for example, compare the spurs when the ckout operating frequency is 622.08 mhz with a reference of 114.285 mhz (see fi gure 21) versus a reference frequency of 38.88 mhz, which is 16 times the xa/xb reference (see figure 18). figure 18. effect of reference frequency on spurs
si5317 34 rev. 1.0 6. power supply filtering this device incorporates an on-chip voltage regulator to po wer the device from supply volt ages of 1.8, 2.5, or 3.3 v. internal core circuitry is driven from the output of this regulator while i/o circ uitry uses the external supply voltage directly. table 4, ?ac characteristics? gi ves the sensitivity of the on-chip oscillator to change s in the supply voltage. the center ground pad under the device must be electr ically and thermally connected to the ground plane. see figure 25, ?ground pad recommended layout,? on page 43. figure 19. typical power supply bypass network figure 20. fin = fout = 155 mhz with 120 hz loop bandwidth, 100 mv, pk-pk supply noise si5317 v dd gnd & gnd pad c 1 ? c 3 c 4 ferrite bead 0.1 uf 1.0 uf system power supply (1.8, 2.5, or 3.3 v) -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 1 10 100 1000 power supply noise to output transfer function power supply noise re jection ratio (db) frequency of power supply noise (khz)
si5317 rev. 1.0 35 7. typical phase noise plots the following is a typical phase noise plot. the clock input source was a rohde and schwarz model sml03 rf generator. the phase noise analyzer was an agilent mo del e5052b. the si5317 operates at 3.3 v with an ac coupled differential pecl output and an ac coupled differ ential sine wave input from the rf generator at 0 dbm. note that, as with any pll, the output jitter that is below th e loop bw is caused by the jitter at the input clock. the loop bw was 120 hz. 7.1. example: sonet oc-192 figure 21. typical phase noise plot note: sonet jitter bands include the sonet skirts. the phase noise plot is brick wall integration. jitter band jitter, rms sonet_oc48, 12 khz to 20 mhz 250 fs sonet_oc192_a, 20 khz to 80 mhz 274 fs sonet_oc192_b, 4 to 80 mhz 166 fs sonet_oc192_c, 50 khz to 80 mhz 267 fs brick wall, 800 hz to 80 mhz 274 fs
si5317 36 rev. 1.0 8. typical application circuit figure 22. si5317 typical application circuit si5317 1. assumes differential lvpecl termination (3.3 v) on clock inputs. 2. denotes tri-level input pins with states designated as l (ground), m (v dd /2), and h (v dd ). 3. for schematic and layout examples, refer to si5317-evb user manual. ckin+ ckin? input clock 1 notes: xa xb crystal option 1: vdd gnd ferrite bead system power supply c 3 c 2 c 1 c 4 0.1 f 0.1 f 0.1 f 1 f 130 ? 130 ? 82 ? 82 ? v dd = 3.3 v clock outputs 0.1 f + ? xa xb ext. refclk+ option 2: 0.1 f ext. refclk? 0.1 f bwsel[1:0] 2 bandwidth select v dd 15 k ? 15 k ? sfout[1:0] 2 signal format select v dd frqsel[3:0] 2 frequency select v dd 15 k ? 15 k ? crystal/ref clk rst reset gnd pad 15 k ? 15 k ? rate[1:0] 2 v dd 15 k ? 15 k ? v dd frqtbl 3 frequency table ckout1+ ckout1? 100 ? 0.1 f ckout2+ ckout2? 100 ? 0.1 f lol pll loss of lock indicator los ckin loss of signal indicator inc dec skew increment skew decrement dbl2_by 2 clock output 2 disable/ bypass mode control
si5317 rev. 1.0 37 9. pin descriptions: si5317 note: pin assignments are preliminary and subject to change. table 15. si5317 pin descriptions pin # pin name i/o signal level description 1rst ilvcmos external reset. active low input that performs external hardware reset of device. resets all internal logic to a known state. clock out- puts are tristated during reset. after rising edge of rst sig- nal, the si5317 will perform an internal self-ca libration when a valid input signal is present. this pin has a weak pull-up. 2 frqtbl i 3-level frequency table. selects frequency table. this pin has a weak pull-up and weak pull-down and defaults to m. some designs may require an external resistor voltage divider when driven by an acti ve device that will tri-state. 3losolvcmos ckin loss of signal. active high loss-of-signal indicator for ckin. once triggered, the alarm will remain active until ckin is validated. 0 = ckin present 1 = los on ckin 5, 10, 32 v dd v dd supply supply. the device operates from a 1.8, 2.5, or 3.3 v supply. bypass capacitors should be associated with the following v dd pins: 5 0.1 f 10 0.1 f 32 0.1 f a 1.0 f should also be placed as close to device as is practical. 1 2 3 29 30 31 32 33 34 35 36 20 21 22 23 24 25 26 27 10 11 12 13 14 15 16 17 4 5 6 7 8 frqtbl nc rst nc los gnd vdd xa vdd rate0 nc nc dbl2_by rate1 ckin+ ckin? nc bwsel0 bwsel1 frqsel1 frqsel2 frqsel3 ckout1? sfout1 gnd vdd sfout0 ckout2- ckout2+ nc gnd pad frqsel0 inc 9 18 19 28 xb lol dec ckout1+
si5317 38 rev. 1.0 7 6 xb xa i analog external crystal or reference clock. external crystal should be conn ected to these pins to use internal oscillator-based referenc e. crystal or reference clock selection is set by the xtal/clock pin. 8,31 gnd gnd supply ground. must be connected to system ground. minimize the ground path impedance for optimal performance of this device. 11 15 rate0 rate1 i 3-level external crystal or reference clock rate. note: see table 14 for settings. 14 dbl2_by i 3-level output 2 disable/bypass mode control. controls enable of ckout2 divider/output buffer path and pll bypass mode. l = ckout2 enabled m = ckout2 disabled h = bypass mode with ckout2 enabled this pin has a weak pull-up and weak pull-down and defaults to m. some designs may require an external resistor voltage divider when driven by an acti ve device that will tri-state. bypass mode is not supported for cmos clock outputs. 16 17 ckin+ ckin? imulti clock input. differential input clock. this in put can also be driven with a single-ended signal. input frequency selected from table 9 on page 22. 18 lol o lvcmos pll loss of lock indicator. this pin functions as the active high pll loss of lock indica- tor. 0 = pll locked 1 = pll unlocked 19 dec i lvcmos skew decrement. this edge-triggered pin decreases the input to output device skew. there is no limit on the range of skew adjustment by this method. detailed operations and timing characteristics for this pin are found in section 3.2, table 8. this pin has a weak pull-down. 20 inc i lvcmos skew increment. this edge-triggered pin increases the input to output device skew. there is no limit on the range of skew adjustment by this method. detailed operations and timing characteristics for this pin are found in section 3.2, table 8. this pin has a weak pull-down. table 15. si5317 pin descriptions (continued) pin # pin name i/o signal level description
si5317 rev. 1.0 39 23 22 bwsel1 bwsel0 i 3-level loop bandwidth select. three level inputs that select the dspll closed loop band- width. see table 9 on page 22 for available settings. these pins have both weak pull-ups and weak pull-downs and default to m. some designs may require an external resistor voltage divider when driven by an acti ve device that will tri-state. 27 26 25 24 frqsel3 frqsel2 frqsel1 frqsel0 frequency select. three level inputs that select the input clock and clock range. see table 9 on page 22. these pins have both weak pull-ups and weak pull-downs and default to m. some designs may require an external resistor voltage divider when driven by an acti ve device that will tri-state. 29 28 ckout1? ckout1+ omulti clock output 1. output signal format is select ed by sfout pins. differential formats supported for lvpecl , lvds, and cml compatible modes. for single-ended cmos format, both output pins drive identical, in-phase clock outputs. 33 30 sfout0 sfout1 i 3-level signal format select. three-level inputs that select the output signal format (com- mon mode voltage and differential swing) for both ckout1 and ckout2. these pins have both weak pull-ups and weak pull-downs and default to m. some designs may require an external resistor voltage divider when driven by an acti ve device that will tri-state.* cmos outputs do not support bypass mode. 34 35 ckout2? ckout2+ omulti clock output 2. output signal format is select ed by sfout pins. differential formats supported for lvpecl , lvds, and cml compatible modes. for single-ended cmos format, both output pins drive identical, in-phase clock outputs. table 15. si5317 pin descriptions (continued) pin # pin name i/o signal level description sfout[1:0] signal format hh reserved hm lvds hl cml mh lvpecl mm reserved ml lvds?low swing lh cmos lm disable ll reserved
si5317 40 rev. 1.0 4,9,12,13, 21,36 nc ? ? no connect. leave floating. make no external connections to this pin for normal operation. gnd pad gnd gnd supply ground pad. the ground pad must provide a low thermal and electrical impedance to a ground plane. *note: lvpecl requires vdd > 2.25 v table 16. si5317 pull-up/-down pin # si5317 pull? 1rst u 2frqtblu, d 11 rate0 u, d 15 rate1 u, d 19 dec d 20 inc d 22 bwsel0 u, d 23 bwsel1 u, d 24 frqsel0 u, d 25 frqsel1 u, d 26 frqsel2 u, d 27 frqsel3 u, d 30 sfout1 u, d 33 sfout0 u, d table 15. si5317 pin descriptions (continued) pin # pin name i/o signal level description
si5317 rev. 1.0 41 10. ordering guide ordering part number output clock freq range device pkg rohs6, pb-free temp range si5317a-c-gm 1?710 mhz 36-lead 6 x 6 mm qfn yes ?40 to 85 c si5317b-c-gm 1?350 mhz 36-lead 6 x 6 mm qfn yes ?40 to 85 c si5317c-c-gm 1?200 mhz 36-lead 6 x 6 mm qfn yes ?40 to 85 c SI5317D-C-GM 1?100 mhz 36-lead 6 x 6 mm qfn yes ?40 to 85 c si5317-evb 1?710 mhz evaluation board note: add an ?r? at the end of the device to denote tape and reel options (i.e., si5317a-c-gmr). table 17. dspll precision clock product selection guide part number control clock inputs/ outputs input frequency (mhz) output frequency (mhz) jitter (12 khz to 20 mhz) pll bandwidth hitless switching digital hold freerun vco freeze signal format package si5315 pin 2/2 0.008 to 644 0.008 to 644 450 fs ms typ 60 hz to 8.4 khz ?? cmos, lvds, lvpecl, cml 36-qfn si5316 pin 2/1 19 to 710 19 to 710 300 fs ms typ 60 hz to 8.4 khz ? 36-qfn si5317 pin 1/2 1 to 710 1 to 710 300 fs ms typ 60 hz to 8.4 khz ? 36-qfn si5319 i 2 c / spi 1/1 0.002 to 710 0.002 to 1417 300 fs ms typ 60 hz to 8.4 khz ?? 36-qfn si5322 pin 2/2 19 to 707 19 to 1050 600 fs ms typ 30 khz to 1.3 mhz ? 36-qfn si5323 pin 2/2 0.008 to 707 0.008 to 1050 300 fs ms typ 60 hz to 8.4 khz ?? 36-qfn si5324 i 2 c / spi 2/2 0.002 to 710 0.002 to 1417 290 fs ms typ 4 to 525 hz ??? 36-qfn si5325 i 2 c/ spi 2/2 10 to 710 10 to 1417 600 fs ms typ 30 khz to 1.3 mhz ? 36-qfn si5326 i 2 c / spi 2/2 0.002 to 710 0.002 to 1417 300 fs ms typ 60 hz to 8.4 khz ??? 36-qfn si5365 pin 4/5 19 to 710 19 to 1050 600 fs ms typ 30 khz to 1.3 mhz ? 100-tqfp si5366 pin 4/5 0.008 to 707 0.008 to1050 300 fs ms typ 60 hz to 8.4 khz ?? 100-tqfp si5367 i 2 c / spi 4/5 10 to 710 10 to 1417 600 fs ms typ 30 khz to 1.3 mhz ? 100-tqfp si5368 i 2 c / spi 4/5 0.002 to 710 0.002 to 1417 300 fs ms typ 60 hz to 8.4 khz ??? 100-tqfp
si5317 42 rev. 1.0 11. package outline: 36-pin qfn figure 23 illustrates the package details for the si5317. table 18 lists the valu es for the dimensions shown in the illustration. figure 23. 36-pin quad flat no-lead (qfn) table 18. package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.80 0.85 0.90 l 0.50 0.60 0.70 a1 0.00 0.02 0.05 ? ? ? 12o b 0.18 0.25 0.30 aaa ? ? 0.10 d 6.00 bsc bbb ? ? 0.10 d2 3.95 4.10 4.25 ccc ? ? 0.08 e 0.50 bsc ddd ? ? 0.10 e 6.00 bsc eee ? ? 0.05 e2 3.95 4.10 4.25 notes: 1. all dimensions shown are in millime ters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline mo-220, variation vjjd. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. ?
si5317 rev. 1.0 43 12. recommended pcb layout figure 24. pcb land pattern diagram figure 25. ground pad recommended layout
si5317 44 rev. 1.0 table 19. pcb land pattern dimensions dimension min max e 0.50 bsc. e5.42 ref. d5.42 ref. e2 4.00 4.20 d2 4.00 4.20 ge 4.53 ? gd 4.53 ? x ? 0.28 y0.89 ref. ze ? 6.31 zd ? 6.31 notes (general): 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. notes (solder mask design): 1. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. notes (stenc il design): 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. notes (card assembly): 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
si5317 rev. 1.0 45 13. si5317 device top mark mark method: laser font size: 0.80 mm right-justified line 1 marking: si5317q customer part number q = speed code: a, b, c, d see ordering guide for options. line 2 marking: c-gm c = product revision g = temperature range ?40 to 85 c (rohs6) m = qfn package line 3 marking: yywwrf yy = year ww = work week r = die revision f = internal code assigned by the assembly hous e. corresponds to the year and work week of the mold date. line 4 marking: pin 1 identifier circle = 0.75 mm diameter lower-left justified xxxx internal code
si5317 46 rev. 1.0 d ocument c hange l ist revision 0.1 to revision 0.15 ? updated corresponding sections and pinouts to add ckout2, inc/dec, an d dbl2_by functionality. ? updated functional block diagram on page 1. ? updated table 2 idd (dd is subscript). ? added differential rise/fall time spec to table 2. ? updated pin assignment symbol and pin description on page 1 and in section 9 to add ckout2, inc/dec, and dbl2_by. ? added section 3.6. "pll bypass mode?. ? updated section 8 diagram to add ckout2 and dbl2_by. ? added additional cmos termination with attenuation figure. ? corrected pin name assignment (pin28) diagram on page 1 and section 9, page 35 to match pin description name. ? updated all the frequency plans in table 8 to provide coverage over the entire frequency range. revision 0.15 to revision 0.2 ? updated bypass mode, esd specifications and absolute max v dd . ? corrected inc/dec pinout. revision 0.2 to revision 1.0 ? removed output short to gndon page 5. ? removed duplicate lock time specification on page 11. ? removed time to clear los alarm on page 11. ? revised spurious noise values. ? revised phase noise values. material material
si5317 rev. 1.0 47 n otes :
si5317 48 rev. 1.0 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/p ages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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