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| 1/14 www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. regulators ics for digital cameras and camcorders system switching regulator ics with built-in fet (10v) bd9739kn, BD9740KN description the 7-channel switching regulators include built-in fets , and are designed for use in digital still cameras. they feature built-in power fets and soft start functi onality, reducing the number of external components. features 1) wide supply voltage range: 1.5 v to 10 v 2) high-precision reference voltage: 1% 3) built-in shutdown circuit for overload (timer-latch type) 4) oscillator frequency is user-adjustable 5) built-in thermal shutdown circuit 6) standby mode current: 0 a 7) built-in load switch circuit 8) selectable step-up/step-down mode 9) supports inverting circuit for negative output voltage 10) support a constant-current le d drive for backlight applications 11) includes multiple synchronous rectification channels applications digital still cameras, portable dvd players, and digital video cameras. product lineup parameter bd9739kn BD9740KN input voltage 1.5 v to 10 v 1.5 v to 10 v reference voltage precision 1 v 1% 1 v 1% operating frequency range 100 k to 1.2 mhz 100 k to 1.2 mhz step-up 3ch 2ch step-down 2ch 1ch step-up/step-down switch regulator 1ch 3ch inverting 1ch 1ch built-in fet 3ch 1ch synchronous rectification 3ch 2ch load switching 3ch ? operating temperature range -20 to +85 -20 to +85 package uqfn64 uqfn48 no.10036eat07
technical note 2/14 www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. bd9739kn,BD9740KN absolute maximum ratings parameter symbol ratings unit bd9739kn BD9740KN maximum supply voltage vbat,vcc,pvcc -0.3 to +12 -0.3 to +12 v pvcch,pvccl -0.3 to +15 -0.3 to +15 v drain*h, drain*l -0.3 to +12 -0.3 to +12 v out1b -0.3 to +20 -0.3 to +20 v out2b -0.3 to +17 D v swout1,4,pgin1,pg2,3 -0.3 to +12 D v swin* -0.3 to +20 D v power dissipation pd uqfn64 uqfn48 mw 550 *1-2 500 *1-3 1000 *2-2 760 *2-3 operating temperature range topr -25 +85 storage temperature range tstg -55 +125 junction temperature t jmax +125 *1: ic without heat sink operation. reduce by 5.5 mw/ (1-2), or 5.0 mw/ (1-3) when ta 25 . *2: when mounted on a pcb (70 mm ? 70 mm ? 1.6 mm (thickness), glass epoxy). reduced by 10.0 mw/ (2-2), or 7.6 mw/ (2-3), when ta 25 . recommended operating ranges parameter symbol ratings unit bd9739kn BD9740KN supply voltage vbat 1.5 to 10 1.5 to 10 v vcc, pvcc 1.5 to 10 2.8 to 10 v pvccl, pvcch 4.0 to 14 4.0 to 14 v parameter symbol ratings unit conditions min. typ. max. [oscillator] oscillating frequency f osc 0.1 ? 1.2 mhz [driver block] drain pin input voltage v drain ? ? 10 v n-channel fet output current (step-down) i ofet1 ? ? 700 ma n-channel fet output current (step-up) i ofet2 ? ? 300 ma led channel output current i oled ? ? 40 ma driver output current i out ? ? 30 ma external fet drive circuit driver peak current i peak ? ? 200 ma external fet drive circuit startup npn tr sink current i npnsink ? ? 500 ma [positive/negative regulators] swout1 pin sink current i swout1 ? ? 10 ma pgout1 pin source current i pgout1 ? ? 100 ma pg23 pin sink current i pg23 ? ? 1 ma swout4 pin source current i swout4 ? ? 50 ma (bd9739kn) swout6 pin source current i swout6 ? ? 50 ma swout7 pin source current i swout7 ? ? 50 ma technical note 3/14 www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. bd9739kn,BD9740KN electrical characteristics (unless otherwise specified, ta = 25 , vbat = 3 v, vcc = 5 v, rt = 11 k ? , ct = 180 pf, stb1 to stb7 = 3 v) parameter symbol limits unit conditions min. typ. max. [reference voltage, reference voltage for inverting] output voltage v ref2 0.99 1.0 1.01 v line regulation dv li 4.0 12.5 mv vcc = 3.0 v to 9.5 v load regulation dv lo 1.0 7.5 mv iref = 10 a to 100 a output current when shorted i os 0.2 1 ma vref = 0 v [internal regulator] output voltage rega v rega 2.4 2.5 2.6 v ireg = 1 ma [under voltage lockout circuit] detection threshold voltage 1 v std1 3.45 3.6 3.75 v pvccl monitor hysteresis width 1 v st1 300 mv detection threshold voltage 2 v std2 2.3 2.4 2.5 v vcc monitor hysteresis width 2 v st2 200 mv detection threshold voltage 3 v std3 2.0 v vrega monitor hysteresis width 3 v st3 50 mv [startup circuit block] oscillating frequency f start 50 120 220 khz operation start vbat voltage v st1 1.5 v vbat pin monitor soft start charge current i ss1 1.1 2.2 3.3 a vss1 = 0 v [short protection circuit ] timer threshold voltage v tc 2.1 2.2 2.3 v fb pin monitor scp pin source current i scp 0.5 1.0 1.5 a vscp = 0.1 v 2 4 6 (BD9740KN) scp pin detection voltage v tsc 0.45 0.50 0.55 v 0.9 1.0 1.1 (BD9740KN) scp pin standby voltage v ssc 22 170 mv [triangular waveform oscillator] oscillating frequency f osc1 450 500 550 khz rt = 11 k ? , ct = 180 pf frequency stability df 0.3 2 % vcc = 3.0 v to 9.5 v rt pin voltage v rt 0.78 1.00 1.22 v [soft start 23 block] (bd9738kn, bd9739kn) soft start charge current i ss23 5 10 15 a vss23 = 0 v [error amp] low-level output voltage v ol 1.3 v inv = 2 v high-level output voltage v oh v rega - 0.3 v inv = 0 v output sink current i oi 36 72 a fb = 1.7 v, vinv = 1.1 v output source current i oo 36 72 a fb = 1.7 v, vinv = 0.9 v dtc pin upper resistance r dtcu 20 30 40 k (BD9740KN) dtc pin lower resistance r dtcd 65 95 125 k (BD9740KN) non pin input range i res -0.3 - 1.5 v non-inverted pin reference voltage v non7 0.2 v [pwm comparator] input threshold voltage v t0 1.49 v 0% duty v t100 1.95 v 100% duty max duty d max1 77 85 93 % vinv = 0.9 v, vscp = 0 v max duty (step-up operation) d max2 77 85 93 % vinv = 0.9 v, vscp, udsel = 0 v [output circuit] high-level output voltage v sath v cc -1.6 v cc -0.8 v io = 30 ma low-level output voltage v satl 0.8 1.6 v io = -30 ma high-side n-channel fet on resistance r onh 270 500 m pvcch = 5 v(io = 200 ma) 300 500 (BD9740KN) low-side n-channel fet on resistance r onl 270 500 m pvccl = 5 v(io = 200 ma) 300 500 (BD9740KN) ch7 n-channel fet on resistance r onl7 0.7 1.4 pvccl = 5 v(io = 50 ma) [step-up/step-down selector ] udsel pin control voltage step-down v uddo v cc 0.7 v cc v step-up v udup 0 v cc 0.3 v note: this ic is not designed to be radiation-resistant. technical note 4/14 www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. bd9739kn,BD9740KN (unless otherwise specified, ta = 25 , vbat = 3 v, vcc = 5 v, rt = 11 k , ct = 180 pf, stb1 to stb7 = 3 v) parameter symbol limits unit conditions min. typ. max. [power on switching block] (bd9739kn) swout1 output voltage v sat 0.1 0.3 v io = 1 ma leak current i leak 0 5 a stb = 0 v swout4 output voltage v sat 0.1 0.3 v io = 100 a leak current i leak 0 5 a stb = 0 v swout4,6 output voltage v sat v swin6 - 0.3 v swin6 - 0.1 v io = 20 ma vswin = 5 v leak current i leak 0 5 a stb = 0 v swout7 output voltage v sat v swin7 - 0.3 v swin7 - 0.1 v io = 10 ma vswin = 10 v leak current i leak 0 5 a stb = 0 v [soft start block] (BD9740KN) soft start time of ch4 t ss1 1.8 3.6 6.0 mse c vcc = pvcc = 5v, pvcch = 5.0v stb 0 3 v soft start time of ch2, 3 t ss2 1.8 3.6 6.0 mse c vcc = pvcc = 5v, stb = 3 v inv4 = 0 1.2 v ch2, ch3 soft start inv4 threshold voltage at start v pg4 0.72 0.80 0.88 v vcc = pvcc = 5 v pvcch = 5.0 v [stb1 to stb7] stb pin control voltage on v stbh 2.0 11 v stb off v stbl -0.3 0.3 v stb pin pull-down resistance r stb 250 400 700 k stb [circuit current] standby current 1 (vbat pin sink current) i stb1 5 a stb1 to stb7 = 0 v standby current 2 (vcc, pvcc pin sink current) i stb2 5 a stb1 to stb7 = 0 v circuit current at startup (vbat pin sink current) i st 30 100 ma ct = 1.7 v vcc = 0 v circuit current 1 (vbat pin sink current) i cc1 100 300 a ct = 1.7 v circuit current 2 (vcc, pvcc pin sink current) i cc2 5 15 ma ct = 1.7 v inv = 2.5 v note: this ic is not designed to be radiation-resistant. pvcch and pvccl input voltages ? synchronous rectification channels with built-in fets include, n-channel fets for both the high-side and low-side config uration. the driver block's power source is supplied to the pvccl pin for the low-side and the pvcch pin for the high-side. (for the BD9740KN, both sides are supplied to the pvcch pin.) in order to turn the fet on, a potential of at least 4 v must be supplied to the pvccl pin, and a potential of at l east, drainh pin voltage + 4 v, must be supplied to the pvcch pin. note: ? the breakdown voltage for the pvccl and pvcch pins is 15 v. for applications that with voltages exce eding 15 v, add a zener diode, or other components, to provide overvoltage protection. ? shorting the drainh pin with the ground, while a charge remains in the output capacitor, may cause unexpected current flow, resulting in damage to the ic. add an external protective diode for applications where this possibility exists. fig. 1 synchronous rectification channel with built-in fet pgnd drainh pvcch pvccl drainl vo technical note 5/14 www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. bd9739kn,BD9740KN block diagram and application circuit (bd9739kn) fig. 2 bd9739kn application circuit the soft start times for ch4, 6, 7 are fixed internally. (see page 9.) set the operating frequency with the rt and ct pins. (see page 8.) this pin is used as the on/off control pin. (see page 7.) set whether ch1 and ch5 will be used as step-up, step-down or inversion. (see page 7.) connect a resistor for setting the output voltage. (see page 8.) connect a capacitor to prevent oscillation to the vref pin. (see page 7.) connect a capacitor to prevent oscillation to the vrega pin. (see page 7.) for more information about setting the scp pin, (see page 7.) apply the pvcch pin voltage with an external charge pump. (see page 4.) connect a capacitor for soft start at dtc pin. (see page 8.) connect a capacitor for setting the soft start time. (see pages 8& 9.) technical note 6/14 www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. bd9739kn,BD9740KN block diagram and application circuit (2) BD9740KN the soft start times for ch2 to ch4 are fixed internally. (see page 9.) connect a capacitor to prevent oscillation to the vref pin. (see page 7.) connect a capacitor to prevent oscillation to the vrega pin. ( see p a g e 7. ) for more information about setting the scp pin, see p a g e 7. apply the pvcch pin voltage with an external charge pump. (see page 4.) connect a capacitor for setting the soft start time. (see page 8&9.) set the operating frequency with the rt and ct pins. ( see p a g e 8. ) this pin is used as the on/off control pin. ( see p a g e 7. ) set whether ch1, ch2, and ch3 will be used as step-up or step-down. ( see p a g e 7. ) connect a resistor for setting the output voltage. (see page 8.) connect a capacitor for soft start at tc pin. (see page 8.) fig. 3 BD9740KN application circuit technical note 7/14 www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. bd9739kn,BD9740KN bd9739kn pin no. pin no. pin name pin no. pin name pin no. pin name 61 vbat 60 out1b 44,36 non5,7 29 vcc 4,5,12,13 drain2,3h 28 ss1 54 pvcc 6,7,10,11 drain2,3l 25 ss23 14 pvcch 55 out1m 34 rt 59 pvccl 56 out1s 33 ct 8,9,57 pgnd23,pgnd 35 vref 32 scp 42 gnd 43 dtc 5 1,64 udsel1,5 30 vrega 26,24,21,47,46,41,39 fb 1 7 15,16,17,18,19,20 stb 1,23,4,5,6,7 51,52,53 out4,5,6 27,23,22,48,45,40 inv 1 6 50,2,62 swin4,6,7 58 out7b 37,38 inv7i,inv7v 31,49,3,63 sw out 1,4,6,7 BD9740KN pin no. pin no. pin name pin no. pin name pin no. pin name 4 vbat 44 main2 30,37 non6,non7 21 vcc 43 sub2 17 ss1 46 pvcc 5 out1b 23 rt 10 pvcch 9 drain4h 24 ct 42 pgnd 8 drain4l 25 scp 6,7 pgnd4 20 vr ef 1 udsel12 31 gnd 3,38,39 dtc 5 7 2 udsel3 22 vrega 16,18,27,28,32,35,36 fb 1 7 11,12,13,14 stb1,234,56,7 40,41,45,47,48 out1,3,5,6,7 15,19,26,29,33,34 inv 1 5,7 block diagram explanation and setting peripheral ic components 1. voltage reference (vref) vref is the reference voltage s ource of 1.0v output voltage. connect a capacitor to prevent oscillation. set the capacitance from 1.0 f to 10 f. 2. rega rega and regd are regulators with output voltages of 2.5 v. rega is used as the power supply for the ic's internal blocks.connect a capacitor to prevent osc illation. set the ca pacitance from 4.7 to 10 f. 3. udsel to enable step-up mode, connect vcc to the udsel pin. to enable step-up mode connect 0v to the udsel pin. when using the startup circuit, set the pin to step-up mode. be cause the pin uses coms inverter input, you must connect the pin to either gnd or vcc in order to prevent undefined input. 4. on/off logic the voltage applied to the stb pins can be controlled whether each channel is on or off. ch1, ch4, and ch5 can be controlled independently, while ch2 and ch3 can be controlled simultaneously. applying a voltage of over 2 v turns on the corresponding channel (s), while leaving the pin open or applying 0 v turns off the corresponding channel(s). turning off all channels causes the ic to be in a standby state. each pin is connected to gnd by a 400 k ? pull-down resistor. 5. setting the short protection detection time the detection time can be set when the capacitor is connected to the scp pin. when the detection time is reached, the latch circui t operates, turning off the output for all channels. to reset the latch circuit, turn all stb pins off, and then back on again. detection time (sec) = cscp ? vtsc / iscp (cscp: capacitance; vtsc: scp pin detection voltage, iscp: scp pin source current) *set the capacitor that is conn ected to the scp pin from 0.001 f to 2.2 f. technical note 8/14 www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. bd9739kn,BD9740KN 6. setting the oscillating frequency the oscillating frequency can be set by connecting the resi stance value to the rt pin and connecting the capacitance value to the ct pin. oscillating frequency = vrt / (ct ? rt) (unit: hz) *set the resistance value, connec ted to the rt pin, from 4.7 k ? to 30 k ? *set the capacitance value, connected to the ct pin, from 100 pf to 10,000 pf. (vrt: rt pin voltage; ct: osc timing ca pacitance; rt: osc timing resistance) 7. startup channel soft-start operation the startup channel's soft start can be controlle d by the capacitor connected to the ss1 pin. times can be determined with the following equation: startup time (sec) = (vss / iss) ? css (vss = ss pin voltage [= 0.7 v], iss = soft start charge current [= approximately 2.0 a]; css = capacitor capacitance) example: when css = 0.01 f, startup time = 0.7 / (2.0 ? 10-6) ? (0.01 ? 10-6) = 3.5 ms *set the capacitance value, connec ted to the ss1 pin, from 0.001 f to 2.2 f. 8. swout1 pin (bd9734kn/bd9738kn/bd9739kn) to prevent current from flowing from vo ut1 to the feedback resistor, during standby operation, connect the ground side of ch1's feedback resistor to swout1. 9. soft start operation depending on ss pins (bd9739kn) soft start operation for ch2 and ch3 can be controlled by the capacitor connected to the ss23 pins. times can be determined with the following equation:startup time (sec) = (vss / iss) ? css23 (vss: ss pin voltage [= 1.0 v]; iss: soft start charge current [= approximately 10 a]; css: capacitance) *startup of ch2 begins when ch3 out put reaches approximately 70%. *set the capacitance value, connec ted to each ss23 pin, from 0.005 f to 1.0 f. 100 1000 100 1000 ct pin capacitance [pf] oscilating frequency: fosc [khz] 11k ? 20k ? 30k ? stby1 ss1 vcc vrega out1b drain1l approximately 0.7 v vcc vrega fb osc vref=1.0 v startup osc (approximately 100 khz) (startup block main) approximately 0.5 v (startup block repeat oscillation prohibited) approximately 1.0 v vcc output voltage waveform ss pin voltage waveform 100 1000 rt pin resistance[k ? ] 10 100 oscilating frequency [khz] 100pf 180pf 330pf fig. 4 oscillating frequency versus rt pin resistance fig. 5 oscillating frequency versus ct pin capacitance fig. 6 startup channel startup waveform (reference data) fig. 7 timing chart fig. 8 dtc external setting circuit ra r1 approximately 30 k ? rb vrega vrega dtc r2 approximately 93 k ? technical note 9/14 www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. bd9739kn,BD9740KN 10. setting max duty the dtc voltage is determined by the internal r1 and r2 resistance values. the dtc voltage can be changed by connecting resistance values that are from 1 to 2 digits smaller than the internal r1 (30 k ? ) and r2 (93 k ? ) resistors, to the ra and rb pins. *the resistors connected to the ra and rb pins should be at least 5 k ? . avoid shorting the vrega and dtc pins. *when vcc falls to 2.8 v or below, a protection circuit will operate to limit max duty in order to prevent the ic from malfunctioning when vrega (the internal circuit power supply) drops. 11. soft start operation triggered by the dtc pin soft start operation can be set by connecting a capacitor to the dtc pin. setting the stby pin to high will cause the capacitor connected to the dtc pin to be charged by the internal pull-up resistor. startup will begin when this voltage reaches the minimum voltage of the ct pin's triangular waveform. *set the capacitance connected to each dtc pin to 10 f or less. 12. internal soft start operation soft start times are set internally for ch4, ch6, and ch7 (bd9739kn); and ch2 to ch4 (BD9740KN). bd9739kn ch4, 6, 7: 2.7 ms BD9740KN ch2 to ch4: 3.6 ms (soft start operation of ch2 and ch3 is del ayed until ch4 reaches approximately 80%.) 13. setting the error amp feedback resistance (1) feedback resistance order (bd9739kn, BD9740KN) error amp differential input is formed by a pnp transistor, wi th the base current of this input flowing into the lower voltage divider resistor. in the worst case, this current may reach 0.2 a. for this reason, when the resistance of the lower resistor is increased, the base current may cause an e rror in the output voltage. for example, resistance values of 40 k ? , 20 k ? , and 10 k ? result in errors of 1%, 0.5%, and 0.25%, respectively. refer to these values when setting the resistance value. (2) setting the inverted channel (bd9739kn, BD9740KN) for the bd9739kn, connect the ch5 error amp reference voltage (inv5) to the ground. for the BD9740KN, the ch6 error amp reference voltage is grounded internally. *it is recommended to use a 10 k ? resistor between vref and ch5 output. use a resistance value from 5 k ? to 20 k ? . technical note 10/14 www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. bd9739kn,BD9740KN i/o equivalent ci rcuit diagrams dtc5 to dtc7 (dead time control) vcc vrega vcc dtc5 dtc6 dtc7 inv2 to inv6, inv7 v (error amp inverted input) vcc inv2 to inv6, inv7v vrega inv1 (error amp inverted input) inv1 vcc vrega vcc rt rt (triangular waveform timing resistor connection) inv7i (error amp inverted input) non7 (error amp non - inverted input) inv7i vcc non7 vref vrega ss1 (startup channel soft start capacitor connection pin) ss1 vcc vcc vbat ct (triangular waveform timing capacitance connection) vcc ct vrega scp (timer latch time setting capacitor connection pin) vcc scp vcc vrega vrega (rega output) vcc vcc vrega vcc udsel (step-up/step-down select input) vcc vcc udsel1 to udsel 5 delay (powergood time constant setting pin) vcc delay vref (reference voltage output) vcc vref vcc vcc fig. 9 i/o equivalent circuit diagrams (1) technical note 11/14 www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. bd9739kn,BD9740KN vcc out7b pgnd4 vcc stby1 to stby7 (ch1 to ch7 on/off control) regon (ccd reg control input) mode (ccd sequence control pin) vcc stby1 to stby7 regon mode 7ch (power transistor drain output) swin (load switch input pin) swout (load switch output pin) fb (error amp output) sync_dtc (synchronous rectification delay time setting pin) pg1in (powergood 1 input) pg1out (powergood switch 1 output) drain1, 2, 3h (power mos drain for ch1, ch2, and ch3) drain1, 2, 3l (power mos drain for ch1, ch2, and ch3) pgnd1, 23 (output step ground) main4 (ch4 main output) sub4 (ch4 sub output) out5 (power transistor connection) out6 (power transistor connection) pvcc (power supply input) pgnd4 (power ground) vbat2 (battery input [driver block]) out1b (ch1 power transistor collector output) swout1, 4 (load switch output pin) pg23 (powergood switch 23 output) swout1, 4 pg23 ss2 (soft start capacitor connection pin) swout4, 6, 7 swin4, 6, 7 pgnd4 pvcc main4 sub4 out5 vbat2 out1b vcc fb1 to fb7 vcc vrega sync_dt c pvcch pg1in pg1out drain1,2,3h vcc drain1,2,3l pgnd1,23 vcc vcc vcc pvcc out6 vcc pgnd4 vcc ss2 vcc vrega fig. 10 i/o equivalent circuit diagrams (2) technical note 12/14 www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. bd9739kn,BD9740KN notes for use 1) absolute maximum ratings an excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. if any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2) reverse polarity connection of the power supply connecting the of power supply in reverse polarity can damage ic. take precautions when connecting the power supply lines. an external direction diode can be added. 3) power supply lines design pcb layout pattern to provide low impedance gnd and supply lines. to obtain a low noise ground and supply line, separate the ground section and supply lines of the digital a nd analog blocks. furthermore, for all power supply terminals to ics, connect a capacitor between the power supply and the gnd terminal. when applying electrolytic capacitors in the circuit, note that capacitance characteristic values are reduced at low temperatures. 4) gnd voltage ground-gnd potential should maintain at the minimum gro und voltage level. furthermore, no terminals should be lower than the gnd potential voltage incl uding an electric transients. 5) thermal design use a thermal design that allows for a suffic ient margin in light of the power dissipa tion (pd) in actual operating conditions. 6) inter-pin shorts and mounting errors use caution when positioning the ic fo r mounting on printed circuit boards. t he ic may be damaged if there is any connection error or if positive and ground power supply termi nals are reversed. the ic may also be damaged if pins are shorted together or are shorted to other circuit?s power lines. 7) operation in a str ong electromagnetic field use caution when using the ic in the presence of a strong electr omagnetic field as doing so may cause the ic to malfunction. 8) aso when using the ic, set the output transistor so that it does not exceed absolute maximum ratings or aso. 9) thermal shutdown circuit (tsd circuit) the ic incorporates a built-in thermal shutdown circuit (tsd circuit). the thermal shutdown circuit (tsd circuit) is designed only to shut the ic off to prevent runaway thermal operation. it is not designed to pr otect the ic or guarantee its operation. do not continue to us e the ic after operating this circuit or use the ic in an environment where the operation of this circuit is assumed. 10) capacitors connected between output and ground pins if a large capacitance value is connected between the output and ground pins, and if the vcc falls to 0 v or becomes shorted with the ground pin, t he current stored in the capacitor may flow to the output pin. this can cause damage to the ic. set capacitors connected between the output and ground pins to values that fall within the recommended range. 11) testing on application boards when testing the ic on an application boar d, connecting a capacitor to a pin with low impedance subjects the ic to stress. always discharge capacitors after each process or step. always turn the ic's power supply off before connecting it to, or removing it from a jig or fixture, dur ing the inspection process. ground the ic during assembly steps as an antistatic measure. use similar precaution w hen transporting and storing the ic. 12) regarding input pin of the ic (fig 11) this monolithic ic contains p + isolation and p substrate layers between adjacent elements to keep them isolated. p?n junctions are formed at the intersection of these p layers with the n layers of ot her elements, creating a parasitic diode or transistor. for example, the relation be tween each potential is as follows: when gnd > pin a and gnd > pin b, the p?n junction operates as a parasitic diode. when pin b > gnd > pin a, the p?n junction operates as a parasitic transistor. parasitic diodes can occur inevitably in t he structure of the ic. the operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the gnd (p substrate) voltage to an input pin, should not be used. technical note 13/14 www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. bd9739kn,BD9740KN 13) ground wiring patterns the power supply and ground lines must be as short and thi ck as possible to reduce line impedance. fluctuating voltage on the power ground line may damage the device. 14) stb pin voltage set the stb pin voltage to 0.3 v or lower when setting channel s to a standby state, or to 2.0 v or higher when setting channels to an operational state. do not lengthen transition times or fix the stb pin voltage to values higher than 0.3 v or lower than 2.0 v. doing so may cause the ic to malfunction. 15) common supply voltage use a common supply voltage for both the driver block and the ma in block. the ic is not compatible with applications requiring the driver block to be used while applying user-selected voltages. 16) setting the max duty max duty limitations may not operate when using the ic at high frequencies. when using the ic in such applications, allow for sufficient margins when setting external components. fig. 11 example of simple bipolar ic architecture parasitic elements parasitic elements ( pin a ) gnd parasitic elements parasitic elements gnd (pin b) b c e other adjacent elements transistor (npn) gnd pcb n p n n p p (pin b) b n e c gnd pcb n p n n p p (pin a) resistor technical note 14/14 www.rohm.com 2010.09 - rev. a ? 2010 rohm co., ltd. all rights reserved. bd9739kn,BD9740KN ordering part number b d 9 7 3 9 k n - e 2 part no. part no. 9739 9740 package kn: uqfn64 uqfn48 packaging and forming specification e2: embossed tape and reel (unit : mm) uqfn64 notice : do not use the dotted line area for soldering 0.05 m 0.05 8.0 0.1 8.2 0.1 8.0 0.1 8.2 0.1 0.22 0.05 0.95max 0. 2 0.05 64 49 48 33 16 1 32 17 (1.1) 0.02 +0.03 - 0.02 ( 0. 2) 4 ? (0. 3 5) 0.4 0.6 +0.1 - 0.3 ? order quantity needs to be multiple of the minimum quantity. r1010 a www.rohm.com ? 2010 rohm co., ltd. all rights reserved. notice rohm customer support system http://www.rohm.com/contact/ thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact us. notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of rohm co.,ltd. the content specied herein is subject to change for improvement without notice. the content specied herein is for the purpose of introducing rohm's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specications, which can be obtained from rohm upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specied in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, rohm shall bear no responsibility for such damage. the technical information specied herein is intended only to show the typical functions of and examples of application circuits for the products. rohm does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by rohm and other parties. rohm shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specied in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, ofce-automation equipment, commu- nication devices, electronic appliances and amusement devices). the products specied in this document are not designed to be radiation tolerant. while rohm always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, re or any other damage caused in the event of the failure of any product, such as derating, redunda ncy, re control and fail-safe designs. rohm shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospac e machinery, nuclear-reactor controller, fuel- controller or other safety device). rohm shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specied herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. |
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