1 file number 4563.3 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | copyright intersil corporation 2000 HS-4080ARH radiation hardened full bridge n-channel fet driver the HS-4080ARH is a monolithic, high frequency, medium voltage full bridge n-channel fet driver ic. the device includes a ttl-level input comparator, which can be used to facilitate the ?ysteresis?and pwm modes of operation. its hen (high enable) lead can force current to freewheel in the bottom two external power mosfets, maintaining the upper power mosfets off. the HS-4080ARH is well suited for use in distributed dc power supplies and dc to dc converters, since it can switch at high frequencies. these devices can also drive medium voltage motors, and two HS-4080ARHs can be used to drive high performance stepper motors, since the short minimum ?n-time?can provide ?e micro-stepping capability. short propagation delays maximize control loop crossover frequencies and dead-times, which can be adjusted to near zero to minimize distortion, resulting in precise control of the driven load. constructed with the intersil dielectrically isolated rad hard silicon gate (rsg) process, these devices are immune to single event latch-up and have been speci?ally designed to provide highly reliable performance in harsh radiation environments. complete your design with radiation hardened mosfets from intersil. speci?ations for rad hard qml devices are controlled by the defense supply center in columbus (dscc). the smd numbers listed here must be used when ordering. detailed electrical speci?ations for these devices are contained in smd 5962-99617. a ?ot-link?is provided on our homepage for downloading. http://www.intersil.com/spacedefense/space.htm pinout HS-4080ARH (flatpack, cdfp3-f20) top view features electrically screened to smd # 5962-99617 qml quali?d per mil-prf-38535 requirements radiation environment - gamma dose . . . . . . . . . . . . . . . . . 300krad(si) (max) - latch-up immune rsg di process drives n-channel fet full bridge including high side chop capability bootstrap supply max voltage to 95v dc ttl comparator input levels drives 1000pf load with rise and fall times of 50ns user-programmable dead time charge-pump and bootstrap maintain upper bias supplies dis (disable) pin pulls gates low operates from single supply . . . . . . . . . . . . . 12v to 18v low power consumption undervoltage protection applications full bridge power supplies pwm motion control 2 3 4 5 6 7 8 120 19 18 17 16 15 14 13 bhb hen dis vss out in+ in- hdel 9 10 12 11 ldel ahb bho bhs blo bls vdd vcc als alo ahs aho ordering information ordering number internal mkt. number temp. range ( o c) 5962f9961701vsc hs9-4080arh-q -55 to 125 5962f9961701qsc hs9-4080arh-8 -55 to 125 hs9-4080arh/proto hs9-4080arh/proto -55 to 125 data sheet febuary 2000
2 HS-4080ARH preliminary pin descriptions pin number symbol description 1 bhb b high-side bootstrap supply. external bootstrap diode and capacitor are required. connect cathode of boot-strap diode and positive side of bootstrap capacitor to this pin. internal charge pump supplies 50 a out of this pin to maintain bootstrap supply. internal circuitry clamps the bootstrap supply to approximately 15v. 2 hen high-side enable input. logic level input that when low overrides in+/in- (pins 6 and 7) to put aho and bho drivers (pins 11 and 20) in low output state. when hen is high aho and bho are controlled by in+/in- inputs. the pin can be driven by signal levels of 0v to 18v (no greater than v dd ). an internal 100 a pull-up to v dd will hold hen high, so no connection is required if high-side and low-side outputs are to be controlled by in+/in -inputs. 3 dis disable input. logic level input that when taken high sets all four outputs low. dis high overrides all other inputs. when dis is taken low the outputs are controlled by the other inputs. the pin can be driven by signal levels of 0v to 18v (no greater than v dd ). an internal 100 a pull-up to v dd will hold dis high if this pin is not driven. 4v ss chip negative supply, generally will be ground. 5 out output of the input control comparator. this rail to rail output signal can be used for feedback and hysteresis. 6 in+ noninverting input of control comparator. this pin can only be driven by signal levels of 0v to 5.5v. if in+ is greater than in- (pin 7) then alo and bho are low level outputs and blo and aho are high level outputs. if in+ is less than in- then alo and bho are high level outputs and blo and aho are low level outputs. dis (pin 3) high level will override in+/in- control for all outputs. hen (pin 2) low level will override in+/in- control of aho and bho. when switching in four quadrant mode, dead time in a half bridge leg is controlled by hdel and ldel (pins 8 and 9). 7 in- inverting input of control comparator. this pin can only be driven by signal levels of 0v to 5.5v. see in+ (pin 6) description. 8 hdel high-side turn-on delay. connect resistor from this pin to v ss to set timing current that de?es the turn-on delay of both high-side drivers. the low-side drivers turn-off with no adjustable delay, so the hdel resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. hdel reference voltage is approximately 5.1v. 9 ldel low-side turn-on delay. connect resistor from this pin to v ss to set timing current that de?es the turn-on delay of both low-side drivers. the high-side drivers turn-off with no adjustable delay, so the ldel resistor guarantees no shoot- through by delaying the turn-on of the low-side drivers. ldel reference voltage is approximately 5.1v. 10 ahb a high-side bootstrap supply. external bootstrap diode and capacitor are required. connect cathode of boot-strap diode and positive side of bootstrap capacitor to this pin. internal charge pump supplies 30 a out of this pin to maintain bootstrap supply. internal circuitry clamps the bootstrap supply to approximately 15v. 11 aho a high-side output. connect to gate of a high-side power mosfet. 12 ahs a high-side source connection. connect to source of a high-side power mosfet. connect negative side of bootstrap capacitor to this pin. 13 alo a low-side output. connect to gate of a low-side power mosfet. 14 als a low-side source connection. connect to source of a low-side power mosfet. 15 v cc positive supply to gate drivers. must be same potential as v dd (pin 16). connect to anodes of two bootstrap diodes. 16 v dd positive supply to lower gate drivers. must be same potential as v cc (pin 15). de-couple this pin to v ss (pin 4). 17 bls b low-side source connection. connect to source of b low-side power mosfet. 18 blo b low-side output. connect to gate of b low-side power mosfet. 19 bhs b high-side source connection. connect to source of b high-side power mosfet. connect negative side of bootstrap capacitor to this pin. 20 bho b high-side output. connect to gate of b high-side power mosfet. HS-4080ARH
3 application block diagram typical application (hysteresis mode switching) 80v gnd HS-4080ARH gnd 12v load bho bhs blo alo ahs aho in- in+ dis hen 6v 80v 12v 12v dis in gnd 6v gnd + - 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 bhb hen dis v ss out in+ hdel in- ldel ahb bho blo bls v dd bhs v cc als alo ahs aho load HS-4080ARH HS-4080ARH
4 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com die characteristics die dimensions: 4760 m x 5660 m (188 mils x 223 mils) thickness: 483 m 25.4 m (19 mils 1 mil) interface materials: glassivation: type: phosphorus silicon glass thickness: 8.0k ? 1.0k ? top metallization: type: alsicu thickness: 16.0k ? 2k ? substrate: radiation hardened silicon gate, dielectric isolation backside finish: silicon assembly related information: substrate potential: unbiased (di) additional information: worst case current density: <2.0 x 10 5 a/cm 2 transistor count: 432 metallization mask layout HS-4080ARH 15 14 13 12 11 10 9 8 7 6 16 17 18 19 20 1 2 3 4 5 HS-4080ARH
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