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publication release date: april 2007 - 1 - revision b14 w681310 3v single-channel voiceband codec data sheet
w681310 - 2 - 1. general description the w681310 is a general-purpose single channel pcm codec with pin-selectable -law or a-law companding. the device is compliant with the itu g.712 specification. it operates from a single +3v power supply and is available in 20-pin s og, ssop and tssop package options. functions performed include digitization and reconstruction of voice signals, and band limiting and smoothing filters required for pcm systems. w681310 performance is specified over the industrial temperature range of ?40 c to +85 c. the w681310 includes an on-chip precision voltage reference and an additional power amplifier, capable of driving 300 loads differentially up to a level of 3.544v peak-to-peak. the analog section is fully differential, reducing noise and improving t he power supply rejection ratio. the data transfer protocol supports both long-frame and short- frame synchronous communications for pcm applications, and idl and gci communications for isdn applications. w681310 accepts eight master clock rates between 256 khz and 4.800 mhz, and an on-ch ip pre-scaler automatically determines the division ratio for the required internal clock. for fast evaluation and prototyping purposes, the w681310dk development kit is available. 2. features ? single +3v power supply (2.7v to 5.25v) ? typical power dissipation of 10 mw, power-down mode of 0.5 w ? fully-differential analog circuit design ? on-chip precision reference of 0.886 v for a -5 dbm tlp at 600 ? push-pull power amplifiers with external gain adjustment with 300 load capability ? eight master clock rates of 256 khz to 4.800 mhz ? pin-selectable -law and a-law companding (compliant with itu g.711) ? codec a/d and d/a filtering compliant with itu g.712 ? industrial temperature range (?40 c to +85 c) ? packages: 20-pin sog (sop), ssop and tssop ? pb-free package options available ? applications ? voip, voice over networks ? digital telephone and communication systems ? wireless voice devices ? pabx/soho systems ? local loop card ? soho routers ? fiber-to-curb equipment ? enterprise phones ? isdn equipment ? modems/pc cards ? digital voice recorders
w681310 publication release date: april 2007 - 3 - revision b14 3. block diagram 256 khz, 512 khz, 1536 khz, 1544 khz, 2048 khz, 2560 khz 4096 khz mclk 256 khz 8 khz 512 khz pre - scaler v dd v ss power conditioning voltage reference v ag pui g.712 codec g.711 /a -law pao+ pao- pai ro - ao ai+ ai- /a - law tra ns mit pc m int erf ace re cei ve pc m int erf ace fst bclkt pcmt fsr bclkr pcmr v ref 256 khz, 512 khz, 1536 khz, 1544 khz, 2048 khz, 2560 khz mclk 256 khz 8 khz pre - scaler power conditioning voltage reference v ag g.712 codec g.711 /a -law ro /a - law g.712 codec g.711 /a -law ro /a - law transmit pcm interface receive pcm interface bclkt bclkt bclkr v & 4800 khz
w681310 - 4 - 4. table of contents 1. general d escription......................................................................................................... ......... 2 2. features .................................................................................................................... ..................... 2 3. block diagram ............................................................................................................... ............... 3 4. table of cont ents ........................................................................................................... ........... 4 5. pin conf igurati on ........................................................................................................... ............ 6 6. pin des cription ............................................................................................................. ................ 7 7. functional descript ion...................................................................................................... ...... 8 7.1. trans mit path ............................................................................................................. ................... 8 7.2. rece ive path .............................................................................................................. ................... 9 7.3. powe r managem ent.......................................................................................................... ............. 9 7.3.1. analog and digital supply ............................................................................................... ...... 10 7.3.2. analog ground reference bypass ....................................................................................... 10 7.3.3. analog ground refe rence volt age outp t ............................................................................. 10 7.4. pcm in terface ............................................................................................................. .......... 10 7.4.1. long fr ame sync......................................................................................................... ......... 11 7.4.2. short frame sync ........................................................................................................ ......... 11 7.4.3. general circui t interfac e (gci) ......................................................................................... .... 11 7.4.4. interchip di gital link (idl)............................................................................................ ......... 12 7.4.5. syst em ti ming ........................................................................................................... ........... 12 8. timing diagrams............................................................................................................. ............. 13 9. absolute maxi mum ratings.................................................................................................... 20 9.1. absolute maximum ratings .................................................................................................. ....... 20 9.2. operati ng condi tions ...................................................................................................... ............. 20 10. electrical character istics ............................................................................................... 21 10.1. general parame ters ....................................................................................................... ........... 21 10.2. analog signal level and gain pa ramete rs ............................................................................... 22 10.3. analog distortion and noise pa ramete rs .................................................................................. 23 10.4. analog input and output amplifier parame ters......................................................................... 24 10.5. digi tal i/o .............................................................................................................. ................. 26 10.5.1. -law encode decode characteri stics............................................................................... 26 10.5.2. a-law encode de code characte ristics .............................................................................. 27 10.5.3. pcm codes for zero and fu ll scale ................................................................................... 28 10.5.4. pcm codes for 0dbm0 output ........................................................................................... 28 11. typical applic ation ci rcuit ................................................................................................ . 29 12. package spec ification ...................................................................................................... .... 31
w681310 publication release date: april 2007 - 5 - revision b14 12.1. 20l sog (sop)- 300mil ..................................................................................................... ........ 31 12.2. 20l sso p-209 mi l ......................................................................................................... ............ 33 12.3. 20l tssop - 4.4x6.5mm .................................................................................................... ...... 35 13. ordering informat ion....................................................................................................... .... 36 14. version history ............................................................................................................ ........... 37
w681310 - 6 - 5. pin configuration 20 19 18 17 16 15 14 13 12 11 single channel codec 1 2 3 4 5 6 7 8 9 10 sog/ssop/tssop v ref ro - pai pao- pao+ v dd fsr pcmr bclkr pui v ag ai+ ai- ao /a v ss fst pcmt bclkt mclk 20 19 18 17 16 15 14 13 12 11 single channel codec 1 2 3 4 5 6 7 8 9 10 v ro - v dd fsr bclkr v ag /a-law v ss bclkt mclk
w681310 publication release date: april 2007 - 7 - revision b14 6. pin description pin name pin no. functionality v ref 1 this pin is used to bypass the on-chip v dd /2 voltage reference. it needs to be decoupled to v ss through a 0.1 f ceramic decoupling capacitor. no exter nal loads should be tied to this pin. ro- 2 inverting output of the receive smoothing f ilter. this pin can typically drive a 2 k load to 0.886 volt peak referenced to the analog ground level. pai 3 this pin is the inverting input to t he power amplifier. its dc level is at the v ag voltage. pao- 4 inverting power amplifier output. the pao- and pao+ can drive a 300 load differentially to 1.772 volt peak referenced to the v ag voltage level. pao+ 5 non-inverting power amplifier output. the pao- and pao+ can drive a 300 load differentially to 1.772 volt peak referenced to the v ag voltage level. v dd 6 power supply. this pin should be decoupled to v ss with a 0.1 f ceramic capacitor. fsr 7 8 khz frame sync input for the pcm receiv e section. this pin also selects channel 0 or channel 1 in the gci and idl modes. it can also be connected to the fst pin when transmit and receive are synchronous operations. pcmr 8 pcm input data receive pin. the data needs to be synchronous with the fsr and bclkr pins. bclkr 9 pcm receive bit clock input pin. this pin also selects the interface mode. the gci mode is selected when this pin is tied to v ss . the idl mode is selected when this pin is tied to v dd . this pin can also be tied to the bclkt when transmit and receive are synchronous operations. pui 10 power up input signal. when this pin is tied to v dd , the part is powered up. when tied to v ss , the part is powered down. mclk 11 system master clock input. possible input frequencies are 256 khz, 512 khz, 1536 khz, 1544 khz, 2048 khz, 2560 khz, 4096 khz & 4800 khz. fo r a better performance, it is recommended to have the mclk signal synchronous and aligned to the fst signal. this is a requirement in the case of 256 and 512 khz frequency. bclkt 12 pcm transmit bit clock input pin. this pi n accepts clocks of 512 khz to 6176 khz in the gci mode and 256 khz to 4800khz in all other pcm modes. pcmt 13 pcm output data transmit pin. the output data is synchronous with the fst and bclkt pins. fst 14 8 khz transmit frame sync input. this pin synchronizes the transmit data bytes. v ss 15 this is the supply ground. th is pin should be connected to 0v. /a-law 16 compander mode select pin. -law companding is selected when this pin is tied to v dd . a-law companding is selected when this pin is tied to v ss . ao 17 analog output of the first gain stage in the transmit path. ai- 18 inverting input of the firs t gain stage in the transmit path. ai+ 19 non-inverting input of the fi rst gain stage in the transmit path. v ag 20 mid-supply analog ground pin, which supplies a v dd /2 volt reference voltage for all-analog signal processing. this pin should be decoupled to v ss with a 0.01 f capacitor. this pin becomes high impedance when the chip is powered down.
w681310 - 8 - 7. functional description w681310 is a single-rail, single channel pcm codec for voiceband applications. the codec complies with the specifications of the itu- t g.712 recommendation. the codec also includes a complete -law and a-law compander. the -law and a-law companders are designed to comply with the specifications of the itu-t g.711 recommendation. the block diagram in section 3 shows the main components of the w681310. the chip consists of a pcm interface, which can process long and short fram e sync formats, as well as gci and idl formats. the pre-scaler of the chip provides the internal clock signals and synchronizes the codec sample rate with the external frame sync frequency. the power conditioning block provides the internal power supply for the digital and the analog section, while the voltage reference block provides a precision analog ground voltage for the analog signal processing. the main codec block diagram is shown in section 3. figure 7.1 the w681310 signal path 7.1. transmit path the a-to-d path of the codec contains an analog i nput amplifier with externally configurable gain setting (see application examples in section 11). t he device has an input operational amplifier whose output is the input to the encoder se ction. if the input amplifier is not required for operation it can be powered down and bypassed. in that case a single ended input signal can be applied to the ao pin or the ai- pin. the ao pin becomes high input impedanc e when the input amplifier is powered down. the input amplifier can be powered down by connecting the ai+ pin to v dd or v ss . the ao pin is selected as an input when ai+ is tied to v dd and the ai- pin is selected as an input when ai+ is tied to v ss (see table 7.1). pao + pao 8 /a - co n t ai + ai - w /a - cont ol ao + ro - - va g ant - aliasi fil te r = h ant i - aliasi n fil te r f c = 200 h high pas fil t s m oot n filter 2 h s m oot n filter 1 8 /a co n t r o l 8 /a - c o n t r o l pai v ag ant - a li as in g fil te r - aliasing fil te r ant - fil te r high pass fil ter s m oot hin g filter filter smoothing filter filter receive path transmit path + - + + + - a/ d co nv e r ter d / a converter f c = 3400hz f c = 3400hz c = 200hz f
w681310 publication release date: april 2007 - 9 - revision b14 ai+ input amplifier input v dd powered down ao 1.2 to v dd -1.2 powered up ai+, ai- v ss powered down ai- table 7.1 input amplif ier modes of operation when the input amplifier is powered down, the input signal at ao or ai- needs to be referenced to the analog ground voltage v ag . the output of the input amplifier is fed through a 3.4 khz switched capac itor low pass filter to prevent aliasing of input signals above 4 khz, due to the samp ling at 8 khz. the output of the 3.4 khz low pass filter is filtered by a high pass f ilter with a 200 hz cut-off frequency. the filters are designed according to the recommendations in the g.712 itu- t specification. from the output of the high pass filter the signal is digitized. the signal is converted into a co mpressed 8-bit digital representation with either -law or a-law format. the -law or a-law format is pin-selectable through the /a-law pin. the compression format can be selected according to table 7.2. /a-law pin format v ss a-law v dd -law table 7.2. pin-selectable compression format the digital 8-bit -law or a-law samples are fed to the pcm interface for serial transmission at the sample rate supplied by the external frame sync fst. 7.2. receive path the 8-bit digital input samples for the d-to-a path are serially shifted in by the pcm interface and converted to parallel data bits. during every cycle of the frame sync fsr, the parallel data bits are fed through the pin-selectable -law or a-law expander and converted to analog samples. the mode of expansion is selected by the /a-law pin as shown in table 7.2. the analog samples are filtered by a low-pass smoothing filter with a 3.4 khz cut-off frequenc y, according to the itu-t g.712 specification. a sin(x)/x compensation is integrated wi th the low pass smoothing filter. the output of this filter is buffered to provide the receive output signal ro-. the ro- output can be exter nally connected to the pai pin to provide a differential output with high driving capab ility at the pao+ and pao- pins. by using external resistors (see section 11 for examples ), various gain settings of this output amplifier can be achieved. if the transmit power amplifier is not in use, it can be powered down by connecting pai to v dd . 7.3. p ower m anagement
w681310 - 10 - 7.3.1. analog and digital supply the power supply for the analog and digital parts of the w681310 must be 2.7v to 5.25v. this supply voltage is connected to the v dd pin. the v dd pin needs to be decoupled to ground through a 0.1 7.3.2. analog ground reference bypass the system has an internal precision voltage reference which generates the v dd /2 mid-supply analog ground voltage. this voltage needs to be decoupled to v ss at the v ref pin through a 0.1 7.3.3. analog ground reference voltage outpt the analog ground reference voltage is available for external reference at the v ag pin. this voltage needs to be decoupled to v ss through a 0.01 7.4. pcm i nterface the pcm interface is controlled by pins bclkr, fsr, bclkt & fst. the input data is received through the pcmr pin and the output data is trans mitted through the pcmt pin. the modes of operation of the interface are shown in table 7.3. bclkr fsr interface mode 64 khz to 4.800 mhz 8 khz long or short frame sync v ss v ss isdn gci with active channel b1 v ss v dd isdn gci with active channel b2 v dd v ss isdn idl with active channel b1 v dd v dd isdn idl with active channel b2 table 7.3 pcm interface mode selections
w681310 publication release date: april 2007 - 11 - revision b14 7.4.1. long frame sync the long frame sync or short frame sync interf ace mode can be selected by connecting the bclkr or bclkt pin to a 64 khz to 4.800 mhz clock and c onnecting the fsr or fst pin to the 8 khz frame sync. the device synchronizes the data word for t he pcm interface and the codec sample rate on the positive edge of the frame sync signal. it recogni zes a long frame sync when the fst pin is held high for two consecutive falling edges of the bit-clo ck at the bclkt pin. the length of the frame sync pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125 sec. during data transmission in the long frame sync m ode, the transmit data pin pcmt will become low impedance when the frame sync signal fst is high or when the 8 bit data word is being transmitted. the transmit data pin pcmt will become high im pedance when the frame sync signal fst becomes low while the data is transmitted or when half of the lsb is transmitted. the internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. to avoid bus collisions, the pcmt pi n will be high impedance for two frame sync cycles after every power down state. more detailed timi ng information can be found in the interface timing section. 7.4.2. short frame sync the w681310 operates in the short frame sync mode w hen the frame sync signal at pin fst is high for one and only one falling edge of the bit-clock at t he bclkt pin. on the following rising edge of the bit-clock, the w681310 starts clo cking out the data on the pcmt pin, which will also change from high to low impedance state. the data transmit pin pcmt will go back to the high impedance state halfway the lsb. the short frame sync operation of the w681310 is based on an 8-bit data word. when receiving data on the pcmr pin, t he data is clocked in on the first falling edge after the falling edge that coincides with the frame sync signal. the internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the pr evious frame sync pulse. to avoid bus collisions, the pcmt pin will be high impedance for two frame sync cycles after every power down state. more detailed timing information can be found in the interface timing section. 7.4.3. general circuit interface (gci) the gci interface mode is selected when the bclkr pin is connected to v ss for two or more frame sync cycles. it can be used as a 2b+d timing inte rface in an isdn application. the gci interface consists of 4 pins : fsc (fst), dcl (bclkt), dout (pcmt) & din (pcmr). the fsr pin selects channel b1 or b2 for transmit and receive. data trans itions occur on the positiv e edges of the data clock dcl. the frame sync positive edge is aligned with the positive edge of the dat a clock dclk. the data rate is running half the speed of the bit-clock. t he channels b1 and b2 are transmitted consecutively. therefore, channel b1 is transmitted on the first 16 clock cycles of dcl and b2 is transmitted on the second 16 clock cycles of dcl. for more timing inform ation, see the timing section. the gci interface supports bit clocks of 512 khz to 6176 khz for data rates of 256 khz to 3088 khz.
w681310 - 12 - 7.4.4. interchip digital link (idl) the idl interface mode is selected when the bclkr pin is connected to v dd for two or more frame sync cycles. it can be used as a 2b+d timing inte rface in an isdn application. the idl interface consists of 4 pins : idl sync (fst), idl clk (b clkt), idl tx (pcmt) & idl rx (pcmr). the fsr pin selects channel b1 or b2 for transmit and receive. the data for channel b1 is transmitted on the first positive edge of the idl clk after the idl sync pulse. the idl sync pulse is one idl clk cycle long. the data for channel b2 is transmitted on the eleventh positive edge of the idl clk after the idl sync pulse. the data for channel b1 is received on t he first negative edge of the idl clk after the idl sync pulse. the data for channel b2 is received on the eleventh negative edge of the idl clk after the idl sync pulse. the transmit signal pin idl tx becomes high impedance when not used for data transmission and also in the time slot of the unus ed channel. for more timing information, see the timing section. 7.4.5. system timing the system can work at 256 khz, 512 khz, 1536 khz, 1544 khz, 2048 khz, 2560 khz, 4096 khz & 4800 khz master clock rates. the system clock is supplied through the master clock input mclk and can be derived from the bit-clock if desired. an in ternal pre-scaler is used to generate a fixed 256 khz and 8 khz sample clock for the internal codec. the pre-scaler measures the master clock frequency versus the frame sync frequency and sets the division ratio accordingly. if the frame sync is low for the entire frame sync period while the mclk and bclk pin clock signals are still present, the w681310 will enter the low power standby mode. another way to power down is to set the pui pin to low. when the system needs to be powered up again, the pui pi n needs to be set to high and the frame sync pulse needs to be present. it will take two frame sy nc cycles before the pin pcmt will become low impedance.
w681310 publication release date: april 2007 - 13 - revision b14 8. timing diagrams figure 8.1 long frame sync pcm timing fst bclkt d7 d6 d5 d4 d3 d2 d1 pcmt msb lsb t hid t bck d0 t bckh t bckl t fs t ftfh t ftrs t ftrh t hid t bdtd t fdtd 01 23 45 7 8 0 1 msb lsb fsr bclkr t bck d6 d5 d4 d3 d2 d1 d0 pcmr d7 t drh t drs t bckh t bckl t fs t frfh t frrs t frrh 01 23 45 67 8 0 1 6 mclk t ftrhm t ftrsm t mckh t mckl t mck t rise t fall t fsl t fsl
w681310 - 14 - symbol description min typ max unit 1/t fs fst, fsr frequency --- 8 --- khz t fsl fst / fsr minimum low width 1 t bck sec 1/t bck bclkt, bclkr frequency 64 --- 4800 khz t bckh bclkt, bclkr high pulse width 50 --- --- ns t bckl bclkt, bclkr low pulse width 50 --- --- ns t ftrh bclkt 0 falling edge to fst rising edge hold time 20 --- --- ns t ftrs fst rising edge to bclkt 1 falling edge setup time 80 --- --- ns t ftfh bclkt 2 falling edge to fst falling edge hold time 50 --- --- ns t fdtd fst rising edge to valid pcmt delay time --- --- 60 ns t bdtd bclkt rising edge to valid pcmt delay time --- --- 60 ns t hid delay time from the later of fst falling edge, or bclkt 8 falling edge to pcmt output high impedance 10 --- 60 ns t frrh bclkr 0 falling edge to fsr rising edge hold time 20 --- --- ns t frrs fsr rising edge to bclkr 1 falling edge setup time 80 --- --- ns t frfh bclkr 2 falling edge to fsr falling edge hold time 50 --- --- ns t drs valid pcmr to bclkr falling edge setup time 0 --- --- ns t drh pcmr hold time from bclkr falling edge 50 --- --- ns table 8.1 long frame sync pcm timing parameters 1 t fsl must be at least
w681310 publication release date: april 2007 - 15 - revision b14 figure 8.2 short frame sync pcm timing d7 d6 d5 d4 d3 d2 d1 msb lsb t bck d0 t bckh t bckl t fs t ftrs t ftrh t hid t bdtd 01 23 45 6 7 8 01 fst bclkt pcmt t bdtd t ftfh -1 t ftfs msb lsb t bck d6 d5 d4 d3 d2 d1 d0 d7 t drh t drs t bckh t bckl t fs t frrs t frrh 01 23 45 6 7 8 01 fsr bclkr pcmr t frfh -1 t frfs mclk t ftrhm t ftrsm t mckh t mckl t mck t rise t fall
w681310 - 16 - symbol description min typ max unit 1/t fs fst, fsr frequency --- 8 --- khz 1/t bck bclkt, bclkr frequency 64 --- 4800 khz t bckh bclkt, bclkr high pulse width 50 --- --- ns t bckl bclkt, bclkr low pulse width 50 --- --- ns t ftrh bclkt ?1 falling edge to fst rising edge hold time 20 --- --- ns t ftrs fst rising edge to bclkt 0 falling edge setup time 80 --- --- ns t ftfh bclkt 0 falling edge to fst falling edge hold time 50 --- --- ns t ftfs fst falling edge to bclkt 1 falling edge setup time 50 --- --- ns t bdtd bclkt rising edge to valid pcmt delay time 10 --- 60 ns t hid delay time from bclkt 8 falling edge to pcmt output high impedance 10 --- 60 ns t frrh bclkr ?1 falling edge to fsr rising edge hold time 20 --- --- ns t frrs fsr rising edge to bclkr 0 falling edge setup time 80 --- --- ns t frfh bclkr 0 falling edge to fsr falling edge hold time 50 --- --- ns t frfs fsr falling edge to bclkr 1 falling edge setup time 50 --- --- ns t drs valid pcmr to bclkr falling edge setup time 0 --- --- ns t drh pcmr hold time from bclkr falling edge 50 --- --- ns table 8.2 short frame sync pcm timing parameters
w681310 publication release date: april 2007 - 17 - revision b14 figure 8.3 idl pcm timing symbol description min typ max unit 1/t fs fst frequency --- 8 --- khz 1/t bck bclkt frequency 256 --- 4800 khz t bckh bclkt high pulse width 50 --- --- ns t bckl bclkt low pulse width 50 --- --- ns t fsrh bclkt ?1 falling edge to fst rising edge hold time 20 --- --- ns t fsrs fst rising edge to bclkt 0 falling edge setup time 60 --- --- ns t fsfh bclkt 0 falling edge to fst falling edge hold time 20 --- --- ns t bdtd bclkt rising edge to valid pcmt delay time 10 --- 60 ns t hid delay time from the bclkt 8 falling edge (b1 channel) or bclkt 18 falling edge (b2 channel) to pcmt output high impedance 10 --- 50 ns t drs valid pcmr to bclkt falling edge setup time 20 --- --- ns t drh pcmr hold time from bclkt falling edge 75 --- --- ns table 8.3 idl pcm timing parameters fst bclkt pcmt pcmr d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 t fs t fsrh t fsfh t fsrs t bdtd t bdtd t bdtd t bdtd t hid t hid t drs t drs t drh t drh bch = 0 b1 channel bch = 1 b2 channel msb msb msb msb lsb lsb lsb lsb t bck t bckh t bckl -1
w681310 - 18 - figure 8.4 gci pcm timing symbol description min typ max unit 1/t fst fst frequency --- 8 --- khz 1/t bck bclkt frequency 512 --- 6176 khz t bckh bclkt high pulse width 50 --- --- ns t bckl bclkt low pulse width 50 --- --- ns t fsrh bclkt 0 falling edge to fst rising edge hold time 20 --- --- ns t fsrs fst rising edge to bclkt 1 falling edge setup time 60 --- --- ns t fsfh bclkt 1 falling edge to fst falling edge hold time 20 --- --- ns t fdtd fst rising edge to valid pcmt delay time --- --- 60 ns t bdtd bclkt rising edge to valid pcmt delay time --- --- 60 ns t hid delay time from the bclkt 16 falling edge (b1 channel) or bclkt 32 falling edge (b2 channel) to pcmt output high impedance 10 --- 50 ns t drs valid pcmr to bclkt rising edge setup time 20 --- --- ns t drh pcmr hold time from bclkt rising edge --- --- 60 ns table 8.4 gci pcm timing parameters fst bclkt pcmt pcmr d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 t fs t fdtd t bdtd t bdtd t bdtd t hid t hid t drs t drs t drh t drh bch = 0 b1 channel bch = 1 b2 channel msb msb msb msb lsb lsb lsb lsb t fsrh t fsfh t fsrs t bck t bckh t bckl 2345678910111213141516171819202122232425262728293031323334 1 0
w681310 publication release date: april 2007 - 19 - revision b14 symbol description min typ max unit 1/t mck master clock frequency --- 256 512 1536 1544 2048 2560 4096 4800 --- khz t mckh / t mck mclk duty cycle for 256 khz operation 45% 55% t mckh minimum pulse width high for mclk(512 khz or higher) 50 --- --- ns t mckl minimum pulse width low for mclk (512 khz or higher) 50 --- --- ns t ftrhm mclk falling edge to fst rising edge hold time 50 --- --- ns t ftrsm fst rising edge to mclk falling edge setup time 50 --- --- ns t rise rise time for all digital signals --- --- 50 ns t fall fall time for all digital signals --- --- 50 ns table 8.5 general pcm timing parameters
w681310 - 20 - 9. absolute maximum ratings 9.1. a bsolute m aximum r atings condition value junction temperature 150 0 c storage temperature range -65 0 c to +150 0 c voltage applied to any pin (v ss - 0.3v) to (v dd + 0.3v) voltage applied to any pin (input current limited to +/-20 ma) (v ss ? 1.0v) to (v dd + 1.0v) v dd - v ss -0.5v to +6v 1. stresses above those listed ma y cause permanent damage to the dev ice. exposure to the absolute maximum ratings may affect device reliability. func tional operation is not imp lied at these conditions. 9.2. o perating c onditions condition value industrial operating temperature -40 0 c to +85 0 c supply voltage (v dd ) +2.7v to +5.25v ground voltage (v ss ) 0v note : exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device.
w681310 publication release date: april 2007 - 21 - revision b14 10. electrical characteristics 10.1. g eneral p arameters symbol parameters conditions min (2) typ (1) max (2) units v il input low voltage 0.6 v v ih input high voltage 2.2 v v ol pcmt output low voltage i ol = 1.6 ma 0.4 v v oh pcmt output high voltage i ol = -1.6 ma v dd ? 0.5 v i dd v dd current (operating) - adc + dac no load 3.3 5 ma i sb v dd current (standby) fst & fsr =v ss ; pui=v dd 10 100 a i pd v dd current (power down) pui= v ss 0.1 10 a i il input leakage current v ss w681310 - 22 - 10.2. a nalog s ignal l evel and g ain p arameters v dd =2.7v to 3.6v; v ss =0v; t a =-40 c to +85 c; all analog signals referred to v ag ; mclk=bclk= 2.048 mhz; fst=fsr=8khz synchronous operation. transmit (a/d) receive (d/a) unit parameter sym. condition typ. min. max. min. max. absolute level l abs 0 dbm0 = -5dbm @ 600 0.616 0.436 --- --- --- --- v pk v rms max. transmit level t xmax 3.17 dbm0 for -law 3.14 dbm0 for a-law 0.8873 0.8843 --- --- --- --- --- --- --- --- v pk v pk absolute gain (0 dbm0 @ 1020 hz; t a =+25 c) g abs 0 dbm0 @ 1020 hz; t a =+25 c 0 -0.20 +0.20 -0.20 +0.20 db absolute gain variation with temperature g abst t a =0 c to t a =+70 c t a =-40 c to t a =+85 c 0 -0.05 -0.10 +0.05 +0.10 -0.05 -0.10 +0.05 +0.10 db frequency response, relative to 0dbm0 @ 1020 hz g rtv 15 hz 50 hz 60 hz 200 hz 300 to 3000 hz 3300 hz 3400 hz 3600 hz 4000 hz 4600 hz to 100 khz --- --- --- --- --- --- --- --- --- --- --- --- --- -1.4 -0.15 -0.35 -0.8 --- --- --- -40 -30 -26 -0.4 +0.2 +0.2 +0.1 0 -14 -32 -0.5 -0.5 -0.5 -0.5 -0.20 -0.4 -0.8 --- --- --- 0 0 0 0 +0.2 +0.15 0 0 -14 -30 db gain variation vs. level tone (1020 hz relative to ?10 dbm0) g lt +3 to ?40 dbm0 -40 to ?50 dbm0 -50 to ?55 dbm0 --- --- --- -0.3 -0.6 -1.6 +0.3 +0.6 +1.6 -0.2 -0.4 -1.6 +0.2 +0.4 +1.6 db
w681310 publication release date: april 2007 - 23 - revision b14 10.3. a nalog d istortion and n oise p arameters v dd =2.7v to 3.6v; v ss =0v; t a =-40 c to +85 c; all analog signals referred to v ag ; mclk=bclk= 2.048 mhz fst=fsr=8khz synchronous operation. transmit (a/d) receive (d/a) parameter sym. condition min. typ. max. min. typ. max. unit total distortion vs. level tone (1020 hz, -law, c-message weighted) d lt +3 dbm0 0 dbm0 to -30 dbm0 -40 dbm0 -45 dbm0 34 33.5 30 25 --- --- --- --- --- --- --- --- 34 36 30 25 --- --- --- --- --- --- --- --- dbc total distortion vs. level tone (1020 hz, a-law, psophometric weighted) d lta -3 dbm0 -6 dbm0 to -27 dbm0 -34 dbm0 -40 dbm0 -55 dbm0 30 35 34.5 28.5 13.5 --- --- --- --- --- --- --- --- 30 36 34.2 30 15 --- --- --- --- --- --- --- --- dbp spurious out-of-band at ro- (300 hz to 3400 hz @ 0dbm0) d spo 4600 hz to 7600 hz 7600 hz to 8400 hz 8400 hz to 100000 hz --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- -30 -40 -30 db spurious in-band (700 hz to 1100 hz @ 0dbm0) d spi 300 to 3000 hz --- --- -47 --- --- -47 db intermodulation distortion (300 hz to 3400 hz ?4 to ?21 dbm0 d im two tones --- --- -41 --- --- -41 db crosstalk (1020 hz @ 0dbm0) d xt --- --- -75 --- --- -75 dbm0 absolute group delay abs 1200hz --- --- 360 --- --- 240 sec group delay distortion (relative to group delay @ 1200 hz) d 500 hz 600 hz 1000 hz 2600 hz 2800 hz --- --- --- --- --- --- --- --- --- --- 750 380 130 130 750 --- --- --- --- --- --- --- --- --- --- 750 370 120 120 750 sec idle channel noise n idl -law; c-message a-law; psophometric --- --- --- --- 19 -68 --- --- --- --- 15 -75 dbrnc0 dbm0p
w681310 - 24 - 10.4. a nalog i nput and o utput a mplifier p arameters v dd =2.7v to 3.6v; v ss =0v; t a =-40 c to +85 c; all analog signals referred to v ag ; parameter sym. condition min. typ. max. unit. ai input offset voltage v off,ai ai+, ai- --- --- 25 mv ai input current i in,ai ai+, ai- --- 0.1 1.0 a ai input resistance r in,ai ai+, ai- to v ag 10 --- --- m ai input capacitance c in,ai ai+, ai- --- --- 10 pf ai common mode input voltage range v cm,ai ai+, ai- 1.2 --- v dd -1.2 v ai common mode rejection ratio cmrr ti ai+, ai- --- 60 --- db ai amp gain bandwidth product gbw ti ao, r ld 10k --- 2150 --- khz ai amp dc open loop gain g ti ao, r ld 10k --- 95 --- db ai amp equivalent input noise n ti c-message weighted --- -24 --- dbrnc ao output voltage range v tg r ld =2k to v ag 0.4 --- v dd -0.4 v load resistance r ldtgro ao, ro to v ag 2 --- --- k load capacitance c ldtgro ao, ro --- --- 200 pf ao & ro output current i out1 0.5 ao,ro- v dd -0.5 1.0 --- --- ma ro- output resistance r ro- ro-, 0 to 3400 hz --- 1 --- ro- output offset voltage v off,ro- ro- to v ag --- --- 25 mv analog ground voltage v ag relative to v ss v dd /2-0.1 v dd /2 v dd /2+0. 1 v v ag output resistance r vag within 25mv change --- 12.5 25 power supply rejection ratio (0 to 100 khz to v dd , c- message) psrr transmit receive 40 40 60 60 --- --- dbc pai input offset voltage v off,pai pai --- --- 25 mv pai input current i in,pai pai --- 0.05 1.0 a pai input resistance r in,pai pai to v ag 10 --- --- m pai amp gain bandwidth product gbw pi pao- no load --- 1000 --- khz output offset voltage v off,po pao+ to pao- --- --- 50 mv
w681310 publication release date: april 2007 - 25 - revision b14 parameter sym. condition min. typ. max. unit. load resistance r ldpo pao+, pao- differentially 300 --- --- load capacitance c ldpo pao+, pao- differentially --- --- 1000 pf pao output current i outpao 0.4 pao+,pao-- v dd - 0.4 6.0 --- --- ma pao output resistance r pao pao+ to pao- --- 1 --- pao differential gain g pao r ld =300 , +3dbm0, 1 khz, pao+ to pao- -0.2 0 +0.2 db pao differential signal to distortion c-message weighted d pao z ld =300 z ld =100nf + 20 z ld =100nf + 100 45 --- --- 60 40 40 --- --- --- dbc pao power supply rejection ratio (0 to 25 khz to v dd , differential out) psrr p ao 0 to 4 khz 4 to 25 khz 40 --- 55 40 --- --- db
w681310 - 26 - 10.5. d igital i/o 10.5.1. -law encode decode characteristics digital code d7 d6 d5 d4 d3 d2 d1 d0 normalized encode decision levels sign chord chord chor d step step step step normalized decode levels 1 0 0 0 0 0 0 0 8031 : 1 0 0 0 1 1 1 1 4191 : 1 0 0 1 1 1 1 1 2079 : 1 0 1 0 1 1 1 1 1023 : 1 0 1 1 1 1 1 1 495 : 1 1 0 0 1 1 1 1 231 : 1 1 0 1 1 1 1 1 99 : 1 1 1 0 1 1 1 1 33 : 1 1 1 1 1 1 1 0 2 1 1 1 1 1 1 1 1 0 8159 7903 : 4319 4063 : 2143 2015 : 1055 991 : 511 479 : 239 223 : 103 95 : 35 31 : 3 1 0 notes: sign bit = 0 for negative values, sign bit = 1 for positive values
w681310 publication release date: april 2007 - 27 - revision b14 10.5.2. a-law encode decode characteristics digital code d7 d6 d5 d4 d3 d2 d1 d0 normalized encode decision levels sign chord chord chor d step step step step normalized decode levels 1 0 1 0 1 0 1 0 4032 : 1 0 1 0 0 1 0 1 2112 : 1 0 1 1 0 1 0 1 1056 : 1 0 0 0 0 1 0 1 528 : 1 0 0 1 0 1 0 1 264 : 1 1 1 0 0 1 0 1 132 : 1 1 1 0 0 1 0 1 66 : 1 1 0 1 0 1 0 1 1 4096 3968 : 2048 2048 : 1088 1024 : 544 512 : 272 256 : 136 128 : 68 64 : 2 0 notes: 1. sign bit = 0 for negative values, sign bit = 1 for positive values 2. digital code includes inversion of all even number bits
w681310 - 28 - 10.5.3. pcm codes for zero and full scale -law a-law level sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) + full scale 1 000 0000 1 010 1010 + zero 1 111 1111 1 101 0101 - zero 0 111 1111 0 101 0101 - full scale 0 000 0000 0 010 1010 10.5.4. pcm codes for 0dbm0 output -law a-law sample sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) 1 0 001 1110 0 011 0100 2 0 000 1011 0 010 0001 3 0 000 1011 0 010 0001 4 0 001 1110 0 011 0100 5 1 001 1110 1 011 0100 6 1 000 1011 1 010 0001 7 1 000 1011 1 010 0001 8 1 001 1110 1 011 0100
w681310 publication release date: april 2007 - 29 - revision b14 11. typical application circuit + 0.01 uf 27k - pcm out 1.0 uf 8 khz frame sy nc differential audio in pcm in - 0.1 uf differential audio out rl > 150 ohms power control 27k 1.0 uf 27k 0.1 uf 2.048 mhz bit clock mode select 27k u2 w681310 6 15 10 16 14 12 13 11 8 9 7 17 18 19 20 1 2 5 3 4 vdd vss pui u/a fst bclkt pcmt mc lk pcmr bclkr fsr ao ai- ai+ vag vref ro- pao+ pai pao- + 27k 27k vdd figure 11.1 typical circuit for differential analog i/o?s audio out rl > 2k ohms 1.0 uf 27k audio in u3 w681310 6 15 10 16 14 12 13 11 8 9 7 17 18 19 20 1 2 5 3 4 vdd vss pui u/a fst bclkt pcmt mc lk pcmr bclkr fsr ao ai- ai+ vag vref ro- pao+ pai pao- 27k pcm in 8 khz frame sy nc 27k pcm out mode select 100 uf vdd 0.1 uf 0.01 uf 27k power control 1.0 uf 0.1 uf 2.048 mhz bit clock 27k audio out rl > 150 ohms 27k figure 11.2 typical circuit for single ended analog i/o?s
w681310 - 30 - 100pf 8 khz frame sy nc power control 62k 2.048 mhz bit clock 1.0 uf 3.9k microphone + 27k 3.9k vdd 27k 0.1 uf 0.01 uf 1k speaker 0.1 uf 1.0 uf 22 uf 27k 100pf u4 w681310 6 15 10 16 14 12 13 11 8 9 7 17 18 19 20 1 2 5 3 4 vdd vss pui u/a fst bclkt pcmt mc lk pcmr bclkr fsr ao ai- ai+ vag vref ro- pao+ pai pao- 1.5k pcm out 1.5k 62k electret pcm in mode select figure 11.3 handset interface 0.1 uf 27k 600 0.01 uf tr an sf or mer b1/b2 select u5 w681310 6 15 10 16 14 12 13 11 8 9 7 17 18 19 20 1 2 5 3 4 vdd vss pui u/a fst bclkt pcmt mc lk pcmr bclkr fsr ao ai- ai+ vag vref ro- pao+ pai pao- 27k pcm out 27k 600 ohm 1:1 mode select vdd 27k 0.1 uf power control 4.096 mhz bit clock 8 khz frame sy nc pcm in 1.0 uf figure 11.4 transformer interface circuit in gci mode
w681310 publication release date: april 2007 - 31 - revision b14 12. package specification 12.1. 20l sog (sop)-300 mil small outline package (same as sog & soic) dimensions l o c e h a1 a e b d seating plane y 0.25 gauge plane e 1 20 11 10
w681310 - 32 - dimension (mm) dimension (inch) symbol min. max. min. max. a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 e 7.40 7.60 0.291 0.299 d 12.60 13.00 0.496 0.512 e 1.27 bsc 0.050 bsc h e 10.00 10.65 0.394 0.419 y - 0.10 - 0.004 l 0.40 1.27 0.016 0.050 0 0o 8o 0o 8o
w681310 publication release date: april 2007 - 33 - revision b14 12.2. 20l ssop-209 mil shrink small outline package dimensions 1 20 d e e y b a1 a2 a seating plane dteail a l l1 detail a seating plane e h 10 11 b
w681310 - 34 - dimension (mm) dimension (inch) symbol min. nom. max. min. nom. max. a - - 2.00 - - 0.079 a1 0.05 - - 0.002 - - a2 1.65 1.75 1.85 0.065 0.069 - b 0.22 - 0.38 0.009 - 0.015 c 0.09 - 0.25 0.004 - 0.010 d 6.90 7.20 7.50 0.272 0.283 0.295 e 5.00 5.30 5.60 0.197 0.209 0.220 h e 7.40 7.80 8.20 0.291 0.307 0.323 e - 0.65 - - 0.0256 - l 0.55 0.75 0.95 0.021 0.030 0.037 l1 - 1.25 - - 0.050 - y - - 0.10 - - 0.004 0 0o - 8o 0 - 8o
w681310 publication release date: april 2007 - 35 - revision b14 12.3. 20l tssop - 4.4x6.5 mm plastic thin shrink small outli ne package (tssop) dimensions dimension (mm) dimension (inch) symbol min. nom. max. min. nom. max. a - - 1.20 - - 0.047 a1 0.05 - 0.15 0.002 - 0.006 a2 0.80 0.90 1. 05 0.031 0.035 0.041 e 4.30 4.40 4.50 0.169 0.173 0.177 he 6.40 bsc .252 bsc d 6.40 6.50 6.60 0.252 0.256 0.260 l 0.50 0.60 0.75 0.020 0.024 0.030 l1 1.00 ref 0.039 ref b 0.19 - 0.30 0.007 - 0.012 e 0.65 bsc 0.026 bsc c 0.09 - 0.20 0.004 - 0.008 0 0o - 8o 0o - 8o y 0.10 basic 0.004 basic
w681310 - 36 - 13. ordering information winbond part number description when ordering w681310 series devices, pleas e refer to the following part numbers. part number w681310s* w681310r* w681310sg w681310rg w681310wg *all pb packages will be availabl e for a limited time. thus, pb-free packages are strongly recommended. package type: s = 20-lead plastic small outline package (sog/sop) r = 20-lead plastic small outline package (ssop) wg = 20-lead free plastic thin small outline package (tssop) product family w681310 product w681310_ _ package material: blank = standard package g = pb-free package
w681310 publication release date: april 2007 - 37 - revision b14 14. version history version date page description a1 august 10, 2003 draft version a2 august 22, 2003 update typo errors and parameters b11 november, 2004 2 6 33 34 22 23 added reference to tssop package and pb-free packaging. added reference to tssop package. added description of tssop package. added w and g package ordering code. extended conditions on table 10.2. extended conditions on table 10.3. corrected idle channel noise min/max and units. improved application diagram improved application diagram b12 april, 2005 36 add important notice b13 september, 2005 29,30 22 various improved application diagram added reference to v rms capitalized logic high/low b14 april, 2007 31 33 35 36 36 sop package diagram legible ssop package diagram legible tssop package diagram legible removed pb tssop package footnote on pb parts limited availability
w681310 - 38 - important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. the information contained in this dat asheet may be subject to change without notice. it is the responsibility of the cu stomer to check the winbond usa website ( www.winbond-usa.com ) periodically for the latest version of this document, and any errata sheets that may be generated between datasheet revisions.

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