M2VD-2HL mpeg-2 video decoder for 1080p single stream or 1080i dual stream silicon image?s M2VD-2HL* is designed to be used in system-on-a-chip solutions for dvd and stb/dtv markets. with its extensive set of features M2VD-2HL enables com- panies to easily provide functions like parallel viewing and recording, picture-in-picture or simultaneous viewing of several channels in television, pc or other relevant environ- ments. the M2VD-2HL decoder is optimized to satisfy a wide range of applications and technologies with optimal performance at lowest possible silicon costs. its interfaces are optimized for easy integration into a system-on-chip architecture using the standard on- chip bus approach. this dramatically reduces the integration effort and enables fast time-to-market developments. applications ? set-top boxes ? digital tv sets and iptv applications ? dvd players and recorders ? portable multimedia players ? surveillance key features ? supports mpeg-1/2 to 1080p @ 60 fps ? full bit rate support up to 80 mbps ? small gate count reduces chip area ? only one irq per picture to external host ip product brief M2VD-2HL system diagram features ? iso/iec 13818-2 - mpeg-2 main profile @ high level ? iso/iec 11172-2 - mpeg-1 constrained parameter set ? support of all atsc and dvb hdtv formats ? real-time decoding of multiple streams only limited by frequency. ? error detection and autonomous error con- cealment with concealment vectors on slice, macroblock and block layer ? counter for concealed mbs within a picture and threshold register which indicates the level of interrupt generation ? software access to relevant internal registers and parameter stores to provide the possibility of a flexible error handling and a robust and error tolerant decoding control ? decoding of packetized elementary stream (pes) and elementary stream (es) sub-modules gate count memory single-ported two ported vd pipeline 69k 64x32 2x64x32 128x26 2x64x12 32x34 96x36 vd_m14x4 70k 96x64 48x64 200x96 M2VD-2HL gate count and ram size estimation gate = 2 input-nand equivalent, using tsmc 0.13 m process and standard cell libraries *M2VD-2HL was formerly part of the sci-worx gmbh product port- folio. silicon image acquired sci- worx in january 2007.
real-time decoding of multiple streams only limited by frequency for example: ? six streams mp@ml (pal or ntsc) @ 133 mhz in a typical system ? one stream mp@hl (hdtv / 1080i) @ 133 mhz in a typical system ? two streams mp@hl (hdtv / 1080i) @ 266 mhz in a typical system ? one stream mp@hl (hdtv / 1080p) @ 266 mhz in a typical system M2VD-2HL features pes parser (vd_pspa) the vd_pspa reads the transmitted packetized elementary stream (pes) from memory interface (vd_mi4x4) and extracts the enclosed video elementary stream (es) data from each pes payload section. all extracted es data is passed to the variable length decoder (vd_vld). presentation time stamps (pts), which are used for video synchronization during picture presen- tation, are collected from pes. further on, the exact position of a picture header in the external stream buffer is detected. this can be used for trick mode, etc. variable length decoder (vd_vld) the vd_vld scans the incoming video bit stream for synchronization and decoding. this stream has a multilayer syntax. on higher lay- ers, general information about the current video sequence is transmitted in a fixed length code. depending on this information, the data of a picture is decoded on macro block and block layer from the variable length code of the stream. concealment vectors are derived from the stream and stored internally. they are used for picture reconstruction from a corrupted stream. inverse quantization (vd_iq) the inverse quantization is performed block ori- ented in an 8x8 matrix in default or alternate scan order regarding the mpeg-1 and mpeg-2 standard. quantizer weighting matrices from higher stream layers are stored in a ram to be used for inverse quantization. inverse discrete cosine transformation (vd_idct) after a block of coefficients has been de-quan- tized, the vd_idct unit performs the two dimensional idct on the 8x8 block to form a reconstructed image block. a transposition ram is used for storing interim results. frame reconstruction (vd_fr) the frame reconstruction process forms predic- tion values from previously decoded pictures which are added to the transmitted difference values (output of vd_idct via intermediate memory) to recover the final decoded pels of a picture. the location of the values in previously decoded pictures depends on the specified pre- diction type and the motion vectors. a shared ram is used for the reconstruction process. command interface (vd_cmd) the system processor has transparent access to all relevant internal registers and parameter stores via the command interface. the built-in control logic of the vd_cmd allows control over the video decoder by a well defined and powerful set of instructions. memory interface (vd_mi4x4) the high performance memory interface con- tains buffers for stream data, user data, video data write and reference data read. the buffers, together with a four by four pixel mapping of the reference data, allow efficient burst access to a system memory (e.g. ddr2 sdram) via four 64-bit bvci interfaces. the reference data read port copes with pipelined latencies of more than 100 clock cycles without impact on the decoding performance. ? 2007 silicon image, inc. all rights reserved. silicon image, the silicon image logo, M2VD-2HL and designobject are trademarks or registered trademarks of silicon image, inc. in the united states and other coun- tries. other trademarks are property of their respective holders. product specifications are subject to change without notice. part number: M2VD-2HL sii-pb-1010 rev1 3/07 silicon image, inc. 1060 e. arques avenue sunnyvale, ca 94085 t 408.616.4000 f 408.830.9530 www.siliconimage.com
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