; even- or odd-number ed parity by uartcr1) are added to the transfer data. the transfer data formats are shown as follows. figure 11-2 transfer data format figure 11-3 caution on ch anging transfer data format note: in order to switch the transfer data format, perform transmit operations in the above figure 11-3 sequence except for the initial setting. start bit 0 bit 1 bit 6 bit 7 stop 1 start bit 0 bit 1 bit 6 bit 7 stop 1 stop 2 start bit 0 bit 1 bit 6 bit 7 parity stop 1 start bit 0 bit 1 bit 6 bit 7 parity stop 1 stop 2 pe 0 0 1 1 stbt frame length 0 1 123 89101112 0 1 without parity / 1 stop bit with parity / 1 stop bit without parity / 2 stop bit with parity / 2 stop bit
page 127 TMP86CS25ADFG 11.4 transfer rate the baud rate of uart is set of uartcr1. th e example of the baud rate are shown as follows. when tc5 is used as the uart transfer rate (when uartcr1 = ?110?), the tr ansfer clock and transfer rate are determined as follows: transfer clock [hz] = tc5 source clock [hz] / ttreg5 setting value transfer rate [baud] = transfer clock [hz] / 16 11.5 data sampling method the uart receiver keeps sampling input using the cloc k selected by uartcr1 until a start bit is detected in rxd pin input. rt clock star ts detecting ?l? level of the rxd pin. once a start bit is detected, the start bit, data bits, stop bi t(s), and parity bit are sampled at three times of rt7, rt8, and rt9 during one receiver clock interval (rt clock). (rt0 is the position where the bit supposedly starts.) bit is determined according to majority rule (the data are the same twice or more out of three samplings). figure 11-4 data sampling method table 11-1 transfer rate (example) brg source clock 16 mhz 8 mhz 4 mhz 000 76800 [baud] 38400 [baud] 19200 [baud] 001 38400 19200 9600 010 19200 9600 4800 011 9600 4800 2400 100 4800 2400 1200 101 2400 1200 600 rt0 1 2 3 4 5 6 7 8 9101112 1314 15  01234567891011 bit 0 start bit bit 0 start bit (a) without noise rejection circuit rt clock internal receive data rt0 1 2 3 4 5 6 7 8 9101112 1314 15  01234567891011 bit 0 start bit bit 0 start bit rt clock internal receive data (b) with noise rejection circuit rxd pin rxd pin
page 128 11. asynchronous serial interface (uart ) 11.6 stop bit length TMP86CS25ADFG 11.6 stop bit length select a transmit stop bit length (1 bit or 2 bits) by uartcr1. 11.7 parity set parity / no parity by uartcr1 and set parity type (odd- or even-numbered) by uartcr1. 11.8 transmit/receive operation 11.8.1 data transmit operation set uartcr1 to ?1?. read uartsr to check ua rtsr = ?1?, then write data in tdbuf (transmit data buffer). writing data in tdbuf zero-cl ears uartsr, transfers the data to the transmit shift register and the data are sequenti ally output from the txd pin. the data output include a one-bit start bit, stop bits whose number is specified in uartcr1 and a parity bit if parity addition is specified. select the data transfer baud rate using uartcr1. when data transmit st arts, transmit buffer empty flag uartsr is set to ?1? a nd an inttxd interrupt is generated. while uartcr1 = ?0? and from when ?1? is written to uartcr1 to when send data are written to tdbuf, the txd pin is fixed at high level. when transmitting data, first read uartsr, then write data in tdbuf. otherwise, uartsr is not zero-cleared and transm it does not start. 11.8.2 data receive operation set uartcr1 to ?1?. when data are received vi a the rxd pin, the receive data are transferred to rdbuf (receive data buffer). at this time, the data transmitted includes a start bit and stop bit(s) and a parity bit if parity addition is specified. when stop bit(s) are received, data only are extracted and transferred to rdbuf (receive data buffer). then the receive buffer full flag ua rtsr is set and an intrxd interrupt is generated. select the data transfer baud rate using uartcr1. if an overrun error (oerr) occurs when data are received, the da ta are not transferre d to rdbuf (receive data buffer) but discarded; data in the rdbuf are not affected. note:when a receive operation is disabled by setting ua rtcr1 bit to ?0?, the setting becomes valid when data receive is completed. however, if a framing error occurs in data receive, the receive-disabling setting may not become valid. if a framing error occurs , be sure to perform a re-receive operation.
page 129 TMP86CS25ADFG 11.9 status flag 11.9.1 parity error when parity determined using the receive data bits diff ers from the received parity bit, the parity error flag uartsr is set to ?1?. the uartsr is cl eared to ?0? when the rdbuf is read after read- ing the uartsr. figure 11-5 generation of parity error 11.9.2 framing error when ?0? is sampled as the stop bit in the receive data, framing error flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the rdbuf is r ead after reading the uartsr. figure 11-6 generati on of framing error 11.9.3 overrun error when all bits in the next data are received while unread data are still in rdbuf, overrun error flag uartsr is set to ?1?. in this case, the receive data is discarded; data in rdbuf are not affected. the uartsr is cleared to ?0? when the rdbuf is read af ter reading the uartsr. parity stop shift register pxxxx0 * 1pxxxx0 xxxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears perr. final bit stop shift register xxxx0 * 0xxxx0 xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears ferr.
page 130 11. asynchronous serial interface (uart ) 11.9 status flag TMP86CS25ADFG figure 11-7 generati on of overrun error note:receive operations are di sabled until the overrun error flag uartsr is cleared. 11.9.4 receive data buffer full loading the received data in rdbuf sets receive data buffer full flag uartsr to "1". the uartsr is cleared to ?0? when the rdbuf is read after reading the uartsr. figure 11-8 generation of receive data buffer full note:if the overrun error flag uartsr is set during the period between reading the uartsr and reading the rdbuf, it cannot be cleared by only reading the rdbuf. therefore, after reading the rdbuf, read the uartsr again to check whether or not the overrun er ror flag which should have been cleared still remains set. 11.9.5 transmit data buffer empty when no data is in the transmit buffer tdbuf, uartsr is set to ?1?, that is, when data in tdbuf are transferred to the transmit shif t register and data transmit star ts, transmit data buffer empty flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the tdbuf is written after reading the uartsr. final bit stop shift register xxxx0 * 1xxxx0 yyyy xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears oerr. rdbuf uartsr final bit stop shift register xxxx0 * 1xxxx0 xxxx yyyy xxx0 ** rxd pin uartsr intrxd interrupt rdbuf after reading uartsr then rdbuf clears rbfl.
page 131 TMP86CS25ADFG figure 11-9 generation of transmit data buffer empty 11.9.6 transmit end flag when data are transmitted and no data is in tdbuf (uartsr = ?1?), transmit end flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the data transmit is stated after writing the tdbuf. figure 11-10 generation of transmit end flag and transmit data buffer empty shift register data write data write zzzz xxxx yyyy start bit 0 final bit stop 1xxxx0 ***** 1 * 1xxxx **** 1x ***** 1 1yyyy0 tdbuf txd pin uartsr inttxd interrupt after reading uartsr writing tdbuf clears tbep. shift register * 1yyyy *** 1 xx **** 1 x ***** 1 stop start 1yyyy0 bit 0 txd pin uartsr uartsr inttxd interrupt data write for tdbuf
page 132 11. asynchronous serial interface (uart ) 11.9 status flag TMP86CS25ADFG
page 133 TMP86CS25ADFG 12. synchronous serial interface (sio0) the TMP86CS25ADFG has a clocked-sync hronous 8-bit serial in terface. serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transf er up to 64 bits of data. serial interface is connected to outside peri pherl devices via so0, si0, sck0 port. 12.1 configuration figure 12-1 serial interface sio control / status register serial clock shift clock shift register 3 2 1 0 7 6 5 4 transmit and receive data buffer (8 bytes in dbr) control circuit cpu serial data output serial data input 8-bit transfer 4-bit transfer serial clock i/o buffer control circuit so0 si0 sck 0 sio0cr2 sio0cr1 sio0sr intsio0 interrupt request
page 134 12. synchronous serial interface (sio0) 12.2 control TMP86CS25ADFG 12.2 control the serial interface is controlled by sio control registers (sio0cr1/sio0cr2 ). the serial interface status can be determined by reading sio status register (sio0sr). the transmit and receive data buffer is controlled by th e sio0cr2. the data buff er is assigned to address 0f90h to 0f97h for sio in the dbr area, and can continuously transfer up to 8 words (bytes or nibbles) at one time. when the specified number of words has b een transferred, a buffer empty (in th e transmit mode) or a buffer full (in the receive mode or tran smit/receive mode) interrupt (intsio0) is generated. when the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive mode, a fixed interval wait can be applied to the serial clock fo r each word transferred. four different wait times can be selected with sio0cr2. note 1: fc; high-frequency clock [hz], fs; low-frequency clock [hz] note 2: set sios to "0" and sioinh to "1" when setting the transfer mode or serial clock. note 3: sio0cr1 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. sio control register 1 sio0cr176543210 (0f98h) sios sioinh siom sck (initial value: 0000 0000) sios indicate transfer start / stop 0: stop write only 1: start sioinh continue / abort transfer 0: continuously transfer 1: abort transfer (automatically cleared after abort) siom transfer mode select 000: 8-bit transmit mode 010: 4-bit transmit mode 100: 8-bit transmit / receive mode 101: 8-bit receive mode 110: 4-bit receive mode except the above: reserved sck serial clock select normal1/2, idle1/2 mode slow1/2 sleep1/2 mode write only dv7ck = 0 dv7ck = 1 000 fc/2 13 fs/2 5 fs/2 5 001 fc/2 8 fc/2 8 - 010 fc/2 7 fc/2 7 - 011 fc/2 6 fc/2 6 - 100 fc/2 5 fc/2 5 - 101 fc/2 4 fc/2 4 - 110 reserved 111 external clock ( input from sck0 pin ) sio control register 2 sio0cr276543210 (0f99h) wait buf (initial value: ***0 0000)
page 135 TMP86CS25ADFG note 1: the lower 4 bits of each buffer are used during 4-bit tr ansfers. zeros (0) are stored to the upper 4bits when receiving. note 2: transmitting starts at the lowest address. received data are also stored starting from the lowest address to the highest address. ( the first buffer address transmitted is 0f90h ). note 3: the value to be loaded to buf is held after transfer is completed. note 4: sio0cr2 must be set when the serial interface is stopped (siof = 0). note 5: *: don't care note 6: sio0cr2 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. note 1: t f ; frame time, t d ; data transfer time note 2: after sios is cleared to "0", siof is cleared to "0" at the termination of transfer or the setting of sioinh to "1". figure 12-2 fr ame time (t f ) and data transfer time (t d ) 12.3 serial clock 12.3.1 clock source internal clock or external clock for the source clock is selected by sio0cr1. wait wait control always sets "00" except 8-bit transmit / receive mode. write only 00: t f = t d (non wait) 01: t f = 2t d (wait) 10: t f = 4t d (wait) 11: t f = 8t d (wait) buf number of transfer words (buffer address in use) 000: 1 word transfer 0f90h 001: 2 words transfer 0f90h ~ 0f91h 010: 3 words transfer 0f90h ~ 0f92h 011: 4 words transfer 0f90h ~ 0f93h 100: 5 words transfer 0f90h ~ 0f94h 101: 6 words transfer 0f90h ~ 0f95h 110: 7 words transfer 0f90h ~ 0f96h 111: 8 words transfer 0f90h ~ 0f97h sio status register sio0sr76543210 (0f99h) siof sef siof serial transfer operating status moni- tor 0: 1: transfer terminated transfer in process read only sef shift operating status monitor 0: 1: shift operation terminated shift operation in process td tf (output) s ck0 output
page 136 12. synchronous serial interface (sio0) 12.3 serial clock TMP86CS25ADFG 12.3.1.1 internal clock any of six frequencies can be selected. the serial clock is output to the outside on the sck0 pin. the sck0 pin goes high when transfer starts. when data writing (in the transmit mo de) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wa it function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. note: 1 kbit = 1024 bit (fc = 16 mhz, fs = 32.768 khz) figure 12-3 automatic wait fu nction (at 4-bit transmit mode) 12.3.1.2 external clock an external clock connected to the sck 0 pin is used as the serial clock. in this case, output latch of this port should be set to "1". to ensure shifting, a pulse width of at least 4 machine cycles is required. this pulse is needed for the shift operatio n to execute certainly. actually, there is necessary processing time for interrupting, writing, and reading. the minimum pulse is determined by setting the mode and the pro- gram. therfore, maximum transfer frequenc y will be 488.3k bit/sec (at fc=16mhz). figure 12-4 external clock pulse width table 12-1 serial clock rate normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 sck clock baud rate clock baud rate clock baud rate 000 fc/2 13 1.91 kbps fs/2 5 1024 bps fs/2 5 1024 bps 001 fc/2 8 61.04 kbps fc/2 8 61.04 kbps - - 010 fc/2 7 122.07 kbps fc/2 7 122.07 kbps - - 011 fc/2 6 244.14 kbps fc/2 6 244.14 kbps - - 100 fc/2 5 488.28 kbps fc/2 5 488.28 kbps - - 101 fc/2 4 976.56 kbps fc/2 4 976.56 kbps - - 110 - - - - - - 111 external external external external external external a 1 a 2 b 0 b 1 b 2 b 3 c 0 c 1 a 3 a c b a 0 pin (output) pin (output) written transmit data a utomat i ca ll y wait function sck0 so0 t sckl t sckh tcyc = 4/fc (in the normal1/2, idle1/2 modes) 4/fs (in the slow1/2, sleep1/2 modes) t sckl , t sckh > 4tcyc sck0 pin (output)
page 137 TMP86CS25ADFG 12.3.2 shift edge the leading edge is used to transmit, a nd the trailing edge is used to receive. 12.3.2.1 leading edge transmitted data are shifted on the leading edge of the serial clock (falling edge of the sck 0 pin input/ output). 12.3.2.2 trailing edge received data are shifted on th e trailing edge of the serial clock (rising edge of the sck 0 pin input/out- put). figure 12-5 shift edge 12.4 number of bits to transfer either 4-bit or 8-bit serial transfer can be selected. when 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer re gister are used. the upper 4 bits are cleared to ?0? when receiving. the data is transferred in sequence star ting at the least significant bit (lsb). 12.5 number of w ords to transfer up to 8 words consisting of 4 bits of data (4-bit serial tran sfer) or 8 bits (8-bit serial tr ansfer) of data can be trans- ferred continuously. the number of words to be transferred can be selected by sio0cr2. an intsio0 interrupt is generated when the specified number of words has been transferred. if the number of words is to be changed during transfer , the serial interface must be stopped before making the ch ange. the number of words can be changed during automatic-wa it operation of an internal clock. in this case, the serial interface is not required to be stopped. bit 1 bit 2 bit 3 * 321 3210 ** 32 *** 3 bit 0 shift register shift register bit 1 bit 0 bit 2 bit 3 0 *** **** 210 * 10 ** 3210 (a) leading edge (b) trailing edge * ; don?t care so0 pin si0 pin sck0 pin sck0 pin
page 138 12. synchronous serial interface (sio0) 12.6 transfer mode TMP86CS25ADFG figure 12-6 number of words to transfer (example: 1word = 4bit) 12.6 transfer mode sio0cr1 is used to select the tran smit, receive, or transmit/receive mode. 12.6.1 4-bit and 8-bit transfer modes in these modes, firstly set the sio control register to the transmit mode, and then write first transmit data (number of transfer words to be transfer red) to the data buffer registers (dbr). after the data are written, the transmission is star ted by setting sio0cr1 to ?1?. the data are then output sequentially to the so pin in synchronous with th e serial clock, starting with the least significant bit (lsb). as soon as the lsb has been output, the data are transferred from the data buffer register to the shift register. when the final data bit has b een transferred and the data buffer re gister is empty, an intsio0 (buffer empty) interrupt is generated to request the next transmitted data. when the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next transmitted data are not loaded to the data buffer regist er by the time the number of data words specified with the sio0cr2 has been transmitted. writing even one word of data cancels the automatic-wait; there- fore, when transmitting two or more words, always wr ite the next word before transmission of the previous word is completed. note:automatic waits are also canceled by writing to a dbr not being used as a transmit data buffer register; there- fore, during sio do not use such dbr for other applicati ons. for example, when 3 words are transmitted, do not use the dbr of the remained 5 words. when an external clock is used, the data must be writte n to the data buffer register before shifting next data. thus, the transfer speed is determin ed by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. the transmission is ended by clear ing sio0cr1 to ?0? or se tting sio0cr1 to ?1? in buffer empty interrupt service program. a 1 a 2 a 3 a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 a 0 a 1 a 0 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 (a) 1 word transmit (b) 3 words transmit (c) 3 words receive so0 pin intsio0 interrupt intsio0 interrupt intsio0 interrupt so0 pin si0 pin sck0 pin sck0 pin sck0 pin
page 139 TMP86CS25ADFG sio0cr1 is cleared, the operation will end after all bi ts of words are transmitted. that the transmission has ended can be determin ed from the status of sio0sr because sio0sr is cleared to ?0? when a transfer is completed. when sio0cr1 is set, the transmission is immediately ended and sio0sr is cleared to ?0?. when an external clock is used, it is also necessary to clear sio0cr1 to ?0? before shifting the next data; if sio0cr1 is not cleared before shift out, dummy data will be transmitted and the operation will end. if it is necessary to change th e number of words, si o0cr1 should be cleared to ?0?, then sio0cr2 must be rewritten after confirming that sio0sr has been cleared to ?0?. figure 12-7 transfer m ode (example: 8bit, 1word tr ansfer, internal clock) figure 12-8 transfer mode (example: 8b it, 1word transfer , external clock) a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck0 pin (output) so0 pin intsio0 interrupt sio0cr1 sio0sr sio0sr sio0sr a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck0 pin (input) so0 pin intsio0 interrupt sio0cr1 sio0sr sio0sr
page 140 12. synchronous serial interface (sio0) 12.6 transfer mode TMP86CS25ADFG figure 12-9 transmiiied data ho ld time at end of transfer 12.6.2 4-bit and 8- bit receive modes after setting the control registers to the receive mode, set sio0cr1 to ?1? to enab le receiving. the data are then transferred to the shift register via the si pin in synchronous with the serial clock. when one word of data has been received, it is tran sferred from the shift register to the data buffer register (dbr). when the number of words specified with the sio0cr2 has been received, an intsio0 (buffer full) interrupt is generated to request that these data be read out. the da ta are then read from the da ta buffer registers by the interrupt service program. when the internal clock is used, and the previous data are not read from the data buffer register before the next data are received, the serial cloc k will stop and an automatic-wait will be initiated until the data are read. a wait will not be initiated if even one data word has been read. note:waits are also canceled by readi ng a dbr not being used as a received data buffer register is read; therefore, during sio0 do not use such dbr for other applications. when an external clock is used, the shift operation is synchronized with the extern al clock; therefore, the previous data are read before the next data are transferred to the data buffer register. if the previous data have not been read, the next data will not be transferred to th e data buffer register and th e receiving of any more data will be canceled. when an external clock is used, th e maximum transfer speed is determined by the delay between the time when the interrupt request is gene rated and when the data received have been read. the receiving is ended by clearing sio0cr1 to ?0? or setting sio0cr1 to ?1? in buffer full interrupt service program. when sio0cr1 is cleared, th e current data are transferred to the buffer. after sio0cr1 cleared, the receiving is ended at the ti me that the final bit of the data has been received. that the receiving has ended can be determined from the status of sio0sr . sio0sr is cleared to ?0? when the receiving is ended. after confirmed the receiving te rmination, the final recei ving data is read. when sio0cr1 is set, the receivi ng is immediately ended and sio0sr is cleared to ?0?. (the received data is ignored, and it is not required to be read out.) if it is necessary to change the number of words in external clock operation, sio0cr1 should be cleared to ?0? then sio0cr2 mu st be rewritten after confirming that sio0sr has been cleared to ?0?. if it is necessary to chan ge the number of words in internal clock, during automatic-wait operation which occurs after completion of data receiving, sio0cr2 must be rewr itten before the received data is read out. note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by clearing sio0cr1 to ?0?, read the last data and then switch the trans- fer mode. msb of last word t sodh = min 3.5/fc [s] ( in the normal1/2, idle1/2 modes) t sodh = min 3.5/fs [s] (in the slow1/2, sleep1/2 modes) sck0 pin so0 pin sio0sr
page 141 TMP86CS25ADFG figure 12-10 receive mode (example: 8b it, 1word transfer, internal clock) 12.6.3 8-bit trans fer / receive mode after setting the sio control register to the 8-bit transmit/recei ve mode, write the data to be transmitted first to the data buffer registers (dbr). af ter that, enable the transmit/receive by setting sio0cr1 to ?1?. when transmitting, the data are output from the so0 pin at leading edges of the serial clock. when receiving, the data are input to th e si0 pin at the trailing edges of the serial clock. when the all receive is enabled, 8-bit data are transferred from the shift re gister to the data buffer register. an intsio0 interrupt is generated when the number of data words specified with the sio0cr2 has been transferred. usually, read the receive data from the buffer register in the interrupt service. the data buffer register is used for both transmitting and receiving; therefore, always writ e the data to be transmitted af ter reading the all received data. when the internal clock is used, a wait is initiated until the received data are read and the next transfer data are written. a wait will not be initiated if ev en one transfer data word has been written. when an external clock is used, the shift operation is synchronized with the external clock; therefore, it is necessary to read the received data and write the data to be transmitted next before starting the next shift oper- ation. when an external clock is us ed, the transfer speed is determined by the maximum delay between genera- tion of an interrupt request and the received data are read and the data to be transmitted next are written. the transmit/receive operation is ended by clearing sio0cr1 to ?0? or setting sio0cr1 to ?1? in intsio0 interrupt service program. when sio0cr1 is cleared, the current data ar e transferred to the buff er. after sio0cr1 cleared, the transmitting/ receiving is ended at the time that the fi nal bit of the data has been transmitted. that the transmitting/receiving has ended can be determined fr om the status of sio0sr. sio0sr is cleared to ?0? when the transmitting/recei ving is ended. when sio0cr1 is set, th e transmit/receive operation is imm ediately ended and sio0sr is cleared to ?0?. if it is necessary to change the number of words in external clock operation, sio0cr1 should be cleared to ?0?, then sio0cr2 must be rewritten after confirming that sio0sr has been cleared to ?0?. if it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of transmit /receive operation, sio0 cr2 must be rewrit ten before reading and writing of the receive/transmit data. a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 dbr b a clear sios read out read out sck0 pin (output) si0 pin intsio0 interrupt sio0cr1 sio0sr sio0sr
page 142 12. synchronous serial interface (sio0) 12.6 transfer mode TMP86CS25ADFG note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by clearing sio0cr1 to ?0?, read the last data and then switch the trans- fer mode. figure 12-11 transfer / receive mode (examp le: 8bit, 1word transfe r, internal clock) figure 12-12 transmitted data hold ti me at end of tr ansfer / receive a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 c 1 c 0 c 2 c 3 c 4 c 5 c b c 6 c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 clear sios dbr d a read out (c) write (a) read out (d) write (b) sck0 pin (output) so0 pin intsio0 interrupt sio0cr1 sio0sr sio0sr si0 pin bit 7 of last word bit 6 t sodh = min 4/fc [s] ( in the normal1/2, idle1/2 modes) t sodh = min 4/fs [s] (in the slow1/2, sleep1/2 modes) sck0 pin so0 pin sio0sr
page 143 TMP86CS25ADFG 13. synchronous serial interface (sio1) the TMP86CS25ADFG has a clocked-sync hronous 8-bit serial in terface. serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transf er up to 64 bits of data. serial interface is connected to outside peri pherl devices via so1, si1, sck1 port. 13.1 configuration figure 13-1 serial interface sio control / status register serial clock shift clock shift register 3 2 1 0 7 6 5 4 transmit and receive data buffer (8 bytes in dbr) control circuit cpu serial data output serial data input 8-bit transfer 4-bit transfer serial clock i/o buffer control circuit so1 si1 sck 1 sio1cr2 sio1cr1 sio1sr intsio1 interrupt request
page 144 13. synchronous serial interface (sio1) 13.2 control TMP86CS25ADFG 13.2 control the serial interface is controlled by sio control registers (sio1cr1/sio1cr2 ). the serial interface status can be determined by reading sio status register (sio1sr). the transmit and receive data buffer is controlled by th e sio1cr2. the data buff er is assigned to address 0fa0h to 0fa7h for sio in the dbr area, and can continuously transfer up to 8 words (bytes or nibbles) at one time. when the specified number of words has been transferre d, a buffer empty (in the tran smit mode) or a buffer full (in the receive mode or tr ansmit/receive mode) interrup t (intsio1) is generated. when the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive mode, a fixed interval wait can be applied to the serial clock fo r each word transferred. four different wait times can be selected with sio1cr2. note 1: fc; high-frequency clock [hz], fs; low-frequency clock [hz] note 2: set sios to "0" and sioinh to "1" when setting the transfer mode or serial clock. note 3: sio1cr1 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. sio control register 1 sio1cr176543210 (0fa8h) sios sioinh siom sck (initial value: 0000 0000) sios indicate transfer start / stop 0: stop write only 1: start sioinh continue / abort transfer 0: continuously transfer 1: abort transfer (automatically cleared after abort) siom transfer mode select 000: 8-bit transmit mode 010: 4-bit transmit mode 100: 8-bit transmit / receive mode 101: 8-bit receive mode 110: 4-bit receive mode except the above: reserved sck serial clock select normal1/2, idle1/2 mode slow1/2 sleep1/2 mode write only dv7ck = 0 dv7ck = 1 000 fc/2 13 fs/2 5 fs/2 5 001 fc/2 8 fc/2 8 - 010 fc/2 7 fc/2 7 - 011 fc/2 6 fc/2 6 - 100 fc/2 5 fc/2 5 - 101 fc/2 4 fc/2 4 - 110 reserved 111 external clock ( input from sck1 pin ) sio control register 2 sio1cr276543210 (0fa9h) wait buf (initial value: ***0 0000)
page 145 TMP86CS25ADFG note 1: the lower 4 bits of each buffer are used during 4-bit tr ansfers. zeros (0) are stored to the upper 4bits when receiving. note 2: transmitting starts at the lowest address. received data are also stored starting from the lowest address to the highest address. ( the first buffer address transmitted is 0fa0h ). note 3: the value to be loaded to buf is held after transfer is completed. note 4: sio1cr2 must be set when the serial interface is stopped (siof = 0). note 5: *: don't care note 6: sio1cr2 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. note 1: t f ; frame time, t d ; data transfer time note 2: after sios is cleared to "0", siof is cleared to "0" at the termination of transfer or the setting of sioinh to "1". figure 13-2 fr ame time (t f ) and data transfer time (t d ) 13.3 serial clock 13.3.1 clock source internal clock or external clock for the source clock is selected by sio1cr1. wait wait control always sets "00" except 8-bit transmit / receive mode. write only 00: t f = t d (non wait) 01: t f = 2t d (wait) 10: t f = 4t d (wait) 11: t f = 8t d (wait) buf number of transfer words (buffer address in use) 000: 1 word transfer 0fa0h 001: 2 words transfer 0fa0h ~ 0fa1h 010: 3 words transfer 0fa0h ~ 0fa2h 011: 4 words transfer 0fa0h ~ 0fa3h 100: 5 words transfer 0fa0h ~ 0fa4h 101: 6 words transfer 0fa0h ~ 0fa5h 110: 7 words transfer 0fa0h ~ 0fa6h 111: 8 words transfer 0fa0h ~ 0fa7h sio status register sio1sr76543210 (0fa9h) siof sef siof serial transfer operating status moni- tor 0: 1: transfer terminated transfer in process read only sef shift operating status monitor 0: 1: shift operation terminated shift operation in process td tf (output) s ck1 output
page 146 13. synchronous serial interface (sio1) 13.3 serial clock TMP86CS25ADFG 13.3.1.1 internal clock any of six frequencies can be selected. the serial clock is output to the outside on the sck1 pin. the sck1 pin goes high when transfer starts. when data writing (in the transmit mo de) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wa it function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. note: 1 kbit = 1024 bit (fc = 16 mhz, fs = 32.768 khz) figure 13-3 automatic wait fu nction (at 4-bit transmit mode) 13.3.1.2 external clock an external clock connected to the sck 1 pin is used as the serial clock. in this case, output latch of this port should be set to "1". to ensure shifting, a pulse width of at least 4 machine cycles is required. this pulse is needed for the shift operatio n to execute certainly. actually, there is necessary processing time for interrupting, writing, and reading. the minimum pulse is determined by setting the mode and the pro- gram. therfore, maximum transfer frequenc y will be 488.3k bit/sec (at fc=16mhz). figure 13-4 external clock pulse width table 13-1 serial clock rate normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 sck clock baud rate clock baud rate clock baud rate 000 fc/2 13 1.91 kbps fs/2 5 1024 bps fs/2 5 1024 bps 001 fc/2 8 61.04 kbps fc/2 8 61.04 kbps - - 010 fc/2 7 122.07 kbps fc/2 7 122.07 kbps - - 011 fc/2 6 244.14 kbps fc/2 6 244.14 kbps - - 100 fc/2 5 488.28 kbps fc/2 5 488.28 kbps - - 101 fc/2 4 976.56 kbps fc/2 4 976.56 kbps - - 110 - - - - - - 111 external external external external external external a 1 a 2 b 0 b 1 b 2 b 3 c 0 c 1 a 3 a c b a 0 pin (output) pin (output) written transmit data a utomat i ca ll y wait function sck1 so1 t sckl t sckh tcyc = 4/fc (in the normal1/2, idle1/2 modes) 4/fs (in the slow1/2, sleep1/2 modes) t sckl , t sckh > 4tcyc sck1 pin (output)
page 147 TMP86CS25ADFG 13.3.2 shift edge the leading edge is used to transmit, a nd the trailing edge is used to receive. 13.3.2.1 leading edge transmitted data are shifted on the leading edge of the serial clock (falling edge of the sck 1 pin input/ output). 13.3.2.2 trailing edge received data are shifted on th e trailing edge of the serial clock (rising edge of the sck 1 pin input/out- put). figure 13-5 shift edge 13.4 number of bits to transfer either 4-bit or 8-bit serial transfer can be selected. when 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer re gister are used. the upper 4 bits are cleared to ?0? when receiving. the data is transferred in sequence star ting at the least significant bit (lsb). 13.5 number of w ords to transfer up to 8 words consisting of 4 bits of data (4-bit serial tran sfer) or 8 bits (8-bit serial tr ansfer) of data can be trans- ferred continuously. the number of words to be transferred can be selected by sio1cr2. an intsio1 interrupt is generated when the specified number of words has been transferred. if the number of words is to be changed during transfer , the serial interface must be stopped before making the ch ange. the number of words can be changed during automatic-wa it operation of an internal clock. in this case, the serial interface is not required to be stopped. bit 1 bit 2 bit 3 * 321 3210 ** 32 *** 3 bit 0 shift register shift register bit 1 bit 0 bit 2 bit 3 0 *** **** 210 * 10 ** 3210 (a) leading edge (b) trailing edge * ; don?t care so1 pin si1 pin sck1 pin sck1 pin
page 148 13. synchronous serial interface (sio1) 13.6 transfer mode TMP86CS25ADFG figure 13-6 number of words to transfer (example: 1word = 4bit) 13.6 transfer mode sio1cr1 is used to select the tran smit, receive, or transmit/receive mode. 13.6.1 4-bit and 8-bit transfer modes in these modes, firstly set the sio control register to the transmit mode, and then write first transmit data (number of transfer words to be transfer red) to the data buffer registers (dbr). after the data are written, the transmission is star ted by setting sio1cr1 to ?1?. the data are then output sequentially to the so pin in synchronous with th e serial clock, starting with the least significant bit (lsb). as soon as the lsb has been output, the data are transferred from the data buffer register to the shift register. when the final data bit has b een transferred and the data buffer re gister is empty, an intsio1 (buffer empty) interrupt is generated to request the next transmitted data. when the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next transmitted data are not loaded to the data buffer regist er by the time the number of data words specified with the sio1cr2 has been transmitted. writing even one word of data cancels the automatic-wait; there- fore, when transmitting two or more words, always wr ite the next word before transmission of the previous word is completed. note:automatic waits are also canceled by writing to a dbr not being used as a transmit data buffer register; there- fore, during sio do not use such dbr for other applicati ons. for example, when 3 words are transmitted, do not use the dbr of the remained 5 words. when an external clock is used, the data must be writte n to the data buffer register before shifting next data. thus, the transfer speed is determin ed by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. the transmission is ended by clear ing sio1cr1 to ?0? or se tting sio1cr1 to ?1? in buffer empty interrupt service program. a 1 a 2 a 3 a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 a 0 a 1 a 0 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 (a) 1 word transmit (b) 3 words transmit (c) 3 words receive so1 pin intsio1 interrupt intsio1 interrupt intsio1 interrupt so1 pin si1 pin sck1 pin sck1 pin sck1 pin
page 149 TMP86CS25ADFG sio1cr1 is cleared, the operation will end after all bi ts of words are transmitted. that the transmission has ended can be determin ed from the status of sio1sr because sio1sr is cleared to ?0? when a transfer is completed. when sio1cr1 is set, the transmission is immediately ended and sio1sr is cleared to ?0?. when an external clock is used, it is also necessary to clear sio1cr1 to ?0? before shifting the next data; if sio1cr1 is not cleared before shift out, dummy data will be transmitted and the operation will end. if it is necessary to change th e number of words, si o1cr1 should be cleared to ?0?, then sio1cr2 must be rewritten after confirming that sio1sr has been cleared to ?0?. figure 13-7 transfer m ode (example: 8bit, 1word tr ansfer, internal clock) figure 13-8 transfer mode (example: 8b it, 1word transfer , external clock) a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck1 pin (output) so1 pin intsio1 interrupt sio1cr1 sio1sr sio1sr sio1sr a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck1 pin (input) so1 pin intsio1 interrupt sio1cr1 sio1sr sio1sr
page 150 13. synchronous serial interface (sio1) 13.6 transfer mode TMP86CS25ADFG figure 13-9 transmiiied data ho ld time at end of transfer 13.6.2 4-bit and 8- bit receive modes after setting the control registers to the receive mode, set sio1cr1 to ?1? to enab le receiving. the data are then transferred to the shift register via the si pin in synchronous with the serial clock. when one word of data has been received, it is tran sferred from the shift register to the data buffer register (dbr). when the number of words specified with the sio1cr2 has been received, an intsio1 (buffer full) interrupt is generated to request that these data be read out. the da ta are then read from the da ta buffer registers by the interrupt service program. when the internal clock is used, and the previous data are not read from the data buffer register before the next data are received, the serial cloc k will stop and an automatic-wait will be initiated until the data are read. a wait will not be initiated if even one data word has been read. note:waits are also canceled by readi ng a dbr not being used as a received data buffer register is read; therefore, during sio1 do not use such dbr for other applications. when an external clock is used, the shift operation is synchronized with the extern al clock; therefore, the previous data are read before the next data are transferred to the data buffer register. if the previous data have not been read, the next data will not be transferred to th e data buffer register and th e receiving of any more data will be canceled. when an external clock is used, th e maximum transfer speed is determined by the delay between the time when the interrupt request is gene rated and when the data received have been read. the receiving is ended by clearing sio1cr1 to ?0? or setting sio1cr1 to ?1? in buffer full interrupt service program. when sio1cr1 is cleared, th e current data are transferred to the buffer. after sio1cr1 cleared, the receiving is ended at the ti me that the final bit of the data has been received. that the receiving has ended can be determined from the status of sio1sr . sio1sr is cleared to ?0? when the receiving is ended. after confirmed the receiving te rmination, the final recei ving data is read. when sio1cr1 is set, the receivi ng is immediately ended and sio1sr is cleared to ?0?. (the received data is ignored, and it is not required to be read out.) if it is necessary to change the number of words in external clock operation, sio1cr1 should be cleared to ?0? then sio1cr2 mu st be rewritten after confirming that sio1sr has been cleared to ?0?. if it is necessary to chan ge the number of words in internal clock, during automatic-wait operation which occurs after completion of data receiving, sio1cr2 must be rewr itten before the received data is read out. note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by clearing sio1cr1 to ?0?, read the last data and then switch the trans- fer mode. msb of last word t sodh = min 3.5/fc [s] ( in the normal1/2, idle1/2 modes) t sodh = min 3.5/fs [s] (in the slow1/2, sleep1/2 modes) sck1 pin so1 pin sio1sr
page 151 TMP86CS25ADFG figure 13-10 receive mode (example: 8b it, 1word transfer, internal clock) 13.6.3 8-bit trans fer / receive mode after setting the sio control register to the 8-bit transmit/recei ve mode, write the data to be transmitted first to the data buffer registers (dbr). af ter that, enable the transmit/receive by setting sio1cr1 to ?1?. when transmitting, the data are output from the so1 pin at leading edges of the serial clock. when receiving, the data are input to th e si1 pin at the trailing edges of the serial clock. when the all receive is enabled, 8-bit data are transferred from the shift re gister to the data buffer register. an intsio1 interrupt is generated when the number of data words specified with the sio1cr2 has been transferred. usually, read the receive data from the buffer register in the interrupt service. the data buffer register is used for both transmitting and receiving; therefore, always writ e the data to be transmitted af ter reading the all received data. when the internal clock is used, a wait is initiated until the received data are read and the next transfer data are written. a wait will not be initiated if ev en one transfer data word has been written. when an external clock is used, the shift operation is synchronized with the external clock; therefore, it is necessary to read the received data and write the data to be transmitted next before starting the next shift oper- ation. when an external clock is us ed, the transfer speed is determined by the maximum delay between genera- tion of an interrupt request and the received data are read and the data to be transmitted next are written. the transmit/receive operation is ended by clearing sio1cr1 to ?0? or setting sio1cr1 to ?1? in intsio1 interrupt service program. when sio1cr1 is cleared, the current data ar e transferred to the buff er. after sio1cr1 cleared, the transmitting/ receiving is ended at the time that the fi nal bit of the data has been transmitted. that the transmitting/receiving has ended can be determined fr om the status of sio1sr. sio1sr is cleared to ?0? when the transmitting/recei ving is ended. when sio1cr1 is set, th e transmit/receive operation is imm ediately ended and sio1sr is cleared to ?0?. if it is necessary to change the number of words in external clock operation, sio1cr1 should be cleared to ?0?, then sio1cr2 must be rewritten after confirming that sio1sr has been cleared to ?0?. if it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of transmit /receive operation, sio1 cr2 must be rewrit ten before reading and writing of the receive/transmit data. a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 dbr b a clear sios read out read out sck1 pin (output) si1 pin intsio1 interrupt sio1cr1 sio1sr sio1sr
page 152 13. synchronous serial interface (sio1) 13.6 transfer mode TMP86CS25ADFG note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by clearing sio1cr1 to ?0?, read the last data and then switch the trans- fer mode. figure 13-11 transfer / receive mode (examp le: 8bit, 1word transfe r, internal clock) figure 13-12 transmitted data hold ti me at end of tr ansfer / receive a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 c 1 c 0 c 2 c 3 c 4 c 5 c b c 6 c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 clear sios dbr d a read out (c) write (a) read out (d) write (b) sck1 pin (output) so1 pin intsio1 interrupt sio1cr1 sio1sr sio1sr si1 pin bit 7 of last word bit 6 t sodh = min 4/fc [s] ( in the normal1/2, idle1/2 modes) t sodh = min 4/fs [s] (in the slow1/2, sleep1/2 modes) sck1 pin so1 pin sio1sr
page 153 TMP86CS25ADFG 14. 8-bit ad converter (adc) the TMP86CS25ADFG have a 8-bit successi ve approximation ty pe ad converter. 14.1 configuration the circuit configuration of the 8-bit ad converter is shown in figure 14-1. it consists of control registers adccr1 and adccr2, converted value registers adcdr1 and adcdr2, a da converter, a sample-and-hold circuit, a comp arator, and a successive comparison circuit. figure 14-1 8-bit ad converter (adc) 3 4 8 8 ainds analog input multiplexer adrs r/2 r/2 r ack irefon ad conversion result register1,2 ad converter control register 1,2 adbf eocf intadc interrupt sain successive approximate circuit adccr2 adcdr1 adcdr2 adccr1  sample hold circuit 0 y to n s en shift clock da converter reference voltage analog comparator control circuit varef ain0 ain7 vss vdd
page 154 14. 8-bit ad converter (adc) 14.1 configuration TMP86CS25ADFG 14.2 control the ad converter consists of the following four registers: 1. ad converter control register 1 (adccr1) this register selects the analog channels in which to perform ad conversion and controls the ad con- verter as it starts operating. 2. ad converter control register 2 (adccr2) this register selects the ad conver sion time and controls the connect ion of the da converter (ladder resistor network). 3. ad converted value register (adcdr1) this register is used to store the digital value after being converted by the ad converter. 4. ad converted value register (adcdr2) this register monitors the oper ating status of the ad converter. note 1: select analog input when ad converter stops (adcdr2 = ?0?). note 2: when the analog input is all use disabl ing, the adccr1 should be set to ?1?. note 3: during conversion, do not perform output instruction to ma intain a precision for all of the pins. and port near to analo g input, do not input intense signaling of change. note 4: the adrs is automatically cl eared to ?0? after starting conversion. note 5: do not set adccr1 newly again during ad conv ersion. before setting adccr1 newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signal (intadc) is generated (e.g., interrupt handling routine). note 6: after stop or slow/sleep mode are started, ad conver ter control register 1 (adccr1) is all initialized and no data can be written in this register. therefore, to use ad conv erter again, set the adccr1 newly after returning to normal1 or normal2 mode. note 7: always set bit 5 in adccr1 to ?1? and set bit 6 in adccr1 to ?0?. ad converter control register 1 adccr1 (000eh) 76543210 adrs "0" "1" ainds sain (initial value: 0001 0000) adrs ad conversion start 0: 1: ? start r/w ainds analog input control 0: 1: analog input enable analog input disable sain analog input channel select 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 reserved reserved reserved reserved reserved reserved reserved reserved
page 155 TMP86CS25ADFG note 1: always set bit 0 in adccr2 to ?0? and set bit 4 in adccr2 to ?1?. note 2: when a read instruction for adccr2, bit 6 to 7 in adccr2 read in as undefined data. note 3: after stop or slow/sleep mode are started, ad conver ter control register 2 (adccr2) is all initialized and no data can be written in this register. therefore, to use ad conv erter again, set the adccr2 newly after returning to normal1 or normal2 mode. note 1: settings for ? ? ? in the above table are inhibited. note 2: set conversion time by analog reference voltage (v aref ) as follows. note 1: the adcdr2 is cleared to ?0? when reading the adcdr1. therefore, the ad conversion result should be read to adcdr2 more first than adcdr1. note 2: adcdr2 is set to ?1? when ad conversion starts and cleared to ?0? when the ad conversion is finished. it also is cleared upon entering stop or slow mode. note 3: if a read instruction is executed for adcdr2, read data of bits 7, 6 and 3 to 0 are unstable. ad converter control register 2 adccr2 (000fh) 76543210 irefon ?1? ack ?0? (initial value: **0* 000*) irefon da converter (ladder resistor) connection control 0: 1: connected only during ad conversion always connected r/w ack ad conversion time select 000: 001: 010: 011: 100: 101: 110: 111: 39/fc reserved 78/fc 156/fc 312/fc 624/fc 1248/fc reserved r/w table 14-1 conversion time according to ack setting and frequency condition conbersion time? 16mhz 8mhz 4 mhz 2 mhz 10mhz 5 mhz 2.5 mhz ack 000 39/fc - - - 19.5 s - - 15.6 s 001 reserved 010 78/fc - - 19.5 s39.0 s-15.6 s 31.2 s 011 156/fc - 19.5 s 39.0 s78.0 s 15.6 s 31.2 s 62.4 s 100 312/fc 19.5 s39.0 s 78.0 s 156.0 s 31.2 s 62.4 s 124.8 s 101 624/fc 39.0 s78.0 s156.0 s - 62.4 s 124.8 s- 110 1248/fc 78.0 s 156.0 s- -124.8 s- - 111 reserved - v aref = 4.5 to 5.5 v (15.6 s or more) - v aref = 2.7 to 5.5 v (31.2 s or more) - v aref = 1.8 to 5.5 v (124.8 s or more) ad conversion result register adcdr1 (0020h) 76543210 ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad00 (initial value: 0000 0000) ad conversion result register adcdr2 (0021h) 76543210 eocf adbf (initial value: **00 ****) eocf ad conversion end flag 0: before or during conversion 1: conversion completed read only adbf ad conversion busy flag 0: during stop of ad conversion 1: during ad conversion
page 156 14. 8-bit ad converter (adc) 14.3 function TMP86CS25ADFG 14.3 function 14.3.1 ad conveter operation when adccr1 is set to "1", ad conversion of the voltage at the analog input pin specified by adccr1 is thereby started. after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdr1) and at the same time adcdr2 is set to ?1?, the ad conversion finished interrupt (intadc) is generated. adccr1 is automatically cleared after ad conversion has started. do not set adccr1 newly again (restart) during ad conversion. before setting adrs newly again, check adcdr to see that the conversion is completed or wait until the inte rrupt signal (intadc) is generated (e.g., interrupt han- dling routine). figure 14-2 ad c onverter operation 14.3.2 ad converter operation 1. set up the ad converter control register 1 (adccr1) as follows: ? choose the channel to ad convert using ad input channel select (sain). ? specify analog input enable fo r analog input control (ainds). 2. set up the ad converter control register 2 (adccr2) as follows: ? set the ad conversion time using ad conversion time (ack). for details on how to set the con- version time, refer to table 14-1. ? choose irefon for da converter control. 3. after setting up 1. and 2. above, set ad conversion start (adrs) of ad converter control register 1 (adccr1) to ?1?. 4. after an elapse of the specified ad conversion time, the ad converted value is stored in ad con- verted value register 1 (adcdr1) and the ad conv ersion finished flag (e ocf) of ad converted value register 2 (adcdr2) is set to ?1?, upon wh ich time ad conversion interrupt intadc is gener- ated. 5. eocf is cleared to ?0? by a read of the conversion result. however, if reconverted before a register read, although eocf is cl eared the previous conversi on result is retained until the next conversion is completed. adcdr1 status eocf cleared by reading conversion result conversion result read conversion result read adcdr2 intadc interrupt reading adcdr1 reading adcdr2 adcdr2 adccr1 first conversion result second conversion result indeterminate ad conversion start ad conversion start
page 157 TMP86CS25ADFG 14.3.3 stop and slow m ode during ad conversion when the stop or slow mode is entered forcibly du ring ad conversion, the ad convert operation is sus- pended and the ad converter is initialized (adccr1 and adccr2 are initialized to initial value.). also, the conversion result is indeterminate. (c onversion results up to the previous operation are cleared, so be sure to read the conversion results before entering stop or slow mode.) when restored from stop or slow mode, ad conversion is not automatically restarted, so it is necessary to restart ad conversion. note that since the analog reference voltage is automa tically disconnected, there is no possibility of current flowing into the analog reference voltage. example :after selecting the conversion time of 19.5 s at 16 mhz and the analog input channel ain3 pin, perform ad conversion once. after checking eocf, read the converted value and store the 8-bit data in address 009fh on ram. ; ain select : : : : ; before setting the ad converter register, set each port reg- ister suitably (for detail, see chapter of i/o port.) ld (adccr1), 00100011b ; select ain3 ld (adccr2), 11011000b ; select conversion time (312/fc) and operation mode ; ad convert start set (adccr1). 7 ; adrs = 1 sloop: test (adcdr2). 5 ; eocf = 1 ? jrs t, sloop ; result data read ld a, (adcdr1) ld (9fh), a
page 158 14. 8-bit ad converter (adc) 14.3 function TMP86CS25ADFG 14.3.4 analog input volt age and ad conversion result the analog input voltage is corresponded to the 8-bit digital value converted by the ad as shown in figure 14-3. figure 14-3 analog i nput voltage and ad conv ersion result (typ.) 1 0 01h 02h 03h fdh feh ffh 2 3 253 254 255 256 analog input voltage ad conversion result 256 varef vss
page 159 TMP86CS25ADFG 14.4 precautions about ad converter 14.4.1 analog input pin voltage range make sure the analog input pins (ain 0 to ain7) are used at voltages w ithin vss below varef. if any volt- age outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncer- tain. the other analog input pi ns also are affected by that. 14.4.2 analog input shared pins the analog input pins (ain0 to ain7) are shared wi th input/output ports. when using any of the analog inputs to execute ad convers ion, do not execute in put/output instructions for all other ports. this is necessary to prevent the accuracy of ad conversi on from degrading. not only these analog input shared pins, some other pins may also be affected by noise arising from input/o utput to and from adjacent pins. 14.4.3 noise countermeasure the internal equivalent circuit of the analog input pins is shown in figure 14-4. the higher the output imped- ance of the analog input source, more easily they are su sceptible to noise. therefor e, make sure the output impedance of the signal source in your design is 5 k ? or less. toshiba also reco mmends attaching a capacitor external to the chip. figure 14-4 analog input equivalent ci rcuit and example of input pin processing da converter ainx analog comparator internal resistance allowable signal source impedance internal capacitance 5 k ? (typ) c = 22 pf (typ.) 5 k ? (max) note) i = 7~0
page 160 14. 8-bit ad converter (adc) 14.4 precautions about ad converter TMP86CS25ADFG
page 161 TMP86CS25ADFG 15. key-on wakeup (kwu) in the TMP86CS25ADFG, the stop mode is released by not only p20( int5 / stop ) pin but also four (stop2 to stop5) pins. when the stop mode is released by stop2 to stop5 pins, the stop pin needs to be used. in details, refer to the following section " 15.2 control ". 15.1 configuration figure 15-1 key-on wakeup circuit 15.2 control stop2 to stop5 pins can controlled by key-on wakeup c ontrol register (stopcr). it can be configured as enable/disable in 1-bit unit. when thos e pins are used for stop mode releas e, configure corresponding i/o pins to input mode by i/o port register beforehand. 15.3 function stop mode can be entered by setting up the system control register (syscr1), and can be exited by detecting the "l" level on stop2 to stop5 pins, which are enabled by stopcr, for releasing stop mode (note1). key-on wakeup control register stopcr76543210 (0f9ah) stop5 stop4 stop3 stop2 (initial value: 0000 ****) stop5 stop mode released by stop5 0:disable 1:enable write only stop4 stop mode released by stop4 0:disable 1:enable write only stop3 stop mode released by stop3 0:disable 1:enable write only stop2 stop mode released by stop2 0:disable 1:enable write only stopcr int5 stop stop mode release signal (1: release) (0f9ah) stop2 stop3 stop4 stop5 stop2 stop3 stop4 stop5
page 162 15. key-on wakeup (kwu) 15.3 function TMP86CS25ADFG also, each level of the stop2 to stop5 pins can be co nfirmed by reading correspondi ng i/o port data register, check all stop2 to stop5 pins "h" that is enabled by stopcr before the stop mode is startd (note2). note 1: when the stop mode released by the edge release mo de (syscr1 = ?0?), inhibit input from stop2 to stop5 pins by key-on wakeup control register (stopcr) or must be set "h" level into stop2 to stop5 pins that are available input during stop mode. note 2: when the stop pin input is high or stop2 to stop5 pins input which is enabled by stopcr is low, executing an instruction which starts stop mode wi ll not place in stop mode but instead will immediately start the release sequence (warm up). note 3: stop pin doesn?t have the control register such as stop cr, so when stop mode is released by stop2 to stop5 pins, stop pin also should be used as stop mode release function. note 4: in stop mode, key-on wakeup pin which is enabled as input mode (for releasing stop mode) by key-on wakeup control register (stopcr) may genarate the penet ration current, so the said pin must be disabled ad conversion input (analog voltage input). note 5: when the stop mode is released by stop2 to stop5 pins, the level of stop pin should hold "l" level (figure 15-2). figure 15-2 priority of stop pin and stop2 to stop5 pins table 15-1 release level (edge) of stop mode pin name release level (edge) syscr1="1" (note2) syscr1="0" stop "h" level rising edge stop2 "l" level don?t use (note1) stop3 "l" level don?t use (note1) stop4 "l" level don?t use (note1) stop5 "l" level don?t use (note1) stop pin a) stop release stop mode stop mode stop pin "l" b) release stop mode stop mode in case of stop2 to stop5 stop2 pin
page 163 TMP86CS25ADFG 16. lcd driver the TMP86CS25ADFG incorporates a driv er to directly drive th e liquid crystal display (lcd) and its control cir- cuit. the connecting pi ns with the lcd are as shown below: 1. segment output pin: 40 pins (seg39 to seg0) 2. segment output/ i/o port pin (shared): 20 pins (seg59 to seg40) 3. common output pin: 5 pins (com4 to com0) 4. common output i/o port pin (shared): 11 pins (com15 to com5) in addition, c0, c1, v1, v2, v3 and v4 are provided as the lcd drive booster circuit pins. the following three types of lcd can be driven directly: 1. 1/4 duty lcd: maximum 240 pixels (60 segments 4 digits) 2. 1/8 duty lcd: maximum 480 pixels (60 segments 8 digits) 3. 1/16 duty lcd: maximum 960 pixels (60 segments 16 digits) 16.1 configuration of lcd driver figure 16-1 lcd dr iver block diagram note: the lcd driver circuit has a built-in dedicated divider circuit. thus, during us e of the tool, lcd outputting is not stopped by debugger break processing. branking control dedicated divider low voltage booster circuit common driver disst bres duty3 duty4 duty5 refv duty c0 c1 v1 v2 v3 v4 com0 lcdctl1 lcd driver control register 1 lcdctl2 lcd driver control register 2 com15 segment driver display data buffer register display data select circuit timing gen. circuit duty control dbr data area seg0 fs fc seg39 seg40 seg59 vfsel0 vfsel1 vfsel2
page 164 16. lcd driver 16.1 configuration of lcd driver TMP86CS25ADFG 16.2 controlling lcd driver the lcd driver is controlled by the lcd control register 1 (lcdctl1 ) and the lcd control register 2 (lcdctl2). the display of the lcd driver is enabled by disst. note 1: after reset, lcdctl1 are set to ?0000? (initial value: reserved). set the duty as appropriate for lcd panel. note 2: switch lcdctl1 according to vdd. if it is not se t appropriately, an overcurrent may flow causing damage to the device. caution is especially r equired when vdd is battery-driven. note 3: if lcdctl1 is set to ?0? (lcd displa y blanking), all seg/com pins become vss level. note 4: when lcdctl1 for the lcd reference voltage is se t to ?0?, always make sure the reference power supply is entered from the v4 pin. in this case, input voltage from v4 pin should be kept within 2.7 v v4 vdd. note 5: when lcd is used, always set lcdctl1 to "1". note 6: reserved: not to be set. note: set the lcd control register 2 according to operating frequenc y. for details of the actual frame frequency, see table 16-1 lcd control register 1 lcdctl1 (0027h) 76543210 duty7 refv duty5 duty4 duty3 bres disst (initial value: 0000 00*0) duty7 duyu5 duty4 duty3 select duty. 0***: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: reserved 1/4 duty reserved 1/8 duty reserved reserved reserved 1/16 duty reserved r/w refv sets lcd reference voltage. 0: 1: v4 vdd (note 4) vdd < v4 5.5 v bres sets booster circuit. 0: 1: booster circuit disable booster circuit enable (note 5) disst controls lcd display. 0: 1: lcd display blanking lcd display enable lcd control register 2 lcdctl2 (0028h) 76543210 vfsel2 vfsel1 vfsel0 (initial value: **** *011) vfsel selects base frequency for frame frequency. 000: fc/2 9 (at 16 mhz) r/w 001: fc/2 8 (at 8 mhz) 010: fc/2 7 (at 6 mhz) 011: fc/2 6 (at 2 mhz) 1**: fs (at 32.768 khz)
page 165 TMP86CS25ADFG 16.2.1 frame frequency the frame frequency is set depending on the driving meth od and the base frequency as shown in table 16-1. the base frequency is selected with lcdctl2 depending on the basic clock frequencies fc and fs to be used. note 1: fc ; high-frequency clock frequency [h z], fs ; low-frequency clock frequency [hz] note 2: although this product is guaranteed to operate at fc = 1.32 [mhz] or less is not recommended for lcd dis- play as the frame frequency becomes 61 [hz] or less. 16.3 lcd booster circuit the TMP86CS25ADFG can boost (divide) the externally-su pplied reference voltage using the built-in booster cir- cuit as a power supply for driving the lcd. when v1 pin is the reference voltage, the inputted reference voltage is boosted by two times (v2), 3 times (v3) and 4 times (v4) to generate a voltage for a segment/common signal. when v2 pin is the reference voltage, the inputted reference volta ge is divided/boosted by 1/2 time (v1), 3/2 times (v3) and two times (v4). likewise, when v3 pin or v4 pin is the reference, the inputted reference voltage is boosted/ divided and the voltage ratio is v1 4 = v2 2 = v3 (4/3) = v4. as this circuit uses a 4-times boosting method, the bias ratio is 1/4 only. note 1: when the reference pin is other than v1 pi n, a condenser is required between v1 pin and gnd. note 2: when lcdctl1 is set to ?0?, input voltage from v4 pin should be kept within 2.7 v v4 vdd. table 16-1 frame frequency settings vfsel base frequency [hz] frame frequency [hz] 1/4 duty 1/8 duty 1/16 duty 000 (fc = 16 mhz) 93 93 93 001 (fc = 8 mhz) 93 93 93 010 (fc = 4 mhz) 93 93 93 011 (fc = 2 mhz) 93 93 93 1** fs (fs = 32.768 khz) 97.5 97.5 97.5 fc 2 9 ----- - fc 2 9 84 4 ?? ------------------------ - fc 2 9 42 8 ?? ------------------------ - fc 2 9 21 16 ?? --------------------------- - fc 2 8 ----- - fc 2 8 84 4 ?? ------------------------ - fc 2 8 42 8 ?? ------------------------ - fc 2 8 21 16 ?? --------------------------- - fc 2 7 ----- - fc 2 7 84 4 ?? ------------------------ - fc 2 7 42 8 ?? ------------------------ - fc 2 7 21 16 ?? --------------------------- - fc 2 6 ----- - fc 2 6 84 4 ?? ------------------------ - fc 2 6 42 8 ?? ------------------------ - fc 2 6 21 16 ?? --------------------------- - fs 84 4 ? -------------- fs 42 8 ? -------------- fs 21 16 ? -----------------
page 166 16. lcd driver 16.3 lcd booster circuit TMP86CS25ADFG 16.4 methods of connec ting lcd booster circuit 16.4.1 method of connecting booste r circuit by using a regulator if vdd is not stable because it is battery-driven, etc., we recommend a connection method using a regulator as shown below in order to preserve the quality of display. note: for use with vdd v4 (lcdctl1 = 0), always make sure the reference power supply is entered from v4. figure 16-2 method of c onnecting booster circui t by using a regulator 16.4.2 method of connecting booster circuit without using a regulator if stable vdd supply is achieved (vdd v4), the booster circuit can be connected without using a regulator as shown below. in this case, set lcdctl1 to ?0? and make sure the reference power supply is entered from the v4 pin. note:when lcdctl1 is set to ?0?, input vo ltage from v4 pin should be kept within 2.7 v v4 vdd. figure 16-3 method of connecting booste r circuit without using a regulator vdd c1 c0 seg v4 com v3 v2 v1 vss c c c c regulator regulator vdd c1 c0 seg v4 com v3 v2 v1 vss c c c c c (a) example of voltage step-up operation by a regulator (relative v1 pin) (b) example of voltage step-up operation by a regulator (relative v2 pin) note: c = 0.1 to 0.47 f vdd c1 c0 seg v4 com v3 v2 v1 vss c c c c c vdd c1 c0 seg v4 com v3 v2 v1 vss c r1 (adjustment of contrast) r2 c c c c (c) example of voltage division from vdd (relative to v4 pin) (d) example of voltage division from vdd (relative to v4 pin) note: c = 0.1 to 0.47 f
page 167 TMP86CS25ADFG 16.5 lcd display operation 16.5.1setting display data display data is stored in display data area (128 by tes in addresses 0f00h to 0f7fh) provided in dbr. display data stored in the display data area is automa tically read by hardware and sent to the lcd driver. the lcd driver generates segment and common signals according to display data and the driving method. thus, display patterns can be changed simply by rewriting the contents of display data area in the program. table 16-2 shows the correspondence between display data areas and seg/com pins. the light comes on when display data is ?1? and it goes ou t when ?0?. because the number of pi xels that can be driven varies with the method of driving the lcd, the number of bytes in th e display data area used to store display data also var- ies. thus, bytes not used to store display data and da ta memory corresponding to ddresses not connected to the lcd can be used for storing generally processed data. (see table 16-3) note:because the contents of display data area become unstabl e at powering on, execute the initialize routine for the initial setting. table 16-2 lcd display data area (dbr) 0f00h 0f10h 0f20h 0f30h 0f40h 0f50h 0f60h 0f70h com0 0f01h 0f11h 0f21h 0f31h 0f41h 0f51h 0f61h 0f71h com1 0f02h 0f12h 0f22h 0f32h 0f42h 0f52h 0f62h 0f72h com2 0f03h 0f13h 0f23h 0f33h 0f43h 0f53h 0f63h 0f73h com3 0f04h 0f14h 0f24h 0f34h 0f44h 0f54h 0f64h 0f74h com4 0f05h 0f15h 0f25h 0f35h 0f45h 0f55h 0f65h 0f75h com5 0f06h 0f16h 0f26h 0f36h 0f46h 0f56h 0f66h 0f76h com6 0f07h 0f17h 0f27h 0f37h 0f47h 0f57h 0f67h 0f77h com7 0f08h 0f18h 0f28h 0f38h 0f48h 0f58h 0f68h 0f78h com8 0f09h 0f19h 0f29h 0f39h 0f49h 0f59h 0f69h 0f79h com9 0f0ah 0f1ah 0f2ah 0f3ah 0f4ah 0f5ah 0f6ah 0f7ah com10 0f0bh 0f1bh 0f2bh 0f3bh 0f4bh 0f5bh 0f6bh 0f7bh com11 0f0ch 0f1ch 0f2ch 0f3ch 0f4ch 0f5ch 0f6ch 0f7ch com12 0f0dh 0f1dh 0f2dh 0f3dh 0f4dh 0f5dh 0f6dh 0f7dh com13 0f0eh 0f1eh 0f2eh 0f3eh 0f4eh 0f5eh 0f6eh 0f7eh com14 0f0fh 0f1fh 0f2fh 0f3fh 0f4fh 0f5fh 0f6fh 0f7fh com15 seg7 to seg0 seg15 to seg8 seg23 to seg16 seg31 to seg24 seg39 to seg32 seg47 to seg40 seg55 to seg48 seg59 to seg56 table 16-3 areas used to store display data driving method com number to be used 1/16 duty com15 to com0 1/8 duty com7 to com0 1/4 duty com3 to com0
page 168 16. lcd driver 16.6 method of controlling lcd driver TMP86CS25ADFG 16.5.2blanking the lcd display can be blanked by clearing disst to ?0?. blanking extinguishes the lcd by outputting gnd level to com/seg pins. if the stop mode is entered while the lcd display is on, disst is cleared to ?0? and blanking is performed automatically. if the stop mode is then reverted, disst is set to ?1? and display is resumed automatically. note:at reset, the segment dedicated pins (seg39 to seg0) and common output becomes gnd level, whereas the i/o port/segment shared pins (p1,p3,p5 ports) outpu t, the i/o port/common shared pins (p3,p7 ports) out- put become the high-impedance state. thus, if an external reset input lasts for a significant length of time, it may affect the lcd display such as blurring. 16.6 method of co ntrolling lcd driver 16.6.1 initial setting the procedure of initial setting is shown below. 16.6.2 storing display data display data is normally prepared as fixed data in the program memory (rom) and stored in the display data area by a load instruction. example 1: corresponding to the connection and display using a 1/8 duty lcd shown in figure 16-4, the table 16-4 shows display data and figure 16-5 shows displyay timing. figure 16-4 example of display data (1/8 duty) example :when 60 seg 8 com, 1/8 duty , 5 v-system lcd operates with fc = 8 mhz (at vdd = 5 v) ld (lcdctl1), 10010100b ; 1/8 duty, lcd reference voltage (vdd = v4), booster circuit enable set port setting ; set port condition for lcd related pins ld (lcdctl1), 10010101b ; lcd display enable set








   
page 169 TMP86CS25ADFG figure 16-5 example of di splay timing (1/8 duty) table 16-4 example of display data (1/8 duty) dbr se g 0 se g 1 se g 2 se g 3 se g 4 se g 5 se g 6 se g 7 hex dbr se g 8 se g 9 se g 10 se g 11 se g 12 se g 13 se g 14 se g 15 hex bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 com0 0f00h 1 1 1 1 10 1 1 df 0f10h 100 1 1 10 1b9??? com1 0f01h 0 0 100 100240f11h0 1 1000 1 1c6??? com2 0f02h 0 0 100 1 0 0 24 0f12h 0 1 10000 186??? com3 0f03h 0 0 100 1 0 0 24 0f13h 0 10 1 1 10 1ba??? com4 0f04h 0 0 100 1 0 0 24 0f14h 0 10000 1 1c2??? com5 0f05h 0 0 100 1 0 0 24 0f15h 0 1 1000 1 1c6??? com6 0f06h 0 0 1000 1 1 c4 0f16h 100 1 1 10 1b9??? com70f07h00000000000f17h0000000000??? com0 com1 com2 com7 seg0 seg0-com0 seg0-com1 v4 v4 vss v2 v1 v3 v4 vss tfame off (extinguish) off (extinguish) on (light)
page 170 16. lcd driver 16.6 method of controlling lcd driver TMP86CS25ADFG example 2: corresponding to the connection and display using a 1/16 duty lcd shown in figure 16-6, table 16-5 shows display data and figure 16-7 shows display timing. figure 16-6 example of display data (1/16 duty) table 16-5 example of display data (1/16 duty) dbr se g 0 se g 1 se g 2 se g 3 se g 4 se g 5 se g 6 se g 7 hex dbr se g 8 se g 9 se g 10 se g 11 se g 12 se g 13 se g 14 se g 15 hex bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 com0 0f00h 1 1 1 1 10 1 1 df 0f10h 100 1 1 10 1b9??? com1 0f01h 0 0 100 1 0 0 24 0f11h 0 1 1000 1 1c6??? com2 0f02h 0 0 100 1 0 0 24 0f12h 0 1 10000 186??? com3 0f03h 0 0 100 1 0 0 24 0f13h 0 10 1 1 10 1ba??? com4 0f04h 0 0 100 1 0 0 24 0f14h 0 10000 1 1c2??? com5 0f05h 0 0 100 1 0 0 24 0f15h 0 1 1000 1 1c6??? com6 0f06h 0 0 1000 1 1 c4 0f16h 100 1 1 10 1b9??? com70f07h00000000000f17h0000000000??? com8 0f08h 0 0 1000 1 1 c4 0f18h 100 1 1 10039??? com9 0f09h 0 0 100 1 0 0 24 0f19h 0 1 1000 1046??? com10 0f0ah 0 0 100000040f1ah0 10000 1042??? com11 0f0bh 0 0 100000040f1bh 100 1 1 10 1b9??? com12 0f0ch 0 0 10000 1840f1ch000000 1 1c0??? com13 0f0dh 0 0 1000 1 0 44 0f1dh 0 0 1000 1 1c4??? com14 0f0eh 0 0 100 1 1 1e40f1eh 1 10 1 1 1003b??? com150f0fh00000000000f1fh0000000000???
















  
page 171 TMP86CS25ADFG figure 16-7 example of display timing (1/16 duty) com0 com1 com2 com15 seg0 seg0-com0 seg0-com1 v4 v4 vss v2 v1 v3 v4 vss tfame off (extinguish) on (light) off (extinguish)
page 172 16. lcd driver 16.6 method of controlling lcd driver TMP86CS25ADFG
page 173 TMP86CS25ADFG 17. input/output circuitry 17.1 control pins the input/output circuitries of the TMP86CS25ADFG control pins are shown below. note: the test pin of the tmp86ps25 does not have a pull-down resistor and protect diode (d 1 ). fix the test pin at low-level. control pin i/o input/output circuitry remarks xin xout input output resonator connecting pins (high-frequency) r f = 1.2 m ? (typ.) r o = 1.0 k ? (typ.) xtin xtout input output resonator connecting pins (low-frequency) r f = 6 m ? (typ.) r o = 220 k ? (typ.) reset i/o sink open drain output hysteresis input pull-up resistor r in = 220 k ? (typ.) r = 1 k ? (typ.) test input pull-down resistor r in = 70 k ? (typ.) r = 1 k ? (typ.) fc rf r o osc. enable xin xout vdd vdd fs rf r r o xtin xtout vdd vdd xten osc. enable r in vdd address trap reset watchdog timer reset system clock reset reset input r vdd r in r d 1
page 174 17. input/output circuitry 17.2 input/output ports TMP86CS25ADFG 17.2 input/output ports note: port p1, p3, p5 and p7 are sink open drain output. but they ar e also used as a segment output of lcd. therefore, absolute maximum ratings of port input voltage should be used in ? 0.3 to v dd + 0.3 volts. port i/o input/output circuitry remarks p1 p7 i/o sink open drain output hysteresis input r = 100 ? (typ.) p5 i/o sink open drain output r = 100 ? (typ.) p2 i/o sink open drain output hysteresis input r = 100 ? (typ.) p30 p31 p32 p33 i/o sink open drain output hysteresis input high current output (nch) r = 100 ? (typ.) p34 p35 p36 i/o sink open drain output hysteresis input r = 100 ? (typ.) p6 i/o tri-state i/o hysteresis input r = 100 ? (typ.) initial "high-z" data output seg output p1lcr/p7lcr pin input input from output latch r initial "high-z" data output seg output p5lcr pin input input from output latch r initial "high-z" data output pin input input from output latch vdd r initial "high-z" data output seg output p3lcr pin input input from output latch r initial "high-z" data output com output p3lcr pin input input from output latch r initial "high-z" disable vdd pin input data output r
page 175 TMP86CS25ADFG 18. electrical characteristics 18.1 absolute maximum ratings the absolute maximum ratings are rated values which must not be exceeded during operat ion, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rati ng is exceeded, a device may break down or its performance may be degraded, causi ng it to catch fire or explode resul ting in injury to the user. thus, when designing products which include this de vice, ensure that no absolute maximu m rating value will ever be exceeded. (v ss = 0 v) parameter symbol pins rating unit supply voltage v dd ? 0.3 to 6.5 v input voltage v in ? 0.3 to v dd + 0.3 v output voltage v out ? 0.3 to v dd + 0.3 v output current (per 1 pin) i out1 p6 port ? 1.8 ma i out2 p1, p2, p34 to p36, p5, p6, p7 port 3.2 i out3 p30 to p33 port 30 output current (total) i out2 p1, p2, p34 to p36, p5, p6, p7 port 60 i out3 p30 to p33 port 80 power dissipation [topr = 85 c] pd 350 mw soldering temperature (time) tsld 260 (10 s) c storage temperature tstg ? 55 to 125 operating temperature topr ? 40 to 85
page 176 18. electrical characteristics 18.2 recommended operating condition TMP86CS25ADFG 18.2 recommended op erating condition the recommended operating co nditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. if the device is us ed under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified ac/dc values etc.), malfunction may occur. thus, when designing products which include this device, ensure that the r ecommended operating conditions for the device are always adhered to. note 1: when the supply voltage is v dd =1.8 to 2.0v, the operating tempreture is topr= -20 to 85 c. (v ss = 0 v, topr = ? 40 to 85 c) parameter symbol pins condition min max unit supply voltage v dd fc = 16 mhz normal1, 2 mode 4.5 5.5 v idle0, 1, 2 mode fc = 8 mhz normal1, 2 mode 2.7 idle0, 1, 2 mode fc = 4.2 mhz normal1, 2 mode 1.8 (note1) idle0, 1, 2 mode fs = 32.768 khz slow1, 2 mode sleep0, 1, 2 mode stop mode input high level v ih1 except hysteresis input v dd 4.5 v v dd 0.70 v dd v ih2 hysteresis input v dd 0.75 v ih3 v dd < 4.5 v v dd 0.90 input low level v il1 except hysteresis input v dd 4.5 v 0 v dd 0.30 v il2 hysteresis input v dd 0.25 v il3 v dd < 4.5 v v dd 0.10 lcd reference voltage range v1 in v1 lcdctl1 = ?1? vdd < v4 #1 #1 when lcdctl1 is set to ?1?, always keep the condition of vdd < v4. 1.0 1.375 v2 in v2 2.0 2.750 v3 in v3 3.0 4.125 v4 in v4 4.0 5.500 v4 in v4 #2 #2 when lcdctl1 is set to ?0?, always supply the reference voltage from v4 pin. lcdctl1 = ?0? 2.7 vdd clock frequency fc xin, xout v dd = 1.8 v to 5.5 v 1.0 4.2 mhz v dd = 2.7 v to 5.5 v 8.0 v dd = 4.5 v to 5.5 v 16.0 fs xtin, xtout 30.0 34.0 khz
page 177 TMP86CS25ADFG 18.3 dc characteristics note 1: typical values show those at topr = 25 c, v dd = 5 v note 2: input current (i in1 , i in3 ): the current through pull-up or pull-down resistor is not included. note 3: i dd does not include i ref current. note 4: the supply currents in slow2 and sleep2 modes are equivalent to those in idle0, idle1, and idle2 modes. (v ss = 0 v, topr = ? 40 to 85 c) parameter symbol pins condition min typ. max unit hysteresis voltage v hs hysteresis input ? 0.9 ? v input current i in1 test v dd = 5.5 v v in = 5.5 v/0 v ?? 2 a i in2 sink open drain, tri-state port i in3 reset , stop input resistance r in1 test pull-down v dd = 5.5 v, v in = 5.5 v ?70? k ? r in2 reset pull-up vdd = 5.5 v, vin = 0 v 100 220 450 output leakage current i lo sink open drain, tri-state port v dd = 5.5 v, v out = 5.5 v/0 v ?? 2 a output high voltage v oh2 tri-state port v dd = 4.5 v, i oh = ? 0.7 ma 4.1 ? ? v output low voltage v ol except xout and p30 to p33 port v dd = 4.5 v, i ol = 1.6 ma ??0.4 output low current i ol high current port (p30 to p33 port) v dd = 4.5 v, v ol = 1.0 v ?20?ma supply current in normal 1, 2 mode i dd v dd = 5.5 v v in = 5.3 v/0.2 v fc = 16 mhz fs = 32.768 khz ?6.07.0 ma supply current in idle0, 1, 2 mode ?4.25.0 supply current in slow1 mode v dd = 3.0 v v in = 2.8 v/0.2 v fs = 32.768 khz ?8.525 a supply current in sleep1 mode ?5.015 supply current in sleep0 mode ?3.013 supply current in stop mode v dd = 5.5 v v in = 5.3 v/0.2 v ?0.510
page 178 18. electrical characteristics 18.4 ad conversion characteristics TMP86CS25ADFG 18.4 ad conversi on characteristics note 1: the total error includes all errors except a quantizati on error, and is defined as ma ximum deviation from the ideal conversion line. note 2: conversion time is different in recommended value by power supply voltage. about conversion time, refer to ?8-bit ad converter(adc)?. note 3: please use input voltage to ain input pin in limit of v aref ? v ss . when voltage of range outside is input, conversion val ue becomes unsettled and gives affect to other channel conversion value. note 4: analog reference voltage range: ? v aref = v aref ? v ss note 5: when ad is used with v dd < 2.7 v, the guaranteed temperature range varies with the operating voltage. (v ss = 0.0 v, 4.5 v v dd 5.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit analog reference voltage v aref v dd ? 1.5 ? v dd v analog reference voltage range (note 4) ? v aref 3.0 ? ? analog input voltage v ain v ss ? v aref power supply current of analog reference voltage i ref v dd = v aref = 5.5 v v ss = 0.0 v ?0.61.0ma non linearity error v dd = 5.0 v, v ss = 0.0 v v aref = 5.0 v ?? 1 lsb zero point error ?? 1 full scale error ?? 1 total error ?? 2 (v ss = 0.0 v, 2.7 v v dd < 4.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit analog reference voltage v aref v dd ? 1.5 ? v dd v analog reference voltage range (note 4) ? v aref 2.5 ? ? analog input voltage v ain v ss ? v aref power supply current of analog reference voltage i ref v dd = v aref = 4.5 v v ss = 0.0 v ?0.50.8ma non linearity error v dd = 2.7 v, v ss = 0.0 v v aref = 2.7 v ?? 1 lsb zero point error ?? 1 full scale error ?? 1 total error ?? 2 (v ss = 0.0 v, 2.0 v v dd < 2.7 v, topr = ? 40 to 85 c) (note 5) (v ss = 0.0 v, 1.8 v v dd < 2.0 v, topr = ? 10 to 85 c) (note 5) parameter symbol condition min typ. max unit analog reference voltage v aref v dd ? 0.9 ? v dd v analog reference voltage range (note 4) ? v aref 1.8 v v dd < 2.0 v 1.8 ? ? 2.0 v v dd < 2.7 v 2.0 ? ? analog input voltage v ain v ss ? v aref power supply current of analog reference voltage i ref v dd = v aref = 2.7 v v ss = 0.0 v ?0.30.5ma non linearity error v dd = 1.8 v, v ss = 0.0 v v aref = 1.8 v ?? 2 lsb zero point error ?? 2 full scale error ?? 2 total error ?? 4
page 179 TMP86CS25ADFG 18.5 ac characteristics note 1: when the supply voltage is v dd =1.8 to 2.0v, the operating tempreture is topr= -20 to 85 c. 18.6 timer counter 1 inpu t (ecin) characteristics (v ss = 0 v, v dd = 4.5 to 5.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit machine cycle time tcy normal1, 2 mode 0.25 ? 4 s idle0, 1, 2 mode slow1, 2 mode 117.6 ? 133.3 sleep0, 1, 2 mode high level clock pulse width t wch for external clock operation (xin input) fc = 16 mhz ? 31.25 ? ns low level clock pulse width t wcl high level clock pulse width t wch for external clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low level clock pulse width t wcl (v ss = 0 v, v dd = 2.7 to 4.5 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit machine cycle time tcy normal1, 2 mode 0.5 ? 4 s idle0, 1, 2 mode slow1, 2 mode 117.6 ? 133.3 sleep0, 1, 2 mode high level clock pulse width t wch for external clock operation (xin input) fc = 8 mhz ? 62.5 ? ns low level clock pulse width t wcl high level clock pulse width t wch for external clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low level clock pulse width t wcl (v ss = 0 v, v dd = 1.8 to 2.7 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit machine cycle time tcy normal1, 2 mode 0.95 ? 4 s idle0, 1, 2 mode slow1, 2 mode 117.6 ? 133.3 sleep0, 1, 2 mode high level clock pulse width t wch for external clock operation (xin input) fc = 4.2 mhz ? 119.05 ? ns low level clock pulse width t wcl high level clock pulse width t wch for external clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low level clock pulse width t wcl (v ss = 0 v, topr = ? 40 to 85 c) parameter symbol condition min typ. max unit tc1 input (ecin input) t tc1 frequency measurement mode v dd = 4.5 to 5.5 v single edge count ??1.0 mhz frequency measurement mode v dd = 2.7 to 4.5 v single edge count ??0.5 frequency measurement mode v dd = 1.8 to 2.7 v single edge count ? ? 0.262
page 180 18. electrical characteristics 18.7 recommended oscillating conditions TMP86CS25ADFG 18.7 recommended osc illating conditions note 1: a quartz resonator can be used for high-frequency oscillation only when v dd is 2.7 v or above. if v dd is below 2.7 v, use a ceramic resonator. note 2: to ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will act ually be mounted. note 3: for the resonators to be used with toshiba microcont rollers, we recommend ceramic resonators manufactured by murata manufacturing co., ltd. for details, please visit the website of murata at the following url: http://www.murata.com 18.8 handling precaution - the solderability test conditions for lead-free produc ts (indicated by the suffix g in product name) are shown below. 1. when using the sn-37pb solder bath solder bath temperature = 230 c dipping time = 5 seconds number of times = once r-type flux used 2. when using the sn-3.0ag-0.5cu solder bath solder bath temperature = 245 c dipping time = 5 seconds number of times = once r-type flux used note: the pass criteron of the above test is as follows: solderability rate until forming 95 % - when using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we recommend electrically shielding the package in order to maintain normal operating condition. (2) low-frequency oscillation (1) high-frequency oscillation xin xout c 2 c 1 xtin xtout c 2 c 1
page 181 TMP86CS25ADFG 19. package dimension p-lqfp100-1414-0.50f unit: mm
page 182 19. package dimension TMP86CS25ADFG
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