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? semiconductor components industries, llc, 2004 march, 2004 ? rev. 5 1 publication order number: nbsg53a/d nbsg53a 2.5v/3.3vsige selectable differential clock and data d flip-flop/clock divider with reset and ols* the nbsg53a is a multi?function differential d flip?flop (dff) or fixed divide by two (div/2) clock generator. this is a part of the gigacomm ? family of high performance silicon germanium products. a strappable control pin is provided to select between the two functions. the device is housed in a low profile 4x4 mm 16?pin flip?chip bga (fcbga) or a 3x3 mm 16 pin qfn package. the nbsg53a is a device with data, clock, ols, reset, and select inputs. differential inputs incorporate internal 50 termination resistors and accept necl (negative ecl), pecl (positive ecl), lvcmos/lvttl, cml, or lvds. the ols input is used to program the peak?to?peak output amplitude between 0 and 800 mv in five discrete steps. the reset and select inputs are single?ended and can be driven with either lvecl or lvcmos/lvttl input levels. data is transferred to the outputs on the positive edge of the clock. the differential clock inputs of the nbsg53a allow the device to also be used as a negative edge triggered device. ? maximum input clock frequency (dff) > 8 ghz typical (see figures 4, 6, 8, 10, and 11) ? maximum input clock frequency (div/2) > 10 ghz typical (see figures 5, 7, 9, 10, and 11) ? 210 ps typical propagation delay (ols = float) ? 45 ps typical rise and fall times (ols = float) ? div/2 mode (active with select low) ? dff mode (active with select high) ? selectable swing pecl output with operating range: v cc = 2.375 v to 3.465 v with v ee = 0 v ? selectable swing necl output with necl inputs with operating range: v cc = 0 v with v ee = ?2.375 v to ?3.465 v ? selectable output level (0 v, 200 mv, 400 mv, 600 mv, or 800 mv peak?to?peak output) ? 50 internal input termination resistors on all differential inputs *output level select **for further details, refer to application note and8002/d fcbga?16 ba suffix case 489 marking diagram** sg 53a lyw board description NBSG53ABAEVB nbsg53aba evaluation board http://onsemi.com a = assembly location l = wafer lot y = year w = work week sg53a alyw qfn?16 mn suffix case 485g see detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet. ordering information
nbsg53a http://onsemi.com 2 vtd clk clk vtclk v cc r vtclk d d vtd v cc v ee sel ols q q a b c d 12 34 figure 1. bga?16 pinout (top view) vtd d d vtd v cc r sel ols v ee q q v cc vtclk clk clk vtclk 5678 16 15 14 13 12 11 10 9 1 2 3 4 nbsg53a exposed pad (ep) figure 2. qfn?16 pinout (top view) table 1. pin description pin bga qfn name i/o description c2 1 vtclk ? internal 50 termination pin. see table 4. c1 2 clk ecl, cml, lvcmos, lvds, lvttl input inverted differential input. b1 3 clk ecl, cml, lvcmos, lvds, lvttl input noninverted differential input. b2 4 vtclk ? internal 50 termination pin. see table 4. a1 5 vtd ? internal 50 termination pin. see table 4. a2 6 d ecl, cml, lvcmos, lvds, lvttl input inverted differential input. a3 7 d ecl, cml, lvcmos, lvds, lvttl input noninverted differential input. a4 8 vtd ? internal 50 termination pin. see table 4. d1,b3 9,16 v cc ? positive supply voltage b4 10 q rsecl output inverted differential output. typically terminated with 50 resistor to v tt = v cc ? 2 v. c4 11 q rsecl output noninverted differential output. typically terminated with 50 resistor to v tt = v cc ? 2 v. c3 12 v ee ? negative supply voltage d4 13 ols* input input pin for the output level select (ols). see table 2. d3 14 sel lvecl, lvcmos, lvttl input select logic input. internal 75 k to v ee . d2 15 r lvecl, lvcmos, lvttl input reset d flip?flop. internal 75 k to v ee . n/a ? ep exposed pad. (note 1) 1. all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. the thermally exposed pad (ep) on package bottom (see case drawing) must be attached to a heat?sinking conduit. 2. in the differential configuration when the input termination pins (vtd, vtd , vtclk, vtclk ) are connected to a common termination volt- age, and if no signal is applied then the device will be susceptible to self?oscillation. 3. when an output level of 400 mv is desired and v cc ? v ee > 3.0 v, 2k resistor should be connected from ols pin to v ee .
nbsg53a http://onsemi.com 3 figure 3. simplified logic diagram d d sel clk clk vtd v cc q q flip?flop (div/2) flip?flop (dff) r d d vtd ols r q q v ee vtclk vtclk r 75 k 75 k 50 50 50 50 0 1 2 2 2 2 2 2 2 table 2. output level select (ols) ols q/q vpp ols sensitivity v cc 800 mv ols ? 75 mv v cc ? 0.4 v 200 mv ols 150 mv v cc ? 0.8 v 600 mv ols 100 mv v cc ? 1.2 v 0 ols 75 mv v ee (note 4) 400 mv ols + 100 mv float 600 mv n/a 4. when an output level of 400 mv is desired and v cc ? v ee > 3.0 v, 2.0 k resistor should be connected from ols to v ee . table 3. truth table r sel d clk q function h x x x l reset l h l z l dff l h h z h dff l l x z q div/2 z = low to high transition table 4. interfacing options interfacing options connections cml connect vtclk, vtd and vtclk , vtd to v cc lvds connect vtclk, vtd and vtclk , vtd together ac?coupled bias vtclk, vtd and vtclk , vtd inputs within common mode range (v ihcmr ) rsecl, pecl, necl standard ecl termination techniques lvttl, lvcmos an external voltage (v thr ) should be applied to the unused complementary differential input. nominal v thr is 1.5 v for lvttl and v cc /2 for lvcmos inputs. this voltage must be within the v thr specification.
nbsg53a http://onsemi.com 4 table 5. attributes characteristics value positive operating voltage range for v cc (v ee = 0 v) 2.375 v to 3.465 v negative operating voltage range for v ee (v cc = 0 v) ?2.375 v to ?3.465 v internal input pulldown resistor (r, sel) 75 k esd protection human body model machine model charged device model > 1.5 kv > 50 v > 4 kv moisture sensitivity (note 5) 16?fcbga 16?qfn level 3 level 1 flammability rating ul 94 v?0 @ 0.125 in oxygen index 28 to 34 transistor count 482 meets or exceeds jedec spec eia/jesd78 ic latchup test 5. for additional information, refer to application note and8003/d. table 6. maximum ratings symbol parameter condition 1 condition 2 rating units v cc positive power supply v ee = 0 v 3.6 v v ee negative power supply v cc = 0 v ?3.6 v v i positive input negative input v ee = 0 v v cc = 0 v v i v cc v i v ee 3.6 ?3.6 v v v inpp differential input voltage |d ? d | v cc ? v ee 2.8 v v cc ? v ee < 2.8 v 2.8 |v cc ? v ee | v v i in input current through r t (50 resistor) static surge 45 80 ma ma i out output current continuous surge 25 50 ma ma t a operating temperature range 16 fcbga 16 qfn ?40 to +70 ?40 to +85 c t stg storage temperature range ?65 to +150 c ja thermal resistance (junction?to?ambient) (note 6) 0 lfpm 500 lfpm 0 lfpm 500 lfpm 16 fcbga 16 fcbga 16 qfn 16 qfn 108 86 41.6 35.2 c/w c/w c/w c/w jc thermal resistance (junction?to?case) 2s2p (note 6) 2s2p (note 7) 16 fcbga 16 qfn 5.0 4.0 c/w c/w t sol wave solder < 15 seconds 225 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 6. jedec standard 51?6, multilayer board ? 2s2p (2 signal, 2 power). 7. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
nbsg53a http://onsemi.com 5 table 7. dc characteristics, input with pecl output v cc = 2.5 v; v ee = 0 v (note 8) ?40 c 25 c 70 c(bga)/85 c(qfn)** symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current 33 45 57 33 45 57 33 45 57 ma v oh output high voltage (note 9) 1460 1510 1560 1490 1540 1590 1515 1565 1615 mv v ol output low voltage (note 9) (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols = float) (ols = v cc ? 1.2 v) (ols = v ee ) 555 1235 775 1455 1005 705 1295 895 1505 1095 855 1355 1015 1555 1185 595 1270 810 1490 1040 745 1330 930 1540 1130 895 1390 1050 1590 1220 625 1295 840 1510 1065 775 1355 960 1560 1155 925 1415 1080 1610 1245 mv v outpp output voltage amplitude (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols = float) (ols = v cc ? 1.2 v) (ols = v ee ) 715 125 525 0 325 805 215 615 5 415 705 120 520 0 320 795 210 610 0 410 700 120 515 0 320 790 210 605 5 410 mv v ih input high voltage (single?ended) (notes 11 and 13) clk, clk , d, d v ee + 1275 v cc ? 1000* v cc v ee + 1275 v cc ? 1000* v cc v ee + 1275 v cc ? 1000* v cc mv v il input low voltage (single?ended) (notes 12 and 13) clk, clk , d, d v ee v cc ? 1400* v ih ? 150 v ee v cc ? 1400* v ih ? 150 v ee v cc ? 1400* v ih ? 150 mv v ih input high voltage (single?ended) r, sel 1290 v cc 1355 v cc 1415 v cc mv v il input low voltage (single?ended) r, sel v ee 890 v ee 955 v ee 1015 mv v thr input threshold voltage (single?ended) (note 13) v ee + 1125 v cc ? 75 v ee + 1125 v cc ? 75 v ee + 1125 v cc ? 75 mv v ihcmr input high voltage common mode range (differential configuration) (note 10) 1.2 2.5 1.2 2.5 1.2 2.5 v r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@v ih ) r, sel clk, clk , d, d 35 5 100 50 35 5 100 50 35 5 100 50 a i il input low current (@v il ) r, sel clk, clk , d, d 20 5 100 50 20 5 100 50 20 5 100 50 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. input and output parameters vary 1:1 with v cc . v ee can vary +0.125 v to ?0.965 v. 9. all outputs loaded with 50 to v cc ? 2.0 v. 10. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 11. v ih cannot exceed v cc . |v ih ? v thr | < 2600 mv. 12. v il always v ee . |v il ? v thr | < 2600 mv. 13. v thr is the voltage applied to one input when running in single?ended mode. *typicals used for testing purposes. **the device packaged in fcbga?16 have maximum ambient temperature specification of 70 c and devices packaged in qfn?16 have maximum ambient temperature specification of 85 c.
nbsg53a http://onsemi.com 6 table 8. dc characteristics, input with pecl output v cc = 3.3 v; v ee = 0 v (note 14) ?40 c 25 c 70 c(bga)/85 c(qfn)*** symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current 35 47 59 35 47 59 35 47 59 ma v oh output high voltage (note 15) 2260 2310 2360 2290 2340 2390 2315 2365 2415 mv v ol output low voltage (note 15) (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols = float) (ols = v cc ? 1.2 v) **(ols = v ee ) 1320 2030 1550 2260 1785 1470 2090 1670 2310 1875 1620 2150 1790 2360 1965 1360 2065 1585 2290 1820 1510 2125 1705 2340 1910 1660 2185 1825 2390 2000 1390 2090 1615 2315 1850 1540 2150 1735 2365 1940 1690 2210 1855 2415 2030 mv v outpp output amplitude voltage (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols = float) (ols = v cc ? 1.2 v) **(ols = v ee ) 750 130 550 0 345 840 220 640 0 435 740 125 545 0 340 830 215 635 0 430 735 125 540 0 335 825 215 630 0 425 mv v ih input high voltage (single?ended) (notes 17 and 19) clk, clk , d, d v ee + 1275 v cc ? 1000* v cc v ee + 1275 v cc ? 1000* v cc v ee + 1275 v cc ? 1000* v cc mv v il input low voltage (single?ended) (notes 18 and 19) clk, clk , d, d v ih ? 2600 v cc ? 1400* v ih ? 150 v ih ? 2600 v cc ? 1400* v ih ? 150 v ih ? 2600 v cc ? 1400* v ih ? 150 mv v ih input high voltage (single?ended) r, sel 2090 v cc 2155 v cc 2215 v cc mv v il input low voltage (single?ended) r, sel v ee 1690 v ee 1755 v ee 1815 mv v thr input threshold voltage (single?ended) (note 19) v ee + 1125 v cc ? 75 v ee + 1125 v cc ? 75 v ee + 1125 v cc ? 75 mv v ihcmr input high voltage common mode range (differential configuration) (note 16) 1.2 3.3 1.2 3.3 1.2 3.3 v r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@v ih ) r, sel clk, clk , d, d 35 5 100 50 35 5 100 50 35 5 100 50 a i il input low current (@v il ) r, sel clk, clk , d, d 20 5 100 50 20 5 100 50 20 5 100 50 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. input and output parameters vary 1:1 with v cc . v ee can vary +0.925 v to ?0.165 v. 15. all outputs loaded with 50 to v cc ? 2.0 v. 16. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. 17. v ih cannot exceed v cc . |v ih ? v thr | < 2600 mv. 18. v il always v ee . |v il ? v thr | < 2600 mv. 19. v thr is the voltage applied to one input when running in single?ended mode. *typicals used for testing purposes. **when an output level of 400 mv is desired and v cc ? v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee . ***the device packaged in fcbga?16 have maximum ambient temperature specification of 70 c and devices packaged in qfn?16 have maximum ambient temperature specification of 85 c.
nbsg53a http://onsemi.com 7 table 9. dc characteristics, necl input with necl output v cc = 0 v; v ee = ?3.465 v to ?2.375 v (note 20) ?40 c 25 c 70 c(bga)/85 c(qfn)*** symbol characteristic min typ max min typ max min typ max unit i ee negative power supply current 35 47 59 35 47 59 35 47 59 ma v oh output high voltage (note 21) ?1040 ?990 ?940 ?1010 ?960 ?910 ?985 ?935 ?885 mv v ol output low voltage (note 21) ?3.465 v v ee ?3.0 v (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols =float) (ols = v cc ? 1.2 v) **(ols = v ee ) ?3.0 v < v ee ?2.375 v (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols =float) (ols = v cc ? 1.2 v) (ols = v ee ) ?1980 ?1270 ?1750 ?1040 ?1515 ?1945 ?1265 ?1725 ?1045 ?1495 ?1830 ?1210 ?1630 ?990 ?1425 ?1795 ?1205 ?1605 ?995 ?1405 ?1680 ?1150 ?1510 ?940 ?1335 ?1645 ?1145 ?1485 ?945 ?1315 ?1940 ?1235 ?1715 ?1010 ?1480 ?1905 ?1230 ?1690 ?1010 ?1460 ?1790 ?1175 ?1595 ?960 ?1390 ?1755 ?1170 ?1570 ?960 ?1370 ?1640 ?1115 ?1475 ?910 ?1300 ?1605 ?1110 ?1450 ?910 ?1280 ?1910 ?1210 ?1685 ?985 ?1450 ?1875 ?1205 ?1660 ?990 ?1435 ?1760 ?1150 ?1565 ?935 ?1360 ?1725 ?1145 ?1540 ?940 ?1345 ?1610 ?1090 ?1445 ?885 ?1270 ?1575 ?1085 ?1420 ?890 ?1255 mv v outpp output voltage amplitude ?3.465 v v ee ?3.0 v (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols = float) (ols = v cc ? 1.2 v) **(ols = v ee ) ?3.0 v < v ee ?2.375 v (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols =float) (ols = v cc ? 1.2 v) (ols = v ee ) 750 130 550 0 345 715 125 525 0 325 840 220 640 0 435 805 215 615 5 415 740 125 545 0 340 705 120 520 0 320 830 215 635 0 430 795 210 610 0 410 735 125 540 0 335 700 120 515 0 320 825 215 630 0 425 790 210 605 5 410 mv v ih input high voltage (single?ended) (notes 23 and 25) clk, clk , d, d v ee + 1275 v cc ? 1000* v cc v ee + 1275 v cc ? 1000* v cc v ee + 1275 v cc ? 1000* v cc mv v il input low voltage (single?ended) (notes 24 and 25) clk, clk , d, d v ih ? 2600 v cc ? 1400* v ih ? 150 v ih ? 2600 v cc ? 1400* v ih ? 150 v ih ? 2600 v cc ? 1400* v ih ? 150 mv v ih input high voltage (single?ended) r, sel ?1210 v cc ?1145 v cc ?1085 v cc mv v il input low voltage (single?ended) r, sel v ee ?1610 v ee ?1545 v ee ?1485 mv v thr input threshold voltage (single?ended) (note 25) v ee + 1125 v cc ? 75 v ee + 1125 v cc ? 75 v ee + 1125 v cc ? 75 mv note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. input and output parameters vary 1:1 with v cc . 21. all outputs loaded with 50 to v cc ? 2.0 v. 22. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. 23. v ih cannot exceed v cc . |v ih ? v thr | < 2600 mv. 24. v il always v ee . |v il ? v thr | < 2600 mv. 25. v thr is the voltage applied to one input when running in single?ended mode. *typicals used for testing purposes. **when an output level of 400 mv is desired and v cc ? v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee . ***the device packaged in fcbga?16 have maximum ambient temperature specification of 70 c and devices packaged in qfn?16 have maximum ambient temperature specification of 85 c.
nbsg53a http://onsemi.com 8 table 9. dc characteristics, necl input with necl output v cc = 0 v; v ee = ?3.465 v to ?2.375 v (note 20) (continued) symbol unit 70 c(bga)/85 c(qfn)*** 25 c ?40 c characteristic symbol unit max typ min max typ min max typ min characteristic v ihcmr input high voltage common mode range (differential configuration) (note 22) v ee + 1.2 0.0 v ee + 1.2 0.0 v ee + 1.2 0.0 v r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@v ih ) r, sel clk, clk , d, d 35 5 100 50 35 5 100 50 35 5 100 50 a i il input low current (@v il ) r, sel clk, clk , d, d 20 5 100 50 20 5 100 50 20 5 100 50 a i ols ols input current (see figure 12) (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols = float) (ols = v cc ? 1.2 v) ?3.465 v v ee ?3.0 v *(ols = v ee ) ?3.0 v < v ee ?2.375 v (ols = v ee ) ?300 ?1500 ?1000 300 100 5 ?100 ?600 ?400 900 300 100 ?300 ?1500 ?1000 300 100 5 ?100 ?600 ?400 900 300 100 ?300 ?1500 ?1000 300 100 5 ?100 ?600 ?400 900 300 100 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 20. input and output parameters vary 1:1 with v cc . 21. all outputs loaded with 50 to v cc ? 2.0 v. 22. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. 23. v ih cannot exceed v cc . |v ih ? v thr | < 2600 mv. 24. v il always v ee . |v il ? v thr | < 2600 mv. 25. v thr is the voltage applied to one input when running in single?ended mode. *typicals used for testing purposes. **when an output level of 400 mv is desired and v cc ? v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee . ***the device packaged in fcbga?16 have maximum ambient temperature specification of 70 c and devices packaged in qfn?16 have maximum ambient temperature specification of 85 c.
nbsg53a http://onsemi.com 9 table 10. ac characteristics for fcbga?16 v cc = 0 v; v ee = ?3.465 v to ?2.375 v or v cc = 2.375 v to 3.465 v; v ee = 0 v ?40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency (see figures 4, 6, 8, 10, and 11) dff (see figures 5, 7, 9, 10, and 11) (note 26) div/2 8 10 8 10 8 10 ghz t plh , t phl propagation delay to output differential clk q, q (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols = float) **(ols = v ee ) 160 150 155 155 210 200 205 205 260 250 255 255 160 155 160 160 215 205 210 210 270 255 260 260 165 160 160 160 220 210 215 215 275 260 270 270 ps sel q, q (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols = float) **(ols = v ee ) 165 160 160 160 220 210 215 210 275 260 270 260 170 160 165 160 225 210 220 215 280 260 275 270 170 160 165 165 225 210 220 220 280 260 275 275 r q, q (ols = v cc ) div/2 (ols = v cc ) dff (ols = v cc ? 0.4 v) div/2 (ols = v cc ? 0.4 v) dff (ols = v cc ?0.8 v, ols = float) div/2 (ols = v cc ? 0.8 v, ols = float) dff **(ols = v ee ) div/2 **(ols = v ee ) dff 220 200 215 195 220 200 215 195 295 270 285 260 290 265 285 260 370 340 355 325 360 330 355 325 225 205 220 200 220 200 220 200 300 275 290 265 295 270 290 265 375 345 360 330 370 340 360 330 225 205 220 200 220 200 220 200 300 275 290 265 295 270 290 265 375 345 360 330 370 340 360 330 t skew duty cycle skew (notes 27 and 29) dff 5 20 5 20 5 20 ps t jitter rms random clock jitter f in 8 ghz (see figures 4 and 6) (note 26) peak?to?peak data dependent jitter f in = 8 gb/s 0.5 1.5 0.5 tbd 1.5 0.5 1.5 ps v inpp input voltage swing/sensitivity (differential configuration) (note 28) 75 2600 75 2600 75 2600 mv t r t f output rise/fall times (20% ? 80%) @ 1 ghz q, q (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols = float) **(ols = v ee ) 30 20 25 25 50 40 45 45 65 60 65 65 30 20 25 25 50 40 45 45 65 60 65 65 30 20 25 25 50 40 45 45 65 60 65 65 ps t s setup time d clk 30 14 30 10 30 13 ps t h hold time d clk 25 12 25 7 25 9 ps t rr reset recovery dff, div/2 40 9 40 12 40 10 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 26. measured using a 500 mv source, 50% duty cycle clock source. repetitive 1010 input data pattern. all outputs loaded with 50 to v cc ? 2.0 v. input edge rates is 40 ps (20% ? 80%). 27. see figure 14. t skew = |t plh ? t phl | for a nominal 50% differential clock input waveform. 28. v inpp (max) cannot exceed v cc ? v ee (applicable only when v cc ? v ee < 2600 mv). 29. see figure 10. duty cycle % vs. frequency. **when an output level of 400 mv is desired and v cc ? v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee .
nbsg53a http://onsemi.com 10 table 11. ac characteristics for qfn?16 v cc = 0 v; v ee = ?3.465 v to ?2.375 v or v cc = 2.375 v to 3.465 v; v ee = 0 v ?40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency (see figures 4, 6, 8, 10, and 11) dff (see figures 5, 7, 9, 10, and 11) (note 30) div/2 8 10 8 10 8 10 ghz t plh , t phl propagation delay to output differential (note 34) clk q, q sel q, q r q, q d in /2 dff 150 160 215 195 215 190 280 270 285 280 375 345 150 160 215 195 215 190 280 270 285 280 375 345 150 160 215 195 215 190 280 270 285 280 375 345 ps t skew duty cycle skew (notes 31 and 33) dff 5 20 5 20 5 20 ps t jitter rms random clock jitter f in 8 ghz (see figures 4 and 6) (note 30) peak?to?peak data dependent jitter f in = 8 gb/s 0.5 tbd 1 0.5 tbd 1 0.5 tbd 1 ps v inpp input voltage swing/sensitivity (differential configuration) (note 32) 75 2600 75 2600 75 2600 mv t r t f output rise/fall times (20% ? 80%) @ 1 ghz q, q (ols = v cc ) (ols = v cc ? 0.4 v) (ols = v cc ? 0.8 v, ols = float) **(ols = v ee ) 28 15 25 20 40 40 35 35 65 65 65 65 28 15 25 20 40 40 35 35 65 65 65 65 28 15 25 20 40 40 35 35 65 65 65 65 ps t s setup time d clk 30 14 30 10 30 13 ps t h hold time d clk 25 12 25 7 25 0 ps t rr reset recovery dff, div/2 40 9 40 12 40 10 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 30. measured using a 500 mv source, 50% duty cycle clock source. repetitive 1010 input data pattern. all outputs loaded with 50 to v cc ? 2.0 v. input edge rates is 40 ps (20% ? 80%). 31. see figure 14. t skew = |t plh ? t phl | for a nominal 50% differential clock input waveform. 32. v inpp (max) cannot exceed v cc ? v ee (applicable only when v cc ? v ee < 2600 mv). 33. see figure 10. duty cycle % vs. frequency. 34. for all ols configuration. **when an output level of 400 mv is desired and v cc ? v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee . ***the device packaged in fcbga?16 have maximum ambient temperature specification of 70 c and devices packaged in qfn?16 have maximum ambient temperature specification of 85 c.
nbsg53a http://onsemi.com 11 figure 4. output voltage amplitude (v outpp ) / rms jitter vs. input frequency (f in ) for dff mode (v cc ? v ee = 3.3 v @ 25 c; repetitive 1010 input data pattern) rms jitter input frequency (ghz) output voltage amplitude jitter out ps (rms) 0 100 200 300 400 500 600 700 800 900 123456789101112 0 1 2 3 4 5 6 7 8 9 ols = v cc 0 ols = v cc ? 0.4 v *ols = v ee ols = v cc ? 0.8 v, ols = float input frequency (ghz) output voltage amplitude 0 100 200 300 400 500 600 700 800 900 123456789101112 ols = v cc 0 ols = v cc ? 0.4 v *ols = v ee ols = v cc ? 0.8 v, ols = float figure 5. output voltage amplitude (v outpp ) / rms jitter vs. input frequency (f in ) for div/2 mode (v cc ? v ee = 3.3 v @ 25 c) *when an output level of 400 mv is desired and v cc ? v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee .
nbsg53a http://onsemi.com 12 figure 6. output voltage amplitude (v outpp ) / rms jitter vs. input frequency (f in ) for dff mode (v cc ? v ee = 2.5 v @ 25 c; repetitive 1010 input data pattern) rms jitter input frequency (ghz) output voltage amplitude jitter out ps (rms) 0 100 200 300 400 500 600 700 800 900 123456789101112 0 1 2 3 4 5 6 7 8 9 ols = v cc 0 ols = v cc ? 0.4 v *ols = v ee ols = v cc ? 0.8 v, ols = float input frequency (ghz) output voltage amplitude 0 100 200 300 400 500 600 700 800 900 123456789101112 ols = v cc 0 ols = v cc ? 0.4 v ols = v ee *ols = v cc ? 0.8 v, ols = float figure 7. output voltage amplitude (v outpp ) / rms jitter vs. input frequency (f in ) for div/2 mode (v cc ? v ee = 2.5 v @ 25 c) *when an output level of 400 mv is desired and v cc ? v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee .
nbsg53a http://onsemi.com 13 input frequency (ghz) v oh /v ol (mv) 0 100 200 300 400 500 600 700 800 900 123456789101112 0 v oh (q) v oh (q ) v ol (q ) v ol (q) 1000 1100 1200 input frequency (ghz) v oh /v ol (mv) 0 100 200 300 400 500 600 700 800 900 123456789101112 0 v oh (q) v oh (q ) v ol (q) v ol (q ) 1000 1100 1200 figure 8. v oh /v ol (q/q ) vs. input frequency (f in ) for dff mode (v cc ? v ee = 3.3 v @ 25 c and ols = v cc ? 0.8 v, ols = float) figure 9. v oh /v ol (q/q ) vs. input frequency (f in ) for div/2 mode (v cc ? v ee = 3.3 v @ 25 c and ols = v cc ? 0.8 v, ols = float)
nbsg53a http://onsemi.com 14 70 0 10 20 30 40 50 60 80 90 100 01 3456789101112 2 input frequency (ghz) duty cycle (%) dff mode div/2 mode 70 0 10 20 30 40 50 60 80 90 100 0 1 3456789101112 2 input frequency (ghz) duty cycle (%) dff mode div/2 mode figure 10. duty cycle % vs. input frequency (f in ) (v cc ? v ee = 3.3 v @ 25 c) figure 11. duty cycle % vs. input frequency (f in ) (v cc ? v ee = 2.5 v @ 70 c)
nbsg53a http://onsemi.com 15 i ols ( a) ?700 ?600 ?500 ?400 ?300 ?200 ?100 0 100 200 300 figure 12. typical ols input current vs. ols input voltage (v cc ? v ee = 3.3 v @ 25 c) v ols (mv) v outpp (mv) 0 200 400 600 800 1000 ols (mv) figure 13. ols operating area v ee v cc v cc ? 400 v cc ? 800 v cc ? 1200 v ee v cc v cc ? 400 v cc ? 800 v cc ? 1200 v cc ? 75 v cc ? 250 v cc ? 550 v cc ? 700 v cc ? 900 v cc ? 1125 v cc ? 1275 v ee + 100
nbsg53a http://onsemi.com 16 figure 14. ac reference measurement clk clk q q t phl t plh v inpp = v ih (clk) ? v il (clk) figure 15. typical termination for output driver and device evaluation (refer to application note and8020/d ? termination of ecl logic devices) v outpp = v oh (q) ? v ol (q) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v ordering information device package type shipping 2 nbsg53aba 4x4 mm fcbga?16 100 units / tray nbsg53abar2 4x4 mm fcbga?16 500 / tape & reel nbsg53amn 3x3 mm qfn?16 123 units / rail nbsg53amnr2 3x3 mm qfn?16 3000 / tape & reel 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifi- cations brochure, brd8011/d.
nbsg53a http://onsemi.com 17 package dimensions fcbga?16 ba suffix plastic 4 x 4 (mm) bga flip chip package case 489?01 issue o 0.20 laser mark for pin 1 identification in this area d e m a1 a2 a 0.10 z 0.15 z rotated 90 clockwise detail k 5 view m?m e 3 x s m x 0.15 y z 0.08 z 3 b 16 x feducial for pin a1 identification in this area 4321 a b c d 4 16 x notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. dim min max millimeters a 1.40 max a1 0.25 0.35 a2 1.20 ref b 0.30 0.50 d 4.00 bsc e 4.00 bsc e 1.00 bsc s 0.50 bsc k ?x? ?y? m m ?z?
nbsg53a http://onsemi.com 18 package dimensions qfn?16 mn suffix case 485g?01 issue o x m 0.10 (0.004) t ?t? ?x? note 3 seating plane l a m ?y? b n 0.25 (0.010) t 0.25 (0.010) t j c k r 0.08 (0.003) t g e h f p d y 1 4 58 12 9 16 13 dim min max min max inches millimeters a 3.00 bsc 0.118 bsc b 3.00 bsc 0.118 bsc c 0.80 1.00 0.031 0.039 d 0.23 0.28 0.009 0.011 g 0.50 bsc 0.020 bsc h 0.875 0.925 0.034 0.036 j 0.20 ref 0.008 ref k 0.00 0.05 0.000 0.002 l 0.35 0.45 0.014 0.018 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters. 3. dimension d applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. e 1.75 1.85 0.069 0.073 f 1.75 1.85 0.069 0.073 m 1.50 bsc 0.059 bsc n 1.50 bsc 0.059 bsc p 0.875 0.925 0.034 0.036 r 0.60 0.80 0.024 0.031 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nbsg53a/d gigacomm is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 800?282?9855 toll free usa/canada

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