hi-1565, hi-1566 mil-std-1553 / 1760 5v monolithic dual transceivers description features pin configurations the hi-1565 and hi-1566 are low power cmos dual transceivers designed to meet the requirements of the mil-std-1553 /1760 specifications. the transmitter section of each bus takes complementary cmos / ttl data and converts it to differential voltages suitable for driving the bus isolation transformer. separate transmitter inhibit control signals are provided for each transmitter. the receiver section of each bus converts the 1553 bus bi- phase differential data to complementary cmos / ttl data suitable for inputting to a manchester decoder. each receiver has a separate enable input which can be used to force the output of the receiver to a logic 0 (hi-1565) or logic 1 (hi-1566). manchester ii bi-phase to minimize the package size for this function, the transmitter outputs are internally connected to the receiver inputs, so that only two pins are required for connection to each coupling transformer. compliant to mil-std-1553a & b, mil-std-1760, arinc 708a cmos technology for low standby power smallest footprint available in 44-pin plastic chip-scale package with integral heatsink less than 1.0w maximum power dissipation bus pins esd protected to greater than 8kv also available in dip and small outline (esoic) package options industrial and extended temperature ranges industry standard pin configurations 20 pin ceramic dip package 20 pin plastic esoic - wb package july 2009 (ds1565 rev. f) 07/09 1 busa 2 3 rxena 4 gnda 5 vddb 6 busb 7 8 rxenb 9 gndb 10 vdda busa busb 20 19 txa 18 txinha 17 rxa 16 15 14 txb 13 txinhb 12 rxb 11 txa rxa txb rxb 1565psi 1565pst 1565psm 1566psi 1566pst 1566psm vdda 1 busa 2 3 rxena 4 gnda 5 vddb 6 busb 7 8 rxenb 9 gndb 10 busa busb 20 19 txa 18 txinha 17 rxa 16 15 14 txb 13 txinhb 12 rxb 11 txa rxa txb rxb 1565cdi 1565cdt 1565cdm 1566cdi 1566cdt 1566cdm 44 pin plastic 7mm x 7mm chip-scale package 44 n/c 43 42 41 busa 40 busa 39 vdda 38 vdda 37 36 txa 35 n/c 34 n/c busa busa txa n/c 1 rxena 2 gnda 3 gnda 4 gnda 5 vddb 6 vddb 7 busb 8 busb 9 10 11 busb busb n/c 12 n/c 13 n/c 14 n/c 15 rxenb 16 gndb 17 gndb 18 gndb 19 20 rxb 21 n/c 22 rxb 33 n/c 32 n/c 31 txinha 30 rxa 29 28 n/c 27 n/c 26 25 txb 24 txinhb 23 n/c rxa txb 1565pci 1565pct 1566pci 1566pct holt integrated circuits www.holtic.com
pin descriptions functional description the hi-1565 family of data bus transceivers contain differ- ential voltage source drivers and differential receivers. they are intended for applications using a mil-std-1553 a/b data bus. the device produces a trapezoidal output waveform during transmission. data input to the device?s transmitter section is from the complementary cmos /ttl inputs txa/b and / . the transmitter accepts manchester ii bi-phase data and converts it to differential voltages on . the transceiver outputs are either direct or transformer coupled to the mil-std-1553 data bus. both coupling methods produce a nominal voltage on the bus of 7.5 volts peak to peak. transmitter txa b busa/b and / the transmitter is automatically inhibited and placed in the high impedance state when both txa/b and / are ei- ther at a logic ?1? or logic ?0? simultaneously. a logic ?1? ap- plied to the txinha/b input will force the transmitter to the high impedance state, regardless of the state of txa/b and / busa b txa b txa b. receiver the receiver accepts bi-phase differential data from the mil-std-1553 bus through the same direct or transformer coupled interface as the transmitter. the receiver?s differ- ential input stage drives a filter and threshold comparator that produces cmos/ttl data at the rxa/b and / output pins. rxa b each set of receiver outputs can be independently forced to a logic "0" (hi-1565) or logic ?1? (hi-1566) by setting rxena or rxenb low. a direct coupled interface (see figure 2) uses a 1:2.5 ratio isolation transformer and two 55 ohm isolation resistors between the transformer and the bus. in a transformer coupled interface (see figure 3), the transceiver is connected to a 1:1.79 isolation transformer which in turn is connected to a 1:1.4 coupling transformer. the transformer coupled method also requires two coupling resistors equal to 75% of the bus characteristic impedence (zo) between the coupling transformer and the bus. mil-std-1553 bus interface pin symbol function description (dip/esoic) 1 vdda power supply +5 volt power for bus a 2 busa analog output mil-std-1533 bus driver a, positive signal 3 analog output mil-std-1553 bus driver a, negative signal 4 rxena digital input receiver a enable. if low, forces rxa and low (hi-1565) or high (hi-1566) 5 gnda power supply ground for bus a 6 vddb 7 busb 9 rxenb 10 gndb 11 12 rxb digital output receiver b output, non-inverted 13 txinhb digital input transmit inhibit, bus b. if high busb, disabled 14 txb digital input transmitter b digital data input, non-inverted 15 digital input transmitter b digital data input, inverted 16 digital output busa rxa busb txb rxa power supply +5 volt power for bus b analog output mil-std-1533 bus driver b, positive signal 8 analog output mil-std-1553 bus driver b, negative signal digital input receiver b enable. if low, forces rxb and low (hi-1565) or high (hi-1566) power supply ground for bus b digital output receiver b output, inverted receiver a output, inverted 17 rxa digital output receiver a output, non-inverted 18 txinha digital input transmit inhibit, bus a. if high busa, disabled 19 txa digital input transmitter a digital data input, non-inverted 20 digital input transmitter a digital data input, inverted busb rxb rxb busa txa hi-1565, hi-1566 holt integrated circuits 2
receive waveforms - example pattern rxa/b rxa/b vin (line to line) t dr t dr t rg t dr t rg t dr transmit waveform - example pattern txa/b txa/b busa/b - busa/b hi-1565, hi-1566 figure 1. block diagram txa/b txa/b txinha/b rxa/b rxa/b rxena/b each bus transmit logic receive logic slope control comparator input filter busa/b busa/b transmitter receiver data bus isolation transformer coupler network direct or transformer holt integrated circuits 3
note: stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. these are stress ratings only. operation at the limits is not recommended. absolute maximum ratings recommended operating conditions dc electrical characteristics vdd = 5.0v, gnd = 0v, t = operating temperature range (unless otherwise specified). a parameter symbol condition min typ max units operating voltage vdd 4.75 5 5.25 v total supply current icc1 not transmitting 14 22 ma icc2 transmit one bus @ 340 ma 50% duty cycle icc3 transmit one bus @ 550 ma 100% duty cycle power dissipation pd1 not transmitting 0.11 w pd2 transmit one bus @ 0.70 0.95 w 100% duty cycle min. input voltage (hi) v digital inputs 2.0 1.4 v max. input voltage (lo) v digital inputs 1.4 0.8 v min. input current (hi) i v = 4.9v, digital inputs 20 a max. input current (lo) i v = 0.1v, digital inputs -20 a min. output voltage (hi) v i = -0.4ma, digital outputs 2.7 v max. output voltage (lo) v i = 4.0ma, digital outputs 0.4 v input resistance r differential 20 kohm input capacitance c differential 5 pf common mode rejection ratio cmrr 40 db input level v differential 9 vp-p input common mode voltage v -5.0 5.0 v-pk threshold voltage - direct-coupled detect 1.15 20.0 no detect 0.28 threshold voltage - detect 0.86 14.0 no detect 0.20 200 400 v 1 mhz sine wave vp-p v (measured at point ?a ? in figure 2) vp-p transformer-coupled v 1 mhz sine wave vp-p v (measured at point ?a ? in figure 3) vp-p ih il ih ih il il oh out ih out d receiver (measured at point ?a ? in figure 2 unless otherwise specified) in in in icm thd thnd thd thnd d t supply voltage temperature range industrial screening.........-40c to +85c hi-temp screening........-55c to +125c vdd....................................... 5v... 5% supply voltage ( logic input voltage range power dissipation at 25c 1.0 w ceramic dil, derate 7mw/c solder temperature 275c for 10 sec. junction temperature 175c storage temperature -65c to +150c vdd) -0.3 v to +7 v -0.3 v dc to +5.5 v receiver differential voltage 10 vp-p driver peak output current +1.0 a hi-1565, hi-1566 holt integrated circuits 4
dc electrical characteristics (cont.) vdd = 5.0v, gnd = 0v, t = operating temperature range (unless otherwise specified). a ac electrical characteristics vdd = 5.0v, gnd = 0v, t =operating temperature range (unless otherwise specified). a hi-1565, hi-1566 txa/b txa/b txinha/b transmitter receiver 1:2.5 point ?a ? d 55 55 35 2.5:1 55 55 35 rxena/b busa/b busa/b rxa/b rxa/b figure 2. direct coupled test circuits isolation transformer isolation transformer point ?a ? d parameter symbol test conditions min typ max units receiver enable delay tren from rxena/b rising or falling edge to 40 ns rxa/b or driver delay tdt txa/b, txa/b to busa/b, busa/b 150 ns rise time tr 35 ohm load 100 300 ns fall time tf 35 ohm load 100 300 ns inhibit delay tdi-h inhibited output 100 ns tdi-l active output 150 ns receiver transmitter (measured at point ?a ? in figure 2) (measured at point ?a ? in figure 2) d d receiver delay tdr from input zero crossing to rxa/b or 450 ns receiver gap time trg spacing between rxa/b and rxa/b pulses 90 365 ns rxa/b rxa/b parameter symbol condition min typ max units output voltage direct coupled 35 ohm load 7.0 9.0 vp-p (measured at point ?a ? in figure 2) 70 20.0 27.0 vp-p output noise v differential, inhibited 10.0 mvp-p output dynamic offset voltage v -90 90 mv -250 250 mv output resistance r differential, not transmitting 10 kohm output capacitance c 1 mhz sine wave 15 pf transmitter (measured at point ?a ? in figure 2 unless otherwise specified) d d v transformer coupled v ohm load (measured at point ?a ? in figure 3) direct coupled 35 ohm load (measured at point ?a ? in figure 2) transformer coupled v 70 ohm load (measured at point ?a ? in figure 3) out out dyn t d t on dyn out out holt integrated circuits 5
t a =25c t a =85c t a =125c hi-1565cdi / t / m hi-1566cdi / t / m hi-1565pci / t hi-1566pci / t data taken at vdd=5.0v, continuous transmission at 1mbit/s, single transmitter enabled. 62c 122c package style condition ? ja 54c/w junction temperature 162c hi-1565psi / t / m hi-1566psi / t / m heat sink unsoldered heat sink soldered 157c 117c 57c part number 129c 169c 47c/w 44-pin plastic chip- scale package heat sink unsoldered 49c/w 59c 119c 159c 20-pin thermally enhanced plastic soic (esoic) 20-pin ceramic side-brazed dip socketed 62c/w 69c hi-1565, hi-1566 thermal characteristics txa/b txa/b txinha/b transmitter busa/b busa/b 52.5 (.75 zo) 52.5 (.75 zo) 1.79:1 1:1.79 1:1.4 1.4:1 35 (.5 zo) figure 3. transformer coupled test circuits coupling transformer coupling transformer isolation transformer isolation transformer receiver 52.5 (.75 zo) 52.5 (.75 zo) 35 (.5 zo) rxa/b rxa/b rxena/b point ?a ? t point ?a ? t both the hi-1565psi/t/m and hi-1566psi/t/m use a 20-pin thermally enhanced soic package. the hi-1565pci/t and hi-1566pci/t use a plastic chip-scale package. these packages include a metal heat sink located on the bottom surface of the device. this heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. the heat sink is electrically isolated and may be soldered to any convenient power or ground plane.. heat sink - esoic & chip-scale package holt integrated circuits 6 applications note holt applications note an-500 provides circuit design notes regarding the use of holt's family of mil-std-1553 transceivers. layout considerations, as well as recommended interface and protection components are included.
ordering information hi - (plastic) 156x xx x x transformers. holt recommends the premier magnetics parts as offering the best combination of electrical performance, low cost and small footprint. hi - (ceramic) 156xcd x recommended transformers the hi-1565 and hi-1566 transceivers have been characterized for compliance with the electrical require- ments of mil-std-1553 when used with the following manufacturer part number application turns ratio(s) dimensions premier magnetics pm-db2725ex isolation dual tapped 1:1.79, 1:2.5 .500 x .500 x .375 inches technotrol tl1553-45 isolation dual tapped 1:1.79, 1:2.5 .630 x 630 x .155 inches premier magnetics pm-db2702 stub coupling 1:1.4 .625 x .625 x .250 inches technotrol tq1553-2 stub coupling 1:1.4 .625 x .625 x .250 inches 20 pin ceramic side brazed dip (20c) rxenb = 0 part number 1566cd 1565cd rxa rxa rxb 0 1 0 1 0 1 0 1 rxb 20 pin ceramic side brazed dip (20c) package description rxena = 0 temperature range flow burn in -40c to +85c no i -55c to +125c no t part number t i -55c to +125c yes m m tin / lead (sn / pb) solder lead finish gold (pb-free, rohs compliant) gold (pb-free, rohs compliant) rxenb = 0 part number 1566 1565 rxa rxa rxb 0 1 0 1 0 1 0 1 rxb rxena = 0 package description 20 pin plastic esoic, thermally enhanced wide soic w/heat sink (20hwe) 44 pin plastic chip-scale lpcc (44pcs) not available with ?m? flow part number ps pc temperature range flow burn in -40c to +85c no i -55c to +125c no t part number t i -55c to +125c yes m m lead finish part number 100% matte tin (pb-free, rohs compliant) f blank tin / lead (sn / pb) solder hi-1565, hi-1566 holt integrated circuits 7
hi-1565, hi-1566 revision history document rev. date description of change ds1565 e 09/26/08 clarification of transmitter and receiver functions in description, clarified available temperature ranges, and corrected a dimension in recommended transformers table. f 07/24/09 corrected typographical errors in package dimensions. holt integrated circuits 8
package dimensions 20-pin plastic small outline (esoic) - wb (wide body, thermally enhanced) inches (millimeters) package type: 20hwe bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) electrically isolated heat sink pad on bottom of package. connect to any ground or power plane for optimum thermal dissipation. detail a .504 .008 (12.79 .19) .295 .002 (7.493 .05) 0 to 8 .090 .01 (2.29 .25) .205 (5.21) .290 (7.37) bottom view top view .407 .013 (10.325 .32) .033 .017 (.838 .432) .0075 .004 (.191 .089) .0165 .0035 (.419 .089) .050 (1.27) bsc see detail a typ typ .0105 .0015 (.267 .038) 20-pin ceramic side-brazed dip inches (millimeters) package type: 20c bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .017 .002 (.432 .051) .100 (2.54) .310 010 (7.874 .254) .125 (3.175) .050 typ. (1.270 typ.) .200 (5.080) 1.000 .010 (25.400 .254) .010 002/ .001 (.254 .051 .025) .300 010 (7.620 .254) .085 .009 (2.159 .229) bsc max min holt integrated circuits 9
package dimensions 44-pin plastic chip-scale package inches (millimeters) package type: 44pcs bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .203 .006 (5.15 .15) .016 .002 (0.40 .05) .010 (0.25) .020 (0.50) .008 (0.2) .039 (1.00) .276 (7.00) bsc .203 .006 (5.15 .15) typ typ bottom view top view bsc .276 (7.00) bsc max electrically isolated heat sink pad on bottom of package. connect to any ground or power plane for optimum thermal dissipation. holt integrated circuits 10
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