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AMD-768 peripheral bus controller revision guide publication # 2 4472 r ev: c issue date: march 2 00 2 tm preliminary information
preliminary information trademarks amd, the amd arrow logo, amd athlon, amd-762, and AMD-768 are trademarks of advanced micro devices, inc. microsoft is a registered trademark of microsoft corporation. netware is a trademark of novell, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ? 2002 advanced micro devices, inc. all rights reserved. the contents of this document are provided in connection with advanced micro devices, inc. (?amd?) products. amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in amd?s standard terms and conditions of sale, amd assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. the amd products described herein may contain design defects or errors (?product errata?) that causes the amd products to deviate from published specifications. currently characterized product errata may be available upon request. amd?s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of amd?s product could create a situation where personal injury, death, or severe property or environmental damage may occur. amd reserves the right to discontinue or make changes to its products at any time without notice.
3 24472c?march 2002 AMD-768? peripheral bus controller revision guide preliminary information revision history date rev description march 2002 c added b2 silicon information. february 2002 b initial public release.
4 AMD-768? peripheral bus controller revision guide 24472c?march 2002 preliminary information AMD-768? peripheral bus controller revision guide the purpose of the AMD-768? peripheral bus controller revision guide is to communicate updated product information on the AMD-768? peripheral bus controller to designers of computer systems and software developers. this guide consists of four major sections: product marking identification: this section, which starts on page 5, provides product types, product revisions, opns (ordering part numbers), and product marking information. product errata: this section, which starts on page 6, provides a detailed description of product errata, including potential effects on system operation and suggested workarounds. an erratum is defined as a deviation from the product?s specification. a product errata may cause the behavior of the AMD-768 peripheral bus controller to deviate from the published specifications. revision determination: this section starts on page 15. technical and documentation support: this section, which starts on page 16, provides a listing of available technical support resources. it also lists corrections, modifications, and clarifications to listed documents. revision guide policy occasionally, amd identifies deviations from or changes to the specification of the AMD-768 peripheral bus controller. these changes are documented in the AMD-768? peripheral bus controller revision guide as errata. descriptions are written to assist system and software designers in using the AMD-768 peripheral bus controller and corrections to amd?s documentation on the AMD-768 peripheral bus controller are included. this revision guide documents currently characterized product errata.
5 24472c?march 2002 AMD-768? peripheral bus controller revision guide preliminary information 1 product marking identification amd-751 tm amd-751ac b date code amd 1999 c AMD-768? AMD-768ac product revision family/core AMD-768 package type a = plastic ball grid arra y c = commercial temperature range case temperature a date code 2001 table 1. valid ordering part number combinations opn package type operating voltage case temperature (max.) AMD-768ac 492-pin pbga logic core: 2.375-2.625v i/o core: 3.135-3.465v 85 c note: valid combinations are configurations that are or will be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations.
6 AMD-768? peripheral bus controller revision guide 24472c?march 2002 preliminary information 2 product errata this section documents AMD-768 peripheral bus controller product errata. the errata are divided into categories to assist referencing particular errata. a unique tracking number for each erratum has been assigned within this document for user convenience in tracking the errata within specific revision levels. table 2 cross-references the revisions of the AMD-768 peripheral bus controller to each erratum. an ?x? indicates that the erratum applies to the stepping. the absence of an ?x? indicates that the erratum does not apply to the stepping. note: there can be missing errata numbers. errata that have been resolved from early revisions of the controller have been deleted, and errata that have been reconsidered may have been deleted or renumbered. table 2. cross-reference of product revision to errata erratum number and description revision number b1 b2 10 multiprocessor system may hang while in full apic mode and ioapic interrupt is masked xx 21 pci discard card timer expiration causes data corruption on pci primary bus xx 22 writes to real time clock must be byte width xx 23 ac ?97 modem controller may transmit incorrect data to ac-link xx 24 single processor systems will not resume from c2, c3, or pos low power states xx 25 pci bridge does not handle device initiated target abort cycles correctly xx 26 usb controller may cause secondary pci bus contention x
7 24472c ? march 2002 AMD-768 ? peripheral bus controller revision guide preliminary information 10 multiprocessor system may hang while in full apic mode and ioapic interrupt is masked products affected. b1, b2 normal specified operation. the AMD-768 peripheral bus controller is designed to support full apic mode in multiprocessor systems for system management events. if an interrupt is masked in the apic controller of the AMD-768, then the corresponding interrupt message should not be sent to the processor via the 3-wire apic bus. non-conformance. the AMD-768 peripheral bus controller will send an interrupt message via the 3-wire apic bus regardless if the interrupt is masked or not. potential effect on system. since the processor had previously masked the apic interrupt, it is not expecting to receive future apic messages for the masked interrupt. the apic controller will continuously send the interrupt message via the 3-wire bus until a processor accepts the message, causing the system to hang. a system hang has been observed when executing a server shutdown command in novell netware versions 5.0 or 5.1 while using a serial mouse. during the server shutdown sequence, software writes an invalid cpu id to the ioapic redirection table, and the system does not complete the shutdown. note : no failure has been observed when using a ps/2 mouse. suggested workaround. none. resolution status: no fix planned.
8 AMD-768 ? peripheral bus controller revision guide 24472c ? march 2002 preliminary information 21 pci discard card timer expiration causes data corruption on pci primary bus products affected: b1, b2 normal specified operation: the AMD-768 pci bridge controller supports discarding pci bus master cycles initiated on the primary pci bus. non-conformance: if a primary pci bus master does not retry a prefetchable cycle before the AMD-768 pci bridge, the retry timer expires. the AMD-768 pci bridge controller will supply corrupt data. the primary pci bus master and the pci bridge controller devices interact using the following sequence when transferring data. 1. a primary pci bus master initiates a memory read cycle to memory space on the pci secondary bus. 2. the pci bridge controller responds with a pci retry cycle and continues to obtain the read data. 3. the primary pci bus master initiates a second memory read cycle at a different address than the first request. 4. the pci bridge controller responds with a pci retry cycle, since it is has the data for the first memory read cycle. 5. the primary pci bus master continues to retry the second memory read cycle. 6. once the pci bridge retry timer expires, the pci bridge accepts the second memory read cycle from the primary pci bus master, but the pci bridge did not completely flush its internal prefetch buffer from the first memory read cycle. the data supplied is corrupt. 7. the primary pci bus master retries the first memory read cycle and the pci bridge completes the cycle, but the data supplied is corrupt. 8. all subsequent primary pci bus master reads are now completed with corrupt data. the system may hang. potential effect on system: no impact on system functionality will occur when using the amd-762 ? system controller northbridge. the amd-762 northbridge will not issue prefetchable reads downstream, nor will it retry a memory cycle to the AMD-768 southbridge after the pci retry timer has expired. add-in cards on the primary pci bus perform prefetchable memory accesses only upstream to memory controlled through the northbridge, not downstream through the southbridge to memory residing on the secondary pci bus. suggested workaround: none. resolution status: no fix planned.
9 24472c ? march 2002 AMD-768 ? peripheral bus controller revision guide preliminary information 22 writes to real time clock must be byte width products affected: b1, b2 normal specified operation: the AMD-768 real time clock function is designed to support byte- and word- width write operation to control registers and cmos memory locations. non-conformance: the AMD-768 real time clock function does not support word width write operations to control registers and cmos memory locations. if a word width operation is performed to port 70, then only the least significant byte is written. potential effect on system: none. suggested workaround: use two byte-aligned cycles to perform write operations to rtc control registers and cmos memory locations. the required sequence is: step 1: software writes to port 70 the address index value as a single byte. step 2: software writes to port 71 the data value as a single byte. similarly, use two byte-aligned cycles when port 72 is used for address index value and port 73 is used for data value. resolution status: no fix planned.
10 AMD-768 ? peripheral bus controller revision guide 24472c ? march 2002 preliminary information 23 ac ? 97 modem controller may transmit incorrect data to ac-link products affected: b1, b2 normal specified operation: the AMD-768 ac ? 97 modem controller is designed to transfer either an even number or odd number of digital tone samples to the ac-link. non-conformance: if the ac ? 97 modem controller transfers an odd number of samples and a register reset command is issued to the modem controller, the output data transmitted to the ac-link by the ac ? 97 controller may become corrupt. potential effect on system: data transferred from the pci bus to the ac-link may become corrupt. the modem riser card codec transmits the corrupted data across the telephone line. suggested workaround: none. the ac ? 97 modem is not supported in the AMD-768 peripheral bus controller. note: this errata has no impact on the ac ? 97 audio function. resolution status: no fix planned.
11 24472c ? march 2002 AMD-768 ? peripheral bus controller revision guide preliminary information 24 single processor systems will not resume from c2, c3, or pos low power states products affected: b1, b2 normal specified operation: the AMD-768 power management controller is designed to support timer and ps/2 mouse and keyboard wakeups from the snoop cache capable clock control (c2) state, the non-snoop cache capable (c3) state, and the power on suspend (acpi pos) states. non-conformance: bios places the AMD-768 into virtual wire mode since it does not know if a single or multi-processor system is to be run. in this mode, the io apic and the legacy priority interrupt controller (pic) are enabled. both interrupt controllers support interrupts as wake events. in a single processor operating system, the io apic interrupts are masked when the system is placed into a low power state. the masking of the io apic interrupts inhibits a legacy irq from creating a resume event in power management state machine. the following legacy interrupts will not resume the system. irq0 - programmable interval timer (c2 and c3 state resume) irq1 - ps/2 keyboard interrupt (pos state resume) irq12 - ps/2 mouse interrupt. (pos state resume) the global status register located at offset pm28[irqrsm_sts] bit is not set after a legacy irq event occurs which causes the power management logic to not resume the system. potential effect on system: system will not resume from c2/c3 low power state. system will not resume from pos low power state by ps/2 keyboard or mouse. suggested workaround: a software and hardware workaround exists for resuming from pos state but no work around is possible for c2/c3 state. for pos state software work around: before the acpi complaint operating system places the system into a pos state, bios can disable the advanced priority interrupt controller (apic) in the following sequence: bios clears [apicen] bit (device b function 0 offset 4b'h) just before placing the AMD-768 into pos state the ps/2 keyboard and mouse irqs will now resume the system from pos state once the system has resumed bios can re-enable the apic by setting [apicen] bit hardware work around: motherboard connects super i/o pme output pin to AMD-768 acav input pin. bios enables acav_en bit (general purpose 0 acpi interrupt enable register) at offset pm22. bios enables pme output pin in super i/o. for software support, reference amd application note: power management resume support for the AMD-768 ? peripheral bus controller, order #25818. usb mouse and keyboard will awake system from power on suspend state.
12 AMD-768 ? peripheral bus controller revision guide 24472c ? march 2002 preliminary information for c2/c3 state this workaround will not work for awaking from the c2/c3 state, since the operating system has full control. the (acpi c2/c3) state support is not required for microsoft ? -compatible workstation and server platforms. it is recommended that bios should disable the c2 state by clearing bit c2en (device b function 3 offset 4f'h). it is recommended that bios should disable the c3 state by clearing bit c3en (device b function 3 offset 4f'h). resolution status: no fix planned.
13 24472c ? march 2002 AMD-768 ? peripheral bus controller revision guide preliminary information 25 pci bridge does not handle device initiated target abort cycles correctly products affected: b1, b2 normal specified operation: the pci-to-pci bridge architecture specification revision 1.1 states: if a target-abort occurs on the primary interface when the bridge is acting as a bus master while forwarding a non-posted write transaction upstream, the bridge must: complete the corresponding data phase on the secondary interface by signaling a target-abort set the received target-abort bit in the primary status register if a target-abort occurs on the secondary interface when the bridge is acting as a bus master while forwarding a non-posted write transaction downstream, the bridge must: complete the corresponding data phase on the primary interface by signaling a target-abort set the received target-abort bit in the secondary status register non-conformance: if a target-abort occurs on the primary interface when the bridge is acting as a bus master while forwarding a non-posted write transaction upstream, the AMD-768 pci-to-pci bridge: transfers the first double word of the request followed by three extra data phases containing double words of ffff_ffff'h to the secondary interface does not signal a target-abort cycle on the secondary interface does not set (device a function 0 offset 04) bit rta received target abort if a target-abort occurs on the secondary interface when the bridge is acting as a bus master while forwarding a non-posted write transaction downstream, the AMD-768 pci-to-pci bridge: does signal a target-abort cycle on the primary interface, but no data is transferred to the primary interface does not set (device a function 0 offset 1c) bit rta received target abort potential effect on system: the system may hang if pci adapter cards perform pci target abort cycles whose destination is through the AMD-768 pci-to-pci bridge device. suggested workaround: if a pci adapter card executes a target abort cycle, then a catastrophic error has occurred. either the pci adapter card has a logical defect or software is attempting to access a location that the pci adapter card has no knowledge of. the pci adapter card should be removed from the system. resolution status: no fix planned.
14 AMD-768 ? peripheral bus controller revision guide 24472c ? march 2002 preliminary information 26 usb controller may cause secondary pci bus contention products affected: b1 normal specified operation: the AMD-768 secondary pci bus arbiter is designed to arbitrate pci bus ownership between bus masters on pci adapter cards and the internal usb host controller. non-conformance: secondary pci bus contention will occur if a pci adapter card and the internal usb controller interact in the following manner: the AMD-768 internal usb controller is enabled a pci adapter bus master card relinquishes the pci bus by deasserting its req# on the last clock of a transfer. the states of the following pci signals are ? frame# is de-asserted ? either stop# or trdy# are asserted ? irdy# is asserted ? gnt# is asserted on the next pci clock cycle the pci adapter card initiates another bus mastering cycle by asserting frame# on the same cycle as frame# is asserted, the AMD-768 deasserts gnt# usb activity is pending within the AMD-768 under these conditions the internal usb controller drives a pci transaction onto the secondary pci bus, resulting in pci bus contention. potential effect on system: data corruption leading to eventual system hangs and failures. long term component reliability problems due to bus contention. suggested workaround: disable the internal usb controller. bios can disable the internal usb controller by clearing bit 0 located at device b function 0 offset 48 (secondary pci bus device enable register). typical bios implementations provide a user setup option in the bios setup screen. an external pci-usb adaptor can be used if required. resolution status: fix planned for future silicon revision.
15 24472c ? march 2002 AMD-768 ? peripheral bus controller revision guide preliminary information 3 revision determination the bios checks the pci revision id register for function 0h at offset 8h to determine the version of silicon as shown in table 3. table 3. AMD-768? peripheral bus controller revision ids sequence revision device a function 0h offset 8h 4b104h 5b205h
16 AMD-768 ? peripheral bus controller revision guide 24472c ? march 2002 preliminary information 4 technical and documentation support 4.1 documentation support the following documents provide additional information regarding the operation of the AMD-768 peripheral bus controller: amd-762 ? system controller data sheet , order# 24088. AMD-768 ? peripheral bus controller data sheet , order# 24467. amd athlon ? system bus specification , order# 21902 amd athlon ? processor bios, software, and debug tools developers guide , order# 21656 amd athlon ? mp processor model 6 data sheet , order# 24685 power management resume support for AMD-768 ? peripheral bus controller application note , order# 25818 for the latest updates, refer to www.amd.com and download the appropriate files. for documents under nda, please contact your local sales representative for updates.

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