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datasheet 1.5v low-power wide-rang e frequency clock driver ics98uae877a 1.5v low-power wide-range frequency clock driver 1 ics98uae877a 7181/2 description the pll clock buffer, ics98uae877a, is designed for a v ddq of 1.5v, an av dd of 1.5v and differential data input and output levels. ics98uae877a is a zero delay buffer that distributes a differential clock input pair (clk_int, clk_inc) to ten differential pair of clock outputs (clkt[0:9], clkc[0:9]) and one differential pair feedback clock outputs (fb_outt, fboutc). the clock outputs are controlled by the input clocks (clk_int, clk_inc), the feedback clocks (fb_int, fb_inc), the lvcmos program pins (oe, os) and the analog power input (avdd). when oe is low, the outputs (except fb_outt/fb_outc) are disabled while the internal pll continues to main tain its locked-in frequency. os (output select) is a program pin that must be tied to gnd or v ddq . when os is high, oe will function as described above. when os is low, oe has no effect on clkt7/clkc7 (they are free running in addition to fb_outt/fb_outc). when av dd is grounded, the pll is turned off and bypassed for test purposes. when both clock signals (clk_int, clk_inc) are logic low, the device will enter a low power mode. an input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the pll are off. when the inputs transition from both being logic low to being differential signals, the pll will be turned back on, the inputs and outputs will be enabled and the pll will obtain phase lock between the feedback clock pair (fb_int, fb_inc) and the input clock pair (clk_int, clk_inc) within the specifie d stabilization time tstab. the pll in ics98uae877a clock driver uses the input clocks (clk_int, clk_inc) and the feedback clocks (fb_int, fb_inc) to provide high-performance, low-skew, low-jitter output differential clocks (clkt[0:9], clkc[0:9]). ics98uae877a is also able to track spread spectrum clocking (ssc) for reduced emi. ics98uae877a is available in commercial temperature range (0c to 70c) and industrial temperature range (-40c to +85c). see ordering information for details features ? low skew, low jitter pll clock driver ? 1 to 10 differential clock distribution ? feedback pins for input to output synchronization ? spread spectrum tolerant inputs ? auto pd when input signal is at a certain logic state ? available in 52-ball vfbga and a 40-pin mlf applications ? ddr2 memory modules / zero delay board fan out ? provides complete d dr dimm solution with idt74sstuae32xxx family switching characteristics ? period jitter: 40ps (ddr2-400/533) 30ps (ddr2-667) ? half-period jitter: 60 ps (ddr2-400/533) 50ps (ddr2-667) ? output-output skew 40ps (ddr2-400/533) 30ps (ddr2-667) ? cycle-cycle jitter 40ps
ics98uae877a 1.5v low-power wide-range frequency clock driver co mmercial temperature grade 1.5v low-power wide-range frequency clock driver 2 ics98uae877a 7181/2 block diagram fboutt fboutc fbin_int fbin_inc pll clk_int clk_inc power down and test mode logic ld av dd oe os ld or oe ld, os, or oe pll bypass 10k -100k clkt0 clkc0 clkt1 clkc1 clkt2 clkc2 clkt3 clkc3 clkt4 clkc4 clkt5 clkc5 clkt6 clkc6 clkt7 clkc7 clkt8 clkc8 clkt9 clkc9 (1) note: 1. the logic detect (ld) powers down the device when a logic low is applied to both clk_int and clk_inc.
ics98uae877a 1.5v low-power wide-range frequency clock driver co mmercial temperature grade 1.5v low-power wide-range frequency clock driver 3 ics98uae877a 7181/2 pin configurations 176 ball bga top view 40-pin mlf top view b c d e f g h j k a 123456 12345 6 a clkt1 clkt0 clkc0 clkc5 clkt5 clkt6 b clkc1 gnd gnd gnd gnd clkc6 c clkc2 gnd nb nb gnd clkc7 d clkt2 vddq vddq vddq os clkt7 e clk_int vddq nb nb vddq fb_int f clk_inc vddq nb nb oe fb_inc g agnd vddq vddq vddq vddq fb_outc h avdd gnd nb nb gnd fb_outt j clkt3 gnd gnd gnd gnd clkt8 k clkc3 clkc4 clkt4 clkt9 clkc9 clkc8 v d d q 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 v d d q 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 v d d q v d d q v ddq fb_int fb_inc fboutc 30 29 28 27 26 25 24 23 22 21 fboutt oe os v ddq gnd v ddq agnd av dd clk_int clk_inc v ddq 2 3 4 5 6 7 8 1 9 10 v ddq clkc2 clkt2 clkc7 clkt7 c l k c 3 c l k t 3 c l k c 4 c l k t 4 c l k c 9 c l k t 9 c l k c 8 c l k t 8 c l k c 1 c l k t 1 c l k c 0 c l k t 0 c l k c 5 c l k t 5 c l k c 6 c l k t 6
ics98uae877a 1.5v low-power wide-range frequency clock driver co mmercial temperature grade 1.5v low-power wide-range frequency clock driver 4 ics98uae877a 7181/2 pin descriptions terminal name description electrical characteristics agnd analog ground ground av dd analog power 1.5v nominal clk_int clock input with a 10k-100k pulldown resistor differential input clk_inc complementary clock input with a 10k-100k pulldown resistor differential input fb_int feedback clock input differential input fb_inc complementary feedback clock input differential input fb_outt feedback clock output differential output fb_outc complementary feedback clock output differential output oe output enable (asynchronous) lvcmos input os output select (tied to gnd or v ddq ) lvcmos input gnd ground ground v ddq logic and output power 1.5v nominal clkt[0:9] clock output s differential outputs clkc[0:9] complementary clock outputs differential outputs nb no ball
ics98uae877a 1.5v low-power wide-range frequency clock driver co mmercial temperature grade 1.5v low-power wide-range frequency clock driver 5 ics98uae877a 7181/2 function table absolute maximum ratings stresses greater than those listed under absolute maximum ratings ma y cause permanen t damage to the device. this is a stress rating only and functional operati on of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended per iods may affect reliability. inputs outputs pll av dd oe os clk_ int clk_ inc clkt clkc fb_ outt fb_ outc gnd h x l h l h l h bypassed/off gnd h x h l h l h l bypassed/off gnd l h l h l(z) 1 l(z) 1 bypassed/off gnd l l h l l(z), clkt7 active 1 l(z), clkc7 active 1 h l bypassed/off 1.5v (nom) l h l h l(z) 1 l(z) 1 lh on 1.5v (nom) l l h l l(z), clkt7 active 1 l(z), clkc7 active 1 hl on 1.5v (nom) h x l h l h l h on 1.5v (nom) h x h l h l h l on 1.5v (nom) x x l l l(z) 1 l(z) 1 l(z) 1 l(z) 1 off 1.5v (nom) x x h h reserved 1 outputs are disabled to a low state meeting the i odl limit. item rating supply voltage, (av dd and v ddq ) -0.5v to 2.5v logic inputs gnd - 0.5v to v ddq + 0.5v ambient operating temperature -40 c to +85 c storage temperature -65 to +150 c
ics98uae877a 1.5v low-power wide-range frequency clock driver co mmercial temperature grade 1.5v low-power wide-range frequency clock driver 6 ics98uae877a 7181/2 dc electrical characterist ics over operating range following conditions apply unless otherwise specified: commercial: t a = 0c to +70c, industrial: t a = -40c to +85c; supply voltage av dd /v ddq = 1.5v 0.075v. symbol parameter test conditions min. typ. max. units v oh output high voltage i oh = -100 av ddq - 2 v i oh = -6ma 1.1 1.45 v ol output low voltage i ol = 100 a 0.25 0.1 v i ol = 6ma 0.6 v ik input clamp voltage i in = -18ma -1.2 v i ih input high current clk_int, clk_inc; v i = v dd or gnd 250 a i il input low current os, fb_int, fb_inc; v i = v dd or gnd 10 a i odl output disabled low current oe = l, v odl = 100mv 100 a i dd 1.5 operating supply current c l = 0pf @ 410mhz 300 ma i ddld c l = 0pf 500 a c in 1 1 guaranteed by design, not 100% tested in production. input capacitance v i = v ddq or gnd 2 3 pf c out 1 output capacitance v out = v ddq or gnd 2 3
ics98uae877a 1.5v low-power wide-range frequency clock driver co mmercial temperature grade 1.5v low-power wide-range frequency clock driver 7 ics98uae877a 7181/2 recommended operating conditions following conditions apply unless otherwise specified: commercial: t a = 0c to +70c, industrial: t a = -40c to +85c; supply voltage av dd /v ddq = 1.5v 0.075v. symbol parameter 1 1 unused inputs must be held high or low to prevent them from floating. conditions min. typ. max. units av dd , v ddq supply voltage 1.425 1.5 1.575 v v il low - level input voltage clk_int, clk_inc, fb_int, fb_inc 0.35 x v ddq v oe, os v ih high -level input voltage clk_int, clk_inc, fb_int, fb_inc 0.65 x v ddq v oe, os v in dc input signal voltage 2 2 dc input signal voltage specifies the allowable dc execution of differential input. -0.3 v ddq + 0.3 v v id differential input signal voltage 3 3 differential inputs signal voltag es specifies the differential volt age [vtr-vcp] required for switching, where vtr is the true input level and vcp is the complementary input level. dc - clk_int, clk_inc, fb_int, fb_inc 0.35 v ddq + 0.4 v ac - clk_int, clk_inc, fb_int, fb_inc 0.6 v ox output differential cross-voltage 4 4 differential cross-point voltage is expected to track variations of v ddq and is the voltage at which the differential signal must be crossing. v ddq /2 - 0.1 v ddq /2 +0.1 v v ix input differential cross-voltage 4 v ddq /2 - 0.15 v ddq /2 v ddq /2 + 0.15 i oh high-level output current -6 ma i ol low-level output current 6 t a operating free-air temperature -40 +85 c
ics98uae877a 1.5v low-power wide-range frequency clock driver co mmercial temperature grade 1.5v low-power wide-range frequency clock driver 8 ics98uae877a 7181/2 timing requirements over recommend ed operating free-air temperature range following conditions apply unless otherwise specified: commercial: t a = 0c to +70c, industrial: t a = -40c to +85c; supply voltage av dd /v ddq = 1.5v 0.075v. symbol parameter 1 1 the pll must be able to handle spread spectrum induced skew. conditions min. max. units freq op max clock frequency 2 2 operating clock frequency indicates a range over which the pll must be able to lock, but in which it is not required to meet the other timing parameters. (used for low speed system debug.) 1.5v 0.075v @ 25 c95410mhz freq app application frequency range 3 3 application clock frequency indicates a range over which the pll must meet all timing parameters. 1.5v 0.075v @ 25 c160410mhz d tin input clock duty cycle 40 60 % t stab clk stabilization 4 4 stabilization time is the time requ ired for the integrated pl l circuit to obtain phase lock of its feedback signal to its reference signal, within the value specificied by the static phase offset ( t ? ), after power-up. during normal operation, the stabilizat ion time is also the time required for the integrated pll circuit to ob- tain phase lock of its feedback signal to its reference signal when clk and clk go to a logic low state, enter the power-down mode and later return to active operation. clk and clk may be left floating after they have been driven low for one complete clock cycle. 9 s
ics98uae877a 1.5v low-power wide-range frequency clock driver co mmercial temperature grade 1.5v low-power wide-range frequency clock driver 9 ics98uae877a 7181/2 switching characteristics over recommended free air operating range following conditions apply unless otherwise specified: commercial: t a = 0c to +70c, industrial: t a = -40c to +85c; supply voltage av dd /v ddq = 1.5v 0.075v symbol parameter 1 1 guaranteed for application frequency range. conditions (mhz) min. typ. max. units t en output enable time oe to any output 160 - 410 4.73 8 ns t dis output disable time oe to any output 5.82 8 ns t jit ( per ) period jitter 160 - 270 -40 40 ps 271 - 410 -30 30 t jit ( hper ) half-period jitter 160 - 270 -60 60 ps 271 - 410 -50 50 sl r 1( i ) input slew rate input clock 160 - 410 12.54 v/ns output enable (oe, os) 0.5 sl r 1( o ) output clock slew rate 0.8 2 v/ns t jit ( cc +) cycle-to-cycle period jitter 040 ps t jit ( cc -) 0-40 t (?) dyn dynamic phase offset 160 - 270 -50 50 ps 271 - 410 -20 20 t spo 2 2 static phase offset shifted by design. static phase offset 271 - 410 -60 0 60 ps (su) t jit ( per ) + t (?) dyn + t skew ( o )80ps t(h) t (?) dyn + t skew ( o )60ps t skew output-to-output skew 160 - 270 60 ps 271 - 410 30 ssc modulation frequency 30 33 khz ssc clock input frequency deviation 0-0.5% pll loop bandwidth (-3db from unity gain) 2mhz
ics98uae877a 1.5v low-power wide-range frequency clock driver co mmercial temperature grade 1.5v low-power wide-range frequency clock driver 10 ics98uae877a 7181/2 parameter measureme nt information v dd gnd ics98uae877a v (clk) v (clk) v dd /2 v dd /2 ics98uae877a r=10 z=60 z=60 c = 10pf c = 10pf z=50 z=50 r=1m r=10 l=2.97" l = 2.97" v tt v tt note: v tt =gnd c=1pf r=1m c = 1pf scope gnd z=120 gnd yx, fb_outc yx, fb_outt t c(n) t c(n + 1) t jit(cc) =t c(n) +t c(n + 1) figure 1: ibis model output load figure 2: output load test circuit figure 3: cycle-to-cycle jitter
ics98uae877a 1.5v low-power wide-range frequency clock driver co mmercial temperature grade 1.5v low-power wide-range frequency clock driver 11 ics98uae877a 7181/2 figure 4: static phase offset figure 5: output skew figure 6: period jitter clk_inc clk_int clk_inc clk_int t( ? )n t( ? )n+1 t( ? )= n=n 1 t( ? )n n yx yx yx, fb_outc yx, fb_outt t skew yx, fb_outc yx, fb_outt yx, fb_outc yx, fb_outt t c(n) 1 fo t (jit_per) =t c(n) - 1 fo
ics98uae877a 1.5v low-power wide-range frequency clock driver co mmercial temperature grade 1.5v low-power wide-range frequency clock driver 12 ics98uae877a 7181/2 figure 7: half-period jitter yx, fb_outc yx, fb_outt t jit(hper_n) 1 fo t jit(hper_n+1) t jit(hper) =t jit(hper_n) - 1 2xfo clock inputs and outputs 20% 80% t slr 20% 80% t slf v id v od figure 8: input and output slew rates
ics98uae877a 1.5v low-power wide-range frequency clock driver co mmercial temperature grade 1.5v low-power wide-range frequency clock driver 13 ics98uae877a 7181/2 figure 9: dynamic phase offset figure 10: time delay between oe and clock output (y, y) clk clk fb_in fb_in t( ? ) t( ? )dyn ssc off ssc on t( ? )dyn t( ? ) t( ? )dyn ssc off ssc on t( ? )dyn oe 50% v ddq t en 50% v ddq y, y y y oe 50% v ddq t dis 50% v ddq y y
ics98uae877a 1.5v low-power wide-range frequency clock driver co mmercial temperature grade 1.5v low-power wide-range frequency clock driver 14 ics98uae877a 7181/2 v ddq gnd via card via card bead 0603 4.7uf 1206 0.1uf 0603 2200pf 0603 av dd agnd pll 1 figure 11. av dd filtering *place the 2200pf capacitors close to the pll. *use wide traces for pll analog power and gnd. connect pll and caps to agnd trace and connect trace to one gnd via (farthest from pll). *recommended bead: fair-rite p/n 2506036017y0 or equivalent (0.8 dc max., 600 at 100mhz).
ics98uae877a 1.5v low-power wide-range frequency clock driver co mmercial temperature grade 1.5v low-power wide-range frequency clock driver 15 ics98uae877a 7181/2 package outline and pack age dimensions - bga package dimensions are kept current with jedec publication no. 95 seating plane 0.12 c c a b c d a1 d e top view t htyp dtyp 4321 numeric designations for horizontal grid bref cref typ -e- typ -e- d1 e1 alpha designations for vertical grid (letters i, o, q, and s not used) all dimensions in millimeters d 7.00 bsc e 4.50 bsc t min/max 0.86/1.00 e 0.65 bsc d min/max 0.25/0.45 h min/max 0.15/0.31 d1 5.85 bsc e1 3.25 bsc b 0.575 c 0.625 ball grid ref. dims note: ball grid total indicates maximum ball count for package. lesser quantity may be used. * source ref.: jedec publication 95, mo-205*, mo-255** 10-0055 horiz 6 vert 10 total 60 **
ics98uae877a 1.5v low-power wide-range frequency clock driver co mmercial temperature grade 1.5v low-power wide-range frequency clock driver 16 ics98uae877a 7181/2 package outline and pack age dimensions - mlf package dimensions are kept current with jedec publication no. 95 thermally enhanced, very thin, fine pitc h quad flat / no lead plastic package symbol min. max. a 0.80 1.00 a1 0 0.05 a3 0.25 reference b 0.18 0.30 e 0.50 basic n40 nd 10 ne 10 d x e basic 6.00 x 6.00 d2 2.75 3.05 e2 2.75 3.05 l 0.30 0.5 c 0.08 c seating plane a1 a3 a anvil singulation or sawn singulation n 1 2 index area e d top view l e2 e2/2 (n d -1)x e (ref.) n d &n e even (ref.) if n d &n e are even (typ.) e/2 1 2 b (n e -1)x e (ref.) thermal base n d &n e odd (ref.) e d2/2 d2
ics98uae877a 1.5v low-power wide-range frequency clock driver co mmercial temperature grade 1.5v low-power wide-range frequency clock driver 17 ics98uae877a 7181/2 ordering information xxx xx package device type hlf klf low profile, fine pitch, ball grid array - lead-free very thin, fine pitch quad flat package - lead-free 1.5v low-power wide-range frequency clock driver 877a icss98uae shipping carrier x blank i 0c to +70c (commercial) -40c to +85c (industrial) shipping carrier x t tape and reel
? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 innovate with idt and accelerate your future netw orks. contact: www.idt.com ics98uae877a 1.5v low-power wide-range frequency clock driver commercial temperature grade

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