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lp38856 3a fast-response high-accuracy ldo linear regulator with enable general description the lp38856 is a high-current, fast-response regulator which can maintain output voltage regulation with an ex- tremely low input to output voltage drop. fabricated on a cmos process, the device operates from two input voltages: v bias provides power for the internal bias and control cir- cuits, as well as drive for the gate of the n-mos power transistor, while v in supplies power to the load. the use of an external bias rail allows the part to operate from ultra low v in voltages. unlike bipolar regulators, the cmos architec- ture consumes extremely low quiescent current at any out- put load current. the use of an n-mos power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. the fast transient response of this device makes it suitable for use in powering dsp, microcontroller core voltages and switch mode power supply post regulators. the lp38856 is available in to-220 and to-263 5-lead packages. dropout voltage: 240 mv (typical) at 3a load current. low ground pin current: 14 ma (typical) at 3a load cur- rent. shutdown current: 1 a (typical) i in(gnd) when en pin is low. precision output voltage: 1.0% for t j = 25?c and 2.0% for 0?c t j +125?c, across all line and load conditions features n standard v out values of 0.8v and 1.2v n stable with 10 ? ceramic capacitors n dropout voltage of 240 mv (typical) at 3a load current n precision output voltage across all line and load conditions: 1.0% for t j = 25?c 2.0% for 0?c t j +125?c 3.0% for -40?c t j +125?c n over-temperature and over-current protection n available in 5 lead to-220 and to-263 packages n custom v out values between 0.8v and 1.2v are available n -40?c to +125?c operating temperature range applications n asic power supplies in: - desktops, notebooks, and graphics cards, servers - gaming set top boxes, printers and copiers n server core and i/o supplies n dsp and fpga power supplies n smps post-regulator typical application circuit 20131101 june 2006 lp38856 3a fast-response high-accuracy ldo linear regulator with enable 2006 national semiconductor corporation ds201311 www.national.com
ordering information v out * order number package type package drawing supplied as 0.8v lp38856s-0.8 to263-5 ts5b rail of 45 lp38856sx-0.8 to263-5 ts5b tape and reel of 500 lp38856t-0.8 to220-5 t05d rail of 45 1.2v lp38856s-1.2 to263-5 ts5b rail of 45 lp38856sx-1.2 to263-5 ts5b tape and reel of 500 lp38856t-1.2 to220-5 t05d rail of 45 * for custom v out values between 0.8v and 1.2v please contact the national semiconductor sales office. connection diagrams 20131102 to-263, top view 20131103 to-220, top view pin descriptions to220?5 and to263?5 packages pin # pin symbol pin description 1 en the device enable pin. 2 in the unregulated input voltage pin 3 gnd ground 4 out the regulated output voltage pin 5 bias the supply for the internal control and reference circuitry tab tab the tab is a thermal connection that is physically attached to the backside of the die, and is used as a thermal heat-sink connection. see the application information section for details lp38856 www.national.com 2
absolute maximum ratings (note 1) if military/aerospace specified devices are required, please contact the national semiconductor sales office/ distributors for availability and specifications. storage temperature range ?65?c to +150?c lead temperature soldering, 5 seconds 260?c esd rating human body model (note 2) 2kv power dissipation (note 3) internally limited v in supply voltage (survival) ?0.3v to +6.0v v bias supply voltage (survival) ?0.3v to +6.0v v en voltage (survival) ?0.3v to +6.0v v out voltage (survival) ?0.3v to +6.0v i out current (survival) internally limited junction temperature ?40?c to +150?c operating ratings (note 1) v in supply voltage (v out +v do )tov bias v bias supply voltage 3.0v to 5.5v v en enable input voltage 0.0v to v bias i out 0 ma to 3.0a junction temperature range(note 3) ?40?c to +125?c electrical characteristics unless otherwise specified: v in =v out(nom) + 1v, v bias = 3.0v, i out =10ma, c in =c out = 10 ?, c bias = 1?, v en =v bias . limits in standard type are for t j = 25?c only; limits in boldface type apply over the junction temperature (t j ) range of -40?c to +125?c. minimum and maximum limits are guaranteed through test, de- sign, or statistical correlation. typical values represent the most likely parametric norm at t j = 25?c, and are provided for ref- erence purposes only. symbol parameter conditions min typ max units v out output voltage tolerance v out(nom) +1v v in v bias , 3.0v v bias 5.5v, 10 ma i out 3.0a -1.0 -3.0 0.0 +1.0 +3.0 % v out(nom) +1v v in v bias , 3.0v v bias 5.5v, 10 ma i out 3.0a, 0?c t j 125?c -2.0 0 +2.0 ? v out / ? v in line regulation, v in (note 4) v out(nom) +1v v in v bias - 0.04 - %/v ? v out / ? v bias line regulation, v bias (note 4) 3.0v v bias 5.5v - 0.10 - %/v ? v out / ? i out output voltage load regulation (note 5) 10 ma i out 3.0a - 0.2 - %/a v do dropout voltage v in ?v out (note 6) i out = 3.0a - 240 300 450 mv i gnd(in) ground pin current drawn from v in supply lp38856-0.8 10 ma i out 3.0a - 7.0 8.5 9.0 ma lp38856-1.2 10 ma i out 3.0a -11 12 15 v en 0.5v - 1.0 10 300 ? i gnd(bias) ground pin current drawn from v bias supply 10 ma i out 3.0a - 3.0 3.8 4.5 ma v en 0.5v - 100 170 200 ? uvlo under-voltage lock-out threshold v bias rising until device is functional 2.20 2.00 2.45 2.70 2.90 v uvlo (hys) under-voltage lock-out hysteresis v bias falling from uvlo threshold until device is non-functional 60 50 150 300 350 mv i sc output short-circuit current v in =v out(nom) + 1v, v bias = 3.0v, v out = 0.0v - 6.2 - a lp38856 www.national.com 3
electrical characteristics unless otherwise specified: v in =v out(nom) + 1v, v bias = 3.0v, i out =10ma, c in =c out = 10 ?, c bias = 1?, v en =v bias . limits in standard type are for t j = 25?c only; limits in boldface type apply over the junction temperature (t j ) range of -40?c to +125?c. minimum and maximum limits are guaranteed through test, design, or statistical correlation. typical values represent the most likely parametric norm at t j = 25?c, and are provided for reference purposes only. (continued) symbol parameter conditions min typ max units enable pin i en enable pin current v en =v bias - 0.01 - ? v en = 0.0v, v bias = 5.5v -19 -13 -30 -40 -51 v en(on) enable voltage threshold v en rising until output = on 1.00 0.90 1.25 1.50 1.55 v v en(hys) enable voltage hysteresis v en falling from v en(on) until output = off 50 30 100 150 200 mv t off turn-off delay time r load xc out << t off -20- ? t on turn-on delay time r load xc out << t on -15- ac parameters psrr (v in ) ripple rejection for v in input voltage v in =v out +1v, f = 120 hz -80- db v in =v out + 1v, f=1khz -65- psrr (v bias ) ripple rejection for v bias voltage v bias =v out + 3v, f = 120 hz -58- db v bias =v out + 3v, f=1khz -58- e n output noise density f = 120 hz - 1 - ?/ hz output noise voltage bw = 10 hz ? 100 khz - 150 - ? (rms) bw = 300 hz ? 300 khz - 90 - thermal parameters t sd thermal shutdown junction temperature - 160 - ?c t sd(hys) thermal shutdown hysteresis - 10 - ja thermal resistance, junction to ambient(note 3) to220-5 - 60 - ?c/w to263-5 - 60 - jc thermal resistance, junction to case(note 3) to220-5 - 3 - to263-5 - 3 - note 1: absolute maximum ratings indicate limits beyond which damage to the component may occur. operating ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. for guaranteed specifications, see electrical characteristics. sp ecifications do not apply when operating the device outside of its rated operating conditions. note 2: the human body model (hbm) is a 100 pf capacitor discharged through a 1.5k resistor into each pin. test method is per jesd22-a114. the hbm rating for device pin 1 (en) is 1.5 kv. note 3: device power dissipation must be de-rated based on device power dissipation (t d ), ambient temperature (t a ), and package junction to ambient thermal resistance ( ja ). additional heat-sinking may be required to ensure that the device junction temperature (t j ) does not exceed the maximum operating rating. see the application information section for details. note 4: output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. note 5: output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load. note 6: dropout voltage is defined the as input to output voltage differential (v in -v out ) where the input voltage is low enough to cause the output voltage to drop no more than 2% from the nominal value lp38856 www.national.com 4
typical performance characteristics unless otherwise specified: t j = 25?c, v in =v out(nom) + 1v, v bias = 3.0v, i out = 10 ma, c in =c out = 10 f ceramic, c bias = 1 f ceramic, v en =v bias . v bias ground pin current (i gnd(bias) )vsv bias v bias ground pin current (i gnd(bias) ) vs temperature 20131187 20131161 v in ground pin current (i gnd(in) ) vs temperature load regulation vs temperature 20131162 20131163 dropout voltage (v do ) vs temperature output current limit (i sc ) vs temperature 20131165 20131166 lp38856 www.national.com 5
typical performance characteristics unless otherwise specified: t j = 25?c, v in =v out(nom) + 1v, v bias = 3.0v, i out = 10 ma, c in =c out = 10 f ceramic, c bias = 1 f ceramic, v en =v bias . (continued) v out vs temperature uvlo thresholds vs temperature 20131167 20131168 enable thresholds (v en ) vs temperature enable pull-down current (i en ) vs temperature 20131172 20131173 enable pull-up resistor (r en ) vs temperature v in line transient response 20131174 20131177 lp38856 www.national.com 6
typical performance characteristics unless otherwise specified: t j = 25?c, v in =v out(nom) + 1v, v bias = 3.0v, i out = 10 ma, c in =c out = 10 f ceramic, c bias = 1 f ceramic, v en =v bias . (continued) v in line transient response v bias line transient response 20131178 20131179 v bias line transient response load transient response, c out = 10 f ceramic 20131180 20131181 load transient respose, c out = 10 f ceramic load transient response, c out = 100 f ceramic 20131182 20131183 lp38856 www.national.com 7
typical performance characteristics unless otherwise specified: t j = 25?c, v in =v out(nom) + 1v, v bias = 3.0v, i out = 10 ma, c in =c out = 10 f ceramic, c bias = 1 f ceramic, v en =v bias . (continued) load transient response, c out = 100 f ceramic load transient response, c out = 100 f tantalum 20131184 20131185 load transient response, c out = 100 f tantalum v bias psrr 20131186 20131170 v in psrr output noise 20131171 20131169 lp38856 www.national.com 8
block diagram 20131105 lp38856 www.national.com 9
application information external capacitors to assure regulator stability, capacitors are required on the input, output and bias pins as shown in the typical applica- tion circuit. output capacitor a minimum output capacitance of 10 ?, ceramic, is required for stability. the amount of output capacitance can be in- creased without limit. the output capacitor must be located less than 1 cm from the output pin of the ic and returned to the device ground pin with a clean analog ground. only high quality ceramic types such as x5r or x7r should be used, as the z5u and y5f types do not provide sufficient capacitance over temperature. tantalum capacitors will also provide stable operation across the entire operating temperature range. however, the effects of esr may provide variations in the output voltage during fast load transients. using the minimum recommended 10 ? ceramic capacitor at the output will allow unlimited ca- pacitance, tantalum and/or aluminum, to be added in paral- lel. input capacitor the input capacitor must be at least 10 ?, but can be increased without limit. its purpose is to provide a low source impedance for the regulator input. a ceramic capaci- tor, x5r or x7r, is recommended. tantalum capacitors may also be used at the input pin. there is no specific esr limitation on the input capacitor (the lower, the better). aluminum electrolytic capacitors can be used, but are not recommended as their esr increases very quickly at cold temperatures. they are not recommended for any applica- tion where the ambient temperature falls below 0?c. bias capacitor the capacitor on the bias pin must be at least 1 f. it can be any good quality capacitor (ceramic is recommended). input voltage the input voltage (v in ) is the high current external voltage rail that will be regulated down to a lower voltage, which is applied to the load. the input voltage must be at least v out +v do , and no higher than whatever value is used for v bias . bias voltage the bias voltage (v bias ) is a low current external voltage rail required to bias the control circuitry and provide gate drive for the n-fet pass transistor. the bias voltage must be in the range of 3.0v to 5.5v to ensure proper operation of the device. under voltage lockout the bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is below the under-voltage lock-out (uvlo) threshold of approximately 2.45v. as the bias voltage rises above the uvlo threshold the device control circuitry become active. there is approxi- mately 150 mv of hysteresis built into the uvlo threshold to provide noise immunity. when the bias voltage is between the uvlo threshold and the minimum operating rating value of 3.0v the device will be functional, but the operating parameters will not be within the guaranteed limits. supply sequencing there is no requirement for the order that v in or v bias are applied or removed. however, the output voltage cannot be guaranteed until both v in and v bias are within the range of guaranteed operating values. if used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground. a schottky diode is recommend for this diode clamp. reverse voltage a reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin. typically this will happen when v in is abruptly taken low and c out continues to hold a sufficient charge such that the input to output voltage becomes reversed. the nmos pass element, by design, contains no body diode. this means that, as long as the gate of the pass element is not driven, there will not be any reverse current flow through the pass element during a reverse voltage event. the gate of the pass element is not driven when v bias is below the uvlo threshold. when v bias is above the uvlo threshold the control cir- cuitry is active and will attempt to regulate the output voltage. since the input voltage is less than the output voltage the control circuit will drive the gate of the pass element to the full v bias potential when the output voltage begins to fall. in this condition, reverse current will flow from the output pin to the input pin, limited only by the r ds(on) of the pass element and the output to input voltage differential. this condition is outside the guaranteed operating range and should be avoided. enable operation the enable pin (en) provides a mechanism to enable, or disable, the regulator output stage. the enable pin has an internal pull-up, through a typical 200 k ? resistor, to v bias . if the enable pin is actively driven, pulling the enable pin above the v en threshold of 1.25v (typical) will turn the regulator output on, while pulling the enable pin below the v en threshold will turn the regulator output off. there is approximately 100 mv of hysteresis built into the enable threshold provide noise immunity. if the enable function is not needed this pin should be left open, or connected directly to v bias . if the enable pin is left open, stray capacitance on this pin must be minimized, otherwise the output turn-on will be delayed while the stray capacitance is charged through the internal resistance (r en ). power dissipation and heat-sinking a heat-sink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. under all possible conditions, the junction tem- perature must be within the range specified under operating conditions. the total power dissipation of the device is the sum of three different points of dissipation in the device. the first part is the power that is dissipated in the nmos pass element, and can be determined with the formula: lp38856 www.national.com 10
application information (continued) p d(pass) =(v in -v out )xi out (1) the second part is the power that is dissipated in the bias and control circuitry, and can be determined with the for- mula: p d(bias) =v bias xi gnd(bias) (2) where i gnd(bias) is the portion of the operating ground cur- rent of the device that is related to v bias . the third part is the power that is dissipated in portions of the output stage circuitry, and can be determined with the for- mula: p d(in) =v in xi gnd(in) (3) where i gnd(in) is the portion of the operating ground current of the device that is related to v in . the total power dissipation is then: p d =p d(pass) +p d(bias) +p d(in) (4) the maximum allowable junction temperature rise ( ? t j ) de- pends on the maximum anticipated ambient temperature (t a(max) ) for the application, and the maximum allowable operating junction temperature (t j(max) ): (5) the maximum allowable value for junction to ambient ther- mal resistance, ja , can be calculated using the formula: (6) the lp38856 is available in to-220 and to-263 packages. the thermal resistance in the application depends on amount of copper area or heat-sink, and on air flow. if the maximum allowable value of ja calculated above is 60 ?c/w for to-220 package and 60 ?c/w for to-263 pack- age no heat-sink is needed since the package alone can dissipate enough heat to satisfy these requirements. if the value needed for allowable ja falls below these limits, a heat-sink is required. heat-sinking the to-220 package the to-220 package has a ja rating of 60?c/w, and a jc rating of 3?c/w. these ratings are for the package only, no additional heat-sinking, and with no airflow. the thermal resistance of a to-220 package can be reduced by attaching it to a heat-sink or a copper plane on a pc board. if a copper plane is to be used, the values of ja will be same as shown in next section for to-263 package. the heat-sink to be used in the application should have a heat-sink to ambient thermal resistance, ha : (7) where ja is the required total thermal resistance from the junction to the ambient air, ch is the thermal resistance from the case to the surface of the heat sink, and jc is the thermal resistance from the junction to the surface of the case. for this equation, jc is about 3?c/w for a to-220 package. the value for ch depends on method of attachment, insu- lator, etc. ch varies between 1.5?c/w to 2.5?c/w. consult the heat-sink manufacturer datasheet for details and recom- mendations. heat-sinking the to-263 package the to-263 package has a ja rating of 60?c/w, and a jc rating of 3?c/w. these ratings are for the package only, no additional heat-sinking, and with no airflow. the to-263 package uses the copper plane on the pcb as a heat-sink. the tab of this package is soldered to the copper plane for heat-sinking. the graph below shows a curve for the ja of to-263 package for different copper area sizes, using a typical pcb with 1 ounce copper and no solder mask over the copper area for heat-sinking. as shown in figure 1 , increasing the copper area beyond 1 square inch produces very little improvement. the minimum value for ja for the to-263 package mounted to a pcb is 32?c/w. figure 2 shows the maximum allowable power dissipation for to-263 packages for different ambient temperatures, assuming ja is 35?c/w and the maximum junction tempera- ture is 125?c. 20131125 figure 1. ja vs copper (1 ounce) area for the to-263 package lp38856 www.national.com 11
application information (continued) 20131126 figure 2. maximum power dissipation vs ambient temperature for to-263 package lp38856 www.national.com 12
physical dimensions inches (millimeters) unless otherwise noted to220 5-lead, molded, stagger bend package (to220-5) ns package number t05d to263 5-lead, molded, surface mount package (to263-5) ns package number ts5b lp38856 www.national.com 13
notes national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the right at any time without notice to change said circuitry and specifications. for the most current product information visit us at www.national.com. life support policy national? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president and general counsel of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. banned substance compliance national semiconductor follows the provisions of the product stewardship guide for customers (csp-9-111c2) and banned substances and materials of interest specification (csp-9-111s2) for regulatory environmental compliance. details may be found at: www.national.com/quality/green. lead free products are rohs compliant. national semiconductor americas customer support center email: new.feedback@nsc.com tel: 1-800-272-9959 national semiconductor europe customer support center fax: +49 (0) 180-530 85 86 email: europe.support@nsc.com deutsch tel: +49 (0) 69 9508 6208 english tel: +44 (0) 870 24 0 2171 fran?ais tel: +33 (0) 1 41 91 8790 national semiconductor asia pacific customer support center email: ap.support@nsc.com national semiconductor japan customer support center fax: 81-3-5639-7507 email: jpn.feedback@nsc.com tel: 81-3-5639-7560 www.national.com lp38856 3a fast-response high-accuracy ldo linear regulator with enable

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