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VSC7173 data sheet enhanced 2:1 port selector and 1:2 port multiplier for serial ata and serial attached scsi revision 4.1 may 23, 2005 confidential for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maxim-ic.com. maxim integrated products 1 of 17 to order the VSC7173 device, see ?ordering information,? page 17. g eneral d escription the VSC7173 is a serial ata and serial attached scsi mu ltiplexer and buffer that implements a 2:1 port selector function for 1.5 gbps and 3.0 gbps links. this function is used when dual hosts, such as i/o controllers, must access single-port disk drives in high availability storage subsys tems where redundancy and load sharing are important. the outputs from the i/o controllers are multiplexed to a serial ata or serial attached scsi drive. the output from the serial ata drive is buffered and repli cated to the i/o controller s. when switching from on e i/o controller to the other, a serial ata link must be re-initialized with out-of-band (oob) signals, which are transferred through the VSC7173 transparently. the VSC7173 pr ovides high output swings with pre-emphasis, and programmable receiver sensitivity that are needed to drive long backplanes and external cables. in addition to the above features, the VSC7173 also supports a 1:2 port multiplier mode where one host can connect two drives. port connectivity for the device is configured by driving external i/o pins. see the block diagram on page 2 . f eatures 2:1 port selector and 1:2 port multiplier for both serial ata (sata) and serial attached scsi (sas) links serial ata 1.0 compliant at 1.5 gbps (3.0 gbps capable) passes serial ata patterns transparently programmable receiver sensitivity high output swing mode with pre-emphasis compatible with vsc7175 and vsc7177 designs 0.7 w power dissipation 3.3 v power supply 32-pin, 7 mm x 7 mm qfp-n package a pplications active-passive redundant failover systems dual-port serial ata and serial attached scsi disk arrays (jbods) nas servers raid subsystems disk-based backup systems serial ata and serial attached scsi routing applications buffers for externally connected links serial ata port replicators serial ata host bus adapters selecting between internal and external connectors
2 of 17 VSC7173 data sheet revision 4.1 may 23, 2005 confidential VSC7173 block diagram 0 1 0 1 s 0 1 s p0inp p0inn oobport0 p2outp p2outn p2inp p2inn p0outp p0outn p1outp p1outn p0sltd p1inp p1inn oob s edge-triggered logic 0 1 s oob oob en en en set rst portsel0 portsel1 mode1 mode1 mode0 q qn port 2 port 0 port 1 i/o configuration oobsel [0:1] hiv [0:2]
3 of 17 VSC7173 data sheet revision 4.1 may 23, 2005 confidential application examples the VSC7173 allows two serial ata hos ts to access one serial ata drive. figure 1 shows a common application where redundant i/o cont rollers in disk arrays have multiplexed access to single-port serial ata disk drives. another application example ( figure 2 ) is for simple port replication to enab le an existing serial ata host bus adapter (hba) to connect to two ports. by using the VSC7173, a single channel from the hba may be selectively connected to an internal connector or an external connector. the VSC7173 provides both the mulitplexing functionality and buffering to drive external connections. figure 1. serial ata backplane application figure 2. port multiplier application "tailgate" board backplane VSC7173 i/o controller a i/o controller b serial ata drive (1 of n) port multiplier external connector VSC7173 port a port b internal connector serial ata host bus adaptor pci bus external connector
4 of 17 VSC7173 data sheet revision 4.1 may 23, 2005 confidential f unctional d escriptions modes of operation table 1 summarizes the VSC7173 operational mode choices. the mode of the VSC7173 is determined by the following pins. mode1: controls whether the selection of port 0 to port 1 is edge-sensitive or level-sensitive. when low, port selection is level-sensitive (to enable level-sensitive port selection, pin portsel1 must also be low). when high, port selection is edge-sensitive. mode0: controls the function of the unselected port. when low, the output of this port is turned off. when high, the output of this unselected port is th e same data as seen on the selected port. portsel0: in level-sensitive mode (mode1 is low and portse l1 is low), controls the selection of port 0 or port 1. when low, port 0 is selected; when high, port 1 is selected. in edge-sensi tive mode (mode1 is high), controls the selection of port 0; a rising edge on this pin selects port 0. portsel1: in level-sensitive mode (mode1 is low), must be held low. in edge-sensitive mode (mode1 is high), controls the selection of port 1; a rising edge on this pin selects port 1. x = don?t care; = rising. status pins two output pins, p0sltd and oobport0, are provided for status monitoring. table 2 summarizes the functionality of these two output pins. oobport0 reports whether the signa l on port 0 is above or below the threshold selected in table 5 . p0sltd, depending on the state of mode1, can either report which port is select ed or can report whether the signal on port 1 is above or below the threshold selected in table 5 . x = don?t care; = rising. table 1. port selection operating modes input pins high-speed connections mode1 mode0 portsel0 portsel1 p0out p1out p2out 0 (level) 0 0 0 p2in off p0in 0 (level) 0 1 0 off p2in p1in 0 (level) 1 0 0 p2in p2in p0in 0 (level) 1 1 0 p2in p2in p1in 1 (edge) 0 x off p2in p1in 1 (edge) 0 xp2inoffp0in 1 (edge) 1 x p2in p2in p1in 1 (edge) 1 x p2in p2in p0in table 2. output status pins input pins output status pins mode1 portsel0 portsel1 p0sltd oobport0 0 (level) x x oob status port 1?1 indicates signal is below oob threshold, 0 indicates signal is above oob threshold oob status port 0?1 indicates signal is below oob threshold, 0 indicates signal is above oob threshold 1 (edge) x indicates port selected, 0 = port 1 oob status port 0 1 (edge) x indicates port selected, 1 = port 0 oob status port 0
5 of 17 VSC7173 data sheet revision 4.1 may 23, 2005 confidential reset state the power-up state of the VSC7173 is based on the portsel0 and portsel1 input signals. when in level- sensitive mode, the active port connected to port 2 is controlled directly by the portsel0 input. this is the same behavior as the normal operating condition described above. when in edge-sensitive mo de, the active port connected to port 2 is defined in table 3 . the state diagram in figure 3 indicates the same result in a different format. table 3. power-up state (edge-sensitive mode) portsel0 portsel1 active port p0sltd output 0 0 port 0 selected 1 1 0 port 0 selected 1 0 1 port 1 selected 0 1 1 port 0 selected 1 figure 3. reset state machine (edge-sensitive mode) reset state port 0 selected port 1 selected portsel0=0, portsel1=1 and reset=0 (portsel0=1, portsel1=1 or portsel1=0) and reset=0 portsel0 portsel1 reset=1 reset=1
6 of 17 VSC7173 data sheet revision 4.1 may 23, 2005 confidential high-speed outputs each port has a high-speed output buffer that transmits the differential serial ata data at rates up to 3.0 gbps. the output pins for the ports are p0outp/n, p1outp/n, and p2 outp/n. each output buffer has an input to indicate when oob signals are being transmitted an d a single input to control the output voltage amplitude and to enable pre- emphasis. transmitting oob signals both differential output signals are at the dc-bias voltage when the output buff er is disabled. the output buffer is disabled when oob signals are transmitted and when an out put port is turned ?off.? for more information, see ?functional descriptions,? page 4. output amplitude and pre-emphasis each of the output buffers has an amplitude control input pi n, the state of which sets th e differential output voltage (within normal sata levels). pin hiv0 corresponds to po rt 0, pin hiv1 corresponds to port 1, and pin hiv2 corresponds to port 2. see table 4 . recommended output ac-coupling capacitor values are 0.01 f. when the amplitude control pin is high, the output is configured for high voltage swing mode, which is useful for driving extended length media such as backplanes or external cables. setting the output to high swing mode should be done only in controlled environments, because the output vo ltage exceeds the serial ata 1.0 differential mode specifications. the output buffers have a pre-emphasis circuit that is enabled when hivx is high. pre-emphasis accentuates higher frequency signals in a transmitted data stream. this feature takes into consider ation that a signal loses amplitude and affects the data eye opening as it go es through long trace length runs. figure 5 shows the effects of the pre-emphasis feature. the amplitude increase is between 20% and 30%, and the duration of the amplitude increase is between 150 ps and 300 ps. figure 4. high-speed output buffer table 4. output amplitude and pre-emphasis hivx pin state output swing level pre-emphasis 0 normal none 1 high enabled output outputn data tx common mode hiv
7 of 17 VSC7173 data sheet revision 4.1 may 23, 2005 confidential high-speed inputs the high-speed input receivers are designed to achieve serial ata 1.0 co mpliance using ac-coupling as described in the serial ata 1.0 specification. recommended input ac-coupling capacitor values are 0.01 f. the high-speed input receiver contains an oob signal detector as shown in figure 6 . oob transfer the VSC7173 cleanly transfers oob signal s from high-speed inputs to outputs. two status outputs, oobport0 and oobport1, indicate whether the input signal is data or a common-mode state. oobport1 and oobport1 correspond to port 0 and port 1, respectively. an oob detector monitors the amplitude of an incoming signal in parallel with each high-speed input. when the amplitude is less than the oob threshold, the oob status output is driven high. when the incoming amplitu de is greater than the oob threshold, the oob status output is driven low. setting the oobsel1 and oobsel0 inputs as shown in the following table configures the oob threshold level for all three ports. note: all values are different ial peak-to-peak voltages. figure 5. pre-emphasis diagram figure 6. high-speed input receiver table 5. setting the oob threshold level oobsel1 oobsel0 oob threshold level 1 0 nominal setting (150 mv to 250 mv) 0 0 decrease by ~40 mv 0 1 decrease by ~80 mv 1 1 increase by ~40 mv 0 0 1 1 1 1 1 0 1 0 pre-emphasis disabled 0 0 1 1 1 1 1 0 1 0 pre-emphasis enabled v out v out input inputn input receiver oob detector oob status (oobportx signal) data oobsel0 oobsel1
8 of 17 VSC7173 data sheet revision 4.1 may 23, 2005 confidential e lectrical s pecifications dc characteristics specifications are guaranteed over the r ecommended operating conditions listed in table 11 . table 6. lvttl inputs and outputs symbol parameter minimum typical maximum unit condition v oh output high voltage 2.0 2.2 v dd vi oh = ?4 ma v ol output low voltage 0.0 0.2 0.4 v i ol = 4 ma v ih input high voltage 2.0 v dd v v il input low voltage 0.0 0.8 v i i input current (incl udes a weak pull-up resistor) ?200 +50 a0v < v il < 2.4 v table 7. high-speed inputs and outputs symbol parameter minimum typical maximum unit condition v th input threshold voltage for oob detection 200 mv see table 5 on page 7 . v ocm high-speed output common-mode voltage 2.0 v normal swing mode. 100 ? termination between true and complement outputs. 1.7 v high swing mode. 100 ? termination between true and complement outputs. v icm high-speed input common-mode voltage 1.5 v z in differential input impedance 85 100 115 ? table 8. power supply requirements symbol parameter minimum typical maximum unit condition v dd power supply voltage 3.0 3.3 3.6 v 10% on all supplies i dd power supply current (total on all supply pins) 150 170 ma normal swing mode 200 235 ma high swing mode p d total power dissipation 540 625 mw normal swing mode 720 850 mw high swing mode
9 of 17 VSC7173 data sheet revision 4.1 may 23, 2005 confidential ac characteristics specifications are guaranteed over the recommended operating conditions listed in table 11 on page 11 . 1. refer to application note an-37 for differential measurement techniques. 2. output swings are higher than the serial ata 1.0 specification to compensate for anticipated pcb or connector losses. figure 7. timing waveform table 9. high-speed inputs and outputs symbol parameter minimum maximum unit condition t p propagation delay from any high-speed input to high-speed output 0.4 2.0 ns t on propagation delay from signal present at input to output buffer turned on 3.0 12.0 ns t off propagation delay from no signal at input to output buffer turned off 3.0 12.0 ns t r , t f rise and fall times 67 260 ps 1.5 gbps operation, 20% to 80%. v out (1) outx output differential peak-to-peak voltage swing in normal swing mode (hivx is low) 500 700 mvp-p measured per serial ata 1.0 specification, section 6.6.3. 100 ? termination between true and complement outputs. v out (1, 2) outx output differential peak-to-peak voltage swing in high swing mode (hivx is high) 800 1300 mvp-p measured per serial ata 1.0 specification, section 6.6.3. 100 ? termination between true and complement outputs. v in inx input differential peak-to-peak swing with oobsel1 = 1 and oobsel0 = 0 (oob nominal) 275 1600 mvp-p measured per serial ata 1.0 specification. v in inx input differential peak-to-peak swing with oobsel1 = 0 and oobsel0 = 1 (oob minimal) 225 1600 mvp-p measured per serial ata 1.0 specification, section 6.6.3. high-speed input t on t off high-speed output
10 of 17 VSC7173 data sheet revision 4.1 may 23, 2005 confidential figure 8. timing waveform for port switching table 10. port switch timing symbol parameter minimum maximum unit condition t pw pulse width of the port selection pins (portsel0, portsel1). 4.0 ns t pss separation between rising edge transitions of the port selection pins. 5.0 ns edge-sensitive operation t sw switch time. the time required to make the other host port active following an active edge transition of the port selection pins. 5.0 ns applies to both level and edge-sensitive operations portsel0 active host port (port 0 or port 1) portsel1 * edge sensitive sideband operation shown in timing diagram. t pss t pss t sw t sw t sw t pw portsel0, portsel1 t pw note: edge-sensitive operation shown.
11 of 17 VSC7173 data sheet revision 4.1 may 23, 2005 confidential operating conditions 1. lower limit of specification is ambient temperature, and upper limit is case temperature. maximum ratings stresses listed under maximum ratings may be applied to devices one at a time without causing permanent damage. functionality a t or above the values listed is not implied. exposure to these values for extended periods may affect device reliability. table 11. recommended operating conditions symbol parameter minimum typical maximum unit v dd power supply voltage 3.0 3.3 3.6 v t operating temperature (1) 0+90c table 12. absolute maximum ratings symbol parameter minimum maximum unit v dd power supply voltage ?0.5 +4.0 v v int lvttl input voltage ?0.5 v dd + 0.5 v v outt lvttl output voltage ?0.5 v dd + 0.5 v i ot lvttl output current ?50 +50 ma v ins serial input voltage ?0.5 v dd + 0.5 v v outs serial output voltage ?0.5 v dd + 0.5 v i os serial output current ?50 +50 ma t s storage temperature ?65 +140 c v esd electrostatic voltage dischar ge, human body model ?4000 +4000 v electrostatic discharge this device can be damaged by esd. maxim recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures may adversely affect reliability of the device.
12 of 17 VSC7173 data sheet revision 4.1 may 23, 2005 confidential p in d escriptions the VSC7173 is packaged in a 32-pin, leadless quad flat pack (qfp-n) with an exposed pad. pin diagram figure 9. pin diagram vdd0 vss p0outn p0outp hiv0 p0inn p0inp p0sltd 1 3 5 7 mode0 vdd portsel0 portsel1 oobsel1 mode1 vss oobsel0 23 21 19 17 vdd1 vss p1outn p1outp hiv1 p1inn p1inp oobport0 9 11 13 15 reserved p2inn p2inp hiv2 p2outp vss p2outn vdd2 31 29 27 25 exposed die attach pad (1) (bottom side) 1. the exposed die attach pad (dap) is internally connected to ground and should also be connected to vss on the board. VSC7173 top view
13 of 17 VSC7173 data sheet revision 4.1 may 23, 2005 confidential pin identifications table 13. pin identifications pin number signal type level description 7, 6 15, 14 31, 30 p0outp, p0outn p1outp, p1outn p2outp, p2outn o high- speed these are the high-speed differential outputs for port 0, port 1, and port 2. these outputs must be ac-coupled. 3, 4 11, 12 27, 28 p0inp, p0inn p1inp, p1inn p2inp, p2inn i high- speed these are the high-speed differential inputs for port 0, port 1, and port 2. these inputs must be ac-coupled. 19 18 portsel0 portsel1 i lvttl these two inputs select the active port (port 0 or port 1). for more information on the modes of operation, see table 1 on page 4 . 2 10 26 hiv0 hiv1 hiv2 i lvttl when high, these inputs select the high voltage swing output mode for the corresponding output buffer and enable pre- emphasis. see table 4 on page 6 . 24 23 oobsel0 oobsel1 i lvttl these two inputs control the oob detector threshold voltage for all three input ports. see table 5 on page 7 for threshold levels. 1 p0sltd o lvttl this output reports which port is selected or oob status of port 1, depending on the value of mode1. see table 2 on page 4 . 9 oobport0 o lvttl when high, this output indicates that the input signal for port 0 is below the oob threshold. when lo w, the input signal for port 0 is above the oob threshold. 17 mode0 i lvttl this input is used to select the operating mode for the VSC7173 as described in table 1 on page 4 . 21 mode1 i lvttl this input is used to select the operating mode for the VSC7173 as described in table 1 on page 4 . 20 vdd power 3.3 v power supply for all circuits except the high-speed output buffers. 8, 16 32 vdd0, vdd1 vdd2 power 3.3 v output buffer power supply for p0outp/n, p1outp/n, and p2outp/n, respectively. 25 reserved reserved for future use. leave unconnected. 5, 13, 22, 29 dap vss gnd common ground. dap is the exposed die attach pad on the bottom of the device.
14 of 17 VSC7173 data sheet revision 4.1 may 23, 2005 confidential p ackage i nformation the VSC7173 device is available in a lead(pb)-free package. vs c7173xyi is a 32-pin leadless quad flat pack (qfp-n) with an exposed pad. lead(pb)-free products from maxim comp ly with the temperatures and profiles defined in the joint ipc and jedec standard ipc/jedec j-std-020. for more in formation, see the ipc and jedec standard. thermal specifications thermal specifications for this device are based on the jedec standard eia/jesd51-2 and have been modeled using a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p pcb). for more information, see the jedec standard. to achieve results similar to the modeled thermal resistance measurements, the guidelines for board design described in the jedec standard eia/jesd51 series must be appl ied. for information about sp ecific applications, see the following: eia/jesd51-5, extension of thermal test board standards for packages with direct thermal attachment mechanisms eia/jesd51-7, high effective thermal conductivity test board for leaded surface mount packages eia/jesd51-9, test boards for area array surface mount package thermal measurements eia/jesd51-10, test boards for through-hole perimeter leaded package thermal measurements eia/jesd51-11, test boards for through-hole area array leaded package thermal measurement moisture sensitivity this device is rated moisture sensitivity level 3 or better as specified in the joint ipc and jedec standard ipc/jedec j-std-020. for more informat ion, see the ipc and jedec standard. table 14. thermal resistances part number jc ja (c/w) vs. airflow (ft/min) 0 100 200 VSC7173xyi 18.2 30.0 28.7 27.0
15 of 17 VSC7173 data sheet revision 4.1 may 23, 2005 confidential package drawing figure 10. package drawing notes: drawing not to scale. all units in mm unless otherwise noted. ?b? is measured 0.20 to 0.25 from the terminal tip. item minimum maximum a 0.85 nom. 0.90 a1 0 0.05 a3 0.20 ref b 0.23 0.35 d 7.00 bsc d2 4.95 5.25 e 0.65 bsc l 0.50 0.75 e side view a3 a a1 d d top view 1 b l 25 32 24 1 8 9 16 17 d2 0.45 d2 bottom view 12 max. exposed pad area
16 of 17 VSC7173 data sheet revision 4.1 may 23, 2005 confidential recommended land pattern figure 11. recommended land pattern d e c b land pad detail f g vias (16 places) stencil openings (16 places) a a1 a2 notes: all vias 0.30 to 0.33 diameter, plugged. drawing not to scale. all dimensions are in mm unless otherwise noted. item 7 mm x 7 mm x 0.9 mm exposed pad qfp-n comments a 7.445 maximum a1 5.325 minimum a2 4.92 maximum b 0.37 maximum c1.06 d 4.95 minimum 5.075 typical 5.20 maximum thermal land dimensions e 5.10 solder mask opening dimension f 1.0 stencil opening dimensions g 1.2 stencil opening and via spacing
17 of 17 VSC7173 data sheet revision 4.1 may 23, 2005 confidential o rdering i nformation the VSC7173 device is available in a lead(pb)-free package. VSC7173xyi is 32-pin leadless quad flat pack (qfp-n) with an exposed pad. lead(pb)-free products from maxim comp ly with the temperatures and profiles defined in the joint ipc and jedec standard ipc/jedec j-std-020. for more in formation, see the ipc and jedec standard. table 15. VSC7173 ordering information part number description VSC7173xyi lead(pb)-free 32-pin qfp-n, 7 mm x 7 mm x 0.9 mm body maxim integrated products 120 san gabriel drive sunnyvale, ca 94086 united states 408-737-7600 www.maxim-ic.com copyright ? 2004 to 2005 maxim integrated products maxim cannot assume responsibility for use of any circuitry ot her than circuitry entirely embod ied in a maxim product. maxim re tains the right to make changes to its products or specifications to improve performance, re liability or manufacturability. all infor mation in this document, includ ing descriptions of features, function s, performance, techni cal specifications and availability, is subjec t to change without notice at any time. while the information furn ished herein is held to be accura te and reliable, no responsibilit y will be assumed by maxim for its use. furthermore, the information contai ned herein does not convey to the purchaser of microelectronic devices any license under the patent right of any manufacturer. maxim products are not intended for use in life support products where failure of a maxim product could reasonably be expected to result in death or personal injury. anyone using a maxim product in such an application without express written consent of an o fficer of maxim does so at their own risk, and agr ees to fully indemnify maxim for any damages that may result from such use or sale. is a registered trademark of maxim integrated products, inc. all other products or service names used in this publication are for i dentification purposes only, and may be trademarks or reg istered trademarks of their respective companies. all other trademarks or registered trademarks mentioned herein are the property of th eir respective holders.

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