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fiber channel/ethernet clock generator ic, pll core, dividers, 7 clock outputs AD9572 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features fully integrated dual vco/pll cores 167 fs rms jitter from 0.637 mhz to 10 mhz at 106.25 mhz 178 fs rms jitter from 1.875 mhz to 20 mhz at 156.25 mhz 418 fs rms jitter from 12 khz to 20 mhz at 125 mhz input crystal or clock frequency of 25 mhz preset divide ratios for 106.25 mhz, 156.25 mhz, 33.33 mhz, 100 mhz, 125 mhz choice of lvpecl or lvds output format integrated loop filters copy of reference clock output rates configured via strapping pins space saving, 6 mm 6 mm, 40-lead lfcsp 0.71 w power dissipation (lvds operation) 1.07 w power dissipation (lvpecl operation) 3.3 v operation applications fiber channel line cards, switches, and routers gigabit ethernet/pcie support included low jitter, low phase noise clock generation functional block diagram xtal osc refclk refsel 1 25mhz cmos freqsel AD9572 2 106.25mhz vco pfd/cp lpf 3rd order dividers lvpecl or lvds 2 100mhz or 125mhz vco pfd/cp lpf 3rd order dividers lvpecl or lvds 1 156.25mhz lvpecl or lvds force_low 1 33.33mhz cmos ldo ldo 0 7498-001 figure 1. general description the AD9572 provides a multioutput clock generator function along with two on-chip pll cores, optimized for fiber channel line card applications that include an ethernet interface. the integer-n pll design is based on the analog devices, inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. other applica- tions with demanding phase noise and jitter requirements also benefit from this part. the pll section consists of a low noise phase frequency detector (pfd), a precision charge pump (cp), a low phase noise voltage controlled oscillator (vco), and a preprogrammed feedback divider and output divider. by connecting an external crystal or reference clock to the refclk pin, frequencies up to 156.25 mhz can be locked to the input reference. each output divider and feedback divider ratio is preprogrammed for the required output rates. a second pll also operates as an integer-n synthesizer and drives two lvpecl or lvds output buffers for 106.25 mhz operation. no external loop filter components are required, thus conserving valuable design time and board space. the AD9572 is available in a 40-lead, 6 mm 6 mm lead frame chip scale package (lfcsp) and can be operated from a single 3.3 v supply. the temperature range is ?40c to +85c. quad sfp phy quad sfp phy quad sfp phy quad sfp phy 16-port fibre channel asic 10g sfp+ cpu island AD9572 1 156.25mhz 2 106.25mhz 1 100mhz/125mhz 1 25mhz 1 33.33mhz 0 7498-002 figure 2. typical application
AD9572 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? pll characteristics ...................................................................... 3 ? lvds clock output jitter ............................................................ 4 ? lvpecl clock output jitter ....................................................... 5 ? cmos clock output jitter .......................................................... 5 ? reference input ............................................................................. 5 ? clock outputs ............................................................................... 6 ? timing characteristics ................................................................ 6 ? control pins .................................................................................. 7 ? power .............................................................................................. 7 ? crystal oscillator .......................................................................... 7 ? timing diagrams .............................................................................. 8 ? absolute maximum ratings ............................................................ 9 ? thermal resistance ...................................................................... 9 ? esd caution...................................................................................9 ? pin configuration and function descriptions ........................... 10 ? typical performance characteristics ........................................... 12 ? terminology .................................................................................... 13 ? theory of operation ...................................................................... 14 ? outputs ........................................................................................ 14 ? phase frequency detector (pfd) and charge pump ............ 15 ? power supply ............................................................................... 15 ? cmos clock distribution ........................................................ 15 ? lvpecl clock distribution ..................................................... 16 ? lvds clock distribution .......................................................... 16 ? reference input ........................................................................... 16 ? power and grounding considerations and power supply rejection ...................................................................................... 16 ? outline dimensions ....................................................................... 17 ? ordering guide .......................................................................... 17 ? revision history 7/09revision 0: initial version
AD9572 rev. 0 | page 3 of 20 specifications pll characteristics typical (typ) is given for v s = 3.3 v, t a = 25c, unless otherwise noted. table 1. parameter min typ max unit test conditions/comments phase noise characteristics pll noise (106.25 mhz lvds output) @ 1 khz ?123 dbc/hz 33.33 mhz output disabled @ 10 khz ?127 dbc/hz 33.33 mhz output disabled @ 100 khz ?129 dbc/hz 33.33 mhz output disabled @ 1 mhz ?150 dbc/hz 33.33 mhz output disabled @ 10 mhz ?152 dbc/hz 33.33 mhz output disabled @ 30 mhz ?153 dbc/hz 33.33 mhz output disabled pll noise (156.25 mhz lvds output) @ 1 khz ?118 dbc/hz 33.33 mhz output disabled @ 10 khz ?125 dbc/hz 33.33 mhz output disabled @ 100 khz ?126 dbc/hz 33.33 mhz output disabled @ 1 mhz ?145 dbc/hz 33.33 mhz output disabled @ 10 mhz ?151 dbc/hz 33.33 mhz output disabled @ 30 mhz ?151 dbc/hz 33.33 mhz output disabled pll noise (125 mhz lvds output) @ 1 khz ?119 dbc/hz 33.33 mhz output disabled @ 10 khz ?127 dbc/hz 33.33 mhz output disabled @ 100 khz ?128 dbc/hz 33.33 mhz output disabled @ 1 mhz ?147 dbc/hz 33.33 mhz output disabled @ 10 mhz ?151 dbc/hz 33.33 mhz output disabled @ 30 mhz ?152 dbc/hz 33.33 mhz output disabled pll noise (100 mhz lvds output) @ 1 khz ?121 dbc/hz 33.33 mhz output disabled @ 10 khz ?128 dbc/hz 33.33 mhz output disabled @ 100 khz ?130 dbc/hz 33.33 mhz output disabled @ 1 mhz ?147 dbc/hz 33.33 mhz output disabled @ 10 mhz ?150 dbc/hz 33.33 mhz output disabled @ 30 mhz ?150 dbc/hz 33.33 mhz output disabled pll noise (106.25 mhz lvpecl output) @ 1 khz ?121 dbc/hz 33.33 mhz output disabled @ 10 khz ?128 dbc/hz 33.33 mhz output disabled @ 100 khz ?129 dbc/hz 33.33 mhz output disabled @ 1 mhz ?151 dbc/hz 33.33 mhz output disabled @ 10 mhz ?154 dbc/hz 33.33 mhz output disabled @ 30 mhz ?155 dbc/hz 33.33 mhz output disabled pll noise (156.25 mhz lvpecl output) @ 1 khz ?119 dbc/hz 33.33 mhz output disabled @ 10 khz ?125 dbc/hz 33.33 mhz output disabled @ 100 khz ?126 dbc/hz 33.33 mhz output disabled @ 1 mhz ?147 dbc/hz 33.33 mhz output disabled @ 10 mhz ?152 dbc/hz 33.33 mhz output disabled @ 30 mhz ?153 dbc/hz 33.33 mhz output disabled
AD9572 rev. 0 | page 4 of 20 parameter min typ max unit test conditions/comments pll noise (125 mhz lvpecl output) @ 1 khz ?122 dbc/hz 33.33 mhz output disabled @ 10 khz ?127 dbc/hz 33.33 mhz output disabled @ 100 khz ?128 dbc/hz 33.33 mhz output disabled @ 1 mhz ?148 dbc/hz 33.33 mhz output disabled @ 10 mhz ?152 dbc/hz 33.33 mhz output disabled @ 30 mhz ?153 dbc/hz 33.33 mhz output disabled pll noise (100 mhz lvpecl output) @ 1 khz ?122 dbc/hz 33.33 mhz output disabled @ 10 khz ?128 dbc/hz 33.33 mhz output disabled @ 100 khz ?130 dbc/hz 33.33 mhz output disabled @ 1 mhz ?148 dbc/hz 33.33 mhz output disabled @ 10 mhz ?150 dbc/hz 33.33 mhz output disabled @ 30 mhz ?151 dbc/hz 33.33 mhz output disabled phase noise (33.33 mhz cmos output) @ 1 khz ?130 dbc/hz @ 10 khz ?138 dbc/hz @ 100 khz ?139 dbc/hz @ 1 mhz ?152 dbc/hz @ 5 mhz ?152 dbc/hz phase noise (25 mhz cmos output) @ 1 khz ?133 dbc/hz @ 10 khz ?142 dbc/hz @ 100 khz ?148 dbc/hz @ 1 mhz ?148 dbc/hz @ 5 mhz ?148 dbc/hz spurious content 1 ?70 dbc dominant amplitud e with all outputs active pll figures of merit ?217.5 dbc/hz 1 when the 33.33 mhz, 100 mhz, an d 125 mhz clocks are enabled s imultaneously, a worst-case ?50 db c spurious content might be pre sented on pin 21 and pin 22 only. lvds clock output jitter typical (typ) is given for v s = 3.3 v, t a = 25c, unless otherwise noted. table 2. jitter integration bandwidth (typ) 100 mhz 33m = off/on 106.25 mhz 33m = off/on 125 mhz 33m = off/on 156.25 mhz 33m = off/on unit test conditions/comments 12 khz to 20 mhz 508/490 402/440 418/883 417/423 f s rms lvds output frequency combinations are 1 156.25 mhz, 1 100 mhz, 1 125 mhz, 2 106.25 mhz 1.875 mhz to 20 mhz 178/185 f s rms lvds output frequency combinations are 1 156.25 mhz, 1 100 mhz, 1 125 mhz, 2 106.25 mhz 637 khz to 10 mhz 167/217 f s rms lvds output frequency combinations are 1 156.25 mhz, 1 100 mhz, 1 125 mhz, 2 106.25 mhz 200 khz to 10 mhz 316/308 253/776 f s rms lvds output frequency combinations are 1 156.25 mhz, 1 100 mhz, 1 125 mhz, 2 106.25 mhz 12 khz to 35 mhz 500 (off only) f s rms lvds output frequency combinations are 1 156.25 mhz, 2 125 mhz, 2 106.25 mhz
AD9572 rev. 0 | page 5 of 20 lvpecl clock output jitter typical (typ) is given for v s = 3.3 v, t a = 25c, unless otherwise noted. table 3. jitter integration bandwidth (typ) 100 mhz 33m = off/on 106.25 mhz 33m = off/on 125 mhz 33m = off/on 156.25 mhz 33m = off/on unit test conditions/comments 12 khz to 20 mhz 608/564 418/451 444/2200 420/461 f s rms lvpecl output frequency combinations are 1 156.25 mhz, 1 100 mhz, 1 125 mhz, 2 106.25 mhz 1.875 mhz to 20 mhz 200/277 f s rms lvpecl output frequency combinations are 1 156.25 mhz, 1 100 mhz, 1 125 mhz, 2 106.25 mhz 637 khz to 10 mhz 227/232 f s rms lvpecl output frequency combinations are 1 156.25 mhz, 1 100 mhz, 1 125 mhz, 2 106.25 mhz 200 khz to 10 mhz 337/378 242/2200 f s rms lvpecl output frequency combinations are 1 156.25 mhz, 1 100 mhz, 1 125 mhz, 2 106.25 mhz 12 khz to 35 mhz 523 (off only) f s rms lvpecl output frequency combinations are 1 156.25 mhz, 2 125 mhz, 2 106.25 mhz cmos clock output jitter typical (typ) is given for v s = 3.3 v, t a = 25c, unless otherwise noted. table 4. jitter integration bandwidth 25 mhz 33.3 mhz unit test conditions/comments 12 khz to 5 mhz 781 417 f s rms 200 khz to 5 mhz 764 524 f s rms reference input typical (typ) is given for v s = 3.3 v 10%, t a = 25c, unless otherwise noted. minimum (min) and maximum (max) values are given over full v s and t a (?40c to +85c) variation. table 5. parameter min typ max unit test conditions/comments clock input (refclk) input frequency 25 mhz input high voltage 2.0 v input low voltage 0.8 v input current ?1.0 +1.0 a input capacitance 2 pf
AD9572 rev. 0 | page 6 of 20 clock outputs typical (typ) is given for v s = 3.3 v 10%, t a = 25c, unless otherwise noted. minimum (min) and maximum (max) values are given over full v s and t a (?40c to +85c) variation. table 6. parameter min typ max unit test conditions/comments lvpecl clock outputs output frequency 156.25 mhz output high voltage (v oh ) v s ? 1.24 v s ? 1.05 v s ? 0.83 v output low voltage (v ol ) v s ? 2.07 v s ? 1.87 v s ? 1.62 v output differential voltage (v od ) 700 825 950 mv duty cycle 45 55 % lvds clock outputs output frequency 156.25 mhz differential output voltage (v od ) 250 350 475 mv delta v od 25 mv output offset voltage (v os ) 1.125 1.25 1.375 v delta v os 25 mv short-circuit current (i sa , i sb ) 14 24 ma output shorted to gnd duty cycle 45 55 % cmos clock outputs output frequency 33.33 mhz output high voltage (v oh ) v s ? 0.1 v sourcing 1.0 ma current output low voltage (v ol ) 0.1 v sinking 1.0 ma current duty cycle 42 58 % timing characteristics typical (typ) is given for v s = 3.3 v 10%, t a = 25c, unless otherwise noted. minimum (min) and maximum (max) values are given over full v s and t a (?40c to +85c) variation. table 7. parameter min typ max unit test conditions/comments lvpecl termination = 200 to 0 v; c load = 0 pf output rise time, t rp 480 625 810 ps 20% to 80%, measured differentially output fall time, t fp 480 625 810 ps 80% to 20%, measured differentially lvds termination = 100 differential; c load = 0 pf output rise time, t rl 160 350 540 ps 20% to 80%, measured differentially output fall time, t fl 160 350 540 ps 80% to 20%, measured differentially cmos termination = 50 to 0 v; c load = 5 pf output rise time, t rc 0.25 0.50 2.5 ns 20% to 80% output fall time, t fc 0.25 0.70 2.5 ns 80% to 20%
AD9572 rev. 0 | page 7 of 20 control pins typical (typ) is given for v s = 3.3 v 10%, t a = 25c, unless otherwise noted. minimum (min) and maximum (max) values are given over full v s and t a (?40c to +85c) variation. table 8. parameter min typ max unit test conditions/comments input characteristics refsel pin refsel has a 30 k pull-up resistor. logic 1 voltage 2.0 v logic 0 voltage 0.8 v logic 1 current 1.0 a logic 0 current 155 a freqsel pin freqsel has a 150 k pull-up resistor and a 100 k pull-down resistor. logic 1 voltage 2/3(v s ) + 0.2 v logic 0 voltage 1/3(v s ) ? 0.2 v logic 1 current 45 a logic 0 current 30 a force_low pin force_low has a 16 k pull-down resistor. logic 1 voltage 2.0 v logic 0 voltage 0.8 v logic 1 current 240 a logic 0 current 2.0 a power typical (typ) is given for v s = 3.3 v 10%, t a = 25c, unless otherwise noted. minimum (min) and maximum (max) values are given over full v s and t a (?40c to +85c) variation. table 9. parameter min typ max unit test conditions/comments power supply 3.0 3.3 3.6 v lvds power dissipation 715 870 mw lvpecl power dissipation 1075 1305 mw crystal oscillator typical (typ) is given for v s = 3.3 v 10%, t a = 25c, unless otherwise noted. minimum (min) and maximum (max) values are given over full v s and t a (?40c to +85c) variation. table 10. parameter min typ max unit test conditions/comments crystal specification fundamental mode frequency 25 mhz esr 50 load capacitance 14 pf phase noise ?135 dbc/hz @ 1 khz offset stability ?30 +30 ppm
AD9572 rev. 0 | page 8 of 20 timing diagrams differential lvpecl 80% 20% t rp t fp 0 74 single-ended cmos 5pf load 80% 20% t rc 98-004 figure 3. lvpecl timing, differential differential lvds 80% 20% t rl t fl 0 7498-005 figure 4. lvds timing, differential t fc 0 7498-006 figure 5. cmos timing, single-ended, 5 pf load
AD9572 rev. 0 | page 9 of 20 absolute maximum ratings table 11. parameter rating vs to gnd ?0.3 v to +3.6 v refclk to gnd ?0.3 v to vs + 0.3 v bypassx to gnd ?0.3 v to vs + 0.3 v xo to gnd ?0.3 v to vs + 0.3 v freqsel, force_low, and refsel to gnd ?0.3 v to vs + 0.3 v 25m, 33m, 100m/125m, 106m, and 156m to gnd ?0.3 v to vs + 0.3 v junction temperature 1 150c storage temperature range ?65c to +150c 1 see table 12 for ja. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. thermal impedance measurements were taken on a 4-layer board in still air in accordance with eia/jesd51-7. table 12. thermal resistance package type ja unit 40-lead lfcsp 27.5 c/w esd caution
AD9572 rev. 0 | page 10 of 20 notes 1. * = short to pin 36. pin configuration and fu nction descriptions w 2 . ** = short to pin 14. 3. nc = no connect. 4 . note that the exposed paddle on this package is an electrica l connection as well as a thermal enhancement. for the device to function properly, the paddle must be attached to ground (gnd). pin 1 indicator 1 gnd 2 vs 3 nc 4 25m 5 vs 6 xo 7 xo 8 refclk 9 refsel 10 gnd 23 33m 24 vs 25 vs 26 vs 27 freqsel 28 vs 29 106m 30 106m 22 100m/125m 21 100m/125m 1 1 v s 1 2 * * 1 3 * * 1 5 v s 1 7 1 5 6 m 1 6 v s 1 8 1 5 6 m 1 9 1 0 0 m / 1 2 5 m 2 0 1 0 0 m / 1 2 5 m 1 4 b y p a s s 2 3 3 v s 3 4 g n d 3 5 v s 3 6 b y p a s s 1 3 7 f o r c e _ l o 3 8 * 3 9 v s 4 0 v s 3 2 1 0 6 m 3 1 1 0 6 m top view (not to scale) AD9572 07498-007 figure 6. pin configuration table 13. pin function descriptions 1 pin no. mnemonic description 3 nc no connect. this pin should be left floating. 2 vs power supply connection for the 25m cmos buffer. 4 25m cmos 25 mhz output. 5 vs power supply connection for the crystal oscillator. 6, 7 xo external 25 mhz crystal. 8 refclk 25 mhz reference clock input. tie low when not in use. 9 refsel logic input. used to select the reference source. 11 vs power supply connection for the gbe pll. 1, 10, 34 gnd ground. includes external paddle (epad). 14, 36 bypass2, bypass1 these pins are for bypassing each ldo to ground with a 220 nf capacitor. 15 vs power supply connection for the gbe vco. 16 vs power supply connection for the 156m lv ds output buffer and output dividers. 17 156m lvpecl/lvds output at 156.25 mhz. 18 156m complementary lvpecl/lvds output at 156.25 mhz. 19, 21 100m/125m lvpecl/lvds output at 100 mhz or 125 mhz. selected by freqsel pin strapping. 20, 22 100m / 125m complementary lvpecl/lvds output at 100 mhz or 125 mhz. 23 33m cmos 33.33 mhz output. 24 vs power supply connection for the 33m cmos output buffer and output dividers. 25 vs power supply connection for the 100m/125m lvds output buffer and output dividers. 26 vs power supply connection for the gbe pll feedback divider. 27 freqsel logic input. used to configure output drivers. 28 vs power supply connection for the fc pll feedback divider. 29, 31 106m lvpecl/lvds output at 106.25 mhz. 30, 32 106m complementary lvpecl/lvds output at 106.25 mhz.
AD9572 rev. 0 | page 11 of 20 pin no. mnemonic description 33 vs power supply connection for the 106.25 mhz lvds output buffer and output dividers. 35 vs power supply connection for the fc vco. 37 force_low forces the 33.33 mhz output into a low state. 39 vs power supply connection for the fc pll. 40 vs power supply connection for miscellaneous logic. 1 the exposed paddle on this package is an electrical connection as well as a thermal enhancement. for the device to function pr operly, the paddle must be attached to ground (gnd).
AD9572 rev. 0 | page 12 498-008 of 20 typical performance characteristics both 100 mhz and 125 mhz outputs enabled; 33.3 mhz output disabled. 07 ? 100 ?150 ?140 ?130 ?120 ?110 phase noise (dbc/hz) ? 100 ?160 ?150 ?140 ?130 ?120 ?110 1k 10k 100k 1m 100m 10m phase noise (dbc/hz) frequency (hz) ?160 1k 10k 100k 1m 100m 10m frequency (hz) 07498-011 figure 7. 106.25 mhz phase noise 07498- ? 100 ?150 ?140 ?130 ?120 ?110 phase noise (dbc/hz) 009 ?160 1k 10k 100k 1m 100m 10m frequency (hz) figure 8. 125 mhz phase noise 07498-010 ? 100 ?150 ?140 ?130 ?120 ?110 phase noise (dbc/hz) ?160 1k 10k 100k 1m 100m 10m frequency (hz) figure 9. 25 mhz phase noise figure 10. 156.25 mhz phase noise ? 100 ?160 ?150 ?140 ?130 ?120 ?110 1k 10k 100k 1m 100m 10m phase noise (dbc/hz) frequency (hz) 07498-012 figure 11. 100 mhz phase noise
AD9572 rev. 0 | page 13 of 20 terminology phase jitter an ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle. actual signals, however, display a certain amount of variation from the ideal phase progression over time. this phenomenon is called phase jitter. although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as gaussian (normal) in distribution. this phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. this power spectrum is usually reported as a series of values whose units are dbc/hz at a given offset in frequency from the sine wave (carrier). the value is a ratio (expressed in db) of the power contained within a 1 hz bandwidth with respect to the power at the carrier frequency. for each measurement, the offset from the carrier frequency is also given. phase noise when the total power contained within some interval of offset frequencies (for example, 12 khz to 20 mhz) is integrated, it is called the integrated phase noise over that frequency offset interval, and it can be readily related to the time jitter due to the phase noise within that offset frequency interval. phase noise has a detrimental effect on error rate performance by increasing eye closure at the transmitter output and reducing the jitter tolerance/sensitivity of the receiver. time jitter phase noise is a frequency domain phenomenon. in the time domain, the same effect is exhibited as time jitter. when observing a sine wave, the time of successive zero crossings is seen to vary. in a square wave, the time jitter is seen as a displacement of the edges from their ideal (regular) times of occurrence. in both cases, the variations in timing from the ideal are the time jitter. because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the gaussian distribution. additive phase noise additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. the phase noise of any external oscillators or clock sources has been subtracted. this makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. in many cases, the phase noise of one element dominates the system phase noise. additive time jitter additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. the time jitter of any external oscillator or clock source has been subtracted. this makes it possible to predict the degree to which the device will impact the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. in many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
AD9572 rev. 0 | page 14 of 20 theory of operation refsel xtal osc refclk v s vs bypass1 gnd 1 0 AD9572 divide by 5 divide by 4 divide by 5 divide by 3 33m force_low cmos 33.33mhz 0 1 1 0 125mhz/100mhz lvpecl/ lvds 100m/125m 100m/125m 100m/125m 100m/125m 125mhz/100mhz lvpecl/ lvds 25m cmos ldo phase frequency detector charge pump divide by 17 divide by 5 divide by 4 v ldo vco 106m 106m lvpecl/ lvds 106.25mhz 106m 106m ldo phase frequency detector charge pump divide by 25 divide by 4 divide by 4 v ldo vco 156m 156m 156.25mhz lvpecl/ lvds bypass2 level decode freqsel 07498-013 figure 12. detailed block diagram figure 12 shows a block diagram of the AD9572. the chip combines dual pll cores, which are configured to generate the specific clock frequencies required for networking applications, without any user programming. this pll is based on proven analog devices synthesizer technology, noted for its exceptional phase noise performance. the AD9572 is highly integrated and includes loop filters, regulators for supply noise immunity, all the necessary dividers with multiple output buffers in a choice of formats, and a crystal oscillator. a user need only supply a 25 mhz reference clock or an external crystal to implement an entire line card clocking solution that does not require any processor intervention. a copy of the 25 mhz reference source is also available. outputs table 14 provides a summary of the outputs available. table 14. output formats frequency format copies 25 mhz cmos 1 106.25 mhz lvpecl/lvds 2 156.25 mhz lvpecl/lvds 1 100 mhz or 125 mhz lvpecl/lvds 2 33.33 mhz cmos 1 note that the pins labeled 100m/125m can provide 100 mhz or 125 mhz by strapping the freqsel pin as shown in tabl e 15 .
AD9572 rev. 0 | page 15 of 20 table 15. freqsel (pin 27) definition freqsel frequency available from pin 19 and pin 20 (mhz) frequency available from pin 21 and pin 22 (mhz) 0 125 125 1 100 100 nc 125 100 3.5ma 3.5ma out outb 07498-014 figure 13. lvds output simplified equivalent circuit the simplified equivalent circuits of the lvds and lvpecl outputs are shown in figure 13 and figure 14 . 3.3 v out outb gnd 07498-015 figure 14. lvpecl output simplified equivalent circuit the differential outputs are factory programmed to either lvpecl or lvds format, and either option can e sampled on request. cmos drivers tend to generate more noise than differential outputs and, as a result, the proimity of the 33.33 mhz output to pin 21 and pin 22 does affect the itter performance when feqsel 0 (that is, when the differential output is generating 125 mhz). for this reason, the 33 mhz pin can e forced to a low state y asserting the foce_low signal on pin 37 (see tale 16 ). an internal pull-down enales the 33.33 mhz output if the pin is not connected. table 16. force_low (pin 37) definition force_low 33.33 mhz output (pin 23) 0 or nc 33.33 mhz 1 0 phase frequency detector (pfd) and charge pump the pfd takes inputs from the reference clock and feedback divider to produce an output proportional to the phase and frequency difference between them. figure 15 shows a simplified schematic. 0 7498-016 d1 q1 clr1 refclk high up d2 q2 clr2 high down cp charge pump 3.3 v gnd feedback divider figure 15. pfd simplified schematic power supply the AD9572 requires a 3.3 v 10 power supply for v s . the tables in the specifications section give the performance expected from the AD9572 with the power supply voltage within this range. the absolute maximum range of 0.3 v to 3.6 v, with respect to gnd, must never be exceeded on the vs pin. good engineering practice should be followed in the layout of power supply traces and the ground plane of the pcb. the power supply should be bypassed on the pcb with adequate capacitance (10 f). the AD9572 should be bypassed with adequate capacitors (0.1 f) at all power pins as close as possible to the part. the layout of the AD9572 evaluation board is a good example. the exposed metal paddle on the AD9572 package is an electrical connection, as well as a thermal enhancement. for the device to function properly, the paddle must be properly attached to ground (gnd). the pcb acts as a heat sink for the AD9572 therefore, this gnd connection should provide a good thermal path to a larger dissipation area, such as a ground plane on the pcb. cmos clock distribution the AD9572 provides two cmos clock outputs (one 25 mhz and one 33.33 mhz) that are dedicated cmos levels. whenever single-ended cmos clocking is used, some of the following general guidelines should be followed. point-to-point nets should be designed such that a driver has one receiver only on the net, if possible. this allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the net. series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver.
AD9572 rev. 0 | page 16 of 20 the value of the resistor is dependent on the board design and timing requirements (typically 10 to 100 is used). cmos outputs are limited in terms of the capacitive load or trace length that they can drive. typically, trace lengths less than 6 inches are recommended to preserve signal rise/fall times and signal integrity. 10 ? 60.4 microstrip gnd 5pf ? 1.0 inch cmos 0 7498-017 figure 16. series termination of cmos output termination at the far end of the pcb trace is a second option. the cmos outputs of the AD9572 do not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in figure 17 . the far-end termination network should match the pcb trace impedance and provide the desired switching point. the reduced signal swing may still meet receiver input requirements in some applications. this can be useful when driving long trace lengths on less critical nets. 50? 10? v pullup = 3.3 v cmos 5pf 100 ? 100 ? 0 7498-018 figure 17. cmos output wi th far-end termination lvpecl clock distribution the low voltage, positive emitter-coupled logic (lvpecl) outputs of the AD9572 provide the lowest jitter clock signals available from the AD9572. the lvpecl outputs (because they are open emitter) require a dc termination to bias the output transistors. the simplified equivalent circuit in figure 14 shows the lvpecl output stage. in most applications, a standard lvpecl far-end termination is recommended, as shown in figure 18 . the resistor network is designed to match the transmission line impedance (50 ) and the desired switching threshold (1.3 v). 3.3v lvpecl 50? 50? single-ended (not coupled) 3.3v 3.3 v lvpecl 127? 127? 83? 83 ? v t = v cc ? 1.3v 07498-019 figure 18. lvpecl far-end termination 3.3 v 3.3 v lvpecl differential (coupled) lvpecl 100 ? 0.1nf 0.1nf 200 ? 200? 07498-020 figure 19. lvpecl with parallel transmission line lvds clock distribution low voltage differential signaling ( lvds) is a second differential output option for the AD9572. lvds uses a current mode output stage with a factory programmed current level. the normal value (default) for this current is 3.5 ma, which yields a 350 mv output swing across a 100 resistor. the lvds outputs meet or exceed all ansi/tia/eia-644 specifications. a recommended termination circuit for the lvds outputs is shown in figure 20 . 50 ? 50 ? lvds 100 ? lvds 7498-021 0 figure 20. lvds output termination see the an-586 application note on the analog devices website at www.analog.com for more information about lvds. reference input by default, the crystal oscillator is enabled and used as the reference source, which requires the connection of an external 25 mhz crystal. the refsel pin is pulled high internally by about 30 k to support default operation. when refsel is tied low, the crystal oscillator is powered down, and the refclk pin must provide a good quality 25 mhz reference clock instead. this single-ended input can be driven by either a dc-coupled lvcmos level signal or an ac-coupled sine wave or square wave, provided that an external divider is used to bias the input at v s /2. table 17. refsel (pin 9) definition refsel reference source 0 refclk input 1 internal crystal oscillator power and grounding considerations and power supply rejection many applications seek high speed and performance under less than ideal operating conditions. in these application circuits, the implementation and construction of the pcb is as important as the circuit design. proper rf techniques must be used for device selection, placement, and routing, as well as for power supply bypassing and grounding to ensure optimum performance.
AD9572 rev. 0 | page 17 of 20 outline dimensions 072709-a 0.50 bsc bottom view top view pin 1 indicator exposed pad p i n 1 i n d i c a t o r seating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 6.10 6.00 sq 5.90 0.80 0.75 0.70 forproperconnectionof the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.40 0.35 0.25 min * 4.80 4.70 sq 4.50 compliant to jedec standards mo-220-wjjd-5 with exception to exposed pad dimension. 40 1 11 20 21 30 31 10 figure 21. 40-lead lead frame chip scale package [lfcsp_wq] 6 mm 6 mm body, very very thin quad (cp-40-7) dimensions shown in millimeters ordering guide model temperature range packag e description package option AD9572acpzlvd 1, 2 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_wq] cp-40-7 AD9572acpzlvd-rl 1, 2 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_wq], 7 tape reel, 2,500 pieces cp-40-7 AD9572acpzlvd-r7 1, 2 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_wq], 7 tape reel, 750 pieces cp-40-7 AD9572acpzpec 1, 3 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_wq] cp-40-7 AD9572acpzpec-rl 1, 3 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_wq], 7 tape reel, 2,500 pieces cp-40-7 AD9572acpzpec-r7 1, 3 ?40c to +85c 40-lead lead frame chip scale package [lfcsp_wq], 7 tape reel, 750 pieces cp-40-7 AD9572-evalz-lvd 1, 2 evaluation board AD9572-evalz-pec 1, 3 evaluation board 1 z = rohs compliant part. 2 lvd indicates lvds compliant, differential clock outputs. 3 pec indicates lvpecl compliant, differential clock outputs.
AD9572 rev. 0 | page 18 of 20 notes
AD9572 rev. 0 | page 19 of 20 notes
AD9572 rev. 0 | page 20 of 20 notes ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07498-0-7/09(0)

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