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CY2DM1502 1:2 cml / lvpecl input to cml output fanout buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-56315 rev. *f revised february 25, 2011 features one current mode logic (cml) or low-voltage positive emitter-coupled logic (lvpecl) input pair distributed to two cml output pairs 20-ps maximum output-to-output skew 480-ps maximum propagation delay 0.15-ps maximum additive rms phase jitter at 156.25 mhz (12-khz to 20-mhz offset) up to 1.5 ghz operation 8-pin thin shrunk small outline package (tssop) package 2.5-v or 3.3-v operating voltage [1] commercial and industrial operating temperature range functional description the CY2DM1502 is an ultra-low noise, low-skew, low-propagation delay 1:2 cml or lvpecl to cml fanout buffer targeted to meet the requirements of high-speed clock distribution applications. the device has a fully differential internal architecture that is optim ized to achieve low additive jitter and low skew at operating frequen cies of up to 1.5 ghz. note 1. input ac-coupling capacitors are required for voltage-translation applications. logic block diagram q0 q0# q1 q1# in in# v dd v ss v dd [+] feedback
CY2DM1502 document number: 001-56315 rev. *f page 2 of 12 contents pinouts .............................................................................. 3 absolute maximum ratings ............................................ 3 operating conditions....................................................... 3 dc electrical specifications ............................................ 4 ac electrical specifications ............................................ 5 ordering information........................................................ 8 ordering code definition............................................. 8 package dimension.......................................................... 9 acronyms ........................................................................ 10 document conventions ................................................. 10 document history page ................................................. 11 sales, solutions, and legal information ...................... 12 worldwide sales and design supp ort............. .......... 12 products .................................................................... 12 psoc solutions ......................................................... 12 [+] feedback
CY2DM1502 document number: 001-56315 rev. *f page 3 of 12 pinouts figure 1. pin diagra m ? 8-pin tssop package 1 2 3 45 6 7 8 CY2DM1502 q0 q0# q1 q1# v dd in in# v ss table 1. pin definitions pin no. pin name pin type description 1,3 q(0:1) output cml output clocks 2,4 q(0:1)# output cml complementary output clocks 5v ss power ground 6 in# input cml/lvpecl complementary input clock 7 in input cml/lvpecl input clock 8v dd power power supply absolute maximum ratings parameter description condition min max unit v dd supply voltage nonfunctional ?0.5 4.6 v v in [2] input voltage, relative to v ss nonfunctional ?0.5 lesser of 4.0 or v dd + 0.4 v v out [2] dc output or i/o voltage, relative to v ss nonfunctional ?0.5 lesser of 4.0 or v dd + 0.4 v t s storage temperature nonfunctional ?55 150 c esd hbm electrostatic discharge (esd) protection (human body model) jedec std 22-a114-b 2000 ? v l u latch up meets or exceeds jedec spec jesd78b ic latchup test ul?94 flammability rating at 1/8 in v-0 msl moisture sensitivity level 3 operating conditions parameter description condition min max unit v dd supply voltage 2.5-v supply 2.375 2.625 v 3.3-v supply 3.135 3.465 v t a ambient operating temperature commercial 0 70 c industrial ?40 85 c t pu power ramp time power-up time for v dd to reach minimum specified voltage (power ramp must be monotonic). 0.05 500 ms note 2. the voltage on any i/o pin cannot exceed the power pin during power up. power supply sequencing is not required. [+] feedback
CY2DM1502 document number: 001-56315 rev. *f page 4 of 12 dc electrical specifications (v dd = 3.3 v 5% or 2.5 v 5%; t a = 0 c to 70 c (commercial) or ?40 c to 85 c (industrial)) parameter description condition min max unit i dd operating supply current all cm l outputs floating (internal i dd )?50ma v ih input high voltage, cml / lvpecl inputs in and in# ?v dd + 0.3 v v il input low voltage, cml / lvpecl inputs in and in# ?0.3 ? v v id [3] input differential amplitude see figure 2 on page 6 0.4 1.0 v v icm input common mode voltage see figure 2 on page 6 0.5 v dd ? 0.2 v i ih input high current, cml / lvpecl inputs in and in# input = v dd [4] ? 150 a i il input low current, cml / lvpecl inputs in and in# input = v ss [4] ?150 ? a v oh cml output high voltage terminated with 50 to v dd [5] v dd ? 0.1 ? v v ol cml output low voltage terminated with 50 to v dd [5] v dd ? 0.7 v dd ? 0.3 v c in input capacitance measured at 10 mhz; per pin ? 3 pf notes 3. v id minimum of 400 mv is required to meet all output ac electrical specifications. th e device is functional with v id minimum of greater than 200 mv. 4. positive current flows into the input pin, negative current flows out of the input pin. 5. refer to figure 3 on page 6. [+] feedback
CY2DM1502 document number: 001-56315 rev. *f page 5 of 12 ac electrical specifications (v dd = 3.3 v 5% or 2.5 v 5%; t a = 0 c to 70 c (commercial) or ?40 c to 85 c (industrial)) parameter description condition min typ max unit f in input frequency dc ? 1.5 ghz f out output frequency f out = f in dc ? 1.5 ghz v pp cml differential output voltage peak-to-peak, single-ended. terminated with 50 to v dd [5] fout = dc to 150 mhz 250 ? 700 mv fout = >150 mhz to 1.5 ghz 250 ? 600 mv t pd [6] propagation delay input pair to output pair input rise/fall time < 1.5 ns (20% to 80%) ??480ps t odc [7] output duty cycle 50% duty cycle at input frequency range up to 1 ghz 48?52% t sk1 [8] output-to-output skew any ou tput to any output, with same load conditions at dut ??20ps t sk1 d [8] device-to-device output skew any output to any output between two or more devices. devices must have the same input and have the same output load. ??150ps pn add additive rms phase noise 156.25-mhz input rise/fall time < 150 ps (20% to 80%) v id > 400 mv offset = 1 khz ? ? ?120 dbc/hz offset = 10 khz ? ? ?130 dbc/hz offset = 100 khz ? ? ?135 dbc/hz offset = 1 mhz ? ? ?145 dbc/hz offset = 10 mhz ? ? ?153 dbc/hz offset = 20 mhz ? ? ?155 dbc/hz t jit [9] additive rms phase jitter (random) 156.25 mhz, 12 khz to 20 mhz offset; input rise/fall time < 150 ps (20% to 80%), v id > 400 mv ??0.15ps t r , t f [10] output rise/fall time 50% duty cycle at input, 20% to 80% of full swing (v ol to v oh ) input rise/fall time < 1.5 ns (20% to 80%) measured at 1 ghz ??250ps notes 6. refer to figure 4 on page 6. 7. refer to figure 5 on page 6. 8. refer to figure 6 on page 7. 9. refer to figure 7 on page 7. 10. refer to figure 8 on page 7. [+] feedback
CY2DM1502 document number: 001-56315 rev. *f page 6 of 12 figure 2. input differential and common mode voltages figure 3. output differential voltage figure 4. input to any output pair propagation delay figure 5. output duty cycle in v a v b in# v icm = (v a + v b )/2 v id q v oh v ol q# v pp in# in t pd q x # q x t pw t odc = t pw t period t period q x # q x [+] feedback
CY2DM1502 document number: 001-56315 rev. *f page 7 of 12 figure 6. output-to-outpu t and device-t o-device skew figure 7. rms phase jitter figure 8. output rise/fall time q x # q x q y # q y q z # q z t sk1 t sk1 d device 1 device 2 phase noise phase noise mark offset frequency f1 f2 a rea under the masked phase noise plot noise powe r rms jitter [+] feedback
CY2DM1502 document number: 001-56315 rev. *f page 8 of 12 ordering information ordering code definition part number type production flow pb-free CY2DM1502zxc 8-pin tssop commercial, 0 c to 70 c CY2DM1502zxct 8-pin tssop tape and reel commercial, 0 c to 70 c CY2DM1502zxi 8-pin tssop industrial, ?40 c to 85 c CY2DM1502zxit 8-pin tssop tape and reel industrial, ?40 c to 85 c cy base part number 2dm15 02 number of differential output pairs company id: cy = cypress zx pb-free tssop package temperature range c = commercial i = industrial c/i t tape and reel [+] feedback
CY2DM1502 document number: 001-56315 rev. *f page 9 of 12 package dimension figure 9. 8-pin thin shrunk small outline package (4.40 mm body) z8 51-85093 *c [+] feedback
CY2DM1502 document number: 001-56315 rev. *f page 10 of 12 acronyms document conventions table 2. acronyms used in this document acronym description cml current mode logic esd electrostatic discharge hbm human body model jedec joint electron devices engineering council lvds low-voltage differential signal lvcmos low-voltage complementary metal oxide semiconductor lvpecl low-voltage positive emitter-coupled logic lvttl low-voltage transistor-transistor logic oe output enable rms root mean square tssop thin shrunk small outline package table 3. units of measure symbol unit of measure c degree celsius dbc decibels relati ve to the carrier ghz giga hertz hz hertz k kilo ohm a microamperes f micro farad s microsecond ma milliamperes ms millisecond mv millivolt mhz megahertz ns nanosecond ohm pf pico farad ps pico second vvolts wwatts [+] feedback
CY2DM1502 document number: 001-56315 rev. *f page 11 of 12 document history page document title: CY2DM1502 1:2 cml / l vpecl input to cml ou tput fanout buffer document number: 001-56315 revision ecn orig. of change submission date description of change ** 2782891 cxq 10/09/09 new datasheet. *a 2838916 cxq 01/05/2010 changed status from ?advance? to ?preliminary?. changed from 0.34 ps to 0.25 ps maximum additive jitter in ?features? on page 1 and in t jit in the ac electrical specs table on page 4. added t pu spec to the operating conditions table on page 2. removed v oh spec maximum of v dd in the dc electrical specs table on page 3. changed v ol spec min from v dd - 0.6v to v dd - 0.7v; changed max from v dd - 0.4v to v dd - 0.3v in the dc electrical specs table on page 3. removed v od spec of minimum 300 mv, maximum 450 mv in the dc electrical specs table on page 3. added r p spec in the dc electrical specs table on page 3. min = 60 k , max = 140 k . added a measurement definition for c in in the dc electrical specs table on page 3. added v pp spec to the ac electrical specs table on page 4. v pp max = 700 mv for dc - 150 mhz and max = 600 mv for 150 mhz to 1.5 ghz. v pp min = 250 mv over the entire range. changed letter case and some names of all the timing parameters in the ac electrical specs table on page 4 to be consis tent with eros. lowered all additive phase noise mask specs by 3 db in in the ac electrical specs table on page 4. added condition to t r and t f specs in the ac electrical specs table on page 4 that input rise/fall time must be less than 1.5 ns (20% to 80%). changed letter case and some names of all the timing parameters in figures 3, 4, 5, 6 and 8, to be consistent with eros. *b 3011766 cxq 08/20/2010 changed from 0. 25 ps to 0.11 ps maximum additive jitter in ?features? on page 1 and in t jit in the ac electrical specs table. added note 3 to describe i ih and i il specs. removed reference to data distribution from ?functional description?. changed r p for diff inputs from 100 k to 150 k in the logic block diagram and from 60 k min / 140 k max to 90 k min / 210 k max in the dc electrical specs table. added max v id of 1.0v in dc electrical specs table. updated phase noise specs for 1 k/10 k/100 k/1 m/10 m/20 mhz offset to -120/-130/-135/-150/- 150/-150dbc/hz, respectively, in the ac electrical specs table. added ?frequency range up to 1 ghz? condition to t odc spec. updated package diagram. added acronyms and ordering code definition. *c 3017258 cxq 08/27/2010 corrected outp ut rise/fall time diagram. *d 3100234 cxq 11/18/2010 updated phase jitter to 0.15ps max from 0.11ps max. changed v in and v out specs from 4.0v to ?lesser of 4.0 or v dd + 0.4? removed 200ma min lu spec, replaced wi th ?meets or exceeds jedec spec jesd78b ic latchup test? removed r p spec for differential input clock pins in x and in x #. changed c in condition to ?measured at 10 mhz?. changed pn add specs for 1mhz, 10mhz, and 20mhz offsets. added condition ?measured at 1 ghz? to t r , t f specs. *e 3137726 cxq 01/13/2011 removed ?preliminary? status heading. removed resistors from in/in# in logic block diagram . *f 3090938 cxq 02/25/2011 post to external web. [+] feedback
document number: 001-56315 rev. *f revised february 25, 2011 page 12 of 12 all products and company names mentioned in this document may be the trademarks of their respective holders. CY2DM1502 ? cypress semiconductor corporation, 2009-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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