unisonic technologies co., ltd m7085 cmos ic www.unisonic.com.tw 1 of 7 copyright ? 2012 unisonic technologies co., ltd qw-r502-092, ba pfm step-down dc-dc controller ? description the utc m7085 step-down dc-dc controller is optimized for use with a power pmosfet. it utilize a pulse-frequency modulation (pfm) control scheme that implies high efficiency operation at light loads. there are two user-selectable over-current protection methods one provides over-current protec tion by taking advantage of the r ds(on) of the p- channel. the other pr ovides accurate over-current protection with the use of an external sense resistor. the cycle-by-cycle current limit threshold can be adjusted with a external resistor. ? features * high efficiency 90% and up is possible * low dropout operation 100% duty cycle * maximum operating frequency > 1mhz * two methods of over-current protection * 4.5v ~ 35v wide input range * 1.24v ~ v in adjustable output range ? ordering information ordering number package packing lead free halogen free m7085l-sm1-r M7085G-SM1-R msop-8 tape reel m7085l-sm1-t m7085g-sm1-t msop-8 tube
m7085 cmos ic unisonic technologies co., ltd 2 of 7 www.unisonic.com.tw qw-r502-092, ba ? pin configuration sgnd i sense nc fb adj pgnd pgate v in 1 2 3 4 6 7 8 5 ? pin description pin no pin name description 1 i sense the over-current protection i nput pin that be connected to drain node of the external p-channel. 2 s gnd signal ground. 3 nc no connection. 4 fb the feedback voltage input. 5 adj the over-current protection input pin that adjust current limit threshold. 6 p gnd power ground. 7 gate driver pin to gate of the external p-channel. pgate swings between v in and v in -5v. 8 v in power supply ? block diagram
m7085 cmos ic unisonic technologies co., ltd 3 of 7 www.unisonic.com.tw qw-r502-092, ba ? absolute maximum rating parameter symbol ratings unit input voltage v in -0.3 ~ 36 v p gate voltage v pgate -0.3 ~ 36 v fb voltage v fb -0.3 ~ 5 v i sense voltage v isns -1.0 ~ 36 v adj voltage v adj -0.3 ~ 36 v power dissipation (t a =25 ) p d 400 mw junction temperature t j 150 storage temperature t stg -65 ~ +150 note: absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? operating ratings parameter symbol ratings unit supply voltage 4.5 ~ 35 v operating junction temperature t opr -40 ~ +125 ? electrical characteristics v in = 12v, v isns = v in ? 1v, and v adj = v in ? 1.1v, ta=25 parameter symbol test conditions min typ max unit feedback voltage (note 1) v fb 1.224 1.240 1.256 v 1.215 1.265 minimum driver voltage v pgate(min) v in = 4.5v v fb = 1.0v i gate = 100 a sink 1.15 v comparator hysteresis v hys 10 16 mv 15 21 current limit comparator trip voltage v cl (note2) r adj = 20 ? 110 mv r adj = 160 ? 880 current limit comparator offset v cl ( off ) v fb = 1.5v -20 0 +20 mv current limit adj current source i cl ( adj ) v fb = 1.5v 3.0 5 7.0 a fb pin bias current (note 3) i fb v fb = 1.0v 320 756 na driver output current source i pgate v in = 7v, p gate = 3.5v 0.4 a sink v in = 7v, p gate = 3.5v 0.3 driver resistance source r pgate i source = 100ma 5 ? sink i sink = 100ma 8 current limit one shot off time t cl v adj = 11.5v, v isns = 11.0v, v fb = 1.0v 5 8 13 s minimum on time in normal operation t opr(min) v isns = v adj +0.1v, c load on out = 1000pf, (note 4) 110 ns minimum on time in current limit t cl(min) v isns = v adj +0.1v, v fb = 1.0v c load on out=1000pf (note 4) 185 ns feedback voltage line regulation %v fb /v in 4.5 v in 35v 0.010 %/v quiescent current at ground pin i q fb = 1.5v (not switching) 300 500 a note: 1. the v fb is the trip voltage at the fb pin wh en pgate switches from high to low. 2. v cl = i cl_adj * r adj 3. bias current flows out from the fb pin. 4. a 1000pf capacitor is connected between v in and p gate .
m7085 cmos ic unisonic technologies co., ltd 4 of 7 www.unisonic.com.tw qw-r502-092, ba ? typical application circuit utc m7085 adj i sense p gate v in fb 5 r adj c adj c in 22f v in 4.5v ~ 35v 2.6 6 7 1 4 c out 100uf v out 3.3v d1 r1 33k r2 20k l1 22h q1
m7085 cmos ic unisonic technologies co., ltd 5 of 7 www.unisonic.com.tw qw-r502-092, ba ? application information setting the output voltage select an output voltage between 1.24v and v in by connecting fb to a resistive voltage-divider between v out and gnd (see the typical operating circuit). choose r2 for a reasonable bias current in the resistive divider. a wide range of resistor values is acceptable. r1, r2 is given by: v out = 1.240* (r1 + r2) / r2 setting over current protection threshold by the r ds(on) of the p-channel the utc m7085 has a cycle-by-cycle current limit. current limit is sensed across the v ds of the p-channel or across an additional sense resistor. when current limit is activated, the utc m7085 turns off the external p-channel for a period of 9 s(typical). the current limit is adjusted by an external resistor, r adj . the current limit circuit is composed of the i sense comparator and the one-shot puls e generator. the positive input of the i sense comparator is the adj pin. an internal 5.5a cu rrent sink creates a volt age across the external r adj resistor. this voltage is compared to the voltage across the p-channel or sense resistor. the adj voltage can be calculated as follows: v adj = v in - (r adj * 3.0 a) where 3.0 a is the minimum i cl(adj) value. the negative input of the i sense comparator is the i sense pin that should be connected to the drain of the external p-channel. the inductor current is determined by sensing the v ds . it can be calculated as follows. v isense = v in - (r ds(on) * i ind_peak ) = v in - v ds i sense comp 5.5a adj c adj r adj i sense v ds v in fig. 1 current sensing by v ds 5 1 the current limit is activated when the voltage at the adj pin exceeds the voltage at the i sense pin. the i sense comparator triggers the 9 s one shot pulse generat or forcing the driver to turn th e p-channel off. the driver turns the p-channel back on after 9 s. if the current has not reduced below the set threshold, the cycle will repeat continuously. a filter capacitor, c adj , should be placed as shown in fig. 1 c adj filters unwanted noi se so that the i sense comparator will not be accidentally trig gered. a value of 100pf to 1nf is recommended in most applications. higher values can be used to create a soft-star t function. the current limit comparat or has approximately 100ns of blanking time. this ensures that the p-channe l is fully on when the current is s ensed. however, under extreme conditions such as cold temperature, some p-channels may not fully tu rn on within the blanking time . in this case, the current limit threshold must be increased. if the current limit function is used, the on time must be greater than 100ns. under low duty cycle operation, the maximum operating frequency will be limited by this minimum on time.
m7085 cmos ic unisonic technologies co., ltd 6 of 7 www.unisonic.com.tw qw-r502-092, ba ? application information(cont.) setting over current protection threshold by external sense resistor the v ds of a p-channel will tend to vary significantly over tem perature. this will result an equivalent variation in current limit. to improve current limit accuracy an external sense resistor can be connected from v in to the source of the p-channel, as shown in fig . 2. setting start up time the current limit circuit is active durin g start-up. during start-up the p-channel will stay on until either the current limit or the feedback comparator is tripped if the current limit comparator is tripped first then the fold back characteristic should be taken into account. start-up into fu ll load may require a higher cu rrent limit set point or the load must be applied after start-up. one problem with selecting a higher current limit is inrush current durin g start-up. increasi ng the capacitance(c adj ) in parallel with r adj results in soft-start. c adj and r adj create an rc time constant forcing current limit to activate at a lower current. the output voltage will ramp more slowly when using the soft-start func tionality. there are example start-up plots for c adj equal to 1nf and 10nf in the typical performance characteristics. lower values for c adj will have little to no effect on soft-start. inductor selection (l1) utc m7085 operates over a wide frequency range and can use a wide range of inductance values. the inductance value and the resulting ripple is one of the ke y parameters controlling operating frequency. the second is the esr. output capacitor selection (c out ) the output capacitor, c out , is required to keep the output voltage ri pple small and to ensure regulation loop stability. c out must have low impedance at the switching frequenc y. for most applications, a 200mf capacitor is sufficient. input capacitor selection (c in ) the input capacitor, c in , reduces the current peaks drawn and redu ces switching noise in the ic. a bypass capacitor is required between the input source and ground. it must be located near the source pin of the external p-channel. the input capacitor prevents large voltage transi ents at the input and provides the instantaneous current when the p-channel turns on. the capacitance value should be selected such that the ripple voltage created by the charge and discharge of the capacitance is less t han 10% of the total ripple across the capacitor. catch diode selection (d1) the important parameters for the catc h diode are the peak current, the peak reverse voltage, and the average power dissipation. for high temperature applications, di ode leakage current may become significant and require a higher reverse voltage rating to achieve acceptable performance.
m7085 cmos ic unisonic technologies co., ltd 7 of 7 www.unisonic.com.tw qw-r502-092, ba ? application information(cont.) p-channel mosfet selection(q1) an external p-channel power mosfet must be used the utc m7085 key selection criteria for the power for the p-channel are the maximum drain-source voltage (v ds ) mosfet are the gate threshold, v gs , the ?on? resistance, r ds(on) and its total gate charge. the voltage across the pfet when it is turned off is equal to the sum of the input voltage and the diode forward voltage. the v ds must be selected to provide some margin beyond the input voltage. r ds(on) determines the conduction losses for each switching cy cle, the lower the on resistance, the higher the efficiency can be chivied. a power mosfet with lower gate charge can give lowe r switching losses but the fast transient can cause unwanted emi to the system. compromise in between is required during the design stage. keeping the gate capacitance below 2000pf is recommended. utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
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