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vishay siliconix si4511dy document number: 72223 s09-0867-rev. e, 18-may-09 www.vishay.com 1 n- and p-channel 20-v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 definition ? trenchfet ? power mosfet ? compliant to rohs directive 2002/95/ec applications ? level shift ? load switch product summary v ds (v) r ds(on) ( )i d (a) n-channel 20 0.0145 at v gs = 10 v 9.6 0.017 at v gs = 4.5 v 8.6 p-channel - 20 0.033 at v gs = - 4.5 v - 6.2 0.050 at v gs = - 2.5 v - 5 s 1 d 1 g 1 d 1 s 2 d 2 g 2 d 2 so-8 5 6 7 8 top v ie w 2 3 4 1 orderin g information: si4511dy -t1-e3 (lead (p b )-free) si4511dy -t1-ge3 (lead (p b )-free and halogen-free) s 2 g 2 g 1 s 1 d 2 d 1 notes: a. surface mounted on 1" x 1" fr4 board. b. t 10 s. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol n-channel p-channel unit 10 s steady state 10 s steady state drain-source voltage v ds 20 - 20 v gate-source voltage v gs 16 12 continuous drain current (t j = 150 c) a, b t a = 25 c i d 9.6 7.2 - 6.2 - 4.6 a t a = 70 c 7.7 5.8 - 4.9 - 3.7 pulsed drain current i dm 40 - 40 continuous source current (diode conduction) a i s 1.7 0.9 - 1.7 - 0.9 maximum power dissipation a t a = 25 c p d 2 1.1 2 1.1 w t a = 70 c 1.3 0.7 1.3 0.7 operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol n-channel p-channel unit typ. max. typ. max. maximum junction-to-ambient a t 10 s r thja 50 62.5 50 62.5 c/w steady state 85 110 90 110 maximum junction-to-foot (drain) steady state r thjf 30 40 30 35
www.vishay.com 2 document number: 72223 s09-0867-rev. e, 18-may-09 vishay siliconix si4511dy notes: a. guaranteed by design, not s ubject to production testing. b. pulse test; pulse width 300 s, duty cycle 2 %. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 a n-ch 0.6 1.8 v v ds = v gs , i d = - 250 a p-ch - 0.6 - 1.4 gate-body leakage i gss v ds = 0 v, v gs = 16 v n-ch 100 na v ds = 0 v, v gs = 12 v p-ch 100 zero gate voltage drain current i dss v ds = 20 v, v gs = 0 v n-ch 1 a v ds = - 20 v, v gs = 0 v p-ch - 1 v ds = 20 v, v gs = 0 v, t j = 55 c n-ch 5 v ds = - 20 v, v gs = 0 v, t j = 55 c p-ch - 5 on-state drain current b i d(on) v ds = 5 v, v gs = 10 v n-ch 40 a v ds = - 5 v, v gs = - 4.5 v p-ch - 40 drain-source on-state resistance b r ds(on) v gs = 10 v, i d = 9.6 a n-ch 0.0115 0.0145 v gs = - 4.5 v, i d = - 6.2 a p-ch 0.022 0.033 v gs = 4.5 v, i d = 8.6 a n-ch 0.0135 0.017 v gs = - 2.5 v, i d = - 5 a p-ch 0.035 0.050 forward transconductance b g fs v ds = 15 v, i d = 9.6 a n-ch 33 s v ds = - 15 v, i d = - 6.2 a p-ch 17 diode forward voltag b v sd i s = 1.7 a, v gs = 0 v n-ch 0.8 1.2 v i s = - 1.7 a, v gs = 0 v p-ch - 0.8 - 1.2 dynamic a total gate charge q g n-channel v ds = 10 v, v gs = 4.5 v, i d = 9.6 a p-channel v ds = - 10 v, v gs = - 4.5 v, i d = - 6.2 a n-ch 11.5 18 nc p-ch 17 20 gate-source charge q gs n-ch 3.7 p-ch 4.1 gate-drain charge q gd n-ch 3.3 p-ch 4.3 tu r n - o n d e l ay t i m e t d(on) n-channel v dd = 10 v, r l = 10 i d ? 1 a, v gen = 10 v, r g = 6 p-channel v dd = - 10 v, r l = 10 i d ? - 1 a, v gen = - 4.5 v, r g = 6 n-ch 12 20 ns p-ch 25 40 rise time t r n-ch 12 20 p-ch 30 45 turn-off delay time t d(off) n-ch 55 85 p-ch 70 105 fall time t f n-ch 15 25 p-ch 50 75 source-drain reverse recovery time t rr i f = 1.7 a, di/dt = 100 a/s n-ch 50 100 i f = - 1.7 a, di/dt = 100 a/s p-ch 40 80
document number: 72223 s09-0867-rev. e, 18-may-09 www.vishay.com 3 vishay siliconix si4511dy n-channel typical characteristics 25 c, unless otherwise noted output characteristics on-resistance vs. drain current gate charge 0 8 16 24 32 40 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 v ds - drain-to-so u rce v oltage ( v ) -) a ( t n e r r u c n i a r d i d v gs = 10 v thr u 4 v 2 v 3 v - ( e c n a t s i s e r - n o 0.000 0.005 0.010 0.015 0 . 020 0 8 16 24 32 40 r ds(on) ) i d - drain c u rrent (a) v gs = 10 v v gs = 4.5 v 0 2 4 6 8 10 036912151 8 21 24 - ) v ( e g a t l o v e c r u o s - o t - e t a g q g - total gate charge (nc) v s g v ds = 10 v i d = 9.6 a transfer characteristics capacitance on-resistance vs. junction temperature 0 8 16 24 32 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v gs - gate-to-so u rce v oltage ( v ) -) a ( t n e r r u c n i a r d i d 25 c t c = 125 c - 55 c 0 400 8 00 1200 1600 2000 04 8 12 16 20 v ds - drain-to-so u rce v oltage ( v ) c- ) f p ( e c n a t i c a p a c c rss c oss c iss 0.6 0. 8 1.0 1.2 1.4 1 . 6 - 50 - 25 0 25 50 75 100 125 150 t j - j u nction temperat u re ( v gs = 10 v i d = 9.6 a r ) n o ( s d - sistance e r - n o ) d e z i l a m r o n ( c)
www.vishay.com 4 document number: 72223 s09-0867-rev. e, 18-may-09 vishay siliconix si4511dy n-channel typical characteristics 25 c, unless otherwise noted source-drain diode forward voltage threshold voltage 1.0 1.2 1 10 40 0.00 0.2 0.4 0.6 0. 8 t j = 25 c t j = 150 c v sd - s o u rce-to-drain v oltage ( v ) -) a ( t n e r r u c e c r u o s i s - 0. 8 - 0.6 - 0.4 - 0.2 0.0 0.2 0.4 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a ) v ( e c n a i r a v v ) h t ( s g t j - temperat u re (c) on-resistance vs. gate-to-source voltage single pulse power v gs - gate-to-so u rce v oltage ( v ) 0.00 0.01 0.02 0.03 0.04 0 . 0 5 012345 i d = 9.6 a -( e c n a t s i s e r - n o r ) n o ( s d ) i d = 3 a 0 20 30 10 15 ) w ( r e w o p time (s) 25 1 100 600 10 10 -1 10 -2 5 safe operating area 100 1 0.1 1 10 100 0.01 10 t c = 25 c single p u lse p(t) = 10 dc 0.1 i dm limited i d(on) limited b v dss limited p(t) = 1 p(t) = 0.1 p(t) = 0.01 limited b y r ds(on) * v ds - drain-to-so u rce v oltage ( v ) * v ds > minim u m v gs at w hich r ds(on) is specified i d - drain c u rrent (a) p(t) = 0.0001 p(t) = 0.001
document number: 72223 s09-0867-rev. e, 18-may-09 www.vishay.com 5 vishay siliconix si4511dy n-channel typical characteristics 25 c, unless otherwise noted normalized thermal transient impedance, junction-to-ambient 10 -3 10 -2 1 10 600 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) e v i t c e f f e d e z i l a m r o n t n e i s n a r t e c n a d e p m i l a m r e h t 1. d u ty cycle, d = 2. per unit base = r thja = 8 5 c 3. t jm ? t a = p dm z thja (t) t 1 t 2 t 1 t 2 n otes: 4. s u rface mo u nted p dm normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 1 10 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) e v i t c e f f e d e z i l a m r o n t n e i s n a r t e c n a d e p m i l a m r e h t
www.vishay.com 6 document number: 72223 s09-0867-rev. e, 18-may-09 vishay siliconix si4511dy p-channel typical characteristics 25 c, unless otherwise noted output characteristics on-resistance vs. drain current gate charge 0 8 16 24 32 40 0.0 0.4 0. 8 1.2 1.6 2.0 v gs = 5 v thr u 3.5 v v ds - drain-to-so u rce v oltage ( v ) -) a ( t n e r r u c n i a r d i d 2.5 v 2 v 3 v 1.5 v -( ) e c n a t s i s e r - n o r ) n o ( s d 0.00 0.02 0.04 0.06 0.0 8 0 . 10 0 8 16 24 32 40 i d - drain c u rrent (a) v gs = 4.5 v v gs = 2.5 v 0 1 2 3 4 5 0 3 6 9 12 15 1 8 v ds = 10 v i d = 6.2 a -) v ( e g a t l o v e c r u o s - o t - e t a g q g - total gate charge (nc) v s g transfer characteristics capacitance on-resistance vs. junction temperature 0 8 16 24 32 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 t c = - 55 c 125 c 25 c v gs - gate-to-so u rce v oltage ( v ) -) a ( t n e r r u c n i a r d i d 0 500 1000 1500 2000 2500 3000 04 8 12 16 20 v ds - drain-to-so u rce v oltage ( v ) c rss c oss c iss c- ) f p ( e c n a t i c a p a c 0.6 0. 8 1.0 1.2 1.4 1 . 6 - 50 - 25 0 25 50 75 100 125 150 v gs = 4.5 v i d = 6.2 a t j - j u nction temperat u re (c) ) d e z i l a m r o n ( - e c n a t s i s e r - n o r ) n o ( s d
document number: 72223 s09-0867-rev. e, 18-may-09 www.vishay.com 7 vishay siliconix si4511dy p-channel typical characteristics 25 c, unless otherwise noted source-drain diode forward voltage threshold voltage 0.0 0.3 0.6 0.9 1.2 1. 5 40 10 1 v sd - -) a ( t n e r r u c e c r u o s i s t j = 150 c t j = 25 c so u rce-to-drain v oltage ( v ) - 0.4 - 0.2 0.0 0.2 0.4 0.6 - 50 - 25 0 25 50 75 100 125 150 t j - temperat u re (c) i d = 250 a ) v ( e c n a i r a v v gs(th) on-resistance vs. gate-to-source voltage single pulse power 0.00 0.02 0.04 0.06 0.0 8 0 . 10 012345 i d = 6.2 a - ( e c n a t s i s e r - n o r ) n o ( s d gs - gate-to-so u rce v oltage ( v ) ) v 0 15 30 5 10 ) w ( r e w o p time (s) 25 1 100 600 10 10 -1 10 -2 20 safe operating area 100 1 0.1 1 10 100 0.01 10 t c = 25 c single p u lse p(t) = 10 dc 0.1 i dm limited i d(on) limited b v dss limited p(t) = 1 p(t) = 0.1 limited b y r ds(on) * v ds - drain-to-so u rce v oltage ( v ) * v ds > minim u m v gs at w hich r ds(on) is specified i d - drain c u rrent (a) p(t) = 0.01 p(t) = 0.001
www.vishay.com 8 document number: 72223 s09-0867-rev. e, 18-may-09 vishay siliconix si4511dy p-channel typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72223 . normalized thermal transient im pedance, junction-to-ambient 10 -3 10 -2 1 10 600 10 -1 10 -4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single p u lse d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) e v i t c e f f e d e z i l a m r o n t n e i s n a r t e c n a d e p m i l a m r e h t 1. d u ty cycle, d = 2. per unit base = r thja = 8 5 c 3. t jm ? t a = p dm z thja (t) t 1 t 2 t 1 t 2 n otes: 4. s u rface mo u nted p dm normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 1 10 10 -1 10 -4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 d u ty cycle = 0.5 sq u are w a v e p u lse d u ration (s) e v i t c e f f e d e z i l a m r o n t n e i s n a r t e c n a d e p m i l a m r e h t single p u lse
vishay siliconix package information document number: 71192 11-sep-06 www.vishay.com 1 dim millimeters inches min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.35 0.51 0.014 0.020 c 0.19 0.25 0.0075 0.010 d 4.80 5.00 0.189 0.196 e 3.80 4.00 0.150 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.50 0.93 0.020 0.037 q0808 s 0.44 0.64 0.018 0.026 ecn: c-06527-rev. i, 11-sep-06 dwg: 5498 4 3 1 2 5 6 8 7 h e h x 45 c all le a d s q 0.101 mm 0.004" l ba 1 a e d 0.25 mm (g a ge pl a ne) s oic (narrow): 8-lead jedec p a rt n u m b er: m s -012 s
vishay siliconix trenchfet ? power mosfets application note 808 mounting little foot ? , so-8 power mosfets application note document number: 70740 www.vishay.com revision: 18-jun-07 1 wharton mcdaniel surface-mounted little foot power mosfets use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. leadframe materials and design, molding compounds, and die attach materials have been changed, while the footpr int of the packages remains the same. see application note 826, recommended minimum pad patterns with outline drawin g access for vishay siliconix mosfets, ( http://www.vishay.com/ppg?72286 ), for the basis of the pad design for a little foot so-8 power mosfet. in converting this recommended minimum pad to the pad set for a power mosfet, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. in the case of the so-8 p ackage, the thermal connections are very simple. pins 5, 6, 7, and 8 are the drain of the mosfet for a single mosfet package and are connected together. in a dual package, pi ns 5 and 6 are one drain, and pins 7 and 8 are the other drain. for a small-signal device or integrated circuit, typical co nnections would be made with traces that are 0.020 inches wi de. since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. the total cross section of the copp er may be adequate to carry the current required for the a pplication, but it presents a large thermal impedance. also , heat spreads in a circular fashion from the heat source. in this case the drain pins are the heat sources wh en looking at heat spread on the pc board. figure 1. single mosfet so-8 pad pattern with copper spreading figure 2. dual mosfet so-8 pad pattern with copper spreading the minimum recommended pad patterns for the single-mosfet so-8 with copp er spreading (figure 1) and dual-mosfet so-8 with copper spreading (figure 2) show the starting point for utilizing th e board area available for the heat-spreading copper. to creat e this pattern, a plane of copper overlies the drain pins . the copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat fr om the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. these patterns use all the available area underneath the body for this purpose. since surface-mounted packag es are small, and reflow soldering is the most comm on way in which these are affixed to the pc board, ?t hermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint wi th the copper plane on the drain pins, the solder mask ge neration occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum pow er trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.196 5.0 0.2 88 7.3 0.050 1.27 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.0 88 2.25 0.2 88 7.3 0.050 1.27 0.0 88 2.25
application note 826 vishay siliconix www.vishay.com document number: 72606 22 revision: 21-jan-08 application note recommended minimum pads for so-8 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.172 (4.369) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) return to index return to index
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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