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vishay siliconix sir882adp new product document number: 63367 s11-1662-rev. a, 15-aug-11 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 n-channel 100 v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 definition ? trenchfet ? power mosfet ? 100 % r g and uis tested ? compliant to rohs directive 2002/95/ec applications ? dc/dc primary side switch ? telecom/server 48 v, full/half-bridge dc/dc ? industrial notes: a. package limited. b. surface mounted on 1" x 1" fr4 board. c. t = 10 s. d. see solder profile ( www.vishay.com/ppg?73257 ). the powerpak so-8 is a leadless package. t he end of the lead terminal is exposed copper (not plated) as a result of the singulat ion process in manufacturing. a solder fi llet at the exposed copper tip cannot be guara nteed and is not required to ensure adequate bottom side solder interconnection. e. rework conditions: manual solder ing with a soldering iron is not recommended for leadless components. f. maximum under steady state conditions is 65 c/w. product summary v ds (v) r ds(on) ( ? ) max. i d (a) a q g (typ.) 100 0.0087 at v gs = 10 v 60 19.5 nc 0.0094 at v gs = 7.5 v 60 0.0115 at v gs = 4.5 v 60 ordering information: sir882adp-t1-ge3 (lead (pb)-free and halogen-free) 1 2 3 4 5 6 7 8 s s s g d d d d 6.15 mm 5.15 mm powerpak ? so-8 bottom view n-channel mosfet g d s absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 100 v gate-source voltage v gs 20 continuous drain current (t j = 150 c) t c = 25 c i d 60 a a t c = 70 c 55 t a = 25 c 17.6 b, c t a = 70 c 13.9 b, c pulsed drain current (t = 300 s) i dm 80 continuous source-drain diode current t c = 25 c i s 60 a t a = 25 c 4.9 b, c single pulse avalanche current l = ? 0.1 mh i as 30 single pulse avalanche energy e as 45 mj maximum power dissipation t c = 25 c p d 83 w t c = 70 c 53 t a = 25 c 5.4 b, c t a = 70 c 3.4 b, c operating junction and storage temperature range t j , t stg - 55 to 150 c soldering recommendations (peak temperature) d, e 260 thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient b, f t ? 10 s r thja 18 23 c/w maximum junction-to-case (drain) steady state r thjc 11.5
www.vishay.com 2 document number: 63367 s11-1662-rev. a, 15-aug-11 vishay siliconix sir882adp new product this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0, i d = 250 a 100 v v ds temperature coefficient ? v ds /t j i d = 250 a 67 mv/c v gs(th) temperature coefficient ? v gs(th) /t j - 5.8 gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.2 2.8 v gate-source leakage i gss v ds = 0 v, v gs = 20 v 100 na zero gate voltage drain current i dss v ds = 100 v, v gs = 0 v 1 a v ds = 100 v, v gs = 0 v, t j = 55 c 10 on-state drain current a i d(on) v ds ?? 5 v, v gs = 10 v 30 a drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 20 a 0.0072 0.0087 ? v gs = 7.5 v, i d = 17 a 0.0077 0.0094 v gs = 4.5 v, i d = 15 a 0.0092 0.0115 forward transconductance a g fs v ds = 10 v, i d = 20 a 60 s dynamic b input capacitance c iss v ds = 50 v, v gs = 0 v, f = 1 mhz 1975 pf output capacitance c oss 748 reverse transfer capacitance c rss 60 total gate charge q g v ds = 50 v, v gs = 10 v, i d = 20 a 39.5 60 nc v ds = 50 v, v gs = 7.5 v, i d = 20 a 30.3 45.5 v ds = 50 v, v gs = 4.5 v, i d = 20 a 19.5 29.5 gate-source charge q gs 5.7 gate-drain charge q gd 8.3 output charge q oss v ds = 50 v, v gs = 0 v 61 92 gate resistance r g f = 1 mhz 0.2 0.95 1.9 ? tu r n - o n d e l ay t i m e t d(on) v dd = 50 v, r l = 5 ? i d ? 10 a, v gen = 10 v, r g = 1 ? 11 22 ns rise time t r 12 24 turn-off delay time t d(off) 34 65 fall time t f 918 tu r n - o n d e l ay t i m e t d(on) v dd = 50 v, r l = 5 ? i d ? 10 a, v gen = 7.5 v, r g = 1 ? 13 26 rise time t r 14 24 turn-off delay time t d(off) 32 60 fall time t f 10 20 drain-source body diode characteristics continuous source-drain diode current i s t c = 25 c 60 a pulse diode forward current a i sm 80 body diode voltage v sd i s = 5 a 0.74 1.1 v body diode reverse recovery time t rr i f = 10 a, di/dt = 100 a/s, t j = 25 c 49 95 ns body diode reverse recovery charge q rr 54 105 nc reverse recovery fall time t a 24 ns reverse recovery rise time t b 25 document number: 63367 s11-1662-rev. a, 15-aug-11 www.vishay.com 3 vishay siliconix sir882adp new product this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) output characteristics on-resistance vs. drain current and gate voltage gate charge 0 16 32 48 64 80 0.0 0.5 1.0 1.5 2.0 2.5 i d - drain current (a) v ds - drain-to-source voltage (v) v gs = 2 v v gs = 10 v thru 4 v v gs = 3 v 0.006 0.007 0.008 0.009 0.010 0.011 0 16 32 48 64 80 r ds(on) - on-resistance () i d - drain current (a) v gs = 4.5 v v gs = 7.5 v v gs = 10 v 0 2 4 6 8 10 0 9 18 27 36 45 v gs - gate-to-source voltage (v) q g - total gate charge (nc) v ds = 50 v v ds = 75 v v ds = 25 v i d = 20 a transfer characteristics capacitance on-resistance vs. junction temperature 0 2 4 6 8 10 0 1 2 3 4 5 i d - drain current (a) v gs - gate-to-source voltage (v) t c = 25 c t c = 125 c t c = - 55 c 0 620 1240 1860 2480 3100 0 20 40 60 80 100 c - capacitance (pf) v ds - drain-to-source voltage (v) c iss c oss c rss 0.5 0.8 1.1 1.4 1.7 2.0 - 50 - 25 0 25 50 75 100 125 150 r ds(on) - on-resistance (normalized) t j - junction temperature ( c) i d = 20 a v gs = 10 v v gs = 4.5 v www.vishay.com 4 document number: 63367 s11-1662-rev. a, 15-aug-11 vishay siliconix sir882adp new product this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) source-drain diode forward voltage threshold voltage 0.001 0.01 0.1 1 10 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 i s - source current (a) v sd - source-to-drain voltage (v) t j = 150 c t j = 25 c -1.0 -0.7 -0.4 -0.1 0.2 0.5 -50-250 255075100125150 v gs(th) - variance (v) t j -temperature ( c) i d = 250 a i d = 5 ma on-resistance vs. gate-to-source voltage single pulse power, junction-to-ambient 0.000 0.008 0.016 0.024 0.032 0.040 0246810 r ds(on) - on-resistance () v gs - gate-to-source voltage (v) t j = 125 c t j = 25 c i d = 20 a 0 40 80 120 160 200 0.001 0.01 0.1 1 10 power (w) time (s) safe operating area, junction-to-ambient 0.01 0.1 1 10 100 0.01 0.1 1 10 100 i d - drain current (a) v ds - drain-to-source voltage (v) * v gs > minimum v gs at which r ds(on) is specied 100 ms limited by r ds(on) * 1 ms i dm limited t c = 25 c single pulse bvdss limited 10 ms 10 s 1 s dc i d limited document number: 63367 s11-1662-rev. a, 15-aug-11 www.vishay.com 5 vishay siliconix sir882adp new product this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) * the power dissipation p d is based on t j(max) = 150 c, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determine the current rating, when this rating falls below the package limit. current derating* 0 0 25 50 75 100 150 125 16 32 48 64 80 t c - case temperature (c) i d - drain current (a) package limited power, junction-to-case 0 0 25 50 75 100 125 150 20 40 60 80 100 t c - case temperature (c) power (w) power, junction-to-ambient 0 0 25 50 75 100 125 150 0.5 1.0 1.5 2.0 2.5 t a - ambient temperature (c) power (w) www.vishay.com 6 document number: 63367 s11-1662-rev. a, 15-aug-11 vishay siliconix sir882adp new product this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?63367 . normalized thermal transient im pedance, junction-to-ambient 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 normalized effective transient thermal impedance square wave pulse duration (s) duty cycle = 0.5 0.2 0.1 0.05 0.02 single pulse notes: 1. duty cycle, d = 2. per unit base = r thja = 65 c/w 3. t jm - t a = p dm z thja (t) t 1 t 2 4. surface mounted t 1 p dm t 2 normalized thermal transient impedance, junction-to-case 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 normalized effective transient thermal impedance square wave pulse duration (s) duty cycle = 0.5 0.2 0.1 0.05 0.02 single pulse document number: 71655 www.vishay.com revison: 15-feb-10 1 package information vishay siliconix powerpak ? so-8, (single/dual) millimeters inches dim. min. nom. max. min. nom. max. a 0.97 1.04 1.12 0.038 0.041 0.044 a1 0.00 - 0.05 0.000 - 0.002 b 0.33 0.41 0.51 0.013 0.016 0.020 c 0.23 0.28 0.33 0.009 0.011 0.013 d 5.05 5.15 5.26 0.199 0.203 0.207 d1 4.80 4.90 5.00 0.189 0.193 0.197 d2 3.56 3.76 3.91 0.140 0.148 0.154 d3 1.32 1.50 1.68 0.052 0.059 0.066 d4 0.57 typ. 0.0225 typ. d5 3.98 typ. 0.157 typ. e 6.05 6.15 6.25 0.238 0.242 0.246 e1 5.79 5.89 5.99 0.228 0.232 0.236 e2 3.48 3.66 3.84 0.137 0.144 0.151 e3 3.68 3.78 3.91 0.145 0.149 0.154 e4 0.75 typ. 0.030 typ. e 1.27 bsc 0.050 bsc k 1.27 typ. 0.050 typ. k1 0.56 - - 0.022 - - h 0.51 0.61 0.71 0.020 0.024 0.028 l 0.51 0.61 0.71 0.020 0.024 0.028 l1 0.06 0.13 0.20 0.002 0.005 0.008 0 - 12 0 - 12 w 0.15 0.25 0.36 0.006 0.010 0.014 m 0.125 typ. 0.005 typ. ecn: t10-0055-rev. j, 15-feb-10 dwg: 5881 3. dimensions exclusive of mold flash and cutting burrs. 1. notes 2 inch will govern. dimensions exclusive of mold gate burrs. backside view of single pad backside view of dual pad detail z d d1 d2 c a e1 d1 e2 d2 e b 1 2 3 4 h 4 3 2 1 1 2 3 4 b l d2 d3(2x) z a1 k1 k d e w l1 d5 e3 d4 e4 e4 k l h e2 d4 d5 m e3 0.150 0.008 2 2 vishay siliconix an821 document number 71622 28-feb-06 www.vishay.com 1 powerpak ? so-8 mounting and thermal considerations wharton mcdaniel mosfets for switching applic ations are now available with die on resistances around 1 m and with the capability to handle 85 a. while these die capabilities represent a major advance over what was available just a few years ago, it is important for power mosfet packaging technology to keep pace. it should be obvi- ous that degradation of a high performance die by the package is undesir able. powerpak is a new package technology that addresses these issues. in this appli- cation note, powerpak?s co nstruction is described. following this mounting in formation is presented including land patterns and soldering profiles for max- imum reliability. finally, ther mal and electrical perfor- mance is discussed. the powerpak package the powerpak package was developed around the so-8 package (figure 1) . the powerpak so-8 uti- lizes the same footprint and the same pin-outs as the standard so-8. th is allows powerpak to be substi- tuted directly for a standard so-8 package. being a leadless package, powerpak so-8 utilizes the entire so-8 footprint, freeing space normally occupied by the leads, and thus allowing it to hold a larger die than a standard so-8. in fact, this larger die is slightly larger than a full sized dpak die. th e bottom of the die attach pad is exposed for the purpose of providing a direct, low resistance thermal path to the substrate the device is mounted on. finally, the package height is lower than the standard so-8, making it an excellent choice for applications with space constraints. powerpak so-8 single mounting the powerpak single is simple to use. the pin arrangement (drain, source, gate pins) and the pin dimensions are the same as standard so-8 devices (see figure 2). therefor e, the powerpak connection pads match directly to those of the so-8. the only dif- ference is the extended drain connection area. to take immediate advantage of the powerpak so-8 single devices, they can be mounted to existing so-8 land patterns. the minimum land pattern recommended to take full advantage of the powerpak thermal performance see application note 826, recommended minimum pad patterns with outline draw ing access for vishay sili- conix mosfets . click on the powerpak so-8 single in the index of this document. in this figure, the drain land pattern is given to make full contact to the drain pa d on the powerpak package. this land pattern can be extended to the left, right, and top of the drawn pattern. this ex tension will serve to increase the heat dissipation by decreasing the ther- mal resistance from the foot of the powerpak to the pc board and therefore to the ambient. note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to- ambient thermal resistance. under specific conditions of board configuration, copper weight and layer stack, experiments have found that more than about 0.25 to 0.5 in 2 of additional copper (in addition to the drain land) will yield little improv ement in thermal perfor- mance. figure 1. powerpak 1212 devices figure 2. standard so- 8 po w erpak so- 8 www.vishay.com 2 document number 71622 28-feb-06 vishay siliconix an821 powerpak so-8 dual the pin arrangement (drain, source, gate pins) and the pin dimensions of the po werpak so-8 dual are the same as standard so-8 dual devices. therefore, the powerpak device connection pads match directly to those of the so-8. as in the single-channel package, the only exception is the extended drain connection area. manufacturers can likewise take immediate advantage of the powerpak so-8 dual devices by mounting them to existing so-8 dual land patterns. to take the advantage of the dual powerpak so-8?s thermal performance, the minimum recommended land pattern can be found in application note 826, recommended minimum pad patterns with outline drawing access for vishay siliconix mosfets . click on the powerpak 1212-8 dual in the index of this doc- ument. the gap between the two drain pads is 24 mils. this matches the spacing of the two drain pads on the pow- erpak so-8 dual package. reflow soldering vishay siliconix surface- mount packages meet solder reflow reliability requirement s. devices are subjected to solder reflow as a test preconditioning and are then reliability-tested using tem perature cycle, bias humid- ity, hast, or pressure pot. the solder reflow tempera- ture profile used, and the temperatures and time duration, are shown in figures 3 and 4. for the lead (pb)-free solder profile, see http:// www.vishay.com/doc?73257. ramp-up rate + 6 c /second maximum temperature at 155 15 c 120 seconds maximum temperature above 180 c 70 - 180 seconds maximum temperature 240 + 5/- 0 c time at maximum temperature 20 - 40 seconds ramp-down rate + 6 c/second maximum figure 3. solder reflow temperature profile figure 3. solder reflow temperatures and time durations 210 - 220 c 3 c(max) 4 c/s (max) 10 s (max) 1 8 3 c 50 s (max) reflo w zone 60 s (min) pre-heating zone 3 c(max) 140 - 170 c maxim u m peak temperat u re at 240 c is allo w ed. vishay siliconix an821 document number 71622 28-feb-06 www.vishay.com 3 thermal performance introduction a basic measure of a device?s thermal performance is the junction-to-case thermal resistance, r jc , or the junction-to-foot thermal resistance, r jf . this parameter is measured for the device mounted to an infinite heat sink and is therefore a char acterization of the device only, in other words, independent of the properties of the object to which the device is mounted. table 1 shows a comparison of the dpak, powerpak so-8, and stan- dard so-8. the powerpak has thermal performance equivalent to the dpak, while having an or der of magni- tude better thermal performance over the so-8. thermal performance on standard so-8 pad pattern because of the common fo otprint, a powerpak so-8 can be mounted on an existing standard so-8 pad pat- tern. the question then arises as to the thermal perfor- mance of the powerpak devi ce under these conditions. a characterization was made comparing a standard so-8 and a powerpak device on a board with a trough cut out underneath the powerpak drai n pad. this configuration restricted the heat flow to the so-8 land pads. the results are shown in figure 5. because of the presence of the trough, this result sug- gests a minimum performance improvement of 10 c/w by using a powerpak so-8 in a standard so-8 pc board mount. the only concern when mounting a powerpak on a standard so-8 pad pattern is that there should be no traces running between the body of the mosfet. where the standard so-8 body is spaced away from the pc board, allowing traces to run underneath, the power- pak sits directly on the pc board. thermal performance - spreading copper designers may add additional copper, spreading cop- per, to the drain pad to aid in conducting heat from a device. it is helpful to have some information about the thermal performance for a given area of spreading cop- per. figure 6 shows the thermal resistance of a powerpak so-8 device mounted on a 2-in. 2-in., four-layer fr-4 pc board. the two internal layers and the backside layer are solid copper. the internal layers were chosen as solid copper to model the large power and ground planes common in many applications. the top layer was cut back to a smaller area and at each step junction-to- ambient thermal resistance measurements were taken. the results indicate that an area above 0.3 to 0.4 square inches of spreading copper gives no additional thermal performance improvement. a subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. no significant effect was observed. table 1. dpak and powerpak so-8 equivalent steady state performance dpak powerpak so-8 standard so-8 thermal resistance r jc 1.2 c/w 1.0 c/w 16 c/w figure 5. powerpak so-8 and standard so-0 land pad thermal path si4 8 74dy v s. si7446dp ppak on a 4-layer board so- 8 pattern, tro u gh under drain p u lse d u ration (sec) ) s t t a w / c ( e c n a d e p m i 0.0001 0 1 50 60 10 10000 0.01 40 20 si4 8 74dy si7446dp 100 30 figure 6. spreading copper junction- to-ambient performance r th v s. spreading copper (0 % , 50 % , 100 % back copper) ) s t t a w / c ( e c n a d e p m i 0.00 56 51 46 41 36 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 % 50 % 100 % www.vishay.com 4 document number 71622 28-feb-06 vishay siliconix an821 system and electrical impact of powerpak so-8 in any design, one must take into account the change in mosfet r ds(on) with temperature (figure 7). a mosfet generates internal heat due to the current passing through the channel. this self-heating raises the junction temperature of the device above that of the pc board to which it is mounted, causing increased power dissipation in the device. a major source of this problem lies in the large values of the junction-to-foot thermal resistance of the so-8 package. powerpak so-8 minimizes the junction-to-board ther- mal resistance to where the mosfet die temperature is very close to the temperature of the pc board. consider two devices mounted on a pc board heated to 105 c by other components on the board (figure 8). suppose each device is dissipating 2.7 w. using the junction-to-foot thermal resistance characteristics of the powerpak so-8 and the standard so-8, the die tem- perature is determined to be 107 c for the powerpak (and for dpak) and 148 c for the standard so-8. this is a 2 c rise above the board temperature for the pow- erpak and a 43 c rise for the standard so-8. referring to figure 7, a 2 c difference has minimal effect on r ds(on) whereas a 43c difference has a significant effect on r ds(on) . minimizing the thermal rise above the board tempera- ture by using powerpak has not only eased the thermal design but it has allowed the device to run cooler, keep r ds(on) low, and permits the device to handle more cur- rent than the same mosfet die in the standard so-8 package. conclusions powerpak so-8 has been shown to have the same thermal performance as the dpak package while hav- ing the same footprint as the standard so-8 package. the powerpak so-8 can hold larger die approximately equal in size to the maximum that the dpak can accom- modate implying no sacrifice in performance because of package limitations. recommended powerpak so-8 land patterns are pro- vided to aid in pc board layout for designs using this new package. thermal considerations have indicated that significant advantages can be gained by us ing powerpak so-8 devices in designs where the pc board was laid out for the standard so-8. applications experimental data gave thermal performance data showing minimum and typical thermal performance in a so-8 environment, plus infor- mation on the optimum thermal performance obtainable including spreading copper. this further emphasized the dpak equivalency. powerpak so-8 therefore has the desired small size characteristics of the so-8 combined with the attractive thermal characteristics of the dpak package. figure 7. mosfet r ds(on) vs. temperature figure 8. temperature of devices on a pc board 0.6 0. 8 1.0 1.2 1.4 1.6 1. 8 - 50 - 25 0 25 50 75 100 125 150 v gs = 10 v i d = 23 a on-resistance v s. j u nction temperat u re t j - j u nction temperat u re (c) ) d e z i l a m r o n ( ( e c n a t s i s e r - n o - r ) n o ( s d ) 0. 8 c/ w 107 c po w erpak so- 8 16 c/ w 14 8 c standard so- 8 pc board at 105 c application note 826 vishay siliconix document number: 72599 www.vishay.com revision: 21-jan-08 15 application note recommended minimum pads for powerpak ? so-8 single 0.174 (4.42) recommended mi nimum pads dimensions in inches/(mm) 0.260 (6.61) 0.024 (0.61) 0.154 (3.91) 0.150 (3.81) 0.050 (1.27) 0.050 (1.27) 0.032 (0.82) 0.040 (1.02) 0.026 (0.66) return to index return to index legal disclaimer notice www.vishay.com vishay revision: 12-mar-12 1 document number: 91000 disclaimer all product, product specifications and data are subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, repres entation or guarantee regarding the suitabilit y of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all i mplied warranties, including warra nties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain type s of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular application. it is the customers responsib ility to validate that a particu lar product with the properties descri bed in the product specification is suitable fo r use in a particular application. parameters provided in datasheets and/or specification s may vary in different applications an d performance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vish ays terms and condit ions of purchase, including but not limited to the warranty expressed therein. except as expressly indicate d in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vi shay product could result in personal injury or death. customers using or selling vishay products no t expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale , including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding th e design or manufacture of the part. please contact authorized vishay personnel t o obtain written terms and conditions regardin g products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual prope rty rights is granted by this document or by any conduct of vishay. product names and markings noted herein may be trad emarks of their respective owners. material category policy vishay intertechnology, inc. hereby certi fies that all its products that are id entified as rohs-compliant fulfill the definitions and restrictions defined under directive 2011/65/eu of the euro pean parliament and of the council of june 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (eee) - recast, unless otherwis e specified as non-compliant. please note that some vishay documentation may still make reference to rohs directive 2002/95/ ec. we confirm that all the products identified as being compliant to directive 2002 /95/ec conform to directive 2011/65/eu. |
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