? semiconductor components industries, llc, 2006 april, 2006 ? rev. 1 1 publication order number: nid5004n/d nid5004n self?protected fet with temperature and current limit 40 v, 6.5 a, single n ? channel, dpak self?protected fets are a series of power mosfets which utilize on semiconductor hdplus technology. the self?protected mosfet incorporates protection features such as integrated thermal and current limits. the self ? protected mosfets include an integrated drain ? to ? gate clamp that provides overvoltage protection from transients and avalanche. the device is protected from electrostatic discharge (esd) by utilizing an integrated gate ? to ? source clamp. features ? short circuit protection ? in rush current limit ? thermal shutdown with automatic restart ? avalanche rated ? overvoltage protection ? esd protection (4 kv hbm) ? controlled slew rate for low noise switching ? aec q101 qualified ? this is a pb ? free device applications ? solenoid driver ? relay driver ? small motors ? lighting ? relay replacement ? load switching device package shipping ? ordering information dpak case 369c style 2 drain source temperature limit gate input marking diagram d5004n = device code y = year ww = work week g= pb ? free device current limit current sense r g overvoltage protection esd protection yyw d5 004ng 1 = gate 2 = drain 3 = source 1 2 3 v dss (clamped) r ds(on) typ i d typ (limited) 40 v 110 m @ 10 v 6.5 a ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. http://onsemi.com NID5004NT4G dpak (pb ? free) 2500/tape & reel
nid5004n http://onsemi.com 2 mosfet maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit drain ? to ? source voltage internally clamped v dss 44 vdc gate ? to ? source voltage v gs 14 vdc drain current continuous i d internally limited total power dissipation @ t a = 25 c (note 1) @ t a = 25 c (note 2) p d 1.3 2.5 w thermal resistance junction ? to ? case junction ? to ? ambient (note 1) junction ? to ? ambient (note 2) r jc r ja r ja 3.0 95 50 c/w single pulse drain ? to ? source avalanche energy (v dd = 30 vdc, v gs = 5.0 vdc, i l = 1.8 apk, l = 160 mh, r g = 25 ) (note 3) e as 273 mj operating and storage temperature range (note 4) t j , t stg ? 55 to 150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. surface mounted onto minimum pad size (100 sq/mm) fr4 pcb, 1 oz cu. 2. mounted onto 1 square pad size (700 sq/mm) fr4 pcb, 1 oz cu. 3. not subject to production test 4. normal pre ? fault operating range. see thermal limit range conditions.
nid5004n http://onsemi.com 3 mosfet electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain ? to ? source clamped breakdown voltage (v gs = 0 v, i d = 2 ma) v (br)dss 36 40 44 v zero gate voltage drain current (v ds = 32 v, v gs = 0 v) i dss ? 27 100 a gate input current (v gs = 5.0 v, v ds = 0 v) i gss ? 45 200 a on characteristics gate threshold voltage (v ds = v gs , i d = 150 a) threshold temperature coefficient v gs(th) 1.0 ? 1.85 5.0 2.2 ? v ? mv/ c static drain ? to ? source on ? resistance (note 5) (v gs = 10 v, i d = 2.0 a, t j @ 25 c) r ds(on) ? 110 130 m static drain ? to ? source on ? resistance (note 5) (v gs = 5.0 v, i d = 2.0 a, t j @ 25 c) (v gs = 5.0 v, i d = 2.0 a, t j @ 150 c) r ds(on) ? ? 130 240 150 270 m source ? drain forward on voltage (i s = 7.0 a, v gs = 0 v) v sd ? 0.9 1.1 v switching characteristics (note 6) turn ? on delay time r l = 6.6 , v in = 0 to 10 v, v dd = 13.8 v, i d = 2.0 a, 10% v in to 10% i d td (on) ? 97 115 ns turn ? on rise time r l = 6.6 , v in = 0 to 10 v, v dd = 13.8 v, i d = 2.0 a, 10% i d to 90% i d t rise ? 282 300 ns turn ? off delay time r l = 6.6 , v in = 0 to 10 v, v dd = 13.8 v, i d = 2.0 a, 90% v in to 90% i d td (off) ? 930 1020 ns turn ? off fall time r l = 6.6 , v in = 0 to 10 v, v dd = 13.8 v, i d = 2.0 a, 90% i d to 10% i d t fall ? 690 750 ns slew rate on r l = 6.6 , v in = 0 to 10 v, v dd = 13.8 v, i d = 2.0 a, 70% to 50% v dd dv ds /dt on ? 64 ? v/ s slew rate off r l = 6.6 , v in = 0 to 10 v, v dd = 13.8 v, i d = 2.0 a, 50% to 70% v dd dv ds /dt off ? 28 ? v/ s self protection characteristics (t j = 25 c unless otherwise noted) (note 7) current limit v ds = 10 v, v gs = 5.0 v, t j = 25 c (note 8) v ds = 10 v, v gs = 5.0 v, t j = 100 c (note 6, 8) v ds = 10 v, v gs = 10 v, t j = 25 c (note 6, 8) i lim 4.0 4.0 ? 6.5 5.5 7.9 11 11 ? a temperature limit (turn ? off) v gs = 5.0 v (note 6) t lim(off) 150 180 200 c thermal hysteresis v gs = 5.0 v t lim(on) ? 10 ? c temperature limit (turn ? off) v gs = 10 v (note 6) t lim(off) 150 180 200 c thermal hysteresis v gs = 10 v t lim(on) ? 20 ? c input current during thermal fault v ds = 0 v, v gs = 5.0 v, t j = t j > t (fault) (note 6) v ds = 0 v, v gs = 10 v, t j = t j > t (fault) (note 6) i g(fault) 5.5 12 5.2 11 ? ma esd electrical characteristics (t j = 25 c unless otherwise noted) electrostatic discharge capability human body model (hbm) machine model (mm) (note 6) esd 4000 400 ? ? ? ? v 5. pulse test: pulse width 300 s, duty cycle 2%. 6. not subject to production test 7. fault conditions are viewed as beyond the normal operating range of the part. 8. current limit measured at 380 s after gate pulse.
nid5004n http://onsemi.com 4 typical performance curves t j = 100 c 0 4 5.0 v ds , drain ? to ? source voltage (volts) i d, drain current (amps) 2 0 figure 1. on ? region characteristics 3 3 2 0 figure 2. transfer characteristics v gs , gate ? to ? source voltage (volts) figure 3. on ? resistance vs. gate ? to ? source voltage i d, drain current (amps) figure 4. on ? resistance vs. drain current i d, drain current (amps) ? 55 ? 15 ? 35 5 1.4 1.6 1.0 0.8 0.6 25 figure 5. on ? resistance variation with temperature t j , junction temperature ( c) t j = 25 c t j = ? 55 c 45 t j = 25 c i d = 3.75 a v gs = 10 v r ds(on), drain ? to ? source resistance ( ) t j = 25 c r ds(on), drain ? to ? source resistance ( ) v gs = 10 v 0e+00 figure 6. drain ? to ? source leakage current vs. voltage v ds , drain ? to ? source voltage (volts) 30 i dss , leakage (a) t j = 100 c v gs = 5 v 10 40 4.0 v 1 4 45 6 10 v 4 85 65 5 0.13 0.10 0.14 0.11 0.12 4e ? 04 0 10 10 20 5 02 4.0 2.0 2.8 2.4 1.2 25 8 15 v gs = 3.0 v 3.5 v 3.2 12 6 1 0.15 8e ? 04 0.4 5.0 v 15 20 2e ? 04 6e ? 04 1e ? 03 v gs , gate ? to ? source voltage (volts) r ds(on), drain ? to ? source resistance ( ) 0.10 0.12 0.11 10 3.0 7.0 5.0 9.0 0.15 i d = 2 a t j = 25 c 0.13 0.14 35 5.0 4.0 8.0 6.0 2.2 3.0 2.6 3.4 3.6 3.8
nid5004n http://onsemi.com 5 zl typical performance curves v ds = 0 v t a = 200 c figure 7. diode forward voltage vs. current figure 8. input current vs. gate voltage 2000 0 v gs , gate ? to ? source voltage (volts) i gss ( a) 8 7 6 12000 8000 6000 4000 9 7e ? 3 2 0 time (seconds) figure 9. short circuit response* *(actual thermal cycling response in short circuit dependent on device power level, thermal mounting, and ambient temperature conditions) drain current (amps) 4e ? 3 2e ? 3 0e+0 12 8 5e ? 3 3e ? 3 1e ? 3 6 4 6e ? 3 0.2 1 0 v sd , source ? to ? drain voltage (volts) i s , source current (amps) v gs = 0 v t j = 25 c 5 0.8 0.6 4 3 2 6 7 0.4 8 1.0 0 10000 10 10 v gs = 10 v v gs = 5 v current limit temperature limit 0.1 0.7 0.5 0.3 0.9
nid5004n http://onsemi.com 6 package dimensions dpak case 369c ? 01 issue o d a k b r v s f l g 2 pl m 0.13 (0.005) t e c u j h ? t ? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.180 bsc 4.58 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.090 bsc 2.29 bsc r 0.180 0.215 4.57 5.45 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? 123 4 style 2: pin 1. gate 2. drain 3. source 4. drain 5.80 0.228 2.58 0.101 1.6 0.063 6.20 0.244 3.0 0.118 6.172 0.243 mm inches scale 3:1 soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?t ypicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license un der its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended f or surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in a ny manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 nid5004n/d hdplus is a trademark of semiconductor components industries, llc (scillc) literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
|
