specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage conditi on (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 91411 sy 20110825-s00007 no.a1977-1/9 LV5858M overview LV5858M is a 3a and 1ch step-down switching regulator. 0.1 fet is incorporated on the upper side to achieve high-efficiency operation for large output current. current mode control type, with superior load current response and easy phase compensation on/off pin, allowing the standby mode with the current drain of 60 a or less pulse-by-pulse over-current protection and overheat protection available for protection of load devices soft start pin to be provided with a capacitance for soft start. functions ? wide input dynamic range ( 8 to 42v) ? high efficiency (v in = 24v, v o = 5v, i out = 3a, 88%) ? current mode control type ? standby mode: 60 a ? ? reference voltage: 0.708v ? fixed frequency: 385khz ? load-independent soft start circuit ? built-in pulse-by-pulse ocp circuit. it is detect ed by using on resistance of an external mos. specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage v in max 45 v allowable pin voltage v in , sw 45 v cboot 52 v between cboot and sw 6.0 v en v in max v v dd 6.0 v ss, fb, comp, rt v dd v allowable power dissipation pd max ta 85 c mounted on a specified board * 0.95 w operating temperature topr -40 to 85 c storage temperature tstg -55 to 150 c junction temperature tj max 150 c continued on next page. bi-cmos ic step-down switching regulato r orderin g numbe r : ena1977
LV5858M no.a1977-2/9 continued from preceding page. * specified board: 36.0mm 44.0mm ? 1.6mm, glass epoxy, 2 layer substrate. caution 1) absolute maximum ratings represent the va lue which cannot be exceeded for any length of time. caution 2) even when the device is used within the range of abso lute maximum ratings, as a result of continuous usage under hig h temperature, high current, high voltage, or drastic temperature change, the reliability of th e ic may be degraded. please contact us for the further detai ls. recommended operating conditions at ta = 25 c parameter symbol conditions ratings unit supply voltage range v in 8 to 42 v error amplifier input voltage v fb 0 to 1.6 v electrical characteristics at ta = 25 c, v in = 24v parameter symbol conditions ratings unit min typ max reference voltage block internal reference voltage vref including offset of e/a 0.698 0.708 0.718 v 5v power supply v dd i out =0 to 5ma 4.7 5.2 5.7 v triangular waveform oscillator block oscillation frequency f osc 335 385 435 khz frequency variation f osc dv v in =8.0 to 42v 1 % oscillation frequency fold back detection voltage v osc fb fb voltage detection after ss ends 0.5 v oscillatory frequency after fold back f osc fb 25 45 60 khz on/off circuit block ic start-up voltage v en _on v in =8.0 to 42v 3.4 4.3 v ic off voltage v en _off 1.1 1.3 v soft start circuit block soft start source current i ss _sc en ? 3.5v 4 5 6 a soft start sink current i ss _sk en ? 1v, v dd =5v 2 ma voltage to end the soft start function v ss _end 0.9 1.1 1.3 v uvlo circuit block uvlo lock release voltage v uvlo 7.0 7.4 7.8 v uvlo hysteresis v uvlo _h 0.6 v error amplifier input bias current i ea _in 100 na error amplifier transconductance g ea 1000 1400 1800 a/v common mode input voltage range v ea _r 0.0 1.6 v sink output current i ea _osk fb=1.0v -100 a source output current i ea _osc fb=0v 100 a current detection amplifier gain gisns 1.3 over current limi ter circuit block current limit pead value i lim _ofs vout=5v, l=-10 h 4.0 4.5 a pwm comparator input threshold voltage f osc =125khz) vt max duty cycle=d max 1.0 1.1 1.2 v vt0 duty cycle=0% 0.4 0.5 0.6 v maximum on duty d max 85 90 95 % output block output stage on resistance (the upper side) r on 0.1 the whole device standby current i cc s en ? 1v 60 a mean consumption current i cc a en ? 4.3v 3.3 ma protection function temperature at which the high-temperature protection function operates tsd_on *design guarantee 170 c high-temperature protection function hysteresis tsd_hys *design guarantee 30 c
LV5858M no.a1977-3/9 package dimensions unit : mm (typ) 3403 block diagram sanyo : mfp12sj(225mil) 5.0 4.4 0.1 6.4 0.63 12 12 0.15 0.3 0.8 (0.5) 1.7 max (1.5) -40 0 20 40 60 80 100 0 1.25 1.50 0.25 0.95 pd max -- ta 0.50 0.75 1.00 -20 ambient temperature, ta -- c allowable power dissipation, pd max -- w mounted on a specified board: 44.0 36.0 1.6mm 3 glass epoxy both side 5v regulator reference voltage tsd uvlo + - saw wave oscillator control logic + - + - s r q s r q + - + - + + - + pwm comp 5v v in _s v dd ss fb comp 12pin v in _p en cboot sw ldrv gnd ocp comp v cc current amp 0.7v sd 1.1v sd err amp f osc forced 1/10 0.5v ffold comp 1.0v 0.5v dmax=90% shut down(sd)
LV5858M no.a1977-4/9 pin assignment pin function pin no. pin name function equivalent circuit 1 v in _p power supply pin. 2 cboot bootstrap capacity connection pin. this pin becomes a gate drive power supply of an external nch mosfet. connect a bypath capacitor cboot and sw. cboot sw gnd v in _s v in _p 12 sw pin to connect with switching node. connect the source of external upper nch mosfet and the drain of external lower nch mosfet. 3, 6 gnd ground pin. each reference voltage is based on the voltage of the ground pin. 4 ldrv an external the lower mosfet gate drive pin. ldrv v dd gnd 5 v dd power supply pin for an external the lower mos-fet gate drive. v in _s v dd gnd 7 v in _s control circuit supply pin. this pin is monitored by uvlo function. when the voltage of this pin become 8v or more by uvlo function. the ic state and the soft start function operates. continued on next page. 1 2 3 4 8 7 10 9 cboot sw gnd ss en comp fb top view 5 6 v in _p ldrv 11 12 gnd v dd v in _s
LV5858M ps no.a1977-5/9 continued from preceding page. pin no. pin name function equivalent circuit 8 ss pin to connect a capacitor for soft start. a capacitor for soft start is charged by using the voltage of about 5 a. this pin ends the soft start period by using the voltage of about 1.1v and the frequency fold back function becomes active. fb v dd ss gnd vref 0.708v 1.3v 0.1v 1.1v 9 fb error amplifier reverse input pin. by operating the converter, the voltage of this pin becomes 0.7v. the voltage in which the output voltage is divided by an external resistance is applied to this pin. moreover, when this pin voltage becomes 0.1v or less after a soft start ends, the oscillatory frequency becomes 1/3. 10 comp error amplifier output pin. connect a phase compensation circuit between this pin and gnd. fb v dd gnd 1.6v 11 en on/off pin. en v in _s gnd
LV5858M ps no.a1977-6/9 sample application circuit boot sequence, uvlo, and tsd operation sequence of overcurrent protection v in v dd ss v out sw ldrv tsd uvlo 7.4v 6.8v v dd =90% vref 0.708v 1.1v permission of fold back v in i lim sw i out ss fb 0.708v fb=0.1v driving usually overcurrent protection operation overcurrent protection operation(fold back operation) soft start operate section driving usually en v in _s v in _p v dd ss comp gnd_s fb ldrv sw cboot c1 c2 c8 q l d1 c9 c6 c3 r3 r2 v out c5 c4 r1 c7 on/off v in =8 to 42v d2
LV5858M ps no.a1977-7/9 various settings output voltage setting the setting of output voltage (v out ) follows the following expressions (1). v out = ( 1 + r3 r2 ) vref = ( 1 + 9.1k 1.5k ) 0.708 (typ) [v] (1) ex) to adjust the output voltage to 5v, it becomes r2=1.5k ? and r3=9.1k ? . soft start setting the setting of soft start capacitor (c7) follows the following expressions (2). c7 = i ss t ss vref = 5 t ss 0.708v [f] (2) i ss : charge current value, t ss : soft start time ex) to adjust the soft start time to about 1.5ms, it becomes c5=0.1 f. boot strap capacitor boot strap capacitor (c8) is with a capacitor about 1000 times ciss of power mosfet of building into. ciss of built-in power mosfet is 505pf. ex) c8=505pf 1000=0.505 f. c8 recommends 0.1 to 1 f. selection of input smoothness capacitor the ripple current flows to the input side capacitor of the dc-dc converter by the thing that ic does the switching. duty extends by the flow by there are a lot of output currents of the ripple curren t that flows to the input side capacitor just like the input current, and the input voltage low and a lot of ripple currents flow, too. please select the big one of a permissible ripple current from the valu e requested from the calcula ting formula. it must arrange near power ic, and inductance by the pattern must become small when you mount the input side capacitor. calculating formula (3) from which the execution value is requested becomes the following. i rip _in = ) 1 ( d d ? i out [arms] (3) d is duty cycle defined by v out /v in . selection of output smoothness capacitor please select the one with small impedance by the high freque ncy when the ripple voltage of the output is decided by the impedance of the output smoothness capacitor, and you want to suppress the voltage of the output ripple small. moreover, please select it so as not to exceed the permi ssible ripple current value. moreover, because the high frequency noise is removed, using the ceramic capacitor toge ther is effective. using of the aluminum electrolytic capacitor or the polymer aluminum el ectrolytic capacitor and the ceramic capacitor together is recommended. calculating formula (4) from which the execution value is requested becomes it as follows. i rip _out = 1 3 2 v out (v in -v out ) l f osc v in = [arms] (4) how to request smooth chalk coil l1: please note generation of heat of th e choke coil because of the overload and dc magnetic saturation when the load is short-circuited. the inductance value is d ecided because of voltage (v rip ) of the output ripple and the impedance of the output capacitor of the switching frequency. calculating formula (5) from which the most sm all inductance is requested becomes it as follows. l min = v in - v out f osc v in v out r c v rip [h] (5) esr is used by the above expression instead of the impedan ce of the output capacitor. in many cases, the impedance of the output capacitor of the switching frequency depends on a reason extremely near r c as for this. however, the actual impedance is used in the ceramic capacitor instead of r c . ex) v in (max)=40v, v out =12v, v rip =100mv, r c =10m ? , f osc =385khz l min = 40v - 12v 385k 40v 12v 10m 100mv 2.2 [h] (6)
LV5858M ps no.a1977-8/9 in actual part selection, inductance is se lected from the decision of the ripple voltage with the selection of the start capacitor. please consider the maximum value, minimum valu e, the output voltage, and the load change of the input voltage. the ripple current of inductance is recommended to be confirmed because it often becomes the selection criterion of the output inductance. calculating formula (7) from which the ripple current value is requested becomes it as follows. i rip = v in - v out f osc l d [a] (7) d is duty cycle defined by v out /v in . moreover, an important item is a ripple current shown with i rip /i out . in general, there is no problem if the ripple element is less than 50%. the inductance loss greatness and minute increases when there are a lot of ripple elements. ex) v in =24v, v out =5v, f osc =385khz, l=10 h i rip = 24v - 5v 385k 10 0.2 = 0.99 [a] (8) pattern layout note input capacitor the ripple current flows to the input capacitor of the dc-dc converter by the thing that ic does the switching. mounting and the pattern must be arranged in the input capacitor near the v in _p pin, and inductance by the pattern must become small. c2: please connect it near between the v in _p pin and the gnd pin of ic. c1: please connect the bypass capacitor connected with the v in _s pin of ic near between the v in _s pin and the gnd pin. (unusually, please note that intense ringing might be caused in the v in pin if the bypass capacitor is connected. the recommendation becomes 1000pf.) mosfet q (external fet) drives by using nch-mosfet. the sw node generates q along with on/off, and it changes, and the high frequency noise is generated between v in + and gnd. it influences a peri pheral pattern and the element at this time. please the pattern of the gate and the sw node on a low side must draw around neither ldrv nor the sw pin of ic, and wire for the pattern fat as much as possible. the wiring for ldrv and the sw pin is recommended to wire for the pattern between gnd patterns to prevent the noise from influencing it. when low side fet is turned on, it becomes the current pathway of inductor (l) v out (load) pgnd . it becomes possible to suppress the generation of the noise by doing the thing and the pattern wiring that reduces the area of this current pathway fat, and it becomes malfunction prevention. therefore, please arrange q, c2, and c3 in neighborhood. small signal system: fb, comp, en, cboot, v dd , ss please connect parts connected with the sm all signal system with short wiring as much as possible in ic neighborhood, and make gnd of parts common with the gnd pattern of ic. please do not wire the under of the wiring for the inductor and the sw node and neighborhood for the fb pattern. please there must be a possibility of causing the malfunction, and avoid and wire for the pattern.
LV5858M ps no.a1977-9/9 this catalog provides information as of september, 2011. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliab ility pr oducts, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these pr obab ilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.
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