cystech electronics corp. spec. no. : c872f3 issued date : 2012.12.26 revised date : page no. : 1/9 MTE65N20F3 cystek product specification n -channel enhancement mode power mosfet MTE65N20F3 bv dss 200v i d 33a 61m v gs =10v, i d =11a r dson(typ) v gs =6v, i d =5a features ? low gate charge ? simple drive requirement ? pb-free lead plating package equivalent circuit outline absolute maximum ratings (t c =25 c, unless otherwise noted) MTE65N20F3 to-263 66m g d s g gate d drain s source parameter symbol limits unit drain-source voltage v ds 200 v gs 20 v gate-source voltage i d 33 continuous drain current @ t c =25 c, v gs =10v i d 23 continuous drain current @ t c =100c, v gs =10v pulsed drain current *1 i dm 70 i as 20 a avalanche current avalanche energy @ l=1.6mh, i d =20a, r g =25 e as 320 repetitive avalanche energy@ l=0.1mh (note 2) e ar 4.6 mj total power dissipation @t c =25 168 pd w total power dissipation @t a =25 3.75 operating junction and storage te mperature range tj, tstg -55~+175 c note : *1 . pulse width limited by maximum junction temperature *2. duty cycle 1%
cystech electronics corp. spec. no. : c872f3 issued date : 2012.12.26 revised date : page no. : 2/9 MTE65N20F3 cystek product specification thermal data parameter symbol value unit thermal resistance, junction-to-case, max r th,j-c 0.89 c/w thermal resistance, junction-to-ambient, max* r th,j-a 40 c/w thermal resistance, junction-to-ambient, max r th,j-a 62.5 c/w *when mounted on the minimum pad size (pcb mount). characteristics (tc=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 200 - - v v gs =0, i d =250 a v gs(th) 2.5 3.8 4.5 v v ds =v gs , i d =250 a i gss - - 100 na v gs = 20, v ds =0 - - 1 v ds =180v, v gs =0 i dss - - 25 a v ds =180v, v gs =0, t j =125 c - 61 80 v gs =10v, i d =11a r ds(on) *1 - 66 100 m v gs =6v, i d =5a g fs *1 - 15 - s v ds =15v, i d =11a dynamic qg *1, 2 - 60 - qgs *1, 2 - 12.1 - qgd *1, 2 - 24.2 - nc v ds =160v, i d =25a, v gs =10v t d(on) *1, 2 - 62 - tr *1, 2 - 62 - t d(off) *1, 2 - 200 - t f *1, 2 - 100 - ns v ds =100v, i d =20a, v gs =10v, r g =25 ciss - 2447 - coss - 180 - crss - 102 - pf v gs =0v, v ds =25v, f=1mhz source-drain diode i s *1 - - 20 i sm *3 - - 40 a v sd *1 - 0.82 1.3 v i f =i s , v gs =0v trr - 120 - ns qrr - 400 - nc i f =20a, di f /dt=100a/ s note : *1.pulse test : pulse width 300 s, duty cycle 2% *2.independent of operating temperature *3.pulse width limited by maximum junction temperature. ordering information device package shipping MTE65N20F3-0-t4-s to-252 (pb-free lead plating and rohs compliant package) 800 pcs / tape & reel
cystech electronics corp. spec. no. : c872f3 issued date : 2012.12.26 revised date : page no. : 3/9 MTE65N20F3 cystek product specification typical characteristics typical output characteristics 0 10 20 30 40 50 60 70 0 4 8 121620 v ds , drain-source voltage(v) i d , drain current (a) 10v,9v,8v,7v,6v v gs =5v brekdown voltage vs ambient temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 10 100 1000 0.01 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =6v v gs =5v v gs =10v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 024681 i dr , reverse drain current(a) v sd , source-drain voltage(v) 0 tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 0 40 80 120 160 200 024681 0 drain-source on-state resistance vs junction tempearture 0 0.4 0.8 1.2 1.6 2 2.4 -60 -20 20 60 100 140 180 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =11a r ds( on) @tj=25c : 60.4m v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =11a
cystech electronics corp. spec. no. : c872f3 issued date : 2012.12.26 revised date : page no. : 4/9 MTE65N20F3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 10 100 1000 10000 0.1 1 10 100 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.2 0.4 0.6 0.8 1 1.2 1.4 -60 -20 20 60 100 140 180 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 i d , drain current(a) g fs , forward transfer admittance(s) ta=25c pulsed v ds =15v gate charge characteristics 0 2 4 6 8 10 0 1020304050607080 qg, total gate charge(nc) v gs , gate-source voltage(v) i d =25a v ds =160v v ds =100v \ maximum safe operating area 0.01 0.1 1 10 100 0.1 1 10 100 1000 v ds , drain-source voltage(v) i d , drain current(a) t c =25c, tj=175c v gs =10v, jc =0.89c/w single pulse dc 100ms r dson limited 1s 100 s 1ms 10ms maximum drain current vs case temperature 0 5 10 15 20 25 30 35 40 25 50 75 100 125 150 175 200 t c , case temperature(c) i d , maximum drain current(a) v gs =10v, r jc =0.89c/w
cystech electronics corp. spec. no. : c872f3 issued date : 2012.12.26 revised date : page no. : 5/9 MTE65N20F3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 10 20 30 40 50 60 70 0246810 v gs , gate-source voltage(v) i d , drain current(a) v ds =10v power derating curve 0 20 40 60 80 100 120 140 160 180 0 25 50 75 100 125 150 175 200 t c , case temperature() p d , power dissipation(w) transient thermal response curves 0.001 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r jc (t)=r(t)*r jc 2.duty factor, d=t 1 /t 2 3.t jm -t c =p dm *r jc (t) 4.r jc =0.89c/w
cystech electronics corp. spec. no. : c872f3 issued date : 2012.12.26 revised date : page no. : 6/9 MTE65N20F3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c872f3 issued date : 2012.12.26 revised date : page no. : 7/9 MTE65N20F3 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds ? time(ts min to ts max ) time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c872f3 issued date : 2012.12.26 revised date : page no. : 8/9 MTE65N20F3 cystek product specification to-263 dimension *:typical inches millimeters inches style : pin 1.gate 2.drain 3.source 3-lead plastic surface mounted package cystek package code : f3 marking : e65 n20 device name date code millimeters dim min. max. min. max. dim min. max. min. max. a 0.3800 0.4050 9.65 10.29 i 0.0500 0.0700 1.27 1.78 b 0.3300 0.3700 8.38 9.40 j - *0.1000 - *2.54 c - 0.0550 - 1.40 k 0.0450 0.0550 1.14 1.40 d 0.5750 0.6250 14.61 15.88 l 0.0200 0.0390 0.51 0.99 e 0.1600 0.1900 4.06 4.83 1 - - 6 8 f 0.0450 0.0550 1.14 1.40 2 - - 6 8 g 0.0900 0.1100 2.29 2.79 3 - - 0 5 h 0.0180 0.0290 0.46 0.74 notes : 1.controlling dimension : millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material : ? lead : pure tin plated. ? mold compound : epoxy resin family, flammability solid burning class:ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance . a b c d 123 k l j g h e f 2 1 2 3 i
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