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cmos 8-bit single chip microcomputer description the CXP7400P10 is a cmos 8-bit microcomputer integrating on a single chip an a/d converter, serial interface, timer/counter, time-base timer, capture timer/counter, remote control receive circuit, pwm output, and the like besides the basic configurations of 8-bit cpu, rom, ram, and i/o port. the CXP7400P10 also provides the sleep/stop functions that enable lower power consumption. the CXP7400P10 is the prom-incorporated version of the cxp740056/740096/740010 with built- in mask rom. this provides the additional feature of being able to write directly into the program. thus, it is most suitable for evaluation use during system development and for small-quantity production. features a wide instruction set (211 instructions) which covers various types of data. ?16-bit arithmetic/multiplication and division/boolean bit operation instructions minimum instruction cycle 167ns at 24mhz operation (4.5 to 5.5v) 333ns at 12mhz operation (2.7 to 5.5v) 122s at 32khz operation (2.7 to 5.5v) incorporated prom capacity 120k bytes incorporated ram capacity 4096 bytes peripheral functions ?a/d converter 8 bits, 8 channels, successive approximation method (conversion time 10.3s at 24mhz) ?serial interface srart-stop synchronization (uart), 1 channel incorporated buffer ram (auto transfer for 1 to 32 bytes), 2 channels 8-bit clock syncronization (msb/lsb first selectable), 1 channel ?timer 8-bit timer 2 channels, 8-bit timer/counter 2 channels, 19-bit time-base timer, 16-bit capture timer/counter 32khz timer/counter ?remote control receive circuit noise elimination circuit 8-bit pulse measuring counter, 6-stage fifo ?pwm output 12 bits, 2 channels interruption 22 factors, 15 vectors, multi-interruption possible standby mode sleep/stop package 100-pin plastic qfp/lqfp ?1 e98518a1y-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP7400P10 100 pin qfp (plastic) 100 pin lqfp (plastic) structure silicon gate cmos ic
?2 CXP7400P10 pf0 to pf7 8 ram 4096 bytes interrupt controller a/d converter int3 int1 int0 int2 an0 to an11 12 rst v dd v ss extal xtal av ref av ss rxd txd prom 120k bytes 2 clock generator/ system control port a 2 6 pa0 to pa7 pb0 to pb7 pc0 to pc7 pd0 to pd7 pe0 to pe1 pe2 to pe7 pg0 to pg7 pi1 to pi7 port b port c port d port e port f port g port i ph0 to ph7 port h uart receiver uart transmitter uart baud rate generator 8 8 8 8 8 7 int4 nmi 2 pwm0 12-bit pwm generator 0 12-bit pwm generator 1 pwm1 remocon in buffer ram cs0 si0 so0 sck0 serial interface unit (ch1) 16-bit capture timer/counter 4 to2 8-bit timer/counter 0 8-bit timer 1 ec0 cint ec2 serial interface unit (ch2) si2 so2 sck2 pj0 to pj7 port j 8 av dd rmc cs1 si1 so1 sck1 prescaler/ time-base timer buffer ram tx tex 32khz timer/counter 2 5 port k pk3 to pk7 pk1 to pk2 fifo serial interface unit (ch0) to0 8-bit timer/counter 2 8-bit timer 3 ec1 to1 2 adj vpp spc 700 ii cpu core 8 block diagram
3 CXP7400P10 pin assignment (top view) 100-pin qfp package a a 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 81 82 83 84 75 76 77 78 88 87 86 85 79 89 90 10 0 99 98 97 96 95 94 91 92 93 1 80 pi6/so1 pi7/si1 pe0/int0 pe1/int2 pe2/pwm0 pe3/pwm1 pe4 pe5 pe6 pe7 pg0/txd pg1/rxd pg2/ec0 pg3/ec1 pg4/ec2 pg5/int3 pg6/int4 pg7/cint an0 an1 an2 an3 pf0/an4 pf1/an5 pf2/an6 pf3/an7 av dd av ref av ss pf4/an8 pc5 pc4 pc3 pc2 pc1 pc0 pb7/si2 pb6/so2 pb5/sck2 pb4/to2 pb3 pb2 pb1 pb0 pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pc6 pc7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vpp v dd v ss pk1/tx pk2/tex pi1/rmc pi2/nmi pi3/to0/adj pi4/int1/cs1 pi5/sck1 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 pk7/to1 rst v ss xtal extal pk6/cs0 pk5/si0 pk4/so0 pk3/sck0 pf7/an11 pf6/an10 pf5/an9 note) 1. vpp (pin 90) is left open. 2. v ss (pins 41 and 88) are both connected to gnd.
4 CXP7400P10 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 81 82 83 84 75 76 77 78 88 87 86 85 79 89 90 10 0 99 98 97 96 95 94 91 92 93 1 80 pi6/so1 pi7/si1 pe0/int0 pe1/int2 pe2/pwm0 pe3/pwm1 pe4 pe5 pe6 pe7 pg0/txd pg1/rxd pg2/ec0 pg3/ec1 pg4/ec2 pg5/int3 pg6/int4 pg7/cint an0 an1 an2 an3 pf0/an4 pf1/an5 pf2/an6 pc3 pc2 pc1 pc0 pb7/si2 pb6/so2 pb5/sck2 pb4/to2 pb3 pb2 pb1 pb0 pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 pd7 pd6 pd5 pc6 pc7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vpp v dd v ss pk1/tx pk2/tex pi1/rmc pi2/nmi pi3/to0/adj pi4/int1/cs1 pi5/sck1 ph2 ph1 ph0 pk7/to1 rst v ss xtal extal pk6/cs0 pk5/si0 pk4/so0 pk3/sck0 pf7/an11 pf6/an10 pf5/an9 ph7 ph6 ph5 ph4 ph3 26 27 28 29 30 pd4 pd3 pd2 pd1 pd0 pf4/an8 av ss pf3/an7 av dd av ref pc4 pc5 aa pin assignment (top view) 100-pin lqfp package note) 1. vpp (pin 88) is left open. 2. v ss (pins 39 and 86) are both connected to gnd.
5 CXP7400P10 (port a) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) (port c) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) (port d) 8-bit i/o port. i/o can be set in a unit of single bits. can drive 12ma sink current. incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) (port e) 8-bit port. lower 2 bits are for input; upper 6 bits are for output. (8 pins) (port f) 8-bit i/o port. i/o can be set in a unit of single bits. pf4 to pf7 can be set in a unit of single bits as standby release inputs. incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) analog inputs to a/d converter. (8 pins) pin description symbol pa0 to pa7 pc0 to pc7 pd0 to pd7 pe0/int0 pe1/int2 pe2/pwm0 pe3/pwm1 pe4 to pe7 pf0/an4 to pf7/an11 i/o i/o i/o input/input input/input output/output output/output output i/o/input i/o description (port b) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) external interrupt inputs. (2 pins) 12-bit pwm outputs. (2 pins) 16-bit timer/counter rectangular wave output. serial clock i/o (ch2). serial data output (ch2). serial data input (ch2). i/o i/o/output i/o/i/o i/o/output i/o/input pb0 to pb3 pb4/to2 pb5/sck2 pb6/so2 pb7/si2
6 CXP7400P10 (port h) 8-bit output port. operated as n-ch open drain output for medium voltage drive (12v) and large current (12ma). (8 pins) (port i) 7-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the program in a unit of single bits. (7 pins) (port j) 8-bit i/o port. i/o can be set in a unit of single bits. standby release input can be set in a unit of single bits. incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) (port k) 7-bit port. lower 2 bits are for input; upper 5 bits are for i/o. i/o can be set in a unit of single bits. for pk3 to pk7, incorporation of pull-up resistor can be set through the program in a unit of single bits. (7 pins) uart transmission data output. uart reception data input. external event input for 8-bit timer/counter 0. external event input for 8-bit timer/counter 2. external event input for 16-bit timer/counter. external capture input to 16-bit timer/counter. remote control receiver circuit input. non-maskable interrupt input. output for the 8-bit timer/counter 1 rectanguler waves and tex oscillation frequency demultiplication. serial clock i/o (ch1). serial data output (ch1). serial data input (ch1). crystal connectors for 32-khz timer/counter clock oscillation circuit. for usage as event counter, connect clock oscillation source to tex, and leave tx open. serial clock i/o (ch0). serial data output (ch0). serial data input (ch0). chip select input for serial inteface (ch0). 8-bit timer/counter 3 rectangular wave output. symbol pg0/txd pg1/rxd pg2/ec0 pg3/ec1 pg4/ec2 pg5/int3 pg6/int4 pg7/cint ph0 to ph7 pi1/rmc pi2/nmi pi3/to0/ adj pi4/int1/ cs1 pi5/sck1 pi6/so1 pi7/si1 pj0 to pj7 pk3/sck0 pk4/so0 pk5/si0 pk6/cs0 pk7/to1 i/o/output i/o/input i/o/input i/o/input i/o/input i/o/input i/o/input i/o/input output i/o/input i/o/input i/o/output/ output i/o/input/ input i/o/i/o i/o/output i/o/input i/o i/o/i/o i/o/output i/o/input i/o/input i/o/output i/o description chip select input for serial interface (ch1). external interrupt input. (port g) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the program in a unit of single bits. (8 pins) pk1/tx pk2/tex input input/input external interrupt inputs. (2 pins)
7 CXP7400P10 analog inputs to a/d converter. (4 pins) connects a crystal for system clock oscillation. when a clock is supplied externally, input it to extal pin and input a reversed phase clock to xtal pin. system reset; active at low level. positive power supply pin for incorporated prom writing. leave this pin open for normal operation. (connected to v dd internally.) positive power supply of a/d converter. reference voltage input of a/d converter. gnd of a/d converter. positive power supply. gnd. connect both v ss pins to gnd. symbol i/o description extal xtal input an0 to an3 rst vpp av dd av ref av ss v dd v ss input input input
8 CXP7400P10 18 pins hi-z hi-z after a reset pa0 to pa7 pb0 pb2 pc0 to pc7 pb4/to2 pi3/to0/adj pk7/to1 3 pins internal data bus rd (ports a, b, c) aa aa ip a a aaaaa aaaaa ports a, b, c data 0 after a reset ? aaaaa aaaaa ports a, b, c direction aaaa aaaa pull-up resistor 0 after a reset ? pull-up transistors approx. 100k ? (v dd = 4.5 to 5.5v) approx. 150k ? (v dd = 2.7 to 3.3v) i/o circuit format for pins pin circuit format 2 pins hi-z pb1 pb3 internal data bus rd (port b) aa aa ip a a aaaa aaaa port b data 0 after a reset ? aaaa aaaa port b direction aaaa aaaa pull-up resistor 0 after a reset ? pull-up transistors approx. 100k ? (v dd = 4.5 to 5.5v) approx. 150k ? (v dd = 2.7 to 3.3v) schmitt input internal data bus rd (ports b, i, k) aa aa ip aa aa aaaaa a aaa a aaaaa ports b, i, k function select 0 after a reset ? 0 after a reset aaaa aaaa pull-up resistor to2, to0/adj, to1 0 after a reset ? pull-up transistors approx. 100k ? (v dd = 4.5 to 5.5v) approx. 150k ? (v dd = 2.7 to 3.3v) aaaaa aaaaa ports b, i, k data aaaaa aaaaa ports b, i, k direction port a port b port c port b portb port k port i
9 CXP7400P10 3 pins hi-z hi-z after a reset pb5/sck2 pi5/sck1 pk3/sck0 pb6/so2 pg0/txd pi6/so1 pk4/so0 4 pins aaaa aaaa internal data bus rd (ports b, i, k) aa aa ip aa aa aaaa aaaa ports b, i, k direction 0 after a reset ? ? pull-up transistors approx. 100k ? (v dd = 4.5 to 5.5v) approx. 150k ? (v dd = 2.7 to 3.3v) aaaa aaaa ports b, i, k data 0 after a reset ports b, i, k function select sck2, sck1, sck0 output enable aaaa aaaa output buffer capability 0 after a reset aaaa aaaa pull-up resistor 0 after a reset schmitt input sck2, sck1, sck0 pin circuit format aaaa a aa a aaaa internal data bus rd (ports b, g, i, k) aa ip aa aa aaaa aaaa ports b, g, i, k direction 0 after a reset ? ? pull-up transistors approx. 100k ? (v dd = 4.5 to 5.5v) approx. 150k ? (v dd = 2.7 to 3.3v) aaaa ports b, g, i, k data 0 after a reset aaaa aaaa ports b, g, i, k function select so2, txd, so1, so0 output enable output buffer capability 0 after a reset aaaa aaaa pull-up resistor 0 after a reset port b port i port k port b port g port i port k
10 CXP7400P10 14 pins hi-z hi-z after a reset pb7/si2 pg1/rxd pg2/ec0 pg3/ec1 pg4/ec2 pg5/int3 pg6/int4 pg7/cint pi1/rmc pi2/nmi pi4/int1/cs1 pi7/si1 pk5/si0 pk6/cs0 pe0/int0 pe1/int2 2 pins internal data bus rd (ports b, g, i, k) aaaaa aaaaa a a ports b, g, i, k direction ip aa aa aaaaa aaaaa ports b, g, i, k data aaaaa pull-up resistor 0 after a reset 0 after a reset ? schmitt input si2, rxd, ec0, ec1, ec2, int3, int4, cint, rmc, nmi, int1/cs1, si1, si0, cs0 ? pull-up transistors approx. 100k ? (v dd = 4.5 to 5.5v) approx. 150k ? (v dd = 2.7 to 3.3v) pin circuit format 8 pins hi-z pd0 to pd7 internal data bus rd (port d) aaaa aaaa port d direction aa aa aaaa aaaa port d data aaaa pull-up resistor 0 after a reset ? 2 ? 1 ? 1 large current 12ma (v dd = 4.5 to 5.5v) 4.5ma (v dd = 2.7 to 3.3v) ? 2 pull-up transistors approx. 100k ? (v dd = 4.5 to 5.5v) approx. 150k ? (v dd = 2.7 to 3.3v) a ip aa aa ip aa aa schmitt input rd (port e) internal data bus int0, int2 port b port g port i port k port d port e
11 CXP7400P10 2 pins hi-z after a reset pe2/pwm0 pe3/pwm1 aa aa aaaa port e function select 0 after a reset pwm0, pwm1 aaaa aaaa port e data internal data bus rd (port e) hi-z by writing to port e data register or port e function select register output active 2 pins hi-z pe4 pe5 hi-z by writing to port e data register output active aa aa internal data bus rd (port e) aaaa aaaa port e data 1 pin "h" level pe6 aa aa internal data bus rd (port e) aaaa aaaa port e data 1 after a reset 1 pin pe7 aa aa internal data bus rd (port e) ? ? pull-up transistors approx. 150k ? (v dd = 4.5 to 5.5v) approx. 200k ? (v dd = 2.7 to 3.3v) internal reset signal aaaa aaaa port e data 1 after a reset 4 pins hi-z an0 to an3 aa aa aa ip a/d converter input multiplexer pin circuit format "h" level "h" level at on resistance of pull-up transistor during a reset. ) port e port e port e port e )
12 CXP7400P10 4 pins hi-z hi-z after a reset pf0/an4 to pf3/an7 pf4/an8 to pf7/an11 4 pins internal data bus rd (port f) aaaa aaaa a a port f direction ip aa aa aaaa aaaa port f data aaaa pull-up resistor aaaa aaaa port f function select 0 after a reset 0 after a reset 0 after a reset input multiplexer a/d converter ? ? pull-up transistors approx. 100k ? (v dd = 4.5 to 5.5v) approx. 150k ? (v dd = 2.7 to 3.3v) pin circuit format internal data bus rd (port f) aaaa aaaa port f direction aa aa ip aa aaaa port f data aaaa aaaa pull-up resistor aaaa aaaa port f function select 0 after a reset 0 after a reset 0 after a reset input multiplexer a/d converter ? ? pull-up transistors approx. 100k ? (v dd = 4.5 to 5.5v) approx. 150k ? (v dd = 2.7 to 3.3v) aaaa aaaa polarity select 0 after a reset a a edge detection standby release port f port f
13 CXP7400P10 8 pins hi-z hi-z after a reset ph0 to ph7 pj0 to pj7 8 pins internal data bus rd (port h) aaaa port h data 1 after a reset ? ? high tension proof 12v large current aa aa 12ma (v dd = 4.5 to 5.5v) 4.5ma (v dd = 2.7 to 3.3v) pin circuit format internal data bus rd (port j) aaaa aaaa aa aa port j direction ip aa aaaa port j data aaaa aaaa pull-up resistor 0 after a reset 0 after a reset ? ? pull-up transistors approx. 100k ? (v dd = 4.5 to 5.5v) approx. 150k ? (v dd = 2.7 to 3.3v) aaaa aaaa polarity select 0 after a reset a edge detection standby release oscillation stop port input pk1/tx pk2/tex 2 pins ip ip tex oscillation circuit control rd (port k) schmitt input clock input internal data bus internal data bus 1 after a reset pk2/tex pk1/tx rd (port k) port h port j port k
14 CXP7400P10 2 pins oscillation after a reset extal xtal aa aa aa aa ip aa aa extal xtal diagram shows circuit configuration during oscillation. when program stops the oscillation, the feedback registor disconnects, and xtal is driven at "h" level. a a ip 1 pin "l" level (during a reset) rst aa schmitt input pull-up resistor mask option op aa ip pin circuit format
15 CXP7400P10 supply voltage input voltagte output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation ? 1 av dd and v dd must be set to the same voltage. ? 2 v in and v out must not exceed v dd + 0.3v. ? 3 the large current output pins are port d and h (pd, ph). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsi. v dd vpp av dd av ss av ref v in v out i oh i oh i ol i olc i ol topr tstg p d 0.3 to +7.0 0.3 to +13.0 av ss to +7.0 ? 1 0.3 to +0.3 av ss to +7.0 0.3 to +7.0 ? 2 0.3 to +7.0 ? 2 5 50 15 20 100 20 to +75 55 to +150 600 380 v v v v v v v ma ma ma ma ma c c mw incorporated prom output (value per pin) total for all output pins all pins excluding large current outputs (value per pin) large current outputs (value per pin) ? 3 total for all output pins qfp package lqfp package item symbol rating unit remarks absolute maximum ratings (vss = 0v reference)
16 CXP7400P10 high level input voltage low level input voltage operating temperature supply voltage analog voltage 5.5 5.5 v dd v dd v dd v dd + 0.3 v dd + 0.2 0.3v dd 0.2v dd 0.2v dd 0.4 0.2 +75 v v v v v v v v v v c v v v v item symbol min. 4.5 2.7 5.5 5.5 max. unit remarks fc = 24mhz or less guaranteed operation range for 1/2 and 1/4 frequency dividing clock fc = 12mhz or less v 2.7 5.5 2.5 2.7 0.7v dd 0.8v dd 0.8v dd v dd 0.4 v dd 0.2 0 0 0 0.3 0.3 20 v ih v ihs v ihex v il v ils v ilex topr guaranteed operation range for 1/16 frequency dividing clock or sleep mode guarantteed operaion range for tex guaranteed data hold operation range during stop mode ? 1 ? 2 , ? 6 ? 2 , ? 7 hysteresis input ? 3 extal pin ? 4 , ? 6 , tex pin ? 5 , ? 6 extal pin ? 4 , ? 7 , tex pin ? 5 , ? 7 ? 2 , ? 6 ? 2 , ? 7 hysteresis input ? 3 extal pin ? 4 , ? 6 , tex pin ? 5 , ? 6 extal pin ? 4 , ? 7 , tex pin ? 5 , ? 7 v dd av dd ? 1 av dd and v dd must be set to the same voltage. ? 2 normal input port (pa, pb0, pb2, pb4, pb6, pc, pd, pf, pg0, pi3, pi6, pj, pk1, pk2, pk4, pk7) ? 3 rst, pb1, pb3, pb5/sck2, pb7/si2, pe0/int0, pe1/int2, pg1/rxd, pg2/ec0, pg3/ec1, pg4/ec2, pg5/int3, pg6/int4, pg7/cint, pi1/rmc, pi2/nmi, pi4/int1/cs1, pi5/sck1, pi7/si1, pk3/sck0, pk5/si0, pk6/cs0 ? 4 specifies only when the external clock is input. ? 5 specifies only when the external event count is input. ? 6 this case applies to the range of 4.5 to 5.5v supply voltage (v dd ). ? 7 this case applies to the range of 2.7 to 5.5v supply voltage (v dd ). recommended operating conditions (vss = 0v reference) 2.7 5.5 v
17 CXP7400P10 v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 0.4v v dd = 4.5v, v il = 4.0v v dd = 5.5v v i = 0, 5.5v v dd = 5.5v v oh = 12v high level output voltage low level output voltage input current i/o leakage current 0.5 0.5 0.1 0.1 1.5 2.78 v v v v v a a a a a a a a a pd, ph pa to pd, pe2 to pe7, pf to pg, pi to pj, pk3 to pk7 pb5, pb6 ? 1 , pg0 ? 1 , pi5, pi6 ? 1 , pk3, pk4 ? 1 pa to pd, pe2 to pe7, pf to pg, pi to pj, pk3 to pk7 extal tex rst ? 2 pa to pd ? 3 , pf to pg ? 3 , pi to pk ? 3 item symbol pins conditions min. pa to pd ? 3 , pf to pg ? 3 , pi to pk ? 3 , pe, an0 to an3 rst ? 2 ph typ. 1.5 40 40 10 10 400 45 10 50 max. unit dc characteristics (v dd = 4.5 to 5.5v) electrical characteristics (ta = 20 to +75 c, v ss = 0v reference) v oh v ol i ihe i ile i iht i ilt i ilr i il i iz open drain output leakage current (n-ch tr off state) l loh v dd = 4.5v, i oh = 1.0ma v dd = 4.5v, i oh = 1.2ma v dd = 4.5v, i oh = 0.5ma 4.0 3.5 4.0 3.5 0.4 0.6 v v v dd = 4.5v, i oh = 2.4ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma
18 CXP7400P10 supply current ? 4 item symbol pins conditions min. 50 62 ma ma a a 43 1.8 9.0 80 a 13 40 10 pa to pd, pe0 to pe1, pf to pg, pi to pk, an0 to an3, extal, rst clock 1mhz 0v for all pins excluding measured pins v dd = 5v 0.5v sleep mode v dd = 5v 0.5v 24mhz crystal oscillation (c 1 = c 2 = 15pf) v dd i dd1 i dds1 i dd2 i dds2 i dds3 c in typ. max. unit ? 1 this case applies that port b buffer capability switching register (bufb: 010f4h, bits 6 and 5 = "1, 1") and ports g/i/k buffer capability switching register (bufg: 010f5h, bits 0, 3, 4, 5 and 6 = "1, 1, 1, 1, 1") are on. ? 2 rst pin specifies the input current when the pull-up resistor is selected, and specifies the leakage current when no resistor is selected. ? 3 pa to pd, pf to pg and pi to pk pins specify the input current when the pull-up resistor is selected, and specify the leakage current when no resistor is selected. ? 4 when all output pins are open. v dd = 3v 0.3v sleep mode v dd = 3v 0.3v 32khz crystal oscillation (c 1 = c 2 = 47pf) stop mode (termination of extal and tex pins crystal oscillation) v dd = 5v 0.5v input capacity pf 20 10
19 CXP7400P10 dc characteristics (v dd = 2.7 to 3.3v) electrical characteristics (ta = 20 to +75 c, v ss = 0v reference) v dd = 2.7v, i ol = 4.5ma v dd = 3.3v, v ih = 3.3v v dd = 3.3v, v il = 0.3v v dd = 3.3v, v il = 3.3v v dd = 3.3v, v il = 0.4v v dd = 3.3v, v il = 0.3v v dd = 3.3v, v il = 2.7v v dd = 3.3v v i = 0, 3.3v v dd = 3.3v v oh = 12v high level output voltage low level output voltage input current i/o leakage current 0.3 0.3 0.1 0.1 0.9 1.0 v v v v v a a a a a a a a a pd, ph pa to pd, pe2 to pe7, pf to pg, pi to pj, pk3 to pk7 pb5, pb6 ? 1 , pg0 ? 1 , pi5, pi6 ? 1 , pk3, pk4 ? 1 pa to pd, pe2 to pe7, pf to pg, pi to pj, pk3 to pk7 extal tex rst ? 2 pa to pd ? 3 , pf to pg ? 3 , pi to pk ? 3 item symbol pins conditions min. pa to pd ? 3 , pf to pg ? 3 , pi to pk ? 3 , pe, an0 to an3 rst ? 2 ph typ. 0.9 20 20 10 10 200 20 10 50 max. unit v oh v ol i ihe i ile i iht i ilt i ilr i il i iz open drain output leakage current (n-ch tr off state) l loh v dd = 2.7v, i oh = 0.24ma v dd = 2.7v, i oh = 0.45ma v dd = 2.7v, i oh = 0.12ma 2.5 2.1 2.5 2.1 0.25 0.4 v v v dd = 2.7v, i oh = 0.90ma v dd = 2.7v, i ol = 1.0ma v dd = 2.7v, i ol = 1.4ma
20 CXP7400P10 supply current ? 4 item symbol pins conditions min. 12 30 ma ma a 0.7 3.5 10 pa to pd, pe0 to pe1, pf to pg, pi to pk, an0 to an3, extal, rst clock 1mhz 0v for all pins excluding measured pins v dd = 3.0v 0.3v ? 3 sleep mode v dd = 3.0v 0.3v 12mhz crystal oscillation (c 1 = c 2 = 15pf) v dd i dds1 i dd1 i dds3 c in typ. max. unit stop mode (termination of extal and tex pins crystal oscillation) v dd = 3.0v 0.3v input capacity pf 20 10 ? 1 this case applies that port b buffer capability switching register (bufb: 010f4h, bits 6 and 5 = "1, 1") and ports g/i/k buffer capability switching register (bufg: 010f5h, bits 0, 3, 4, 5 and 6 = "1, 1, 1, 1, 1") are on. ? 2 rst pin specifies the input current when the pull-up resistor is selected, and specifies the leakage current when no resistor is selected. ? 3 pa to pd, pf to pg and pi to pk pins specify the input current when the pull-up resistor is selected, and specify the leakage current when no resistor is selected. ? 4 when all output pins are open.
CXP7400P10 21 ? 1 t sys indicates three values according to the contents of the clock control register (clc: 000feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper two bits = 00 ), 4000/fc (upper two bits = 01 ), 16000/fc (upper two bits = 11 ) extal t xh t xl t cf t cr 0.4v (v dd = 4.5 to 5.5v) v dd 0.4v (v dd = 4.5 to 5.5v) 1/fc v dd 0.2v 0.2v aaaa aaaa aaaa aaaa crystal oscillation ceramic oscillation extal xtal external clock extal xtal 74hc04 c 1 c 2 aaaa aaaa 32khz clock applied conditions crystal oscillation tex tx c 1 c 2 tex ec0 ec1 ec2 t eh t el t ef t er 0.2v dd 0.8v dd t th t tl t tf t tr ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise time, fall time event count input clock pulse width event count input clock rise time, fall time system clock frequency event count input clock pulse width event count input clock rise time, fall time f c t xl , t xh t cr , t cf t eh , t el t er , t ef f c t tl , t th t tr , t tf xtal extal extal extal ec ec tex tx tex tex mhz ns ns ns ms khz s ms item symbol pin conditions min. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 v dd = 2.7 to 5.5v fig. 2 (32khz clock applied condition) fig. 3 fig. 3 1 1 28 37.5 t sys + 50 ? 1 10 typ. 32.768 max. 24 12 200 20 20 (ta = 20 to +75 c, v dd = 2.7 to 5.5v, vss = 0v reference) fig. 2. clock applied conditions fig. 1. clock timing fig. 3. event count clock timing v dd = 4.5 to 5.5v v dd = 4.5 to 5.5v
22 CXP7400P10 note 1) t sys indicates three values according to the contents of the clock control register (clc: 000feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = 00 ), 4000/fc (upper 2 bits = 01 ), 16000/fc (upper 2 bits = 11 ) note 2) cs, sck, si and so represent cs0, sck0, si0 and so0 for ch0; they represent cs1, sck1, si1 and so1 for ch1, respectively. note 3) the load of sck output mode and so output delay time is 50pf + 1ttl. note 4) this case applies that port i/k output buffer capability switching register (bufg: 010f5h, bits 6, 5, 4 and 3 = "0, 0, 0, 0") is off. (2) serial transfer (ch0, ch1) (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) cs sck delay time cs sck floating delay time cs so delay time cs so floating delay time cs high level width t sys + 200 2 t sys + 200 8000/fc t sys + 100 4000/fc 50 t sys + 100 200 2 t sys + 200 100 1.5 t sys + 200 1.5 t sys + 200 1.5 t sys + 200 1.5 t sys + 200 2 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns item symbol pin conditions min. max. unit chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck cycle time sck high and low level width si input setup time (for sck ) si input hold time (for sck ) sck so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck1 sck0 sck1 so0 so1 so0 so1 cs0 cs1 sck0 sck1 sck0 sck1 si0 si1 si0 si1 so0 so1
23 CXP7400P10 note 1) t sys indicates three values according to the contents of the clock control register (clc: 000feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = 00 ), 4000/fc (upper 2 bits = 01 ), 16000/fc (upper 2 bits = 11 ) note 2) cs, sck, si and so represent cs0, sck0, si0 and so0 for ch0; they represent cs1, sck1, si1 and so1 for ch1, respectively. note 3) the load of sck output mode and so output delay time is 50pf. note 4) this case applies that port i/k output buffer capability switching register (bufg: 010f5h, bits 6, 5, 4 and 3 = "1, 1, 1, 1") is on. serial transfer (ch0, ch1) (ta = 20 to +75 c, v dd = 2.7 to 3.3v, vss = 0v reference) cs sck delay time cs sck floating delay time cs so delay time cs so floating delay time cs high level width t sys + 200 2 t sys + 200 8000/fc t sys + 100 4000/fc 100 t sys + 100 200 2 t sys + 200 100 1.5 t sys + 250 1.5 t sys + 250 1.5 t sys + 250 1.5 t sys + 250 2 t sys + 250 125 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns item symbol pin conditions min. max. unit chip select transfer mode (sck = output mode) chip select transfer mode (sck = output mode) chip select transfer mode chip select transfer mode chip select transfer mode input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck cycle time sck high and low level widths si input setup time (for sck ) si input hold time (for sck ) sck so delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck1 sck0 sck1 so0 so1 so0 so1 cs0 cs1 sck0 sck1 sck0 sck1 si0 si1 si0 si1 so0 so1
24 CXP7400P10 cs0 cs1 sck0 sck1 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.2v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 si1 t sik t ksi input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0 so1 fig. 4. serial transfer ch0, ch1 timing
25 CXP7400P10 serial transfer (ch2) (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item symbol pin min. max. unit conditions sck cycle time sck high and low level widths si input setup time (for sck ) si input hold time (for sck ) sck so delay time t kcy t kh t kl t sik t ksi t kso sck2 sck2 si2 si2 so2 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 1000 8000/fc 400 4000/fc 50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns note 1) t sys indicates three values according to the contents of the clock control register (clc: 000feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = 00 ), 4000/fc (upper 2 bits = 01 ), 16000/fc (upper 2 bits = 11 ) note 2) sck, si and so represent sck2, si2 and so2 for ch2, respectively. note 3) the load of sck2 output mode and so2 output delay time is 50pf + 1ttl. note 4) this case applies that port b output buffer capability switching register (bufb: 010f4h, bits 6 and 5 = 0, 0 ) is off. serial transfer (ch2) (ta = 20 to +75 c, v dd = 2.7 to 3.3v, vss = 0v reference) note 1) t sys indicates three values according to the contents of the clock control register (clc: 000feh) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = 00 ), 4000/fc (upper 2 bits = 01 ), 16000/fc (upper 2 bits = 11 ) note 2) sck, si and so represent sck2, si2 and so2 for ch2, respectively. note 3) the load of sck2 output mode and so2 output delay time is 50pf. note 4) this case applies that port b output buffer capability switching register (bufb: 010f4h, bits 6 and 5 = 1, 1 ) is on. item symbol pin min. max. unit conditions sck cycle time sck high and low level widths si input setup time (for sck ) si input hold time (for sck ) sck so delay time t kcy t kh t kl t sik t ksi t kso sck2 sck2 si2 si2 so2 input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode 1000 8000/fc 400 4000/fc 100 100 200 200 100 250 125 ns ns ns ns ns ns ns ns ns ns
26 CXP7400P10 fig. 5. serial transfer ch2 timing t kcy t kl t kh 0.2v dd 0.8v dd t sik t ksi t kso input data output data 0.2v dd 0.8v dd 0.2v dd 0.8v dd sck2 si2 so2
27 CXP7400P10 analog input linearity error v ft v zt 00h 01h feh ffh digital conversion value (3) a/d converter characteristics (ta = 20 to +75 c, v dd = av dd = 4.5 to 5.5v, av ref = 4.0 to av dd , vss = av ss = 0v reference) fig. 6. definition of a/d converter terms ? 1 v zt : value at which the digital conversion value changes from 00h to 01h and vice versa. ? 2 v ft : value at which the digital conversion value changes from feh to ffh and vice versa. ? 3 f adc indicates the below values due to the contents of bit 6 (cks) of the a/d control register (adc: 000f9h). ps3 selected f adc = fc/4 ps4 selected f adc = fc/8 however, when ps3 is selected, fc is 12mhz or less. ? 4 sub clock operated t conv = 34/f tex t samp = 10/f tex resolution linearity errror absolute error conversion time sampling time reference input voltage analog input voltage av ref current t conv t samp v ref v ian i ref i refs av ref an0 to an11 av ref v dd = av dd = 4.5 to 5.5v operation mode sleep mode stop mode 32khz operation mode item symbol pin conditions min. typ. max. unit bits lsb lsb s s v v ma a 8 2 3 1.0 10 0.6 31/f adc ? 3 , ? 4 10/f adc ? 3 , ? 4 av dd 0.5 0 ta = 25 c v dd = av dd = av ref = 5.0v v ss = av ss = 0v resolution linearity errror absolute error conversion time sampling time reference input voltage analog input voltage av ref current t conv t samp v ref v ian i ref i refs av ref an0 to an11 av ref v dd = av dd = 2.7 to 3.3v operation mode sleep mode stop mode 32khz operation mode item symbol pin conditions min. typ. max. unit bits lsb lsb s s v v ma a (ta = 20 to +75 c, v dd = av dd = 2.7 to 3.3v, av ref = 2.7 to av dd , vss = av ss = 0v reference) 8 2 3 0.7 10 0.4 31/f adc ? 3 , ? 4 10/f adc ? 3 , ? 4 av dd 0.3 0 ta = 25 c v dd = av dd = av ref = 3.0v v ss = av ss = 0v
28 CXP7400P10 0.2v dd 0.8v dd t ih t il t il t ih int0 int1 int2 int3 int4 nmi (nmi is specified only for the falling edge) t rsl 0.2v dd rst external interruption high and low level widths reset input low level width int0 int1 int2 int3 int4 nmi rst 1 32/fc s s item symbol pin conditions min. max. unit t ih t il t rsl (4) interruption, reset input fig. 7. interruption input timing fig. 8. rst input timing (ta = 20 to +75 c, v dd = 2.7 to 5.5v, vss = 0v reference)
29 CXP7400P10 appendix fig. 9. recommended oscillation circuit c 2 rd aaaaa aaaaa extal xtal c 1 (i) main clock aaaaa aaaaa tex tx c 1 c 2 rd (iii) sub clock rd aaaa aaaa extal xtal c 1 c 2 (ii) main clock a a a a aa manufacturer river eletec corporation murata mfg co., ltd. csa10.0mtz csa12.0mtz csa16.00mxz040 cst10.0mtw ? cst12.0mtw ? cst16.00mxw0c1 ? kinseki ltd. seiko instruments inc. model hc-49/u03 hc-49/u (-s) vtc-200 sp-t fc (mhz) 10.0 12.0 16.0 10.0 12.0 16.0 8.0 12.0 16.0 8.0 12.0 16.0 30 5 30 5 18 12 10 10 5 open 18 30 5 30 5 18 12 10 10 5 open 18 0 ? 1 330 ? 1 0 ? 1 32.768khz 330k (iii) c 1 (pf) c 2 (pf) rd ( ? ) circuit example (i) ? indicates types with on-chip grounding capacitor (c1, c2). ? 1 xtal series resistor (rd = 500 ? or less) is hard to affect noise by esd. (i) (ii) c l = 12.5pf remarks
30 CXP7400P10 characteristics curve 20 (100a) 3 45 6 0.1 5.0 1.0 v dd supply voltage [v] i dd supply current [ma] i dd vs. v dd (fc = 24mhz, ta = 25 c, typical) 2 0.05 (50a) 0.01 (10a) 0.5 10.0 20.0 1/16 dividing mode 1/4 dividing mode sleep mode 32khz operation mode 0 20 10 fc system clock [mhz] i dd supply current [ma] i dd vs. fc (v dd = 5.0v, ta = 25 c, typical) 10 30 1/2 dividing mode 32khz sleep mode 24 1/2 dividing mode 1/16 dividing mode sleep mode 1/4 dividing mode 0 (100a) 3 45 6 0.1 5.0 1.0 v dd supply voltage [v] i dd supply current [ma] i dd vs. v dd (fc = 12mhz, ta = 25 c, typical) 2 0.05 (50a) 0.01 (10a) 0.5 10.0 20.0 1/16 dividing mode 1/4 dividing mode sleep mode 1/2 dividing mode 20 0 20 10 fc system clock [mhz] i dd supply current [ma] i dd vs. fc (v dd = 3.0v, ta = 25 c, typical) 10 30 24 1/2 dividing mode 1/16 dividing mode sleep mode 1/4 dividing mode 0 40 40 50.0 50.0
31 CXP7400P10 package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 23.9 0.4 qfp-100p-l01 100pin qfp (plastic) 20.0 0.1 + 0.4 0.15 0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 0.1 + 0.4 2.75 0.15 + 0.35 a 0.65 m 0.13 qfp100-p-1420 1.7g 1 100 81 80 51 50 31 30 0.3 0.1 + 0.15 detail a 0 ? to 10 ? 0.8 0.2 (16.3) 0.15 0.1 0.05 + 0.2 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 23.9 0.4 qfp-100p-l01 100pin qfp (plastic) 20.0 0.1 + 0.4 0.15 0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 0.1 + 0.4 2.75 0.15 + 0.35 a 0.65 m 0.13 qfp100-p-1420 1.7g 1 100 81 80 51 50 31 30 0.3 0.1 + 0.15 detail a 0 ? to 10 ? 0.8 0.2 (16.3) 0.15 0.1 0.05 + 0.2 lead plating specifications item lead material 42 alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec.
32 CXP7400P10 package outline unit: mm 100pin lqfp (plastic) 25 26 51 50 75 76 1 100 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy package structure detail a lqfp-100p-l01 p-lqfp100-14x14-0.5 16.0 0.2 14.0 0.1 0.5 b (0.22) a 1.5 ?0.1 + 0.2 0.5 0.2 (15.0) 0? to 10? 0.1 0.1 0.5 0.2 0.1 note: dimension " ? " does not include mold protrusion. 0.7g 0.13 m b = 0.18 ?0.03 ( 0.18 ) (0.127) + 0.08 0.127 ?0.02 + 0.05 detail b ? b 100pin lqfp (plastic) 25 26 51 50 75 76 1 100 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy package structure detail a lqfp-100p-l01 p-lqfp100-14x14-0.5 16.0 0.2 14.0 0.1 0.5 b (0.22) a 1.5 0.1 + 0.2 0.5 0.2 (15.0) 0 ? to 10 ? 0.1 0.1 0.5 0.2 0.1 note: dimension " ? " does not include mold protrusion. 0.7g 0.13 m b = 0.18 0.03 ( 0.18 ) (0.127) + 0.08 0.127 0.02 + 0.05 detail b ? b lead plating specifications item lead material 42 alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec. sony corporation

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