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cmos 8-bit single chip microcomputer description the CXP825P40 is a highly integrated cmos 8-bit single chip microcomputer which is mainly composed of an 8-bit cpu, prom, ram, and i/o ports. this microcomputer features many other high-performance circuits in a single chip cmos design, including an a/d converter, serial interface, timer/counter, time- base timer, capture timer/counter, fluorescent display tube controller/driver, remote control receiver. also, the CXP825P40 provides the power-on reset function as well as the sleep/stop function which assures reduced power consumption. being a prom-incorporated version of the cxp82540 which has on-chip mask rom, the CXP825P40 permits program writing. therefore, it is ideally suited for use in system development stage evaluation and job lot procuction. features instruction set which supports a wide array of data types 213 types 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation instruction minimum instruction cycle during operation 400ns/10mhz incorporated prom capacity 40k bytes incorporated ram capacity 1120 bytes (including the fluorescent display data area) peripheral functions ?a/d converter 8-bit, 8-channel, successive comparison type (conversion time: 32s at 10mhz) ?serial interface 1-channel data interface with an 8-bit, 8-stage fifo (1 to 8 bytes automatic transfer) 1 channel, 8-bit clock synchronized interface ?timers 8-bit timer 8-bit timer/counter 19-bit time-base timer 16-bit capture timer/counter ?fluorescent display tube controller/driver display of up to 336 segments 1 to 16 digits dynamic display dimmer function high voltage tolerance output (40v) built-in pull-down resistor ?remote control receiver built-in noise suppressor circuit built-in 8-bit pulse counter and 6-stage fifo interrupts 14 factors, 15 vectors, multiple interrupt processing standby mode sleep/stop package 80-pin plastic qfp ?1 e92y33b1y-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP825P40 80 pin qfp (plastic) structure silicon gate cmos ic
?2 CXP825P40 int0 an0 to an7 t0 to t7 t8/s28 t15/s21 s0 to s20 v fdp rmc cs0 si0 so0 sck0 ec0 to cint ec1 a/d converter fdp controller/ driver remocon 8 bit timer/counter 0 8 bit timer 1 16 bit capture timer/counter 2 ram 80 bytes fifo serial interface unit 0 fifo interrupt controller spc700 cpu core prom 40k bytes clock generator/ system control ram 1120 bytes 2 2 prescaler/ time base timer 8 8 8 21 int1 int2 int3 vpp v dd rst xtal extal port a port b port c port d port e port f port g 4 8 8 7 8 6 2 pa0 to pa7 pb0 to pb6 pc0 to pc7 pd0 to pd7 pe0 to pe5 pe6 to pe7 pf0 to pf7 pg0 to pg3 si1 so1 sck1 serial interface unit 1 8 pb7 v ss block diagram
3 CXP825P40 pe3/int3 pe4/rmc pe5 pe6 pe7/to pb0/cint pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 pc0/kr0 pc1/kr1 pc2/kr2 pc3/kr3 pc4/kr4 pc5/kr5 pc6/kr6 pc7/kr7 pa0/an0 pa1/an1 pa2/an2 t7 t8/s28 t9/s27 t10/s26 t14/s22 t15/s21 s20 s19 s18 s17 s16 pf5/s13 pf4/s12 pf3/s11 pf2/s10 pf1/s9 pf0/s8 pd7/s7 pa3/an3 pa4/an4 pa5/an5 rst extal xtal v ss pd0/s0 pd1/s1 pd2/s2 vpp pe2/in2 pg2 pg1 pg0 v dd v fdp t0 t1 t2 t3 t4 t5 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 73 74 75 76 77 78 79 80 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 t12/s24 t13/s23 t11/s25 pa6/an6 pa7/an7 40 39 38 37 36 35 pd3/s3 pd4/s4 pd5/s5 pd6/s6 pf7/s15 pf6/s14 t6 pe1/ec1/int1 pe0/ec0/int0 pg3 13 72 note) vpp (pin 73) is always connected to v dd. pin assignment (top view)
CXP825P40 4 pin description (port a) 8-bit i/o port; single bit addressable. (8 pins) (port b) single bit addressable from amongst lower 7 bits; highest bit (pb7) dedicated to output. (8 pins) (port c) 8-bit i/o port; single bit addressable. can provide 12ma sink current. (8 pins) (port e) 8-bit port with lower 6 bits dedicated to input and upper 2 bits dedicated to output. (8 pins) analog input to a/d converter. (8 pins) external capture input for 16-bit timer/counter. chip select input for serial interface (ch0). serial clock (ch0) i/o. serial data (ch0) input. serial data (ch0) output. serial clock (ch1) i/o. serial data (ch1) input. serial data (ch1) output. key return input for fdp segment signal which performs key scanning. input for external interrupt requests. (4 pins) input for remote control receiver circuit. output pin for 16-bit timer/counter rectangular waveform. symbol i/o description pa0/an0 to pa7/an7 pb0/cint pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 pc0/kr0 to pc7/kr7 pe0/int0/ec0 pe1/int1/ec1 pe2/int2 pe3/int3 pe4/rmc pe5 pe6 pe7/to pg0 to pg3 pf0/s8 to pf7/s15 s16 to s20 t8/s28 to t15/s21 t0 to t7 pd0/s0 to pd7/s7 i/o/analog input i/o/input i/o/input i/o/i/o i/o/input i/o/output i/o/i/o i/o/input output/output i/o/input input/input/input input/input/input input/input input/input input/input input output output/output i/o output/output output output/output output output/output (port g) 4-bit i/o port; single bit addressable. (4 pins) (port f) 8-bit dedicated output port. (8 pins) segment signal output for fdp. dual purpose output for fdp timing and segment signals. timing signal output for fdp. (port d) 8-bit dedicated output port. (8 pins) segment signal output for fdp. external event input to timer/counter. (2 pins) segment signal output for fdp.
5 CXP825P40 provides voltage for fdp. connection for system clock oscillation crystal. when using an external clock, input normal signal to the extal pin and reverse phase signal to the xtal pin. system reset, active "l". the rst pin is an input/output pin which outputs a "l" level when the power is turned on and the on-chip power-on reset circuit. positive power supply for the programmable on-chip prom; connect to v dd for normal operation. positive power supply pin. gnd symbol i/o description v fdp extal xtal rst vpp v dd v ss input output i/o
6 CXP825P40 when reset pin circuit format input/output circuit formats for pins ip rd (port b) data bus port b direction port b output select "0" when reset sck in schmitt input port b data "0" when reset sck out output enable hi-z hi-z hi-z pb0/cint pb1/cs0 pb3/si0 pb6/si1 pb2/sck0 pb5/sck1 port b port b 2 pins port a ip input multiplexer rd (port a) data bus port a direction port a data "0" when reset port a input select "0" when reset a/d converter input protection circuit ip rd (port b) data bus port b direction port b data "0" when reset cint cs0 si0 si1 schmitt input pa0/an0 to pa7/an7 8 pins 4 pins
7 CXP825P40 when reset pin circuit format ip rd (port b) data bus port b direction port b output select "0" when reset port b data "0" when reset so output enable port b port c port e 1 pin high level hi-z hi-z pb4/so0 pb7/so1 1 pin 8 pins hi-z pc0/kr0 to pc7/kr7 5 pins pe0/ec0/int0 pe1/ec1/int1 pe2/int2 pe3/int3 pe4/rmc port b ip rd (port c) data bus port c direction port c data "0" when reset key input signal ? capable of driving 12ma large current ? ? ? pull-up transistor about 200k ?
8 CXP825P40 when reset pin circuit format port e port e port e hi-z 1 pin pe5 ip data bus rd (port e) high level 1 pin pe6 port e data "1" when reset high level 1 pin pe7/to port g hi-z 4 pins pg0 to pg3 rd (port e) data bus port e output select "1" when reset port e data "0" when reset output enable (t2oe) to ip rd (port g) data bus port g direction port g data "0" when reset
9 CXP825P40 v fdp ? ("0" when reset) segment output data output select control signal ? high voltage tolerance transistor mask option pull-down resistor op 21 pins oscillation low level when reset s16 to s20 t15/s21 to t8/s28 t0 to t7 extal xtal 2 pins 1 pin rst low level port d port f pin circuit format ip ip extal xtal ? diagram shows circuit construction for oscillation. ? during stop feedback resistor is disconnected. mask option ip schmitt input pull-up resistor from power-on reset circuit op hi-z 16 pins pd0/s0 to pd7/s7 pf0/s8 to pf7/s15 ? rd (port d or port f) data bus "0" when reset port d data or port f data ("0" when reset) segment output data output select control signal ? high voltage tolerance transistor
10 CXP825P40 ? 1 v in and v out cannot exceed v dd + 0.3v. ? 2 rating for output current of general input/output port. ? 3 the large current drive transistor is an n-channel transistor of port c. note) if the absolute maximum ratings are exceeded, the lsi could reach permanent breakdown. also, observing recommended operating conditions is desirable; otherwise, the lsi's reliability could be affected. supply voltage input voltage output voltage display output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd v in v out v od i oh i odh1 i odh2 i oh i odh i ol i olc i ol topr tstg p d as p channel transistor is open drain, v dd voltage is determined as standerd. other than display output pins ? 2 : per pin display outputs s0 to s20: per pin display outputs t0 to t7, t8/s28 to t15/s21: per pin total of pins other than display output pins total of display output pins port 1 pin large current port pin ? 3 : per pin entire pin total item symbol rating unit remarks absolute maximum ratings (vss = 0v) 0.3 to +7.0 0.3 to +7.0 ? 1 0.3 to +7.0 ? 1 v dd 40 to v dd + 0.3 5 15 35 40 100 15 20 100 10 to +75 55 to +150 600 v v v v ma ma ma ma ma ma ma ma c c mw
11 CXP825P40 high level input voltage low level input voltage operating temperature supply voltage 5.5 5.5 5.5 v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v c v item symbol min. max. unit remarks 4.5 3.5 2.5 0.7v dd 0.8v dd v dd 0.4 0 0 0.3 10 v ih v ihs v ihex v il v ils v ilex topr high-speed mode (1/2, 1/4 clock) guaranteed operation range low-speed mode(1/16clock) guaranteed operation range guaranteed data hold operation range during stop ? 1 hysteresis input ? 2 extal pin ? 3 ? 1 hysteresis input extal pin ? 3 v dd ? 1 all regular input ports (pa, pb3, pb4, pb6, pc, pe5, pg). ? 2 for pins rst, cint, cs0, sck0, sck1, ec0/int0, ec1/int1 , int2, int3, rmc. ? 3 rating only for external clock input. recommended operating conditions (vss = 0v)
12 CXP825P40 v dd = 4.5v, i oh = 0.5ma v dd = 4.5v, i oh = 1.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 0.4v high level output voltage 4.0 3.5 0.5 0.5 1.5 8 20 60 v v v v v a a a ma ma a k ? a ma ma a pf pc extal rst item symbol pins conditions min. v dd i dd1 i ddsl i ddst i oh i lol c in v oh v ol i ihe i ile i ilr low level output voltage input current typ. 0.4 0.6 1.5 40 40 400 20 270 10 40 8 30 20 max. unit electrical characteristics dc characteristics (ta = 10 to +75 c, vss = 0v) 10mhz crystal oscillator (c 1 = c 2 = 15pf) sleep mode stop mode supply current ? 1 input capacitance v dd = 4.5v v oh = v dd 2.5v v dd = 5.5v v ol = v dd 35v v fdp = v dd 35v v dd = 5.5v high-speed mode (1/2 clock) operation 1mhz clock 0v for pins other than the measured pins. display output current i iz input/output leak current open drain output leak current (p-ch tr off state) s0 to s20 s21/t15 to s28/t8 t0 to t7 s0 to s20 s21/t15 to s28/t8 t0 to t7 r l v dd = 5v v od v fdp = 30v v dd = 5.5v v i = 0, 5.5v pull-down resistor s0 to s20 s21/t15 to s28/t8 t0 to t7 pa to pc, pe, pg 100 25 3 10 pa, pb, pc,pe6, pe7, pg, rst (for v ol only) for pins other than s0 to s28, t0 to t7, pb7, pe6, pe7, v dd , v ss , v fdp ? 1 all output pins are left open.
13 CXP825P40 ? t sys is determind by the upper two bits of the clock control register (address: 00fe h ; cpu clock selected) resulting in one of the 3 following values: t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") extal t xh t xl t cf t cr 0.4v v dd 0.4v 1/fc aaaaa a aaa a aaaaa external clock extal xtal 74hc04 aaaa a aa a aaaa crystal oscillation ceramic oscillation extal xtal c 1 c 2 ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rising and falling times event count input clock pulse width event count input clock rising and falling times f c t xl , t xh t cr , t cf t eh , t el t er , t ef xtal extal extal extal ec0, ec1 ec0, ec1 mhz ns ns ns ms item symbol pins conditions unit fig. 1, fig. 2 fig. 1, fig. 2 external clock driver fig. 1, fig. 2 external clock driver fig. 3 fig. 3 min. 1 45 t sys + 50 ? max. 10 200 20 (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) fig. 1. clock timing fig. 2. clock applying condition t eh t el t ef t er 0.2v dd 0.8v dd t th t tl t tf t tr ec0 ec1 fig. 3. event count clock timing
14 CXP825P40 chip select transfer mode (sck0 = output mode) chip select transfer mode (sck0 = output mode) chip select transfer mode chip select transfer mode chip select transfer mode input mode output mode input mode output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode note 1) t sys is determind by the upper two bits of the clock control register (address: 00fe h ; cpu clock selected) resulting in one of the 3 following values: t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) the load of sck0 output mode and so0 output delay time is 50pf + 1ttl. (2) serial transfer (ch0) (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) item cs0 sck0 delay time cs0 sck0 float delay time cs0 so0 delay time cs0 so0 float delay time cs0 high level width sck0 cycle time sck0 high and low level width si0 input setup time (against sck0 ) si0 input hold time (against sck0 ) sck0 so0 delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 symbol pin min. t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 100 t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc 50 100 200 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns max. unit condition
15 CXP825P40 fig. 4. serial transfer ch0 timing cs0 sck0 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.2v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 t sik t ksi input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0 15
16 CXP825P40 serial transfer (ch1) (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) item symbol pin min. max. condition sck1 cycle time sck1 high and low level width si1 input setup time (against sck1 ) si1 input hold time (against sck1 ) sck1 so1 delay time t kcy t kh t kl t sik t ksi t kso sck1 sck1 si1 si1 so1 input mode output mode input mode output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode 1000 16000/fc 400 8000/fc 50 100 200 200 100 200 100 unit ns ns ns ns ns ns ns ns ns ns note) the load of sck1 output mode and so1 output delay time is 50pf + 1ttl. fig. 5. serial transfer ch1 timing sck1 si1 so1 t kcy t kl t kh 0.2v dd 0.8v dd t sik t ksi t kso input data output data 0.2v dd 0.8v dd 0.2v dd 0.8v dd
17 CXP825P40 (3) a/d converter characteristics (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) v zt ? 1 v ft ? 2 t conv t samp v ian a/d converter operation only ta = 25 c v dd = 5.0v v ss = 0v 10 4930 160/f adc ? 3 12/f adc ? 3 0 item symbol pin condition min. typ. max. unit bits resolution linearity error zero transition voltage full-scale transition voltage conversion time sampling time analog input voltage 8 3 150 5120 v dd 70 5050 lsb mv mv s s v analog input linearity error 00 h 01 h fe h ff h digital conversion value v zt v ft fig. 6. definition of a/d converter terms an0 to an7 ? 1 v zt : digital value converted between 00 h and 01 h. ? 2 v ft : digital value converted between fe h and ff h . ? 3 f adc : adc operation clock selection (msc: bit 0 of address 01ff h ) and assumes following values: f adc = fc/2 when ps2 is selected. f adc = fc when ps1 is selected.
18 CXP825P40 external interrupt low and high level widths reset input low level width int0 int1 int2 int3 rst 1 8/fc s s item symbol pin condition min. max. unit t ih t il t rsl (4) interrupts, reset inputs (ta = 10 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) 0.8v dd 0.2v dd t ih t il int0 int1 int2 int3 t il t ih 0.8v dd 0.2v dd fig. 7. interrupt input timing t rsl 0.2v dd rst fig. 8. rst input timing 0.2v 0.2v 4.5v v dd t off t r the power supply should be rise smoothly. fig. 9. power-on reset power supply rising time power supply cut-off time t r t off v dd item symbol pin condition min. max. unit ms ms (5) power-on reset power-on reset ? (ta = 10 to +75 c, v dd = 4.5 to 5.5v, v ss = 0v) ? specifies only when power-on reset function is selected. 50 power-on reset repetitive power-on reset 0.05 1
19 CXP825P40 supplement aaaa a aa a aaaa extal xtal c 1 c 2 (i) aaaa a aa a aaaa extal xtal c 2 (ii) c 1 manufacturer murata mfg co., ltd river eletec corporation kinseki ltd. csa4.19mg csa8.00mtz csa10.0mtz cst4.19mgw ? cst8.00mtw ? cst10.0mtw ? hc-49/u03 hc-49/u (-s) model fc (mhz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 30 15 27 30 15 27 c 1 (pf) c 2 (pf) circuit example (i) (ii) (i) ? indicates types with on-chip grounding capacitors (c 1 and c 2 ). product list optional item package rom capacity reset pin pull-up resistor power-on reset circuit high voltage tolerance pin pull-down resistor 80 pin plastic qfp 32k byte/40k bytes existent/non existent existent/non existent existent/non existent 80 pin plastic qfp prom 40k bytes existent existent non existent (s0/pd0 to s15/pf7) existent (t0 to s16) mask CXP825P40q-1- note on operation vpp (pin 73) is always connected to v dd . fig. 10. recommended oscillation circuit
20 CXP825P40 package outline unit: mm package structure sony code eiaj code jedec code qfp-80p-l01 qfp080-p-1420 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy 1.6g 23.9 0.4 20.0 ?0.1 + 0.4 1 80 65 64 41 40 25 24 0.8 0.35 ?0.1 + 0.15 14.0 ?0.1 + 0.4 17.9 0.4 16.3 0.1 ?0.05 + 0.2 2.75 ?0.15 + 0.35 0.8 0.2 0.15 ?0.05 + 0.1 80pin qfp (plastic) m 0.2 0.15 0? to 10? detail a a package structure sony code eiaj code jedec code qfp-80p-l01 qfp080-p-1420 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy 1.6g 23.9 0.4 20.0 0.1 + 0.4 1 80 65 64 41 40 25 24 0.8 0.35 0.1 + 0.15 14.0 0.1 + 0.4 17.9 0.4 16.3 0.1 0.05 + 0.2 2.75 0.15 + 0.35 0.8 0.2 0.15 0.05 + 0.1 80pin qfp (plastic) m 0.2 0.15 0 ? to 10 ? detail a a lead plating specifications item lead material 42 alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec. sony corporation

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