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cmos 4-bit single chip microcomputer description CXP5076/5078 is a cmos 4-bit microcomputer which consists of 4-bit cpu, rom, ram, i/o port, 8-bit timer, 8-bit timer/counter, 18-bit time base timer, 8-bit serial i/o, vector interruption, power on reset function, liquid crystal displayer (lcd) controller/driver, d/a conversion 14-bit pwm output port, a remote control reception circuit with noise eliminating circuit, 3-bit a/d converters, a 32khz timer/event counter and a power supply voltage detection reset function. they are integrated into a single chip with the standby function, etc. which are to be operated at a low power consumption. features instruction cycle 1.9s/4.19mhz 122 s/32khz (possible to select with the program) rom capacity 8192 8 bits (cxp5078) 6144 8 bits (CXP5076) ram capacity 448 4 bits (including stack, display area) 43 general purpose i/o ports 8 high current output ports lcd controller/driver (possible to direct drive) ?possible to select with the program the segment output of 16 to 32 ?possible to select with the program the duty of static, 1/2, 1/3 and 1/4 ?possible to select with the program the bias of 1/2, 1/3 14-bit pwm output for d/a conversion remote control reception circuit 3-bit a/d converter (8 channels per circuit) 32khz timer/event counter power supply voltage detection reset function low voltage operation (2.5v) ..... when operating in 122s/32khz rich wake-up function 8-bit/4-bit variable serial i/o arithmetic and logical operations possible between the entire rom area, i/o area and the accumulator by means of the memory mapped i/o 8-bit timer, 8-bit timer/event counter and 18-bit time base timer, independently controlled 2 kinds of power down modes of sleep and stop power on reset circuit (mask option) provided with 80 pin plastic qfp provided with 80 pin piggyback qfp (cxp5070) structure silicon gate cmos ic ?1 e88037a78-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP5076/5078 80 pin qfp (plastic)
? 2 CXP5076/5078 block diagram p o r t a p o r t b p o r t c p o r t d p o r t e p o r t f p o r t g p o r t h p o r t i 4 4 4 4 ( c o m m o n w i t h a / d c o n v e r t e r a n a l o g i n p u t ) ( i n p u t a n d o u t p u t i s p o s s i b l e b y b i t u n i t ) ( c o m m o n w i t h s e g m e n t o u t p u t s 2 7 t o s 2 4 ) ( c o m m o n w i t h s e g m e n t o u t p u t s 3 1 t o s 2 8 ) ( c o m m o n w i t h s e g m e n t o u t p u t s 1 9 t o s 1 6 ) ( c o m m o n w i t h s e g m e n t o u t p u t s 2 3 t o s 2 0 ) ( c o m m o n w i t h a / d c o n v e r t e r a n a l o g i n p u t ) ( i n p u t a n d o u t p u t i s p o s s i b l e b y p o r t u n i t ) 4 4 4 ( i n p u t a n d o u t p u t i s p o s s i b l e b y p o r t u n i t ) 4 4 8 4 b i t s r e s i s t e r d a t a m e m o r y s t a c k d a t a m e m o r y a l u a c c u m u l a t o r f l a g t i m e r ( 8 ) s u b t i m e ( 8 ) t i m e r / c o u n t e r ( 8 ) s e r i a l i / o ( 8 ) i n t e r r u p t c o n t r o l p r o g r a m c o u n t e r ( 1 3 ) p r o g r a m m e m o r y 8 1 9 2 8 b i t s ( c x p 5 0 7 8 ) 8 1 4 4 8 b i t s ( c x p 5 0 7 6 ) p w m ( 1 4 ) a / d c o n v e r t e r r e m o t e c o n t r o l r e c e i v i n g i n s t r u c t i o n c o n t r o l t i m e b a s e t i m e r ( 1 8 ) c l o c k c o n t r o l 3 2 k h z t i m e r / e v e n t c o u n t e r p o r t x p o r t y l c d c o n t r o l l e r / d r i v e r 1 6 1 6 4 v l v l c 1 v l c 2 v l c 3 e x t a l x t a l t e x t x ( c o m m o n w i t h s e r i a l i / o ) ( c o m m o n w i t h p o r t c , p o r t d , p o r t g , p o r t h ) s e g 1 6 t o s e g 3 1 s e g 0 t o s e g 1 5 c o m 0 t o c o m 3 p x 2 / s i p x 1 / s o p x 0 / s c p y 3 / e c p y 2 / w p p y 1 / p w m p y 0 i n t v d d v s s r s t v r e f r m c
? 3 CXP5076/5078 pin configuration (top view) p g 1 / s e g 1 8 p g 2 / s e g 1 7 p g 3 / s e g 1 6 s e g 1 5 s e g 1 4 s e g 1 3 s e g 1 2 s e g 1 1 s e g 1 0 s e g 9 s e g 8 s e g 7 s e g 6 s e g 5 s e g 4 s e g 3 s e g 2 s e g 1 s e g 0 c o m 3 c o m 2 c o m 1 c o m 0 v l c 1 p d 1 / s e g 3 0 p d 0 / s e g 3 1 p y 3 / e c p y 2 / w p p e 2 p e 1 p e 0 p f 3 p f 2 p f 1 p f 0 p a 3 p a 1 p a 0 p x 2 / s i p x 1 / s o p x 0 / s c n c p b 3 / a d 7 p b 2 / a d 6 v l c 2 v l c 3 v l r m c i n t x t a l e x t a l r s t n c v d d a d 0 / p i 0 a d 1 / p i 1 a d 2 / p i 2 a d 3 / p i 3 a d 4 / p b 0 a d 5 / p b 1 n c p g 0 / s e g 1 9 p h 3 / s e g 2 0 p h 1 / s e g 2 2 p h 0 / s e g 2 3 v r e f t e x t x v s s p c 3 / s e g 2 4 p c 2 / s e g 2 5 p c 1 / s e g 2 6 p c 0 / s e g 2 7 p d 3 / s e g 2 8 p d 2 / s e g 2 9 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 7 0 6 9 6 8 6 7 6 3 6 4 6 5 6 6 6 1 6 2 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 1 p a 2 p y 0 p e 3 p y 1 / p w m p h 2 / s e g 2 1 note) do not make any connections to nc pins.
? 4 CXP5076/5078 pin description symbol name i/o equivalent circuit description supply voltage grounding voltage clock input clock output reset external interrupt remote control input port x2 serial input port x1 serial output i o i/o i i i i/o positive voltage supply pin gnd pin clock oscillation circuit input pin. connect the crystal oscillator or ceramic resonator between the extal and xtal. when using as the external clock input, connect the clock oscillation source to the extal pin and open the xtal pin. clock oscillation circuit output pin serves as the incorporated power-on reset circuit output pin. when inputting a reset signal from the outside, provide 2 instruction cycles or longer of an "l" level (0v). serves the interrupt input pin. permits the selection with a program of the edge and the level modes. remote control receiver input pin doubles as a serial interface (8 bits) input pin and as bit "2" (input) of port x. doubles as a serial interface (8 bits) output pin and as bit "1" (input) of port x. (so output possible to inhibit with the program.) e x t a l x t a l p n p n p n e m a s k o p t i o n ( n o t e 2 ) d a t a o u t p u t s e l e c t d i s a b l e s t a n d b y p n ( o n l y d u r i n g t r i - s t a t e o u t p u t ) v dd v ss extal xtal rst int rmc px2/si px1/so output pull-up resistor (p-ch tr) n-ch tr output schmitt inverter input see note 2) for the output circuit format. inverter input schmitt inverter input
? 5 CXP5076/5078 symbol name i/o equivalent circuit description port x0 serial clock port y3 event count input port y2 wake-up input port y1 pwm generator output port y0 port a port b analog voltage input port e port f port i analog voltage input i/o i i o o i/o i/o i/o i/o i/o ( n o t e 2 ) d a t a o u t p u t s e l e c t d i s a b l e s t a n d b y ( o n l y d u r i n g t r i - s t a t e o u t p u t ) px0/sc py3/ec py2/wp py1/pwm py0 pa0 to pa3 pb0/ad4 to pb3/ad7 pe0 to pe3 pf0 to pf3 pi0/ad0 to pi3/ad3 see note 2) for the output circuit format. schmitt inverter input ( n o t e 2 ) d a t a o u t p u t s e l e c t d i s a b l e s t a n d b y p n ( o n l y d u r i n g t r i - s t a t e o u t p u t ) see note 2) for the output circuit format. inverter input see note 1) for the output circuit format. schmitt inverter input doubles as shift clock input/output pin for the serial interface and as bit "0" (input) of port x. doubles as event counter (8 bits) input pin and as bit "3" (input) of port y. doubles as wake-up input pin to release the standby state and as bit "2" (input) of port y. doubles as pwm generator (14 bits) output pin and as bit "1" (output) of port y. output pin for bit "0" of port y. this 4-bit input/output port permits its each individual bit to be programmed to serve either as input or output. for the output format, a tri-state and pull- up resistor possible to be programmed , and it is also used as the standby resetting pin. this 4-bit input/output port has the functions that are equivalent to those of port a. it is also used for a/d converter input. this 4-bit input/output port permits its each individual port to be programmed to serve either as input or output. for the output format, a tri-state and pull- up resistor possible to be programmed. this 4-bit input/output port has the functions that are equivalent to those of port e. this 4-bit input/output port has the functions that are equivalent to those of port e. it is also used for a/d converter input. ( n o t e 1 ) d a t a o u t p u t s e l e c t d i s a b l e
? 6 CXP5076/5078 symbol name i/o equivalent circuit description port d segment output port c segment output port h segment output port g segment output segment output common output power supply for lcd cut-off output o o o o o o o doubles as a 4-bit output port (for the output format, the inverter and pull-up resistor possible to be programmed.) and as the segment signal output pin for lcd. doubles as a 4-bit output port (the output format is equivalent to port d.) and as the segment signal output pin for lcd. doubles as a 4-bit output port (the output format is equivalent to port d.) and as the segment signal output pin for lcd. (possible to designate in bit units.) doubles as a 4-bit output port (the output format is equivalent to port d.) and as the segment signal output pin for lcd. segment signal output pin for lcd common signal output pin for lcd bias power supply pin for lcd control pin which cuts off the current input to the bias resistor for the external lcd during standby. p n s e g m e n t ( n o t e 3 ) d a t a o u t p u t s e l e c t s t a n d b y p o r t c , d , g , h l c d / p o r t s e l e c t p n p n pd3/ seg31 to pd0/ seg28 pc3/ seg27 to pc0/ seg24 ph3/ seg23 to ph0/ seg20 pg3/ seg19 to pg0/ seg16 seg0 to seg15 com0 to com3 v lc1 to v lc3 v l the transfer gate input signal is controlled based on 1/2, 1/3 bias method in advance. see note 3) for the output circuit format. transfer gate output the transfer gate input signal is controlled based on 1/2, 1/3 bias methods in advance. n
? 7 CXP5076/5078 symbol name i/o equivalent circuit description wake-up input 32khz t/c clock input 32khz t/c clock output reference voltage input i i o i it is the input pin to release the standby mode, and release by "1". input pin for 32khz timer clock generation circuit. connect the 32.768khz crystal oscillator between tex and tx. when using as the event clock input, connect the clock oscillation source to the tex pin, open the tx pin. output of clock generation circuit reference voltage input for power supply voltage resetting circuit. connect the zener diode normally. wp tex tx v ref t e x t x p n p n m a s k o p t i o n schmitt inverter input for all output ports, the output states of ports during standby possible to be programmed to the state holding before standby or the change to the high impedance. when the pull-up resistor output is selected, it becomes a pulled-up state even it is input port. during standby, it is impossible to change to the high impedance of py0 and py1 in the inverter output state. to change to the high impedance, select the pull-up resistor output, and then set to the high level output ("1" state).
? 8 CXP5076/5078 note 1) possible to select out of the following two ways for the output circuit format. (port units: programmable) (a) inverter output (b) pull-up resistor output note 2) possible to select out of the following two ways for the output circuit format. (port units: programmable) (a) tri-state output (b) pull-up resistor output note 3) possible to select out of the following two ways for the output circuit format. (port units: programmable) (a) inverter output (b) pull-up resistor output * as the output pull-up resistor is cmos pull-up output of about 10k , the pull-up resistor becomes off state during "l" output. s t a n d b y o u t p u t s e l e c t d a t a p p * p n s t a n d b y o u t p u t s e l e c t d a t a p p * p n d i s a b l e s t a n d b y o u t p u t s e l e c t d a t a p p * p n l c d / p o r t s e l e c t
? 9 CXP5076/5078 absolute maximum ratings (ta = ?0 to +75 c, v ss = 0v) item power supply voltage lcd bias voltage input voltage output voltage high level output current high level total output current low level output current low level total output current operating temperature storage tamperature allowable power dissipation symbol v dd v cl1 , v cl2 , v cl3 v in v out i oh i oh i ol i olc i ol topr tstg p d rating ?.3 to +7.0 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 ? ?0 15 20 100 ?0 to +75 ?5 to +150 600 unit v v v v ma ma ma ma ma c c mw remarks general purpose port * 2 : per pin entire pins total general purpose port * 2 : per pin high current port * 3 : per pin entire pins total * 1 v lc1 , v lc2 , v lc3 , v in and v out should not exceed v dd + 0.3v. * 2 specifies the output current of the general purpose i/o port pa to pi, so, sc, py0 and py1. * 3 the high current operation transistors are the n-ch transistors of the pc and pd ports. note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should better take place under the recommended operation conditions. exceeding those conditions may adversely affect the reliability of the lsi. recommended operating condition (vss = 0v) item power supply voltage lcd bias voltage high level input voltage low level input voltage operating temperature symbol min. max. 4.5 2.5 v ss 0.7v dd 0.8v dd v dd ?0.4 0 0 ?.3 ?0 5.5 5.5 v dd v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 unit v v v v v v v v v c remarks guaranteed range of operation by extal clock guaranteed range of operation by tex clock, guaranteed range of data hold during stop. liquid crystal power supply range * 1 hysteresis input * 2 extal pin * 3 hysteresis input * 2 extal pin * 3 * 1 the optimum value is determined by the characteristics of the liquid crystal display element used. * 2 the tex pin when the counter mode is selected by each of int, rmc, px0, px2, py2, py3, rst pins and mask option. * 3 specified only during external clock input. v dd v cl1 , v cl2 , v cl3 v ih v ihs v ihex v il v ils v ilex topr
? 10 CXP5076/5078 electrical characteristics dc characteristics (ta = ?0 to +75 c, vss = 0v) item high level output voltage low level output voltage input current high impedance i/o leakage current common output impedance segment output impedance supply current input capacity symbol pin pa to pi * 1 px0, px1 py0, py1 vl (v ol only) rst (v ol only) pc * 1 , pd * 1 extal tex * 4 rst * 5 pa * 6 , pb * 6 , pe * 6 , pf * 6 , pi * 6 , px0 * 6 , px1 * 6 , px2 * 8 , py0 * 7 , py1 * 7 , py2 * 8 , py3 * 8 , int * 8 , rmc * 8 , rst * 5 , tex * 4 com0 to com3 seg0 to seg15 seg16 to seg31 * 1 v dd other than v lc1 to v lc3 , com0 to com3, seg0 to seg15, seg16 to seg31 * 1 , v ss , v dd pins unit v v v v v v v a a a a a a a k k ma a ma a a a pf condition v dd = 4.5v, i oh = ?.5ma * 2 v dd = 4.5v, i oh = ?.0ma * 2 v dd = 4.5v, i oh = ?0 a * 3 v dd = 4.5v, i oh = ?00 a * 3 v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v i = 0, 5.5v v dd = 5v v lc1 = 3.75v v lc2 = 2.5v v lc3 = 1.25v entire output pins open crystal oscillation (c1 = c2 = 22pf) of v dd = 5.5v, 4.19mhz crystal oscillation (c1 = c2 = 47pf) of v dd = 3v, 32khz sleep mode v dd = 5.5v, 4.19mhz oscillation v dd = 3v, 32khz oscillation stop mode v dd = 3v, 32khz with t/c v dd = 5.5v, 32khz without t/c (for mask option select counter, pin is fixed.) clock 1mhz 0v other than the measured pins max. 0.4 0.6 1.5 40 ?0 10 ?0 ?00 10 10 5 15 20 250 12 200 40 10 20 typ. 3 5 7 50 5 40 7 10 min. 4.0 3.5 4.0 2.4 0.5 ?.5 0.1 ?.1 ?.5 v oh v ol i ihe i ile i iht i ilt i ilr i il i iz r com r seg i dd1 i dd2 i ddsp1 i ddsp2 i dds1 i dds2 c in
? 11 CXP5076/5078 ac characteristics (1) clock timing (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) item system clock frequency system clock input pulse width system clock input rising and falling times system clock frequency event count clock input pulse width event count clock input rising and falling times event count input clock input pulse width event count input clock rising and falling times symbol pin xtal extal extal tex * 2 tx ec ec tex * 3 tex * 3 unit mhz ns ns khz s ms s ms condition fig. 1, fig. 2 fig. 1, fig. 2 (external clock drive) v dd = 2.5 to 5.5v fig. 3 fig. 4 fig. 4 fig. 4 fig. 4 max. 5 200 20 20 typ. 32.768 min. 1 90 tsys * 1 + 0.05 10 fc t xl t xh t cr t cf f cs t el t eh t er t ef t tl t th t tr t tf * 1 the pc, pd, pg and ph show when the combined pins are selected as the port, and seg16 to seg31 show when the combined pins are selected as the segment output. * 2 it is when the respective pins of pa to pi, px0 and px1 select the tri-state output circuit, and py0 and py1 are when the inverter output circuit is selected. * 3 it is when the respective pins of pa to pi, px0, px1, py0 and py1 select the pull-up resistor. * 4 the tex pin specifies the input current when the crystal oscillation is selected by the mask option, and specifies the leakage current when the schmitt input is selected. * 5 the rst pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. * 6 the respective pins of pa, pb, pe, pf, pi, px0 and px1 specify the input current when the pull-up resistor is selected, and specify the leakage current when the port state during using the tri-state output circuit or standby is selected at high impedance. * 7 the respective pins of py0 and py1 specify the input current when the pull-up resistor is selected, and specify the leakage current when the port state during standby is selected at high impedance. * 8 the respective pins of px2, py2, py3, int and rmc only specify the leakage current. * 1 tsys in the extal input clock is 8/fc. tsys in the tex input clock is 4/fcs. * 2 specified when the crystal oscillation mode is selected by the mask option. * 3 specified when the counter mode is selected by the mask option. note) when adjusting the frequency accurately, there may be cases in which they may differ from fig. 2.
? 12 CXP5076/5078 e x t a l t x h t x l t c f t c r 0 . 4 v v d d 0 . 4 v 1 / f c fig. 1. clock timing a a a a a a a a a a a a e x t e r n a l c l o c k e x t a l x t a l o p e n a a a a a a a a a a a a a a a c r y s t a l o s c i l l a t i o n c e r a m i c o s c i l l a t i o n e x t a l x t a l c 1 c 2 fig. 2. clock applying condition c 1 a a a a a a a a a a a a c r y s t a l o s c i l l a t i o n t e x t x c 2 fig. 3. 32khz clock applying condition e c t e x t e h t t h t e l t t l t e f t t f t e r t t r 0 . 2 v d d 0 . 8 v d d fig. 4. event count clock timing
? 13 CXP5076/5078 (2) serial transfer (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) item serial transfer clock (sc) cycle time serial transfer clock (sc) high and low level widths serial data input setup time (against sc - ) serial data input hold time (against sc - ) high data output delay time from sc falling * 3 high data output delay time from sc falling * 4 low data output delay time from sc falling symbol pin sc sc si si so so so unit s s s s s s s s s s s s condition input mode output mode input mode output mode * 1 output mode * 2 sc input mode sc output mode sc input mode sc output mode max. tsys/8 + 0.5 tsys/8 + 1.6 tsys/8 + 0.5 min. tsys/4 + 1.42 2tsys tsys/8 + 0.7 tsys ?0.1 tsys ?1.6 0.1 0.2 tsys/8 + 0.5 0.1 t kcy t kh t kl t sik t ksi t kso t kso t kso notes) 1. tsys in the extal input clock is 8/fc. (it is impossible to use in tex input clock.) 2. the load of data output delay is 50pf + 1ttl. * 1 it is specified when px0/sc pin is selected to the tri-state output by the program. * 2 it is specified when px0/sc pin is selected to the pull-up resistance by the program. as the tsys receives restriction by this item, take notice that it limits the upper limit of the system clock frequency fc. * 3 this item is specified when px1/so pin is selected to the tri-state output by the program. * 4 this item is specified when px1/so pin is selected to the pull-up resistance by the program. 0 . 2 v d d 0 . 8 v d d t k l t k h s o t k c y t s i k t k s i 0 . 2 v d d 0 . 8 v d d t k s o 0 . 2 v d d 0 . 8 v d d o u t p u t d a t a i n p u t d a t a s i s c fig. 5. serial transfer timing
? 14 CXP5076/5078 (3) a/d converter (ta = ?0 to +75 c, vss = 0v) analog input voltage 0.0 to 0.33v 0.82 to 1.29v 1.78 to 2.21v 2.69 to 3.06v 3.56 to 4.06v 4.62 to 5.0v pin ad0 to ad7 condition v dd = 5v digital conversion value 000 001 010 011 100 101 note) the digital conversion value are the values when ab h address of the ram file 1 in the program are read. (4) power supply voltage detection reset function (ta = ?0 to + 75 c, vss = 0v) item power supply voltage detection reset function of operation voltage range power supply voltage drop detection function symbol pin v dd v dd unit v v condition voltage range allowing system operation (32khz system operation below v dd = 4.5v) when v ref pin voltage is 3.3v flag set when voltage drops system reset when voltage rises max. 5.5 4.2 typ. 4.0 min. 2.5 3.8 v lpop v pop the graph in fig. 6 shows the relationship between the power supply voltage v dd and reference voltage v ref of the power supply voltage detection reset function. note) the graph in fig. 6 serves as guide to the function operation area obtained using average devices. individual adjustment is needed when zener diodes, etc., are connected to the v ref pin. 5 . 5 2 . 5 0 1 . 6 5 . 0 a a a a a a a a a a a a v r e f [ v ] v d d [ v ] fig. 6. power supply voltage detection reset function chart
? 15 CXP5076/5078 fig. 7. interruption input timing (5) others (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v) item external interruption high and low level widths reset input low level width wake-up input high level width wake-up input low level width symbol pin int rst wp pa0 to pa3 unit s s ns s ns s condition during edge detection mode stop mode sleep mode stop mode sleep mode max. min. tsys + 0.05 2tsys * 1 500 tsys + 0.05 500 tsys + 0.05 t i1h , t i1l t rsl t wph t wpl note) tsys in the extal input clock is 8/fc. tsys in the tex input clock is 4/fcs. * 1 for resetting when operating in tex input clock, hold the low level more than the oscillation stabilizing time of extal input clock. t i 1 l t i 1 h 0 . 2 v d d 0 . 8 v d d i n t ( r i s i n g e d g e ) t i 1 h t i 1 l 0 . 2 v d d 0 . 8 v d d i n t ( f a l l i n g e d g e ) fig. 8. reset input timing t r s l 0 . 2 v d d r s t fig. 9. wake-up input timing w p t w p h 0 . 8 v d d fig. 10. wake-up input timing t w p l 0 . 2 v d d p a 0 t o p a 3
? 16 CXP5076/5078 power on reset * (ta = ?0 to +75 c, vss = 0v) item power supply rising time power supply cut-off time symbol pin v dd unit ms ms condition power on reset repetitive power on reset max. 50 min. 0.05 1 t r t off * specifies only when power on reset function is selected. v d d t r 0 . 2 v 4 . 5 v 0 . 2 v t o f f t h e p o w e r s u p p l y s h o u l d r i s e s m o o t h l y . fig. 11. power on reset
? 17 CXP5076/5078 notes on application see fig. 11, additive capacity calculation chart, when using the crystal oscillator and select the appropriate capacity. fig. 12. crystal oscillation circuit additive capacity calculation chart note) the above chart shows a range in which the average quartz resonator has a relatively fast oscillation rising edge and stable characteristics. the capacity should be selected to correspond to the appropriate constant for each quartz resonator, should the frequency of the quartz resonator be accurately adjusted. fig. 13 shows an example of a circuit which can accurately adjust the frequency. used here a trimmer capacitor. fig. 13. frequency adjustment circuit when using the a/d converter as the key input, it is recommended that the circuit structure shown in fig. 14 be used. v d d a d v s s 8 . 2 k s w 5 s w 4 3 . 3 k s w 3 1 . 8 k s w 2 1 . 2 k s w 1 4 . 7 k ( r e s i s t a n c e i s a l l e 1 2 s e r i e s ) e x t a l x t a l c 1 c 2 v d d r d a a a a a a a a a a a a a a a 0 . 1 1 1 0 1 0 0 f c r y s t a l o s c i l l a t i o n f r e q u e n c y [ m h z ] 5 0 1 0 0 1 5 0 2 0 0 c a d d i t i v e c a p a c i t y [ p f ] t a = 2 0 t o + 7 5 c , v d d = 4 . 5 t o 5 . 5 v e x t a l x t a l c 1 c 2 c 1 = c 2 = c 5 fig. 14. recommended example of key circuit by a/d converter
? 18 CXP5076/5078 package outline unit: mm p a c k a g e s t r u c t u r e s o n y c o d e e i a j c o d e j e d e c c o d e q f p - 8 0 p - l 0 1 q f p 0 8 0 - p - 1 4 2 0 p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y 1 . 6 g 2 3 . 9 0 . 4 2 0 . 0 0 . 1 + 0 . 4 1 8 0 6 5 6 4 4 1 4 0 2 5 2 4 0 . 8 0 . 3 5 0 . 1 + 0 . 1 5 1 4 . 0 0 . 1 + 0 . 4 1 7 . 9 0 . 4 1 6 . 3 0 . 1 0 . 0 5 + 0 . 2 2 . 7 5 0 . 1 5 + 0 . 3 5 0 . 8 0 . 2 0 . 1 5 0 . 0 5 + 0 . 1 8 0 p i n q f p ( p l a s t i c ) m 0 . 1 2 0 . 1 5 0 t o 1 0 d e t a i l a a

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