SSTL16857 14-bit sstl_2 registered driver with differential clock inputs product specification supersedes data of 1999 apr 29 1999 sep 30 integrated circuits www.datasheet.co.kr datasheet pdf - http://www..net/
philips semiconductors product specification SSTL16857 14-bit sstl_2 registered driver with differential clock inputs 2 1999 sep 30 853-2155 22448 features ? stub-series terminated logic for 2.5v vddq (sstl_2) ? optimized for ddr (double data rate) sdram applications ? supports sstl_2 signal inputs and outputs ? flow-through architecture optimizes pcb layout ? meets sstl_2 class i and class ii specifications ? latch-up protection exceeds 500ma per jedec std 17 ? esd protection exceeds 2000 v per mil std 833 method 3015 and 200 v per machine model ? full ddr solution provided when used with pck857 and cbt3857 description the SSTL16857 is a 14-bit sstl_2 registered driver with differential clock inputs. both v cc and v ddq support 2.5v and 3.3v operation however. v ddq must not exceed v cc . inputs are sstl_2 type with v ref normally at 0.5*v ddq . the outputs support class i which can be used for standard stub-series applications or capacitive loads. master reset (reset ) asynchronously resets all registers to zero. the SSTL16857 is intended to be incorporated into standard dimm (dual in-line memory module) designs defined by jedec, such as ddr (double data rate) sdram or sdram ii memory modules. different from traditional sdram, ddr sdram transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. a ddr dram rated at 100 mhz will have a burst rate of 200 mhz. the modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. the SSTL16857 is intended to be used for sstl_2 input and output signals. the device data inputs consist of differential receivers. one differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. the clock input is fully differential to be compatible with dram devices that are installed on the dimm. however, since the control inputs to the sdram change at only half the data rate, the device must only change state on the positive transition of the clk signal. in order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device must support an asynchronous input pin (reset), which when held to the low state will assume that all registers are reset to the low state and all outputs drive a low signal as well. pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 vddq q5 q6 q9 q10 d12 d11 d10 d9 d8 reset vref gnd vcc clk+ clk d7 d6 d5 d4 d3 vcc gnd d2 d1 21 22 23 24 25 26 27 28 vddq q14 d14 d13 gnd vcc q1 q2 gnd q3 q4 gnd vddq q7 vddq gnd q8 vddq gnd q11 q12 gnd q13 sw00311 quick reference data gnd = 0 v; t amb = 25 c; t r =t f 2.5 ns symbol parameter conditions typical unit t phl /t plh propagation delay; clk to qn c l = 30 pf; v ddq = 2.5 v 1.8 ns c i input capacitance v cc = 2.5v 2.9 pf notes: 1. c pd is used to determine the dynamic power dissipation (p d in m w) p d = c pd v cc 2 x f i (c l v cc 2 f o ) where: f i = input frequency in mhz; c l = output load capacity in pf; f o = output frequency in mhz; v cc = supply voltage in v; (c l v cc 2 f o ) = sum of the outputs. ordering information packages temperature range order code dwg number 48-pin plastic tssop type i 0 c to +70 c SSTL16857 dgg sot362-1 www.datasheet.co.kr datasheet pdf - http://www..net/
philips semiconductors product specification SSTL16857 14-bit sstl_2 registered driver with differential clock inputs 1999 sep 30 3 pin description pin number symbol name and function 34 reset lvcmos asynchronous master reset (active low) 48, 47, 44, 43, 42, 41, 40, 33, 32, 31, 30, 29, 26, 25 d1 d14 sstl_2 data inputs 1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19, 20, 23, 24 q1 q14 sstl_2 data outputs 35 vref sstl_2 input reference level 3, 8, 13, 17, 22, 27, 36, 46 gnd ground (0 v) 28, 37, 45 v cc positive supply voltage 4, 9, 12, 16, 21 v ddq output supply voltage 38 39 clk+ clk differential clock inputs function table inputs output reset clk clk d q l x x x l h h h h l l h l or h l or h x q 0 h = high voltage level l = high voltage level = high-to-low transition = low-to-high transition x = don't care logic diagram sw00312 register register register register register register register register register register register register register register reset vref d1 d2 ad d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 clk+ clk q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 absolute maximum ratings 1, 2 symbol parameter condition limits unit symbol parameter condition min max unit v cc dc supply voltage 0.5 +4.6 v i ik dc input diode current v i < 0 50 ma v i dc input voltage 3 0.5 v ddq + 0.5 v i ok dc output diode current v o < 0 50 ma v out dc output voltage 3 note 3 0.5 v ddq + 0.5 v i o dc output current v o = 0 to v ddq 50 ma i out continuous current 4 v cc , v ddq , or gnd 100 ma t stg storage temperature range 65 +150 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 3. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 4. the continuous current at v cc , v ddq , or gnd should not exceed 100 ma. www.datasheet.co.kr datasheet pdf - http://www..net/
philips semiconductors product specification SSTL16857 14-bit sstl_2 registered driver with differential clock inputs 1999 sep 30 4 recommended operating conditions 1 symbol parameter test conditions min typ max unit v cc supply voltage v ddq 3.6 v v ddq output supply voltage 2.3 2.7 v v ref reference voltage (v ref = 0.5 x v ddq ) 1.15 1.25 1.35 v v tt termination voltage v ref 40mv v ref v ref + 40mv v v i input voltage 0 v cc v v ih ac high-level input voltage all inputs v ref + 350mv v v il ac low-level input voltage all inputs v ref 350mv v v ih dc high-level input voltage all inputs v ref + 180mv v ddq + 0.5v v v il dc low-level input voltage all inputs v ss 0.5v v ref 180mv v i oh high-level output current 20 ma i ol low-level output current 20 ma tamb operating free-air temperature range 0 70 c note: 1. unused control inputs must be held high or low to prevent them from floating. dc electrical characteristics over recommended operating conditions. voltages are referenced to gnd (ground = 0v). limits symbol parameter test conditions temp = 0 c to +70 c unit min typ 2 max v ik i/o supply voltage v cc = 2.3v; i i = 18ma 1.2 v cc = 2.3v to 2.7v; i oh = 100 m a v cc 0.2 2.3 v v oh high level output voltage v cc = 2.3v; i oh = 8ma 1.95 2.2 v v cc = 2.3v; i oh = 16ma 1.95 2.1 v cc = 2.3v to 2.7v; i ol = 100 m a 0.002 0.2 v ol low level output voltage v cc = 2.3v; i ol = 8ma 0.14 0.35 v v cc = 2.3v; i ol = 16ma 0.30 0.35 v cmr clk, clk common mode range for reliable performance 0.97 1.53 v v pp clk, clk minimum peak-to-peak input to ensure logic state 360 mv v cc = 2.7v ; v i = 1.7v or 0.8v 0.01 5 data in p uts reset v cc = 2.7v ; v i = 2.7v or 0v v = 1 15v or 1 35v 0.01 5 m a data inp u ts , reset v cc = 3.6v ; v i = 1.7v or 0.8v v ref = 1 . 15v or 1 . 35v 0.01 5 m a v cc = 3.6v ; v i = 2.7v or 0v 0.01 5 i v cc = 2.7v ; v i = 1.7v or 0.8v 0.05 5 i i clk clk v cc = 2.7v ; v i = 2.7v or 0v v = 1 15v or 1 35v 0.05 5 m a clk , clk v cc = 3.6v ; v i = 1.7v or 0.8v v ref = 1 . 15v or 1 . 35v 0.05 5 v cc = 3.6v ; v i = 2.7v or 0v 0.05 5 ma v v cc = 2.7v v = 1 15v or 1 35v 0.05 5 m a v ref v cc = 3.6v v ref = 1 . 15v or 1 . 35v 0.05 5 m a v cc = 2.7v ; v i = 1.7v or 0.8v 12 25 i cc quiescent supply current clk and clk in o pp osite v cc = 2.7v ; v i = 2.7v or 0v 10 25 ma i cc clk and clk in o osite state 1 v cc = 3.6v ; v i = 1.7v or 0.8v 12 25 ma v cc = 3.6v ; v i = 2.7v or 0v 10 25 notes: 1. when clk and clk are high, typical i cc = 25ma. 2. all typical values are at v cc = 3.3v and t amb = 25 c (unless otherwise specified). www.datasheet.co.kr datasheet pdf - http://www..net/
philips semiconductors product specification SSTL16857 14-bit sstl_2 registered driver with differential clock inputs 1999 sep 30 5 timing requirements over recommended operating conditions; t amb = 0 c to +70 c (unless otherwise noted) (see figure 1) limits symbol parameter test conditions v cc = 2.5v 0.2v v cc = 3.3v 0.3v unit min max min max f clock clock frequency 200 200 mhz t w pulse duration, clk, clk high or low 1.0 1.0 ns t setu p time data before clk , clk 0.8 0.9 ns t su set u p time reset high before clk , clk 0.8 1.0 ns t h hold time 0.5 0.5 ns switching characteristics over recommended operating conditions; t amb = 0 c to +70 c; v ddq = 2.3 2.7v and v ddq does not exceed v cc. class i, v ref = v tt = v ddq x 0.5 and c l = 10pf (unless otherwise noted) (see figure 1) limits limits symbol from (input) to (output) v cc = 2.5v 0.2v v cc = 3.3v 0.3v unit (input) (output) min max min max f max maximum clock frequency 200 200 mhz t plh /t phl clk and clk q 1.0 3.1 0.7 2.6 ns t phl reset q 2.0 5.0 1.4 4.0 ns 184/200-pin ddr sdram dimm sdram sdram sdram sdram sdram sdram sdram sdram sdram the pll clock distribution device and sstl registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation sw00393 cbt3857 (9) cbt cbt cbt cbt cbt cbt cbt cbt cbt sdram sdram sdram sdram sdram sdram sdram sdram sdram SSTL16857 pck857 SSTL16857 back side front side www.datasheet.co.kr datasheet pdf - http://www..net/
philips semiconductors product specification SSTL16857 14-bit sstl_2 registered driver with differential clock inputs 1999 sep 30 6 parameter measurement information ac waveforms v ol t plh t phl output v ref v ref v ref v ih v il clk v oh v ref sw00338 waveform 1. propagation delay times inverting and non-inverting outputs v ref v ref v ih v il output t phl sw00402 v oh v ol reset waveform 2. propagation delay reset to output. v ref v ref v ih v il input sw00339 t w waveform 3. pulse duration v ref v ih v il timing input sw00340 v ref v ref v il data input t h t su v ih waveform 4. setup and hold times test circuit v tt test point 25 w c l = 10pf or 30pf 25 w = sstl_2 class ii 50w = sstl_2 class i notes: c l includes probe and jig capacitance all input pulses are supplied by generators having the following characteristics: prr 10mhz, z o = 50 w , t r 1.25ns/v, t f 1.25ns/v. the outputs are measured one at a time with one transition per measurement. v tt = v ref = v ddq x 0.5 sw00337 figure 1. load circuitry 50pf 500 w sw00336 figure 2. sw00335 50pf figure 3. www.datasheet.co.kr datasheet pdf - http://www..net/
philips semiconductors product specification SSTL16857 14-bit sstl_2 registered driver with differential clock inputs 1999 sep 30 7 tssop48: plastic thin shrink small outline package; 48 leads; body width 6.1mm sot362-1 www.datasheet.co.kr datasheet pdf - http://www..net/
philips semiconductors product specification SSTL16857 14-bit sstl_2 registered driver with differential clock inputs 1999 sep 30 8 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1999 all rights reserved. printed in u.s.a. date of release: 0999 document order number: 939775006455
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design. www.datasheet.co.kr datasheet pdf - http://www..net/
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