1/9 june 2004 STS8DNH3LL dual n-channel 30v - 0.018 ? - 8a so-8 low gate charge stripfet? iii power mosfet rev.0.2 typical r ds (on) = 0.018 ? optimal r ds (on) x qg trade-off @ 4.5v conduction losses reduced switching losses reduced description this application specific mosfet is the third generation of stmicroelectronis unique "single feature size?" strip-based process. the resulting transistor shows the best trade-off between on-resistance and gate charge. when used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. this is extremely important for motherboards where fast switching and high efficiency are of paramount importance. applications specifically designed and optimised for high efficiency cpu core dc/dc converters for mobile pc s ordering information type v dss r ds(on) i d STS8DNH3LL 30 v <0.022 ? 8 a sales type marking package packaging STS8DNH3LL s8dnh3ll so-8 tape & reel so-8 absolute maximum ratings ( ?) pulse width limited by safe operating area. symbol parameter value unit v ds drain-source voltage (v gs = 0) 30 v v dgr drain-gate voltage (r gs = 20 k ? ) 30 v v gs gate- source voltage 16 v i d drain current (continuous) at t c = 25c 8a i d drain current (continuous) at t c = 100c 5a i dm ( ?) drain current (pulsed) 32 a p tot total dissipation at t c = 25c 2w internal schematic diagram
STS8DNH3LL 2/9 tab.1 thermal data (*) when mounted on 1 inch 2 fr-4 board, 2 oz of cu, t 10s electrical characteristics (t j = 25 c unless otherwise specified) tab.2 off tab.3 on (* ) tab.4 dynamic rthj-amb t j t stg (*) thermal resistance junction-ambient maximum operating junction temperature storage temperature max 62.5 150 -55 to 150 c/w c c symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 30 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating v ds = max rating t c = 125c 1 10 a a i gss gate-body leakage current (v ds = 0) v gs = 16 v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs i d = 250 a 1v r ds(on) static drain-source on resistance v gs = 10 v i d = 4 a v gs = 4.5 v i d = 4 a 0.018 0.020 0.022 0.025 ? ? symbol parameter test conditions min. typ. max. unit g fs (*) forward transconductance v ds =15 v i d =4 a 8.5 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 25v, f = 1 mhz, v gs = 0 857 147 20 pf pf pf
3/9 STS8DNH3LL tab.5 switching on tab.6 switching off tab.7 source drain diode (*) pulsed: pulse duration = 300 s, duty cycle 1.5 %. ( ?) pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time v dd = 15 v i d = 4 a r g =4.7 ? v gs = 10 v (resistive load, figure 1) 12 14.5 ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd = 15 v i d = 8 a v gs = 4.5 v (see test circuit, figure 2) 7.0 2.5 2.3 10 nc nc nc symbol parameter test conditions min. typ. max. unit t d(off) t f turn-off delay time fall time v dd = 15 v i d = 4 a r g =4.7 ?, v gs = 10 v (resistive load, figure 1) 23 8 ns ns symbol parameter test conditions min. typ. max. unit i sd i sdm ( ? ) source-drain current source-drain current (pulsed) 8 32 a a v sd (*) forward on voltage i sd = 4 a v gs = 0 1.5 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 8 a di/dt = 100a/s v dd = 15 v t j = 150c (see test circuit, figure 3) 15 5.7 0.76 ns nc a electrical characteristics (continued) safe operating area thermal impedance
STS8DNH3LL 4/9 output characteristics transfer characteristics transconductance static drain-source on resistance gate charge vs gate-source voltage capacitance variations
5/9 STS8DNH3LL normalized gate threshold voltage vs temperature normalized on resistance vs temperature source-drain diode forward characteristics normalized breakdown voltage temperature . . .
STS8DNH3LL 6/9 fig. 2: gate charge test circuit fig. 3: test circuit for diode recovery behaviour fig. 1: switching times test circuits for resistive load
7/9 STS8DNH3LL dim. mm inch min. typ. max. min. typ. max. a1.750.068 a1 0.1 0.25 0.003 0.009 a2 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.25 0.5 0.010 0.019 c1 45 (typ.) d 4.8 5.0 0.188 0.196 e 5.8 6.2 0.228 0.244 e1.27 0.050 e3 3.81 0.150 f 3.8 4.0 0.14 0.157 l 0.4 1.27 0.015 0.050 m0.60.023 s8 (max.) 0016023 so-8 mechanical data
STS8DNH3LL 8/9 revision history date revision description of changes tuesday 15 june 2004 0.2 first issue
9/9 STS8DNH3LL i nformation furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the con sequence s o f use of such information nor for any infringement of patents or other rights of third parties which may result from its use. n o license is grante d b y implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicatio n are subje ct t o change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics produ cts are n ot a uthorized for use as critical components in life support devices or systems without express writte n approval of stmicroelectron ics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco -singapore - spain - sweden - switzerland - united kingdom - united states. www.st.com
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