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this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev 1.0 / dec. 2008 1 1 h27u518s2c series 512 mbit (64 m x 8 bit) nand flash 512 mb nand flash h27u518s2c
rev 1.0 / dec. 2008 2 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash document title 512 mbit (64 m 8 bit ) nand flash memory revision history revision no. history draft date remark 0.0 initial draft jul. 29. 2008 preliminary 0.1 correct partnumber nov. 25. 2008 preliminary 1.0 preliminary removed dec. 10. 2008 rev 1.0 / dec. 2008 3 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash features summary high density nand flash memories - cost effective solutions for mass storage applications nand interface - x8 bus width - address/ data multiplexing - pinout compatiblity for all densities supply voltage - 3.3 v device : vcc = 2.7 v ~ 3.6 v memory cell array - (512 + 16) bytes x 32 pages x 4096 blocks page size - (512 + 16 spare) bytes block size - (16 k + 512 spare) bytes page read / program - random access : 12 us (max.) - sequential access : 30 ns (min.) - page program time : 200 us (typ.) copy back program - automatic block download without latency time fast block erase - block erase time : 1.5 ms (typ.) status register - normal status register (read/program/erase) - extended status register (edc) electronic signature - 1st cycle : manufacturer code - 2nd cycle : device code chip enable don?t care - simple interface with microcontroller hardware data protection - program/erase locked during power transitions. data retention - 100,000 program/erase cycles (with 1bit/528byte ecc) - 10 years data retention package - h27u518s2ctr-bx : 48-pin tsop1 (12 20 1.2 mm) - h27u518s2ctr-bx (lead & halogen free) rev 1.0 / dec. 2008 4 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash 1. summary description hynix nand h27u518s2c series have 64 m 8 bit with spare 2 m 8 bit capacity. the device is offered in 3.3 v vcc power supply, and with x8 i/o interface. its nand cell provides the most cost-effective solution for the solid state mass storage market. the device is divided into blocks that can be erased independ ently so it is possible to preserve valid data while old data is erased. the device contains 4096 blocks, composed by 32 pages consis ting in two nand sturctures of 16 series connected flash cells. a program operation allows to write the 512-byte page in typical 200 us and an erase operation can be performed in typical 1.5 ms on a 16 k-byte block. data in the page can be read out at 30 ns cycle time pe r byte. the i/o pins serve as the ports for address and data input/output as well as command input. this interface allows a reduced pin count and easy migration towards different densities, without any rea rrangement of footprint. commands, data and addresses are sy nchronously introduced using ce , we , re, ale and cle input pin. the on-chip program/erase controller automates all read, program and eras e functions including pulse re petition, where required, and internal verification and margin ing of data. the modify operatio ns can be locked using the wp input. the output pin r/b (open drain buffer) signals the status of the device during ea ch operation. in a system wi th multiple memories the r/b pins can be connected all together to provide a global status signal. the copy back function allows the optimization of defective blocks management. when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. even the write-intensive systems can take advantage of th e h27u518s2c series extended reliability of 100k program/ erase cycles by supporting ecc (error correcting code) with real time mapping-out algo rithm. the chip supports ce don?t care function. this function al lows the direct download of the code from the nand flash memory device by a microcon- troller, since the ce transitions do not stop the read operation. this device includes also extra features li ke otp/unique id area, read id2 extension. the h27u518s2c is available in 48-tsop1 12 x 20 mm. 1.1 product list part number organization vcc range package h27u518s2c x8 2.7 ~ 3.6 volt 48 tsop 1 rev 1.0 / dec. 2008 5 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash figure 1 : logic diagram io7 - io0 data input / outputs cle command latch enable ale address latch enable ce chip enable re read enable we write enable wp write protect r/b ready / busy vcc power supply vss ground nc no connection table 1 : signal names vcc vss wp cle ale re we ce io0~io7 r/b rev 1.0 / dec. 2008 6 1prepreliminaryeee h27u518s2c series 512 mbit (64 m x 8 bit) nand flash figure 2 : 48 tsop 1 contact, x8 device 1 & 1 & 1 & 1 & 1 & 1 & 5 % 5 ( & |