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preliminary w79e217 a /21 6 a data sheet 8 - bit microcontrolle r publication release date: december , 2006 - 1 - revision a 0. 2 table of contents - 1 general description ................................ ................................ ................................ ................................ ......... 5 2 features ................................ ................................ ................................ ................................ ................................ ...... 5 3 parts infor mation list ................................ ................................ ................................ ................................ .... 6 3.1 l ead f ree (r o hs) p arts information lis t ................................ ................................ ................................ . 6 4 pin configuration ................................ ................................ ................................ ................................ ................ 7 5 pin description ................................ ................................ ................................ ................................ ....................... 9 5.1 p ort 4 ................................ ................................ ................................ ................................ ................................ ...... 11 6 memory organization ................................ ................................ ................................ ................................ ..... 12 6.1 p rogram m emory ( on - chip f lash ) ................................ ................................ ................................ ............... 12 6.2 d ata m emory ................................ ................................ ................................ ................................ ........................ 12 6.3 a uxiliary sram ................................ ................................ ................................ ................................ ................... 13 6.4 2 - kb nvm d ata f lash m emory ................................ ................................ ................................ ..................... 13 6.4.1 operation ................................ ................................ ................................ ................................ ....................... 15 7 special function registers ................................ ................................ ................................ ...................... 18 8 instruction set ................................ ................................ ................................ ................................ .................... 69 8.1 i nstruction t iming ................................ ................................ ................................ ................................ ............. 76 8.1.1 external data memory acces s timing ................................ ................................ ................................ 78 9 p ower m anagement ................................ ................................ ................................ ................................ .......... 81 9.1 i dle m ode ................................ ................................ ................................ ................................ ............................... 81 9.2 p ower d ow n m ode ................................ ................................ ................................ ................................ ............ 81 10 r eset c onditions ................................ ................................ ................................ ................................ ............ 83 10.1 s ources of reset ................................ ................................ ................................ ................................ ............... 83 10.1.1 external reset ................................ ................................ ................................ ................................ .............. 83 10.1.2 power - on reset (por) ................................ ................................ ................................ ............................ 83 10.1.3 watchdog timer reset ................................ ................................ ................................ ............................. 83 10.2 r eset s tate ................................ ................................ ................................ ................................ .......................... 83 11 interrupts ................................ ................................ ................................ ................................ ............................ 85 11.1 i nterrupt s ources ................................ ................................ ................................ ................................ ............ 85 11.2 p riority l evel s tructure ................................ ................................ ................................ .............................. 85 11.2.1 response time ................................ ................................ ................................ ................................ ............ 88 12 programmable timers/ counters ................................ ................................ ................................ ..... 89 12.1 t imer /c ounters 0 & 1 ................................ ................................ ................................ ................................ ....... 89 12.1.1 time - base selection ................................ ................................ ................................ ................................ .. 89 12.1.2 m ode 0 ................................ ................................ ................................ ................................ ............................ 89 12.1.3 m ode 1 ................................ ................................ ................................ ................................ ............................ 89
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 2 - revision a 0. 2 12.1.4 mode 2 ................................ ................................ ................................ ................................ ............................ 90 12.1.5 m ode 3 ................................ ................................ ................................ ................................ ............................ 91 12.2 t imer /c ounter 2 ................................ ................................ ................................ ................................ ................. 91 12.2.1 c apture m ode ................................ ................................ ................................ ................................ .............. 92 12.2.2 a uto - reload m ode , c ounting up ................................ ................................ ................................ ............. 92 12.2.3 auto - reload mode, counting up/down ................................ ................................ ................................ 93 12.2.4 baud rate generator mode ................................ ................................ ................................ .................... 94 13 watchdog timer ................................ ................................ ................................ ................................ .............. 95 14 pulse - width - modulate d (pwm) outputs ................................ ................................ ...................... 98 14.1 pwm f eatures ................................ ................................ ................................ ................................ .................... 98 14.2 pwm c ontrol r egisters ................................ ................................ ................................ ............................... 98 14.3 c omplementary pwm with d ead - time and o verride functions ................................ .................. 103 14.4 d ead - t ime i nsertion ................................ ................................ ................................ ................................ ........ 103 14.5 pwm o utput o verride ................................ ................................ ................................ ................................ .. 105 14.6 e dge aligned pwm ( up - counter ) ................................ ................................ ................................ .............. 108 14.7 c enter a ligned pwm ( up / down counter ) ................................ ................................ ............................. 111 14.8 s ingle s hot (u p - c ounter ) ................................ ................................ ................................ ........................... 113 14.9 s mart f ault d etector ................................ ................................ ................................ ................................ ... 116 15 motion feedback module ................................ ................................ ................................ ..................... 118 15.1 i nput c apture m odule (ic) ................................ ................................ ................................ ........................... 118 15.1.1 compare mode ................................ ................................ ................................ ................................ ......... 125 15.1.2 reload mode ................................ ................................ ................................ ................................ ............. 126 15.2 q uadrature e ncoder i nterface (qei) ................................ ................................ ................................ .... 126 15.2.1 free - counting mode ................................ ................................ ................................ ................................ 127 15.2.2 compare - counting mode ................................ ................................ ................................ ....................... 127 15.2.3 x2/x4 coun ting modes ................................ ................................ ................................ .......................... 128 15.2.4 direction of count ................................ ................................ ................................ ................................ .... 128 15.2.5 up - counting ................................ ................................ ................................ ................................ ............... 130 15.2.6 down - counting ................................ ................................ ................................ ................................ ......... 130 16 s erial p ort ................................ ................................ ................................ ................................ ....................... 132 16.1 m ode 0 ................................ ................................ ................................ ................................ ................................ ... 132 16.2 m ode 1 ................................ ................................ ................................ ................................ ................................ ... 133 16.3 m ode 2 ................................ ................................ ................................ ................................ ................................ ... 134 16.4 m ode 3 ................................ ................................ ................................ ................................ ................................ ... 135 16.5 f raming e rr or d etection ................................ ................................ ................................ ............................ 135 16.6 m ultiprocessor c ommunications ................................ ................................ ................................ ............. 136 17 i2c serial ports ................................ ................................ ................................ ................................ ............ 137 17.1 sio p ort ................................ ................................ ................................ ................................ .............................. 138 17.2 t he i2c c ontrol r egisters ................................ ................................ ................................ ......................... 138 17.2.1 slave address registers, i2addr ................................ ................................ ................................ .... 138 17.2.2 data register, i2dat ................................ ................................ ................................ ............................. 138 17.2.3 control register, i2con ................................ ................................ ................................ ....................... 139
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 3 - revision a 0. 2 17.2.4 status register, i2status ................................ ................................ ................................ .................. 139 17.2.5 i2c clock baud rate control , i2clk ................................ ................................ ................................ 139 17.2.6 i2c time - out counter, i2timer ................................ ................................ ................................ ........... 140 17.2.7 i2c maskable slave address ................................ ................................ ................................ ............... 140 17.3 m odes of o peration ................................ ................................ ................................ ................................ ....... 140 17.3.1 master t ransmitter mode ................................ ................................ ................................ ...................... 140 17.3.2 master receiver mode ................................ ................................ ................................ ........................... 141 17.3.3 slave receiver mode ................................ ................................ ................................ ............................. 141 17.3.4 slave transmitter mode ................................ ................................ ................................ ........................ 141 17.4 d ata t ransfer f low in f ive o perating m odes ................................ ................................ .................... 141 17.4.1 master/transmitt er mode ................................ ................................ ................................ ...................... 142 17.4.2 master/receiver mode ................................ ................................ ................................ ........................... 143 17.4.3 slave/transmitter mode ................................ ................................ ................................ ........................ 144 17.4.4 slave/receiver mode ................................ ................................ ................................ ............................. 145 17.4.5 gc mode ................................ ................................ ................................ ................................ ..................... 146 18 serial peripheral in terface (spi) ................................ ................................ ................................ . 147 18.1 g eneral descriptions ................................ ................................ ................................ ................................ .... 147 18.2 b lock descriptions ................................ ................................ ................................ ................................ ......... 147 18.3 f unctional descriptio ns ................................ ................................ ................................ ............................... 149 18.3.1 master mode ................................ ................................ ................................ ................................ .............. 149 18.3.2 slave mode ................................ ................................ ................................ ................................ ................ 151 18.3.3 slave se lect ................................ ................................ ................................ ................................ ................ 154 18.3.4 /ss output ................................ ................................ ................................ ................................ ................... 154 18.3.5 spi i/o pins mode ................................ ................................ ................................ ................................ .... 155 18.3 .6 programmable serial clock?s phase and polarity ................................ ................................ .......... 155 18.3.7 receive double buffered data register ................................ ................................ .............................. 155 18.3.8 lsb first enable ................................ ................................ ................................ ................................ ........ 156 18.3.9 write collision detection ................................ ................................ ................................ ........................ 156 18.3.10 transfer complete interrupt ................................ ................................ ................................ .............. 156 18.3.11 mode fault ................................ ................................ ................................ ................................ ............. 156 19 analog - to - digital co nverter ................................ ................................ ................................ .......... 159 19.1 o peration of adc ................................ ................................ ................................ ................................ ............ 159 19.2 adc r esolution and a nalog s upply ................................ ................................ ................................ ....... 160 20 lcd display ................................ ................................ ................................ ................................ ....................... 161 20.1 lcd f eatures ................................ ................................ ................................ ................................ .................... 1 61 20.2 lcd f requency ................................ ................................ ................................ ................................ ................. 162 20.3 lcd p ower c onnection ................................ ................................ ................................ ................................ 168 20.4 lcd o ption b its ................................ ................................ ................................ ................................ ................ 171 20.5 lcd d isplay ................................ ................................ ................................ ................................ ........................ 171 21 timed access protect ion ................................ ................................ ................................ ..................... 174 22 port 4 structure ................................ ................................ ................................ ................................ ........ 176 23 in - system programmin g ................................ ................................ ................................ ......................... 179
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 4 - revision a 0. 2 23.1 t he l oader p rogram l ocates at ldf lash m emory ................................ ................................ .......... 179 23.2 t he l oader p rogram l ocates at apf lash m emory ................................ ................................ .......... 179 24 option bits ................................ ................................ ................................ ................................ ......................... 180 24.1 c onfig 0 ................................ ................................ ................................ ................................ ................................ . 180 24.2 c onfig 1 ................................ ................................ ................................ ................................ ................................ . 181 25 electrical character istics ................................ ................................ ................................ ............. 182 25.1 a bsolute m aximum r atings ................................ ................................ ................................ .......................... 182 25.2 dc c haracteristics ................................ ................................ ................................ ................................ ........ 182 25.3 ac c haracteristics ................................ ................................ ................................ ................................ ........ 184 25.3.1 e xternal c lock c haracteristics ................................ ................................ ................................ ............ 184 25.3.2 ac s pecification ................................ ................................ ................................ ................................ ....... 184 25.3.3 movx characteristics u sing s tretch m emor y c ycle ................................ ................................ .. 185 25.4 t he adc c onverter dc electrical characteristics ................................ ........................ 186 25.5 i2c b us t iming c haracteristics ................................ ................................ ................................ ................ 187 25.6 p rogram m emory r ead c ycle ................................ ................................ ................................ .................... 188 25.7 d ata m emory r ead c ycle ................................ ................................ ................................ ............................. 188 25.8 d ata m emory w rite c ycle ................................ ................................ ................................ ........................... 189 26 typical application circuits ................................ ................................ ................................ ............ 190 26.1 e xpanded e xternal p rogram m emory and c rystal ................................ ................................ ......... 190 26.2 e xpanded e xternal d ata m emory and o scillator ................................ ................................ ............ 190 27 package dimension ................................ ................................ ................................ ................................ .... 191 27.1 1 00l qfp (14 x 20 x 2.75 mm footprint 4.8 mm ) ................................ ................................ ......................... 191 28 application note ................................ ................................ ................................ ................................ ......... 192 29 revision history ................................ ................................ ................................ ................................ ........... 198
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 5 - revision a 0. 2 1 gen eral description the w79e217 /217 is a fast , 8051/52 - compatible microcontroller with a redesigned processor core that eliminates wasted clock and memory cycles . typically, the w79e217 /217 execut es instructions 1.5 to 3 times faster than that of the traditio nal 8051/52, depending on the type of instruction , and the overall performance is about 2.5 times better at the same crystal speed. as a result, with the fully - static cmos design , the w79e217 /217 can accomplish the same throughput with a lower clock speed, reducing power consumption. the w79e217 /217 provides 256 bytes of on - chip ram ; 2 - kb of nvm memory flash eprom ; 2 - k b of auxiliary ram ; seven 8 - bit , bi - directional and bit - addressable i/o ports; an additional 4 - bit port p4; three 16 - bit timer/counters; moti on feedback module support ; 2 uart serial port s ; 1 channels of i2c wi th master/slave capability ; 1 channels of serial peripheral interface (spi) , 8 channels of 12 bit pwm with configurable dead time and 8 channels of 10 - bit adc . these peripherals are all s upported by 20 interrupt sources with 4 levels of priority . the w79e217 /217 also contains a 64 /32 - k b flash eprom whose contents may be updated in - system by a loader program stored in an auxiliary, 4 - kb flash eprom. once the contents are confirmed, it can b e protect ed for security. 2 features ? ? fully - static - design 8 - bit 4t - 80 51 cmos microcontroller up to 40 mhz . ? ? 64 /32 - kb of in - system - programmable flash eprom (ap flash eprom) . ? ? 4 - kb of auxiliary flash eprom for the loader program (ld flash eprom ) . user can optional ly reboot from ld flash eprom by pull low at either p4.3 or p3.6 and p3.7, at external reset. ? ? 2 - kb auxiliary ram, software - selectable, accessed by movx instruction . ? ? 2 - kb of nvm data flash eprom for customer data storage used . ? ? 256 bytes of scratch - pad ram . ? ? seven 8 - bit bi - directional ports ; port 0 has internal pull - up resisters enabled by software . ? ? one 4 - bit multipurpose i /o port4 with chips select ( cs) and boot function . ? ? three 16 - bit time rs . ? ? one 16 - bit timer 3 for motion feed - back module . ? ? motion feedback mo dule - qei decoder and 3 inputs capture. ? ? eight channel s of 12 - bit pwm : - ? ? complementary paired output with programmable dead - time insertion . ? ? three modes: edge aligned, center aligned and single shot . ? ? output override control for bldc motor application . ? ? 10 - bit adc with 8 - channel inputs . ? ? two enhanced full - duplex uart with framing - error detection and automatic address recognition . ? ? one channel of i2c with master/slave capability . ? ? one channel of spi with master/slave capability . ? ? lcd driver output: - ? ? 32segment x 4co mmon . ? ? 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) driving mode can be selected . ? ? lcd driver output pin can be used as dc output . ? ? software programmable access cycle to external ram/peripherals . ? ? 2 0 interrupt sources with four levels of priority . ? ? software reset f unction .
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 6 - revision a 0. 2 ? ? optional h/l state of ale/psen during power down mode . ? ? built - in power management . ? ? code protection . ? ? pa c kage : - ? ? lead free (rohs) p qfp 100 : w79e217 a f g ? ? lead free (rohs) pqfp 100: w79e216 a fg device operating frequency operating voltage w79e217 a f g up to 40mhz 4.5v ~ 5.5v w79e216 afg up to 40 mhz 4.5 v ~ 5.5v 3 p arts information lis t 3.1 lead free (rohs) parts information list part no. eprom flash size ram nvm flash eprom package remark w79e217 af g 64kb 256b + 2kb 2k b pqfp - 10 0 pin w79e216 af g 32 kb 256b + 2kb 2 k b pqfp - 10 0 pin
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 7 - revision a 0. 2 4 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 w 79 e 21 j pqfp - 100 d h 1 d h 2 v l c d 1 v l c d 2 c o m 3 c o m 2 c o m 1 c o m 0 v d d p w m v s s p w m p 2 . 7 , s d a , a 1 5 , f a [ 1 5 ] p 2 . 5 , p w m 5 , a 1 3 , f a [ 1 3 ] p 2 . 4 , p w m 4 , a 1 2 , f a [ 1 2 ] p 2 . 3 , p w m 3 , a 1 1 , f a [ 1 1 ] p 2 . 2 , p w m 2 , a 1 0 , f a [ 1 0 ] p 2 . 6 , s c l , a 1 4 , f a [ 1 4 ] p 2 . 1 , p w m 1 , a 9 , f a [ 9 ] v d d v s s p 0 . 7 , a d 7 , i n t 5 , f d [ 7 ] p 2 . 0 , p w m 0 , a 8 , f a [ 8 ] p 0 . 6 , a d 6 , i n t 4 , f d [ 6 ] p 0 . 5 , a d 5 , i n t 3 , f d [ 5 ] p 0 . 4 , a d 4 , i n t 2 , f d [ 4 ] p 0 . 3 , s s , a d 3 , f d [ 3 ] p 0 . 2 , s p c l k , a d 2 , f d [ 2 ] p 0 . 1 , m o s i , a d 1 , f d [ 1 ] p 0 . 0 , m i s o , a d 0 , f d [ 0 ] seg 12 , p 5 . 4 seg 11 , p 5 . 3 seg 10 , p 5 . 2 seg 9 seg 8 seg 6 seg 5 seg 4 seg 2 seg 7 seg 3 seg 14 , p 5 . 6 seg 13 , p 5 . 5 seg 15 , p 5 . 7 seg 16 , p 6 . 0 seg 18 , p 6 . 2 seg 17 , p 6 . 1 seg 19 , p 6 . 3 f w i n m e m , w r , p 3 . 6 a v s s f a [ 7 ] , a d c 7 , p 1 . 7 f a [ 6 ] , a d c 6 , p 1 . 6 f a [ 5 ] , a d c 5 , p 1 . 5 f a [ 4 ] , a d c 4 , p 1 . 4 f a [ 3 ] , t x d 1 , a d c 3 , p 1 . 3 f a [ 2 ] , r x d 1 , a d c 2 , p 1 . 2 f a [ 1 ] , b r a k e , a d c 1 , p 1 . 1 f a [ 0 ] , t 2 , a d c 0 , p 1 . 0 v d d v s s p 7 . 7 , s e g 3 1 p 7 . 6 , s e g 3 0 p 7 . 5 , s e g 2 9 p 7 . 4 , s e g 2 8 p 7 . 3 , s e g 2 7 p 7 . 2 , s e g 2 6 a v d d f o e n , t 1 , i c 1 / q e b , p 3 . 5 p 7 . 1 , s e g 2 5 p 6 . 6 , s e g 2 2 p 6 . 7 , s e g 2 3 p 7 . 0 , s e g 2 4 f c e n , t 0 , i c 0 / q e a , p 3 . 4 f c t r l [ 3 ] , i n t 1 , p 3 . 3 f c t r l [ 2 ] , i n t 0 , p 3 . 2 f c t r l [ 1 ] , t x d , p 3 . 1 s e g 0 s e g 1 seg 20 , p 6 . 4 seg 21 , p 6 . 5 b a n k , r d , p 3 . 7 f c t r l [ 0 ] , r x d , p 3 . 0 nc p 4 . 3 p 4 . 2 t 2 ex , ic 2 / indx , p 4 . 1 stadc , p 4 . 0 vdd vss xtal 1 rst ea psen ale pwm 6 , p 5 . 0 pwm 7 , p 5 . 1 xtal 2 nc tms tck tdo tdi
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 8 - revision a 0. 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 w 79 e 217 a / 216 a pqfp - 100 d h 1 d h 2 v l c d 1 v l c d 2 c o m 3 c o m 2 c o m 1 c o m 0 v d d p w m v s s p w m p 2 . 7 , s d a , a 1 5 , f a [ 1 5 ] p 2 . 5 , p w m 5 , a 1 3 , f a [ 1 3 ] p 2 . 4 , p w m 4 , a 1 2 , f a [ 1 2 ] p 2 . 3 , p w m 3 , a 1 1 , f a [ 1 1 ] p 2 . 2 , p w m 2 , a 1 0 , f a [ 1 0 ] p 2 . 6 , s c l , a 1 4 , f a [ 1 4 ] p 2 . 1 , p w m 1 , a 9 , f a [ 9 ] v d d v s s p 0 . 7 , a d 7 , i n t 5 , f d [ 7 ] p 2 . 0 , p w m 0 , a 8 , f a [ 8 ] p 0 . 6 , a d 6 , i n t 4 , f d [ 6 ] p 0 . 5 , a d 5 , i n t 3 , f d [ 5 ] p 0 . 4 , a d 4 , i n t 2 , f d [ 4 ] p 0 . 3 , s s , a d 3 , f d [ 3 ] p 0 . 2 , s p c l k , a d 2 , f d [ 2 ] p 0 . 1 , m o s i , a d 1 , f d [ 1 ] p 0 . 0 , m i s o , a d 0 , f d [ 0 ] seg 12 , p 5 . 4 seg 11 , p 5 . 3 seg 10 , p 5 . 2 seg 9 seg 8 seg 6 seg 5 seg 4 seg 2 seg 7 seg 3 seg 14 , p 5 . 6 seg 13 , p 5 . 5 seg 15 , p 5 . 7 seg 16 , p 6 . 0 seg 18 , p 6 . 2 seg 17 , p 6 . 1 seg 19 , p 6 . 3 f w i n m e m , w r , p 3 . 6 a v s s f a [ 7 ] , a d c 7 , p 1 . 7 f a [ 6 ] , a d c 6 , p 1 . 6 f a [ 5 ] , a d c 5 , p 1 . 5 f a [ 4 ] , a d c 4 , p 1 . 4 f a [ 3 ] , t x d 1 , a d c 3 , p 1 . 3 f a [ 2 ] , r x d 1 , a d c 2 , p 1 . 2 f a [ 1 ] , b r a k e , a d c 1 , p 1 . 1 f a [ 0 ] , t 2 , a d c 0 , p 1 . 0 v d d v s s p 7 . 7 , s e g 3 1 p 7 . 6 , s e g 3 0 p 7 . 5 , s e g 2 9 p 7 . 4 , s e g 2 8 p 7 . 3 , s e g 2 7 p 7 . 2 , s e g 2 6 a v d d f o e n , t 1 , i c 1 / q e b , p 3 . 5 p 7 . 1 , s e g 2 5 p 6 . 6 , s e g 2 2 p 6 . 7 , s e g 2 3 p 7 . 0 , s e g 2 4 f c e n , t 0 , i c 0 / q e a , p 3 . 4 f c t r l [ 3 ] , i n t 1 , p 3 . 3 f c t r l [ 2 ] , i n t 0 , p 3 . 2 f c t r l [ 1 ] , t x d , p 3 . 1 s e g 0 s e g 1 seg 20 , p 6 . 4 seg 21 , p 6 . 5 b a n k , r d , p 3 . 7 f c t r l [ 0 ] , r x d , p 3 . 0 nc nc nc nc nc p 4 . 3 p 4 . 2 t 2 ex , ic 2 / indx , p 4 . 1 stadc , p 4 . 0 vdd vss xtal 1 rst ea psen ale pwm 6 , p 5 . 0 pwm 7 , p 5 . 1 xtal 2 nc
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 9 - revision a 0. 2 5 pin description symbol type descriptions ea i external access enable: this pin forces the processor to execute from externa l rom. the rom address and data are not presented on the bus if the ea pin is high. psen o h program store enable: psen enables the external rom data in the port 0 address/data bus. when internal ro m access is performed, psen strobe signal will not be output from this pin. ale o h address latch enable: ale enable s the address latch that separates the address from the data on port 0. rst i l reset: set this pin high for two mac hine cycles while the oscillator is running to reset the device. xtal1 i crystal 1: c rystal oscillator input or external clock input. xtal2 o crystal 2: c rystal oscillator output. v ss i ground : g round potential. v dd i power supply: supply voltage for o peration. v lc d1, v lc d2 i lcd voltage input. positive (+) supply voltage terminal for lcd biasing. avdd i analog power supply . avss i analog ground potential . vddpwm i pwm power supply . vsspwm i pwm ground potential . p0.0 ? p0.7 i/o d s h port 0 : port 0 is an open - drain bi - directional i/o port. this port also provides a multiplexed low byte address/data bus during accesses to external memory. there is an embedded weakly pull - up resistor on each port 0 pin which can be enable d or disabled by setting or c lear ing of pup0, bit0 in a2h. the ports have alternate functions which are described below : p0.0, miso p0.1 , mosi p0.2 , spclk p0.3 , /ss p0.4 , in t2 p0.5 , in t3 p0.6 , int 4 p0.7 , int 5 p1.0 ? p1.7 i/o s h port 1 : 8 - bit, bi - directional i/o port with internal pul l - ups. the ports have alternate functions which are described below : p1.0, adc0, t2 p1.1, adc1, brake p1.2, adc2, rxd1
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 10 - revision a 0. 2 p1.3, adc3, txd1 p1.4, adc4 p1.5, adc5 p1.6, adc6 p1.7, adc7 p2.0 - p2.7 i/o s h port 2 : 8 - bit, bi - directional i/o port with internal pu ll - ups. this port also provides the upper address bits for accesses to external memory. p2.6 to p2.7 can be software configured as i2c serial ports. p2.0 to p2.5 also provides pwm0 to pwm5 outputs. p2.0, a8, pwm0 p2.1, a9, pwm1 p2.2, a10, pwm2 p2.3, a11, pwm3 p2.4, a12, pwm4 p2.5, a13, pwm5 p2.6, a14, scl p2.7, a15, sda p3.0 - p3.7 i/o s h port 3 : 8 - bit, bi - directional i/o port with internal pull - ups. the ports have alternate functions which are described below : p3.0, rxd p3.1, txd p3.2 , /int0 p3.3 , /int1 p3.4 , t0, ic0, qe a p3.5 , t1, ic1, qeb p3.6, /wr p3.7, /rd p4.0 - p4.3 i/o s h port 4 : 4 - bit multipurpose programmable i/o port with alternate functions. the port 4 has four different operation modes. p4.0, stadc p4.1, t2ex, ic2, indx p4.2 p4.3 p5.0 - p5.7 i /o s h port 5 : 8 - bit, bit - directional i/o port. this port is not bit address able . the alte rnate functions are described below : p5.0, pwm6 p5.1, pwm7 p5[7:2] = seg [15:10] p6.0 - p6.7 i/o d h port 6 : 8 - bit, bit - directional i/o port. this port is not bit addr ess able . p6 [7: 0 ] = seg [23:16] p7.0 - p7.7 i/o s h port 7 : 8 - bit, bit - directional i/o port. this port is not bit address able . p7 [7: 0 ] = seg [31:2 4 ] seg0 - seg 9 o lcd segment output s. can also be used as dc output ports specified by code option.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 11 - revision a 0. 2 dh1, dh2 i capacitor input for lcd driver. com0 - com3 lcd common output s . 1/3 duty 1/4 duty com0 used used com1 used used com2 used used com3 not used used the lcd alternating frequency can be selected by code option. ? ? note : type i: input, o: output, i/o: bi - directional, h: pull - high, l: pull - low, d: open drain s: schmitt trigger 5.1 port 4 port 4, sfr p4 at address a5h, is a 4 - bit multipurpose programmable i/o port which functions are i/o, insert wait function and chip - select function. it has four different o peration mode s : ? ? m ode 0 - p4.0 ~ p4.3 is 4 - bit bi - directional i/o port which is the same as port 1. the default port 4 is a general i/o function. ? ? m ode1 - p4.0 ~ p4.3 are read data strobe signals which are synchronized with rd signal at specified addresses. these read data strobe signals can be used as chip - select signals for external peripherals. ? ? m ode2 - p4.0 ~ p4.3 are write data strobe signals which are synchronized with wr signal at specified addresses. these writ e data strobe signals can be used as chip - select signals for external peripherals. ? ? m ode3 - p4.0 ~ p4.3 are read /write data strobe signals which are synchronized with rd or wr signal at specified addresses. these rea d/write data strobe signals can be used as chip - select signals for external peripherals. when port 4 is configured with the feature of chip - select signals, the chip - select signal address range depends on the contents of the sfr p4xah, p4xal, p4cona and p4 conb. p4xah and p4xal contain the 16 - bit base address of p4.x. p4cona and p4conb contain the control bits to configure the port 4 operation mode.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 12 - revision a 0. 2 6 memory o rganization the w79e217 /217 separates the memory into two sections ; program memory and data memory. program memory store s instruction op - codes, while data memory store s data or memory - mapped devices. 6.1 program memory (on - chip flash) w79e217 /217 includes one 64 /32 k bytes of main flash eprom for application program (ap flash eprom) and one 4k bytes of flash eprom for loader program (ld flash eprom) to operat e the in - system programming (isp) feature , and one 2 k bytes of nvm flash eprom for data storage. the 64 /32 k bytes flash eprom is ap0 bank . the default active bank is ap0. in normal operation, the microco ntroller will execute the code from main flash eprom. by setting program registers, user can force the microcontroller to switch to programming mode which wi ll cause it to execute the code (loader program) from the 4k bytes of auxiliary ld flash eprom to u pdate the contents of the 64 /32 k bytes of main flash eprom. after reset, the microcontroller will executes the new application program in the main flash epro m. this isp feature makes the job easy and efficient in which the application needs to update firmw are frequently without opening the chassis. 6.2 data m emory w79e217 /217 can access up to 64kbytes of external data memory. this memory region is accessed by the movx instructions. u nlike the 8051 derivatives, w79e217 /217 contains on - chip 2 kbytes of data memo ry, which only can be accessed by movx instructions. these 2 kbytes of sram is between address 0000h and 07ffh. access to the on - chip data memory is optional under software control. when enabled by dmeo bit of pmr register , a movx instruction that uses thi s area will go to the on - chip ram. if movx instruction accesses the addresses greater than 07ffh cpu will automatically access external memory through port 0 and 2. when disabled, the 2 kb memory area is transparent to the system memory map. any movx direc ted to the space between 0000h and ffffh goes to the expanded bus on the port 0 and 2. this is the default condition. in addition , the device has the standard 256 bytes of on - chip ram. this can be accessed either by direct addressing or by indirect address ing. there are also some special function registers (sfrs), which can only be accessed by direct addressing. indirect addressing ram direct & indirect addressing ram sfrs direct addressing only 00 h 7 fh 80 h ffh 2 k byte on chip nvm flash eprom movx indirect addressing 2 k byte on chip sram 0000 h 07 ffh 0000 h 07 ffh 64 k / 32 k * bytes on chip ap flash memory 64 k bytes external data memory 4 k bytes ld flash ffffh 0000 h 0000 h 0 fffh 7 fffh w 79 e 218 : 64 k w 79 e 217 : 32 k * figure 6 - 1 : w79e217 a /217a memory map
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 13 - revision a 0. 2 6.3 auxiliary sram w79e217 /217 has a 2 kb of data space sram which is read/write accessible and is memory mapped. this on - chip sram is accessed by the movx instruction. there is no conflict or overlap among the 256 bytes scratch - pad memory and the 2 kb auxiliary sram as they use different addressing modes and instructions. access to the on - chip data memory is optional under software control. set dmeo bit of pmr sfr to 1 will enable the on - chip 2 kb movx sram and at the same time e n nvm bit must be clear ed as nvm memory uses the same instruct ion of movx. refer to table 6 - 3 : w79e217 /217 nvm page ( n) area definition table . 6.4 2 - k b nvm data flash memory w79e217 /217 2 - kb nvm memory blo ck shown in the diagram on figure 6 - 1 : shar es the same address as aux - ram address. due to overlapping of aux - ram, nvm data memory and external data memory physical address, the following table is defined. ennvm bit (nvmcon.5) will enable read access to nvm data memory area. dme0 (pmr.0) will enable read access to au x - ram. e n nvm dme0 data memory area 0 0 enable external ram read/write access by movx 0 1 enable aux - ram read/write access by movx 1 x enable nvm data memory read access by movx only. if eer or ewr is set and nvm flash erase or write control is busy, to set this bit read nvm data is invalid. table 6 - 1 : bits setting for movx access to data memory area ennvm = 1 nvm size = sram (2k) instructions addr = 2k addr > 2k movx a, @dptr (read) nvm ext memory movx a, @r0 (read) nvm nop read access movx a, @r1 (read) nvm nop movx @dptr, a (write) nop ext memory movx @r0, a (write) nop nop write access movx @r1, a (write) nop nop table 6 - 2 : movx read/write access destination it is partition in to 32 pages area and each page has 64 bytes data as below figure. the page 0 is from 0000h ~ 003fh , page 1 is from 00 40 h ~ 00 7f h until page 31 address located at 07coh ~ 07ff h .
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 14 - revision a 0. 2 2 k bytes flash eprom page 31 64 bytes page 30 64 bytes | | | | | | page 03 64 bytes page 02 64 bytes page 01 64 bytes page 00 64 bytes 07 ffh 07 c 0 h 07 bfh 0780 h 0000 h 003 fh 0040 h 007 fh 0080 h 00 bfh 00 c 0 h 00 ffh 0000 h 07 ffh figure 6 - 2 : w79e217 /217 nvm memory mapping page start address end address page start address end address 0 0000h 003fh 16 0400h 043fh 1 0040h 007fh 17 0440h 047fh 2 0080h 00bfh 18 0480h 04bfh 3 00c0h 00ffh 19 04c 0h 04ffh 4 0100h 013fh 20 0500h 053fh 5 0140h 017fh 21 0540h 057fh 6 0180h 01bfh 22 0580h 05bfh 7 01c0h 01ffh 23 05c0h 05ffh 8 0200h 023fh 24 0600h 063fh 9 0240h 027fh 25 0640h 067fh 10 0280h 02bfh 26 0680h 06bfh 11 02c0h 02ffh 27 06c0h 06ffh
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 15 - revision a 0. 2 12 0 300h 033fh 28 0700h 073fh 13 0340h 037fh 29 0740h 077fh 14 0380h 03bfh 30 0780h 07bfh 15 03c0h 03ffh 31 07c0h 07ffh table 6 - 3 : w79e217 /217 nvm page ( n) area definition table it has a dedicated on - chip rc oscillator that is fixed at 6mhz +/ - 25% frequency to support clock source for the 2 k nvm data flash memory. t he on chip oscillator is enabled only during program or erase operation , through ewr or eer in nvmcon sfr. ewr or eer bits are cleared by hardware after program or erase operation completed. the program/erase time is automatically controlled by hardware. 6mhz rc osc 2k bytes nvm data memory block nvmf envm(enable nvm interrupt) ennvm clock source eer ewr erc internal signal flag figure 6 - 3 : nvm control 6.4.1 operation user is required to enable ennvm (nvmcon.5) bit for all nvm access (read/write/erase). before write data to nvm memory, the page must be erased . a page is erased by set ting page address which address will decode and enable page ( n) on nvmaddr h and nvmaddrl , then set eer ( nvmcon.7 ) and ennvm (nvmcon.5). the device will then automatic execute page erase. when completed , nvmf will be set by hardware . nvmf should be cleared by software . interrupt request will be generated if envm (eie1.5) is enabled. eer bit will be cleared by hardware wh en erase is completed. the total erase time is about 5ms. for write, user must set address and data to nvmaddr h/l and nvmdat, respectively. and then set ewr (nvmcon.6) and ennvm ( nvmcon. 5) to enable data write . when completed, the device will set nvmf fla g. nvmf flag should be cleared by soft ware. similarly, interrupt request will be generated if envm (eie1.5) is enabled. the program time is about 50us. the following shows some examples of nvm operations: read nvm data is by movx a,@dptr /r0/r1 instruction :
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 16 - revision a 0. 2 a read exceed 2k will read the external address e xample1: dptr =0x07ff, r0/r1 = 0xff , xramah=0x07, ennvm=1 movx a,@dptr ? read nvm data at address 0x07ff movx a,@ r0 ? read nvm data at address 0x07ff movx a,@ r1 ? read nvm data at address 0x07ff example2 : dptr = 0x2000 , ennvm=1, dme0=0 movx a,@dptr ? read external ram data at address 0x2000 , erase nvm by sfr register : example1: nvmaddrh = 0x07, nvmaddrl = 0xf0, page 31 will be enabled. after set eer, the page 31 will be erased. example2: nvmaddrh = 0x10, nvmaddrl = 0x00, invalid nvm erase instruction (address exceed nvm boundary). write nvm by sfr register : example1: nvmaddrh = 0x07, nvmaddrl = 0xf0 after set ewr, data will be written to the nvm address = 0x07f0 location. example2: nvmaddrh = 0x10, nvma ddrl = 0x00, after set ewr, invalid nvm write instruction (address exceed nvm boundary). during erase, write is invalid. likewise, during write, erase is invalid. a n erase or write is invalid if nvmf is not clear by software. a write to nvmaddrh and nvmad drl is invalid during erase or write , and a writ e to nvmdat is invalid only during nvm write access. ennvm busy eer/ ewr nvmf enable nvm data memory that can be erased, written or read active erase or write erase or write time erase or write time finished erase or write, then set nvmf flag active erase or write cleared ennvm keeping eraes or write finished erase or write, then set nvmf flag to set eer or ewr is invalid to clear nvmf flag by software after finished, hardware will clear after finished, it can be read by movx the nvm memory can?t be read figure 6 - 4 : nvm data memory control t iming for security purposes , this nvm data flash provide s an independent ?lock bit? located in security bits .
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 17 - revision a 0. 2 i t is used to protect the customer?s 2 k bytes of data code. it may be enabled after the external programmer finishes the programming and verif ying sequence. once this bit is set to log ic 0, the 2 k bytes of nvm flash eprom data can not be accessed again by external device . note: 1. nvmf can be poll ed or by h/w interrupt to indicate nvm data memory erase or write operation has completed . 2. while user program is erasing or writing to nv m data memory, the pc counter will continue to fetch for next instruction. 3. when uc is in idle mode and if nvm interrupt and global interrupt are enabled, the completion of either erasing or programming the nvm data memory will exit the idle condition.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 18 - revision a 0. 2 7 special function registers the w79e217 /217 uses special function registers (sfr) to control and monitor peripherals. the sfr reside in register locations 80 - ffh and are only accessed by direct addressing. the w79e217 /217 contains all the sfr present in th e standard 8051/52 , as well as some additional sfr , and, i n some cases , unused bits in the standard 8051/52 have new functions. sfr whose addresses end in 0 or 8 (hex) are bit - addressable . the following table of sfr is condensed , with eight locations per r ow. empty locations indicate that there are no registers at these addresses. f8 eip eie1 eip1 ccl0 /pcntl cch0 /pcnth ccl1 /plscntl cch1 /plscnth intctrl f0 b spcr spsr spdr i2csaden eiph e8 eie i2con i2addr nvmadd rh i2dat i2status i2clk i2timer e0 acc ad c con adch adcl lcdcn pdtc1 p dtc 0 pwmcon4 d8 wdcon pwmpl pwm0l nvmadd rl pwmcon 1 pwm2l pwm6l pwmcon3 d0 psw pwmph pwm0h nvmdat qeicon pwm2h pwm6h wdcon2 c8 t2con t2mod rcap2l rcap2h tl2 th2 pwmcon2 pwm4l c0 scon1 sbuf1 t3mod t3con pmr fsplt adcps t a b8 ip saden saden1 povm povd pio pwmen pwm4h b0 p3 p5 p6 p7 rcap3l rcap3h eip1h iph a8 ie saddr saddr1 lcdpt sfral sfrah sfrfd sfrcn a0 p2 xramah p4csin capcon0 capcon1 p4 ccl2 /maxcntl cch2 /maxcnth 98 scon sbuf p42al p42ah p43al p43ah nvmcon chpco n 90 p1 exif p4cona p4conb p40al p40ah p41al p41ah 88 tcon tmod tl0 tl1 th0 th1 ckcon ckcon1 80 p0 sp dpl dph tl3 th3 lcddata pcon table 7 - 1 : special function register location table
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 19 - revision a 0. 2 symbol definition ad dr ess msb bit _ address, symbol lsb reset intctrl interrupt control register ffh - - int5ct1 int5ct0 int4ct1 int4ct0 int3ct1 int3ct0 xx00 0000b cch1 /plscnth cap ture c ounter high 1 re gister fe h cch1.7 /plscnt h. 7 cch1.6 /plscnt h. 6 cch1.5 /plscnt h. 5 cch1.4 /plscnt h. 4 cch1.3 /plscnt h. 3 cch1.2 /plscnt h. 2 cch1.1 /plscnt h. 1 cch1.0 /plscnt h.0 0000 0000b ccl1 /plscntl cap ture c ounter low 1 register fd h ccl1.7 /plscnt l. 7 ccl1.6 /plscnt l. 6 ccl1 .5 /plscnt l. 5 ccl1.4 /plscnt l. 4 ccl1.3 /plscnt l. 3 ccl1.2 /plscnt l. 2 ccl1.1 /plscnt l. 1 ccl1.0 /plscnt l.0 0000 0000b cch0 /pcnth cap ture c ounter high 0 register fc h cch0.7 /pcnth.7 cch0.6 /pcnth.6 cch0.5 /pcnth.5 cch0.4 /pcnth.4 cch0.3 /pcnth.3 cch0.2 /pcnt h.2 cch0.1 /pcnth.1 cch0.0 /pcnth.0 0000 0000b ccl0 /pcntl cap ture c ounter low 0 register fb h ccl0.7 /pcntl. 7 ccl0.6 /pcntl. 6 ccl0.5 /pcntl. 5 ccl0.4 /pcntl. 4 ccl0.3 /pcntl. 3 ccl0.2 /pcntl. 2 ccl0.1 /pcntl. 1 ccl0.0 /pcntl.0 0000 0000b eip1 extended interru pt priority 1 fah - - pnvmi pcptf pt3 pbkf ppwmf pspi x x 00 0000b eie1 interrupt enable 1 f9h - - envm ecptf et3 ebk epwm espi xx 00 0000b eip extended interrupt priority f8h (ff) ps1 (fe) p x5 (fd) p x4 (fc) pwdi (fb) px3 (fa) px2 (f9) - (f8) pi2c 0000 00x0 b eiph extended interrupt high priority f7h ps1 h p x5 h p x4 h pwdi h px3 h px2 h - pi2c h 0000 00x0b i2csaden i2c slave address mask f6h i2csade n.7 i2csade n.6 i2csade n.5 i2csade n.4 i2csade n.3 i2csade n.2 i2csade n.1 i2csade n.0 1111 1110 b spdr serial peripheral d ata register f5h spd.7 spd.6 spd.5 spd.4 spd.3 spd.2 spd.1 spd.0 xxxx xxxxb spsr serial peripheral status register f4h spif wcol spiovf modf drss - - - 00 0 0 0 xxx b spcr serial peripheral control register f3h ssoe spe lsbfe mstr cpol cpha spr1 spr0 0000 01 00b b b register f0h (f7) (f6) (f5) (f4) (f3) (f2) (f1) (f0) 0000 0000b i2timer i2c timer counter register efh - - - - - enti div4 tif xxxx x 000b i2clk i2c clock rate ee h i2clk.7 i2clk.6 i2clk.5 i2clk.4 i2clk.3 i2clk.2 i2clk.1 i2clk.0 0000 0000b i2stat us i2c status registe r ed h i2statu s .7 i2statu s .6 i2statu s .5 i2statu s .4 i2statu s .3 - - - 1111 1000b i2dat i2c data ec h i2d at. 7 i2d at. 6 i2d at. 5 i2d at. 4 i2d at. 3 i2d at. 2 i2d at. 1 i2d at. 0 0000 0000b nvmaddrh nvm high byte address eb h - - - - - nvmadd rh.10 nvm add rh.9 nvmadd rh.8 xxxx x000 b i2addr i2c slave address ea h addr.7 addr.6 addr.5 addr.4 addr.3 addr.2 addr.1 gc 0000 000 0 b i2con i2c control register e9 h - ens sta sto si aa i2cin - x 000 00 0 xb eie extended interrupt enable e8h (ef) es1 (ee) e x5 (ed) e x4 (ec) ewdi (eb) ex3 (ea) ex2 (e9) (e8) ei2c 0000 00x 0b pwmcon4 pwm control register 4 e7h pwmeo m pwmoo m pwm6o m pwm7o m - - - bkf 0000 x xx 0b p dtc 0 dead time control register 0 e6h p dt c 0 . 7 p dt c 0 . 6 p dt c 0 . 5 p dt c 0 . 4 p dt c 0 . 3 p dt c 0 . 2 p dt c 0 . 1 p dt c 0 .0 0000 0000b p dtc 1 dead time control register 1 e5 h pdtc1.7 pdtc1.6 pdtc1.5 pdtc1.4 pdtc1.3 pdtc1.2 pdtc1.1 pdtc1.0 00 00 0000b lcdcn lcd control register e 4 h lcden clear duty pump - fs2 fs1 fs0 0000 x 000b adc l adc converter result low byte e 3 h adclk1 adclk0 - - - - adc.1 adc.0 00 xx xxxxb adch adc converter result high byte e 2 h adc.9 adc.8 adc.7 adc.6 adc.5 adc.4 adc.3 adc.2 xxxx xxxxb adccon adc control register e1 h adcen - adcex adci adcs aadr2 aadr1 aadr0 0 x00 0 0 00b acc accumulator e0h (e7) (e6) (e5) (e4) (e3) ( e2) (e1) (e0) 0000 0000b pwmcon3 pwm control register 3 dfh pwm7b pwm6b pwm5b pwm 4b pwm 3 b pwm 2 b pwm 1 b pwm0 b 000 0 000 0b pwm6l pwm 6 low bits register deh pwm6.7 pwm6.6 pwm6.5 pwm6.4 pwm6.3 pwm6.2 pwm6.1 pwm6.0 0000 00 00b pwm2l pwm 2 low bits register ddh pwm 2 . 7 pwm 2 . 6 pwm 2 . 5 pwm 2 . 4 pwm 2 . 3 pwm 2 . 2 pwm 2 . 1 pwm 2 .0 0000 0000b pwmcon1 pwm control register 1 dch pwmru n l oad pwm f clrpwm pwm 6 i pwm 4 i pwm 2 i pwm0i 0000 0000b nvmaddrl nvm low byte address dbh nvmadd nvmadd nvmadd nvmadd nvmadd nvm add nvmadd nvmadd 0000 0000b
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 20 - revision a 0. 2 rh.7 rh.6 rh.5 rh.4 rh.3 rh.2 rh.1 rh.8 pwm0l pwm 0 low bits register dah pwm0.7 pwm0.6 pwm0.5 pwm0.4 pwm0.3 pwm0.2 pwm0.1 pwm0.0 0000 0000b pwmpl pwm counter low register d9h pwmp.7 pwmp.6 pwmp.5 pwmp.4 pwmp.3 pwmp.2 pwmp.1 pwmp.0 0000 0000b wdcon wat ch - dog control d8h (df) - (de) por (dd) - (dc) - (db) wdif (da) wtrf (d9) ewt (d8) rwt 0100 0000b wdcon2 watch - dog control2 d7h - - - - - - - strld 0000 0000b pwm6h pwm 6 high bits register d6h - - - - pwm 6 .11 pwm 6 .10 pwm 6 .9 pwm 6 .8 x xxx 00 00b pwm2h pwm 2 high bits register d5h - - - - pwm2.11 pwm2.10 pwm2.9 pwm2.8 x xxx 00 00b qeicon qei control register d4h - - - disidx dir qeim1 qeim0 qeien x xx 0 0000b nvmdat nvm data d3h nvmdat. 7 nvmdat. 6 nvmdat. 5 nvmdat. 4 nvmdat. 3 nvmdat. 2 nvmdat. 1 nvmdat. 0 0000 0000 b pwm0h pwm 0 high bits register d2h - - - - pwm0.11 pwm0.10 pwm0.9 pwm0.8 xxxx 0000b pwmph pwm counter high register d1h - - - - pwmp.11 pwmp.10 pwmp.9 pwmp.8 xxxx 0000b psw program status word d0h (d7) cy (d6) ac (d5) f0 (d4) rs1 (d3) rs0 (d2) ov (d1) f1 (d0) p 0000 0000b pwm4l pwm 4 low bits register cfh pwm 4 . 7 pwm 4 . 6 pwm 4 . 5 pwm 4 . 4 pwm 4 . 3 pwm 4 . 2 pwm 4 . 1 pwm 4 .0 0000 0000b pwmcon2 pwm control register 2 ceh bkch bkps bpen bken fp1 fp0 p mod1 pmod0 0000 0000b th2 t2 reg. high cdh th2.7 th2.6 th2.5 th2.4 th2.3 th2.2 th2.1 th2.0 0000 0000b tl2 t2 reg. low cch tl2.7 tl2.6 tl2.5 tl2.4 tl2.3 tl2.2 tl2.1 tl2.0 0000 0000b rcap2h t2 capture low cbh rcap2h. 7 rcap2h. 6 rcap2h. 5 rcap2h. 4 rcap2h. 3 rcap2h. 2 rcap2h. 1 rcap2h. 0 0000 0000b rcap2l t2 capture high cah rca p2l. 7 rcap2l. 6 rcap2l. 5 rcap2l. 4 rcap2l. 3 rcap2l. 2 rcap2l. 1 rcap2l. 0 0000 0000b t2mod timer 2 mode c9h hc5 hc 4 hc 3 hc 2 t2cr - - dcen 0000 0xx0b t2con timer 2 control c8h (cf) tf2 (ce) exf2 (cd) rclk (cc) tclk (cb) exen2 (ca) tr2 (c9) c/t2 (c8) cp/rl2 000 0 0000b ta time access register c7h ta.7 ta.6 ta.5 ta.4 ta.3 ta.2 ta.1 ta.0 0000 0000b ddio disable digital i/o c6h ddio.7 ddio.6 ddio.5 ddio.4 ddio.3 ddio.2 ddio.1 ddio.0 0000 0000b fsplt fault sampling time register c5h scmp1 scmp0 sfp1 sfp0 sfcen sfc st sfcdir lsbd 0000 0000b pmr power management register c4h - - - - - aleoff - dme0 x xxx x0x0b t3con timer 3 control c 3 h tf3 - - - - tr3 - 0xxx x0x 0b t3mod timer 3 mode control c 2 h enld icen2 icen1 icen0 t3cr - - - 0000 0xxxb sbuf1 serial buffer 1 c1 h sbuf1.7 sbuf1. 6 sbuf1. 5 sbuf1. 4 sbuf1. 3 sbuf1. 2 sbuf1. 1 sbuf1. 0 xxxx xxxxb scon1 serial control 1 c0 h (bf) sm0 _1 /f e _1 (be) sm1 _1 (bd) sm2 _1 (bc) ren _1 (bb) tb8 _1 (ba) rb8 _1 (b9) ti _1 (b8) ri _1 0000 0000b pwm4h pwm 4 high bits register bfh - - - - pwm 4 . 11 pwm 4 .10 pwm 4 .9 pwm 4 .8 x xxx 00 00b pwmen pwm output enable register beh pwm7en pwm6en pwm5en pwm4en pwm3en pwm2en pwm1en pwm0en 0000 0000b pio pwm pin output source select bdh pio7 pio6 pio5 pio4 pio3 pio2 pio1 pio0 0000 0000b povd pwm output state reg isters bch povd.7 povd.6 povd.5 povd.4 povd.3 povd.2 povd.1 povd.0 0000 0000b povm pwm output override control registers bbh povm.7 povm.6 povm.5 povm.4 povm.3 povm.2 povm.1 povm.0 0000 0000b saden1 slave address mask 1 bah saden1 . 7 saden1 . 6 saden1 . 5 sad en1 . 4 saden1 . 3 saden1 . 2 saden1 . 1 saden1 . 0 0000 0000b saden slave address mask b9h saden.7 saden.6 saden.5 saden.4 saden.3 saden.2 saden.1 saden.0 0000 0000b ip interrupt priority b8h (bf) (be) p adc (bd) pt2 (bc) ps (bb) pt1 (ba) px1 (b9) pt0 (b8) px0 0 0 00 0000b iph interrupt high priority b7h - p adch pt2 h ps h pt1 h px1 h pt0 h px0 h x 000 0000b eip1h extended interrupt high priority 1 b6h - - pnvmih pcptfh pt3h pbkfh ppwmh pspi h xx 00 0000b rcap3h reload capture 3 high register b5h rcap 3 h. 7 rcap 3 h. 6 rcap 3 h. 5 rcap 3 h. 4 rcap 3 h. 3 rcap 3 h. 2 rcap 3 h. 1 rcap 3 h. 0 0 000 0000b rcap3l reload capture 3 low register b4h rcap 3 l. 7 rcap 3 l. 6 rcap 3 l. 5 rcap 3 l. 4 rcap 3 l. 3 rcap 3 l. 2 rcap 3 l. 1 rcap 3 l. 0 0 000 0000b p7 port 7 b3h seg.31 seg. 30 seg. 29 seg. 28 seg. 27 seg. 26 seg. 25 seg. 24 11 11 1111b p6 port 6 b2h seg.23 seg. 22 seg. 21 seg. 20 seg. 19 seg.1 8 seg. 17 seg.1 6 1111 1111b
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 21 - revision a 0. 2 p5 port 5 b1h seg.15 seg.1 4 seg.1 3 seg.1 2 seg.1 1 seg.1 0 pwm7 pwm6 1111 1111b p3 port 3 b0h (b7) rd (b6) wr (b5) t1 / ic1/qe b (b4) t0 / ico/qe a (b3) / int1 (b2) / int0 (b1) txd (b0) rxd 1111 1111b sfrcn f/w flash control afh - wfwin noe nce ctrl3 ctrl2 ctrl1 ctrl0 x 011 1111b sfrfd f/w flash data aeh d7 d6 d5 d4 d3 d2 d1 d0 xxxx xxxxb sfrah f/w flash high address adh a15 a14 a13 a12 a11 a10 a9 a8 0000 0000b sfral f/w flash low address ach a7 a6 a5 a4 a3 a2 a1 a0 0000 0000b lcdpt lcd pointer abh - - - - lcdpt .3 lcdpt .2 lcdpt .1 lcdpt .0 xxxx 0000b saddr1 slave address 1 aah saddr1. 7 saddr1. 6 saddr1. 5 saddr1. 4 saddr1. 3 saddr1. 2 saddr1. 1 saddr1. 0 0000 0000b saddr slave address a9h saddr.7 saddr.6 saddr.5 saddr.4 saddr.3 saddr.2 saddr.1 saddr.0 0000 0000b ie interrupt enable a8h (af) ea (ae) eadc (ad) et2 (ac) es (ab) et1 (aa) ex1 (a9) et0 (a8) ex0 0000 0000b cch2 /maxc nth input capture 2 high register/ maximum counter high register a 7h cch2.7 /maxcnt h.7 cch2.6 maxcnt h.6 cch2.5 /maxcnt h.5 cch2.4 /maxcnt h.4 cch2.3 /maxcnt h.3 cch2.2 /maxcnt h.2 cch2.1 /maxcnt h.1 cch2.0 /maxcnt h.0 0000 0000b ccl2 /maxc ntl input capture 2 low register/ maximum counter low register a 6h ccl2.7 /maxcnt l.7 ccl2.6 /maxcnt l.6 ccl2.5 /maxcnt l.5 ccl2.4 /maxcnt l.4 ccl2.3 /maxcnt l.3 ccl2.2 /maxcnt l.2 ccl2.1 /maxcnt l.1 ccl2.0 /maxcnt l.0 0000 0000b p4 port 4 a5h - - - - p4.3 p4.2 t2ex/ic2 /indx stadc xxxx 1111b capcon1 capture control 1 register a4h - - enf2 enf1 enf0 cptf2 / qeif cptf1 / dirf cptf0 xx 00 0000b capcon0 capture control 0 register a3h cct2.1 cct2.0 cct1.1 cct1.0 cct0.1 cct0.0 ccld1 ccld0 0000 0000b p4csin p4 cs sign a2h p43inv p42inv p41inv p40inv - pwdnh rmwfp p0up 0000 x 000b xramah ram hi gh byte address a1h - - - - - a10 a9 a8 0000 0000b p2 port 2 a0h (a7) a15 / sda (a6) a14 / scl (a5) a13 / pwm5 (a4) a12 / pwm4 (a3) a11 / pwm3 (a2) a10 / pwm2 (a1) a9 / pwm1 (a0) a8 / pwm0 1111 1111b chpcon on chip programming control 9fh swrst/ reboot - ld/ap - - - ldsel enp 0000 0000b nvmcon nvm control 9eh eer ewr ennvm - - - - nvmf 000x xxx0b p43ah hi addr. comparator of p4.3 9dh a15 a14 a13 a12 a11 a10 a9 a8 0000 0000b p43al lo addr. comparator of p4.3 9ch a7 a6 a5 a4 a3 a2 a1 a0 0000 0000b p42ah hi addr . comparator of p4.2 9bh a15 a14 a13 a12 a11 a10 a9 a8 0000 0000b p42al lo addr. comparator of p4.2 9ah a7 a6 a5 a4 a3 a2 a1 a0 0000 0000b sbuf serial buffer 99h sbuf.7 sbuf.6 sbuf.5 sbuf.4 sbuf.3 sbuf.2 sbuf.1 sbuf.0 xxxx xxxxb scon serial control 98h (9f) sm0/fe (9e) sm1 (9d) sm2 (9c) ren (9b) tb8 (9a) rb8 (99) ti (98) ri 0000 0000b p41ah hi addr. comparator of p4.1 97h a15 a14 a13 a12 a11 a10 a9 a8 0000 0000b p41al lo addr. comparator of p4.1 96h a7 a6 a5 a4 a3 a2 a1 a0 0000 0000b p40ah hi addr. co mparator of p4.0 95h a15 a14 a13 a12 a11 a10 a9 a8 0000 0000b p40al lo addr. comparator of p4.0 94h a7 a6 a5 a4 a3 a2 a1 a0 0000 0000b p4conb p4 control register b 93h p43 fun 1 p43 fun 0 p43c mp 1 p43c mp 0 p42 fun 1 p42 fun 0 p42c mp 1 p42c mp 0 0000 0000b p4cona p4 control register a 92h p41 fun 1 p41 fun 0 p41c mp 1 p41c mp 0 p40 fun 1 p40 fun 0 p40c mp 1 p40c mp 0 0000 0000b exif external interrupt flag 91h ie5 ie4 ie3 ie2 - - - - 0000 xxxxb p1 port 1 90h (97) adc7 (96) adc6 (95) adc5 (94) adc4 (93) txd1 / adc3 (92) rxd1 / adc2 (9 1) adc1/ brake (90) t2 / adc0 1111 1111b ckcon1 clock control 1 8fh - - - - - - ccdiv1 ccdiv0 0000 0000b ckcon clock control 8eh wd1 wd0 t2m t1m t0m md2 md1 md0 0000 0001b th1 timer high 1 8dh th1.7 th1.6 th1.5 th1.4 th1.3 th1.2 th1.1 th1.0 0000 0000b
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 22 - revision a 0. 2 t h0 timer high 0 8ch th0.7 th0.6 th0.5 th0.4 th0.3 th0.2 th0.1 th0.0 0000 0000b tl1 timer low 1 8bh tl1.7 tl1.6 tl1.5 tl1.4 tl1.3 tl1.2 tl1.1 tl1.0 0000 0000b tl0 timer low 0 8ah tl0.7 tl0.6 tl0.5 tl0.4 tl0.3 tl0.2 tl0.1 tl0.0 0000 0000b tmod timer mode 89h gate t c / m1 m0 gate t c / m1 m0 0000 0000b tcon timer control 88h (8f) tf1 (8e) tr1 (8d) tf0 (8c) tr0 (8b) ie1 (8a) it1 (89) ie0 (88) it0 0000 0000b pcon power control 87h smod smod0 - - gf1 gf0 pd idl 00xx 0000b lcddata lcd data 86h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0000 0000b th3 timer high 3 85h th 3 .7 th3.6 th 3 .5 th 3 .4 th 3 .3 th 3 .2 th 3 .1 th 3 .0 0000 0000b tl3 timer low 3 84h tl 3 .7 tl 3 .6 tl 3 .5 tl 3 .4 tl 3 .3 tl 3 .2 tl 3 .1 tl 3 .0 0000 0000b dph data pointer hig h 83h dph .7 dph .6 dph .5 dph .4 dph .3 dph .2 dph .1 dph .0 0000 0000b dpl data pointer low 82h dpl.7 dpl.6 dpl.5 dpl.4 dpl.3 dpl.2 dpl.1 dpl.0 0000 0000b sp stack pointer 81h sp.7 sp.6 sp.5 sp.4 sp.3 sp.2 sp.1 sp.0 0000 0111b p0 port 0 80h (87) int5 (86) int 4 (85) int3 (84) int2 (83) /ss (82) spclk (81) mosi (80) miso 1111 1111b table 7 - 2: special function register s
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 23 - revision a 0. 2 port 0 bit: 7 6 5 4 3 2 1 0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 mnemonic: p0 address: 80h port 0 is an open - drain 8 - bit bi - directional i/o port. as an alternate function port 0 can function as the multiplexed address/data bus to access off - chip memory. during the time when ale is high, the lsb of a memory address is presented. when ale is low , the port transi t s to a bi - directional data bus. this bus is used for read ing external rom and for read ing or writ ing external ram memory or peripherals. when used as a memory bus, the port provides active high drivers. the reset condition of port 0 is tri - state. pull - up resistors are required when using port 0 as an i/o port. bit name function 0 p0.0 miso: spi master in slave out . 1 p0.1 mosi: spi master out slave in . 2 p0.2 spclk: spi clock . 3 p0.3 /ss: slave select . 4 p0.4 in t2: external interrupt 2. 5 p0.5 in t3: external i nterrupt 3. 6 p0.6 int 4: external interrupt 4. 7 p0.7 int 5: external interrupt 5. stack pointer bit: 7 6 5 4 3 2 1 0 sp.7 sp.6 sp.5 sp.4 sp.3 sp.2 sp.1 sp.0 mnemonic: sp address: 81h the stack pointer stores the scratch - pad ram address where the stac k begins. in other words it always points to the top of the stack. data pointer low bit: 7 6 5 4 3 2 1 0 dpl.7 dpl.6 dpl.5 dpl.4 dpl.3 dpl.2 dpl.1 dpl.0 mnemonic: dpl a ddress: 82h this is the low byte of the standard 8032 16 - bit data pointer. data poi nter high bit: 7 6 5 4 3 2 1 0 dph.7 dph.6 dph.5 dph.4 dph.3 dph.2 dph.1 dph.0 mnemonic: dph a ddress: 83h this is the high byte of the standard 8032 16 - bit data pointer.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 24 - revision a 0. 2 timer 3 lsb bit: 7 6 5 4 3 2 1 0 tl 3 .7 tl 3 .6 tl 3 .5 tl 3 .4 tl 3 .3 tl 3 .2 tl 3 .1 tl 3 . 0 mnemonic: tl3 a ddres s: 84 h bit name function 7 - 0 timer 3 lsb lsb of timer3 timer 3 msb bit: 7 6 5 4 3 2 1 0 th 3 .7 th3.6 th 3 .5 th 3 .4 th 3 .3 th 3 .2 th 3 .1 th 3 .0 mnemonic: th 3 address: 85 h bit name function 7 - 0 timer 3 msb msb of timer3 lcd d ata regist er bit: 7 6 5 4 3 2 1 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mnemonic: lcddata address: 86 h bit name function 7 - 0 lcddata data written to this register will be display to the lcd segment and common . 0: turn off lcd. 1: turn on lcd. power control bi t: 7 6 5 4 3 2 1 0 sm o d smod0 - - gf1 gf0 pd idl mnemonic: pcon address: 87h bit name function 7 smod this bit doubles the serial port baud rate in mode 1, 2, and 3 when set to 1. 6 smod0 framing error detection enable . when smod0 is set to 1, then s con.7 (scon1.7) now indicates a frame error and acts as the fe (fe_1) flag. when smod0 is 0, then scon.7 (scon1.7) acts as per the standard 8032 function. 5 - 4 - reserved. 3 - 2 gf1 - 0 these two bits are general purpose user flags. 1 pd setting this bit cau ses the device to go into the powerdown mode. in this mode all the clocks are stopped and program execution is frozen. 0 idl setting this bit causes the device to go into the idle mode. in this mode the clock to the cpu is stopped, so program execution is frozen, but the clock to the serial ports , timer , pwm, adc, spi and interrupt blocks is not stopped, and these blocks continue operating unhindered.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 25 - revision a 0. 2 timer control bit: 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 mnemonic: tcon address: 88h bit nam e function 7 tf1 timer 1 o verflow f lag . this bit is set when timer 1 overflows. it is cleared automatically when the program does a timer 1 interrupt service routine. software can also set or clear this bit. 6 tr1 timer 1 r un c ontrol . this bit is set or cleared by software to turn timer/counter on or off. 5 tf0 timer 0 o verflow f lag . this bit is set when timer 0 overflows. it is cleared automatically when the program does a timer 0 interrupt service routine. software can also set or clear this bit. 4 tr 0 timer 0 r un c ontrol . this bit is set or cleared by software to turn timer/counter on or off. 3 ie1 interrupt 1 e dge d etect flag : set by hardware when an edge/level is detected on int1. this bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. otherwise it follows the inverse of the pin. 2 it1 interrupt 1 t ype c ontrol . set/cleared by software to specify falling edge/ low level triggered external inputs. 1 ie0 interrupt 0 e dge d etect flag. set by ha rdware when an edge/level is detected on int0. this bit is cleared by hardware when the service routine is vectored to only if the interrupt was edge triggered. otherwise it follows the inverse of the pin. 0 it0 interrupt 0 type c ontrol: set/cleared by so ftware to specify falling edge/ low level triggered external inputs. timer mode control bit: 7 6 5 4 3 2 1 0 gate t c / m1 m0 gate t c / m1 m0 timer1 timer0 mnemonic: tmod address: 89h bit name function 7 gate gat ing control: when this bit is set, timer 1 is enabled only while the int1 pin is high and the tr 1 control bit is set. when clear ed, the int1 pin has no effect, and timer 1 is enabled whenever tr1 is set. 6 t c/ timer or counter select: when clear, t imer 1 is incremented by the internal clock. when set, the timer counts falling edges on the t 1 pin. 5 m1 timer 1 m ode s elect bit 1. see table below. 4 m0 timer 1 m ode s elect bit 0. see table below.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 26 - revision a 0. 2 3 gate gating c ontrol: when this bit is set, timer 0 is enabled only while the int0 pin is high and the tr 0 control bit is set. when clear ed , the int0 pin has no effect, and timer 0 is enabled whenever tr0 is set. 2 t c/ time r or counter select: when clear, t imer 0 is incremented by the internal clock. when set, the timer counts falling edges on the t 0 pin. 1 m1 timer 0 m ode s elect bit 1. see table below. 0 m0 timer 0 m ode s elect bit 0. see table below. m1, m0: mode select bits: m1 m0 mode 0 0 mode 0: 8 - bit timer/counter tlx serves as 5 - bit pre - scale. 0 1 mode 1: 16 - bit timer/counter , no pre - scale. 1 0 mode 2: 8 - bit timer/counter with auto - reload from thx 1 1 mode 3: (timer 0) tl0 is an 8 - bit timer/counter controlled by the standard timer - 0 control bits. th0 is a n 8 - bit timer only controlled by timer - 1 control bits. (timer 1) timer/ c ounter 1 is stopped. t imer 0 lsb bit: 7 6 5 4 3 2 1 0 tl0.7 tl0.6 tl0.5 tl0.4 tl0.3 tl0.2 tl0.1 tl0.0 mnemonic: tl0 address: 8ah tl0.7 - 0 timer 0 lsb timer 1 lsb bit: 7 6 5 4 3 2 1 0 tl1.7 tl1.6 tl1.5 tl1.4 tl1.3 tl1.2 tl1.1 tl1.0 mnemonic: tl1 address: 8bh tl1.7 - 0 timer 1 lsb timer 0 msb bit: 7 6 5 4 3 2 1 0 th0.7 th0.6 th0.5 th0.4 th0.3 th0.2 th0.1 th0.0 mnemonic: th0 address: 8ch th 0.7 - 0 timer 0 msb timer 1 msb bit: 7 6 5 4 3 2 1 0 th1.7 th1.6 th1.5 th1.4 th1.3 th1.2 th1.1 th1.0 mnemonic: th1 address: 8dh th1.7 - 0 timer 1 msb
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 27 - revision a 0. 2 clock control bit: 7 6 5 4 3 2 1 0 wd1 wd0 t2m t1m t0m md2 md1 md0 mnemonic: ckcon address: 8eh bit na me function 7 wd1 watchdog t imer mode select bit 1. see table below. 6 wd0 watchdog t imer mode select bit 0. see table below. 5 t2m timer 2 clock select: 1 : divide - by - 4 clock . 0 : divide - by - 12 clock . 4 t1m timer 1 clock select: 1 : divide - by - 4 clock . 0 : divide - by - 12 clock . 3 t0m timer 0 clock select: 1 : divide - by - 4 clock . 0 : divide - by - 12 clock . 2 md2 stretch movx select bit 2 : md2, md1, and md0 select the stretch value for the movx instruction. the rd or wr strobe is st retched by the selected interval , which enables the device to access faster or slower external memory devices or peripherals without the need for external circuits. by default, the stretch value is one . see table below. (note: when accessing on - chip sram, these bits have no effect, and the movx instruction always takes two machine cycles. ) 1 md1 stretch movx select bit 1. see md2. 0 md0 stretch movx select bit 0 . see md2. wd 1, wd 0: mode select bits: these bits determine the time - out period s for the watch dog timer. t he reset time - out period is 512 clocks more than the interrupt time - out period. wd1 wd0 interrupt time - out reset time - out 0 0 2 17 2 17 + 512 0 1 2 20 2 20 + 512 1 0 2 23 2 23 + 512 1 1 2 26 2 26 + 512 md2, md1, md0 : stretch movx select bits: m d 2 m d 1 m d 0 stretch value movx duration 0 0 0 0 2 machine cycles 0 0 1 1 3 machine cycles (default) 0 1 0 2 4 machine cycles 0 1 1 3 5 machine cycles 1 0 0 4 6 machine cycles
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 28 - revision a 0. 2 1 0 1 5 7 machine cycles 1 1 0 6 8 machine cycles 1 1 1 7 9 machine cycles c lock control 1 bit: 7 6 5 4 3 2 1 0 - - - - - - cc div1 ccdiv0 mnemonic: ckcon 1 address: 8 f h bit name function 7 - 2 - reserved. 1 - 0 ccdiv timer 3 clock select. ccdiv1 ccdiv0 timer 3 clock 0 0 fosc 0 1 fosc/4 1 0 fosc/16 1 1 fosc/32 port 1 bit: 7 6 5 4 3 2 1 0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 mnemonic: p1 address: 90h bit name function 7 - 0 p1 general purpose i/o port. most instructions will read the port pins in case of a port read access, however in case of read - modify - write instructi ons, the port latch is read. some pins also have alternate input or output functions. th e alternate functions are described below . alternate function1 alternate function2 p1.0 t2 : external i/o for timer/counter 2 adc0: analog input0 p1.1 pwm brake adc 1: analog input1 p1.2 rxd1 adc2: analog input2 p1.3 txd1 adc3: analog input3 p1.4 adc4: analog input4 p1.5 adc5: analog input5 p1.6 adc6: analog input6 p1.7 adc7: analog input7
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 29 - revision a 0. 2 external interrupt flag bit: 7 6 5 4 3 2 1 0 ie5 ie4 ie3 ie2 - - - - mnemonic: exif address: 9 1 h bit name function 7 ie5 external interrupt 5 flag. set by hardware when a rising/falling/both edges is detected onint5 pin. 6 ie4 external interrupt 4 flag. set by hardware when a rising/falling/both edges is detected on int4 pin. 5 ie3 external interrupt 3 flag. set by hardware when a rising/falling/both edges is detected on int3 pin. 4 ie2 external interrupt 2 flag. set by hardware when a rising edge is detected on int2 pin. 3 - 0 - reserved. port 4 control register a bit: 7 6 5 4 3 2 1 0 p41 fun 1 p41 fun 0 p41c mp 1 p41c mp 0 p40 fun 1 p40 fun 0 p40c mp 1 p40c mp 0 mnemonic: p4cona address: 92h port 4 control register b bit: 7 6 5 4 3 2 1 0 p43 fun 1 p43 fun 0 p43c mp 1 p43c mp 0 p42 fun 1 p42 fun 0 p42c mp 1 p42c mp 0 mnemonic: p4conb addres s: 9 3h
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 30 - revision a 0. 2 p4.0 base address low byte register bit: 7 6 5 4 3 2 1 0 a7 a6 a5 a4 a3 a2 a1 a0 mnemonic: p40al address: 94h p4.0 base address high byte register bit: 7 6 5 4 3 2 1 0 a15 a14 a13 a12 a11 a10 a9 a8 mn emonic: p40ah address : 95h p4.1 base address low byte register bit: 7 6 5 4 3 2 1 0 a7 a6 a5 a4 a3 a2 a1 a0 mnemonic: p4 1 al address: 9 6 h p4.1 base address high byte register bit: 7 6 5 4 3 2 1 0 a15 a14 a13 a12 a11 a10 a9 a8 mnemonic: p4 1 ah address: 9 7 h serial port cont rol bit: 7 6 5 4 3 2 1 0 sm0/fe sm1 sm2 ren tb8 rb8 ti ri mnemonic: scon address: 98h bit name function bit name function p4x fun 1, p4x fun 0 port 4 alternate modes. =00 : mode 0. p4.x is a general purpose i/o port which is the same as port 1. =01 : mode 1. p4.x is a read strobe signal for chip select purpose. the address range depends on the sfr p4xah, p4xal and bits p4xc mp 1, p4xc mp 0. =10 : mode 2. p4.x is a write strobe signal for chip select purpose. the address range depends on the sfr p4xah, p4xal and bits p4xc mp 1, p4xc mp 0. =11 : mode 3. p4.x is a read/write strobe signal for chip select purpose. the a ddress range depends on the sfr p4xah, p4xal and bits p4xc mp 1, p4xc mp 0. p4xc mp 1, p4xc mp 0 port 4 chip - select mode address comparison: =00 : compare the full address (16 bits length) with the base address registers p4xah and p4xal. =01 : compare the 15 high bits (a15 - a1) of address bus with the base address registers p4xah and p4xal. =10 : compare the 14 high bits (a15 - a2) of address bus with the base address registers p4xah and p4xal. =11 : compare the 8 high bits (a15 - a8) of address bus with the base address registers p4xah and p4xal.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 31 - revision a 0. 2 7 sm0/fe serial p ort m ode select bit 0 or framing error flag: this bit is controlled by t he smod0 bit in the pcon register. ( sm0 ) see table below. ( fe ) t his bit indicate s an invalid stop bit. it must be manually cleared by software. 6 sm1 serial p ort mode select bit 1. see table below. 5 sm2 serial port clock or multi - p rocessor c ommunication. (mode 0) this bit controls the serial port clock. if set to zero , the serial port runs at a divide - by - 12 clock of the oscillator. this is compatib le with the standard 8051/52. if set to one, the serial clock is a divide - by - 4 clock of the oscillator. (mode 1) if sm2 is set to one, ri is not activated if a valid s top bit is not received. (modes 2 / 3) this bit enables multi - processor communication. if sm2 is set to one, ri is not activated if rb8, the ninth data bit, is zero. 4 ren receive enable: 1 : enable serial reception . 0: disable serial reception . 3 tb8 (mo des 2 / 3) this is the 9th bit to transmit . this bit is set by software. 2 rb8 (mode 0) no function. (mode 1) if sm2 = 0, rb8 is the stop bit that was received. (m odes 2 / 3 ) t his is the 9th bit that was received . 1 ti transmit interrupt flag: this flag is set by the hardware at the end of the 8th bit in mode 0 or at the beginning of the stop bit in the other modes during serial transmission. this bit must be cleared by software. 0 ri receive interrupt flag: this flag is set by the hardware at the end of the 8th bit in mode 0 or halfway through the stop bits in the other modes during serial reception. however , sm2 can restrict this behavior . this bit can only be cleared by software. s m1, s m0: mode select bits: s m1 s m0 mode description length baud rate 0 0 0 synchronous 8 tclk divided by 4 or 12 0 1 1 asynchronous 10 variable 1 0 2 asynchronous 11 tclk divided by 32 or 64 1 1 3 asynchronous 11 variable serial data buffer bit: 7 6 5 4 3 2 1 0 sbuf.7 sbuf.6 sbuf.5 sbuf.4 sbuf.3 sbuf.2 sbuf.1 sbuf.0 m nemonic: sbuf address: 99h bit name function 7 - 0 sbuf serial data is read from or writt en to this location. it consists of two separate 8 bit registers. on e is the receive buffer , and the other is the transmit buffer. any read access gets data from the re ceive data buffer, while write access is to the transmit data buffer. p4.2 base address low byte register
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 32 - revision a 0. 2 bit: 7 6 5 4 3 2 1 0 a7 a6 a5 a4 a3 a2 a1 a0 mnemonic: p4 2 al a ddress: 9 a h p4.2 base address high byte register bit: 7 6 5 4 3 2 1 0 a15 a14 a13 a12 a11 a10 a9 a8 mnemonic: p4 2 ah address: 9 b h p4.3 base address low byte register bit: 7 6 5 4 3 2 1 0 a7 a6 a5 a4 a3 a2 a1 a0 mnemonic: p4 3 al address: 9 c h p4.3 base address high byte register bit: 7 6 5 4 3 2 1 0 a15 a14 a13 a12 a11 a10 a9 a8 mn emonic: p4 3 ah address: 9 d h nvm control bit: 7 6 5 4 3 2 1 0 eer ewr e n nvm - - - - nvmf mnemonic: nvmcon address: 9e h bit name function 7 eer set this bit to erase nvm data of page (n) to ffh. the nvm has 32 page s that each page ha s 64 bytes data memory . b y select nvmaddr h and nvmaddrl of nvm address register s that will automatic enable page area . if set this bit, the page will be page erased , after finished, the nvmf flag will be set to ? 1 ? , then this bit will be cleared. if nvmf flag is set, the erase and write nvm data memory are invalid . 6 ewr set this bit is write data to nvm data memory by nvmaddrh and nvmaddrl to decode nvm data memory. if finished, nvmf flag will be set to ? 1 ? , and then this bit will be cleared . if nvmf flag is set, the erase an d write nvm are invalid . 5 ennvm to enable read nvm data memory area, refer as below table. 0: to disable the movx instruction to read nvm data memory. 1: to enable the movx instruction to read nvm data memory, the external ram or aux - ram will be disabled . 4 ~1 - reserved . 0 nvmf nvm data memory erases or writes finished flag. if nvm data memory is finished by erase or write, it will be set to ? 1 ? by har d ware and clear by software. a nd it will be interrupted when nvm erase/write interrupt is enabled. is p control register bit: 7 6 5 4 3 2 1 0
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 33 - revision a 0. 2 swrst/ hwb - ld / ap - - - ldsel enp mnemonic: chpcon address: 9f h bit name function 7 w:swrst r:hwb write access to this bit is different from read access. write this bit to 1 to force the microcontroller to reset to the initial condition , just like power - on reset. this action re - boot s the microcontroller and start s normal operation. this bit will be cleared during the reset. r ead this bit to determine whether or not a hardware reboot is in progress . if cpu is rebo oted by p 3 .6 & p 3 .7 or p4.3, this bit is set to 1 after the hardware reboot. 6 - reserved. 5 ld/ap (read - only) 0: cpu is executing a p flash eprom 1: cpu is executing ld flash eprom 4 - 2 - reserved. 1 ldsel (write - only) loader program location select ion . this bit should be set before entering isp mode. 0: the executing program is in the 64 - kb ap flash ep rom. the 4 - kb ld flash ep rom is the destination for re - programming. 1: the executing program is in the 4 - kb memory bank. the 64 - kb ap flash ep rom is the destination for re - programming. 0 enp flash eprom programming enable. 1: e nable in - system programming mode . in this mode, erase, program and read operations are achieve d . 0: d isable in - system programming mode . the on - chip flash memory is read - only. the way to enter isp mode is to set enp to 1 and write ldsel properly then force cpu in idle mode, after idle mode is released cpu will restart from ap or ld rom according the value of ldsel. port 2 bit: 7 6 5 4 3 2 1 0 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2. 0 mnemonic: p2 address: a0h bit name function 7 - 0 p2 this port functions as an address bus during external memory access, and as a general - purpose i/o port on devices that incorporate internal program memory. when p2 functions a n on - multiplexed address b us a15 - a8 the port latch cannot be used for general i/o purposes but exists to support the movx instructions. port 2 data will only be brought out on the p2.7 - 0 pins during indirect movx instructions. alternate function p2.0 pwm0 output . p2.1 pwm 1 out put .
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 34 - revision a 0. 2 p2.2 pwm 2 output . p2.3 pwm 3 output . p2.4 pwm 4 output . p2.5 pwm 5 output . p2.6 scl, i2c serial clock. p2.7 sda, i2c serial data . xramah bit: 7 6 5 4 3 2 1 0 - - - - - a1 0 a 9 a 8 mnemonic: xramah address: a1h bit name function 7 - 3 - reserved. 2 - 0 a10 - 8 xramah is used for high byte address memory access through a15 - 8, when cpu executes movx with r0 (or r1) instructions. depending ennvm and dme0 setting, and address, the memory accessed may differs. table below shows the memory access destination . this device has on - chip sram fixed at 2k bytes. ennvm = 1 nvm size = sram (2k) nvm size (1k) : note < sram (2k) dme0 = 0 dme0 = 1 instr. addr = 2k addr > 2k addr = 1k/512b/256 b 1k < addr < 2k addr > 2k addr = 1k/512b/2 56b 1k < addr < 2k addr > 2k movx a, @dptr (read) nvm 1 ext memory 1 nvm 1 ext memory 1 ext memory 1 nvm 1 sram 1 ext memory 1 movx a, @r0 (read) nvm 2 inv alid (see n ote) nvm 2 ext memory port2:gpio 3 invalid (see n ote) nvm 2 sram 2 invalid (see n ote) movx a, @r1 (read) nvm 2 invalid (see n ote) nvm 2 ext memory port2:gpio 3 invalid (see n ote) nvm 2 sram 2 invalid (see n ote) movx @d ptr, a (write) nop ext memory 1 nop ext memory 1 ext memory 1 nop sram 1 ext memory 1 movx @r0, a (write) nop nop nop ext memory port2:gpio 3 invalid (see n ote) nop sram 2 invalid (see n ote) movx @r1, a nop nop nop ext memory port2:gpio 3 i nvalid (see n ote) nop sram 2 invalid (see n ote)
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 35 - revision a 0. 2 (write) tabel 7 - 1 : memory access destination 1. a15~a0=dptr 2. a15~a8=xramah 3. a15~a8=p2(gpio), xramah is invalid. note: user should take care when accessing the memory with this instruction. access to invalid regions may cause undesirable results. p ort 4 c hip - select p olarity bit: 7 6 5 4 3 2 1 0 p43inv p42inv p41inv p40inv - pwdnh rmwfp pup0 mnemonic: p4csin address: a2h bit name function 7 - 4 p4xinv the a ctive p olarity of p4.x when it is set as a chip - select strobe output . high = active high. low = active low. note: x = 3,2,1,0. 3 - reserved. 2 pwdnh set pwdnh to logic 1 then ale and psen will keep high state, clear this bit to logic 0 then ale and pse n will output low during power down mode. 1 rmwfp control read path of instruction ? read - modify - write ? . when this bit is set, the read path of executing ? read - modify - write ? instruction is from port pin otherwise from sfr. 0 pup0 enable port 0 weak pull u p. capture control 0 register bit: 7 6 5 4 3 2 1 0 cct2.1 cct2.0 cct1.1 cct1.0 cct0.1 cct0.0 ccld1 ccld0 mnemonic: capcon0 address: a3 h bit name function 7 - 6 cct2.1 - 0 capture 2 edge select. cc t2. 1 cct2. 0 description 0 0 rising edge trigger 0 1 falli ng edge trigger 1 0 rising and falling edge trigger 1 1 reserved. 5 - 4 cct1.1 - 0 capture 1 edge select. cc t1. 1 cct1. 0 description 0 0 rising edge trigger 0 1 falling edge trigger 1 0 rising and falling edge trigger
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 36 - revision a 0. 2 1 0 rising and falling edge trigger 1 1 reserved. 3 - 2 cct0.1 - 0 capt ure 0 edge select. cc t0. 1 cct0. 0 description 0 0 rising edge trigger 0 1 falling edge trigger 1 0 rising and falling edge trigger 1 1 reserved. 1 - 0 ccld.1 - 0 reload trigger select. cc ld 1 ccld 0 description 0 0 timer 3 overflow (default) 0 1 reload b y capture 0 block 1 0 reload by capture 1 block 1 1 reload by capture 2 block capture control 1 register bit: 7 6 5 4 3 2 1 0 - - enf2 enf1 enf0 cptf2 cptf1 / di r f cptf0 / qeif mnemonic: capcon1 address: a4h bit name function 7 - 6 - reserved. 5 enf2 enable filter for capture input 2 . 4 enf1 enable filter for capture input 1 . 3 enf0 enable filter for capture input 0 . 2 cptf2/ qeif input capture/reload 2 interrupt flag . 1 cptf1 /driif input capture 1 flag share the same bit with di r f flag . ic mode - input capture/reload 1 interrupt flag . qei mode - direction changed interrupt flag. bit is set by hardware when direction index (di r) changes state and direction change interrupt is requested if it is enabled. drif is cleared by software. 0 cptf0 input ca pture 0 flag share the same bit with qei flag . ic mode ? input capture/reload 0 interrupt flag. qei mode - qei interrupt flag. 1. in free - counting mode, if pulse counter is overflow or underflow. 2. in compare - cou nting mode, if pulse counter match es maximu m counter value . port 4 bit: 7 6 5 4 3 2 1 0
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 37 - revision a 0. 2 - - - - p4.3 p4.2 p4.1 p4.0 mnemonic: p4 a ddress: a5h bit name function 7 - 4 - reserved. 3 - 2 p4 gpio. 1 p4 gpio. alternate function t2ex/ic2/ indx for timer 2 external trigger/input capture 2/ index input re spectively. 0 p4 gpio. alternate function stadc . external start adc trigger input . input capture 2/maximum counter low register bit: 7 6 5 4 3 2 1 0 ccl2.7/ maxcnt l.7 ccl2.6/ maxcnt l.6 ccl2.5/ maxcnt l.5 ccl2.4/ maxcnt l.4 ccl2.3/ maxcnt l.3 ccl2.2/ maxcnt l.2 ccl2.1/ maxcnt l.1 ccl2.0/ maxcnt l.0 mnemonic: ccl2/maxcnt l address: a6 h input capture 2/maximum counter high register bit: 7 6 5 4 3 2 1 0 cch2.7/ maxcnt h.7 cch2.6/ maxcnt h.6 cch2.5/ maxcnt h.5 cch2.4/ maxcnt h.4 cch2.3/ maxcnt h.3 cch2.2/ maxcnt h.2 cch2 .1/ maxcnt h.1 cch2.0/ maxcnt h.0 mnemonic: cch2/maxcnt h address: a7 h interrupt enable bit: 7 6 5 4 3 2 1 0 ea eadc et2 es et1 ex1 et0 ex0 mnemonic: ie address: a8h bit name function 7 ea global enable: enable/disable all interrupts . 6 eadc enable adc interrupt . 5 et2 enable timer 2 interrupt. 4 es enable serial port 0 interrupts. 3 et1 enable timer 1 interrupt. 2 ex1 enable external interrupt 1. 1 et0 enable timer 0 interrupt. 0 ex0 enable external interrupt 0. slave address bit: 7 6 5 4 3 2 1 0 saddr.7 saddr.6 saddr.5 saddr.4 saddr.3 saddr.2 saddr.1 saddr.0 mnemonic: saddr address: a9h
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 38 - revision a 0. 2 bit name function 7 - 0 saddr the saddr should be programmed to the given or broadcast address for serial port to which the slave processor is designated. sla ve address 1 bit: 7 6 5 4 3 2 1 0 saddr1. 7 saddr1. 6 saddr1. 5 saddr1. 4 saddr1. 3 saddr1. 2 saddr1. 1 saddr1. 0 mnemonic: saddr 1 address: a a h bit name function 7 - 0 saddr 1 the saddr 1 should be programmed to the given or broadcast address for serial port 1 to which the slave processor is designated. lcd pointer register bit: 7 6 5 4 3 2 1 0 - - - - lcdpt .3 lcdpt .2 lcdpt .1 lcdpt .0 mnemonic: lcdpt address: a b h bit name function 7 - 4 - reserved. 3 - 0 lcdpt address pointer between 0h~fh. isp address low byte bit: 7 6 5 4 3 2 1 0 a7 a6 a5 a4 a3 a2 a1 a0 mnemonic: sfral address: ach low byte destination address for in system programming operations. isp address high byte bit: 7 6 5 4 3 2 1 0 a15 a14 a13 a12 a11 a10 a9 a8 mnemonic: sfr a h address: a d h lo w byte destination address for in system programming operations. (sfrah, sfral) represents the address of the rom byte that will be erased, programmed or read. isp data buffer bit: 7 6 5 4 3 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 mnemonic: sfrfd address: ae h in isp mode, read/write a specific byte rom content must go through sfrfd register. isp operation modes bit: 7 6 5 4 3 2 1 0 - wfwin noe nce ctrl3 ctrl2 ctrl1 ctrl0 mnemonic: sfrcn address: afh
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 39 - revision a 0. 2 bit name function 7 - reserved. 6 wfwin on - chip flash eprom bank select for in - system programming. 0= ap flash eprom bank is selected as destination for re - programming. 1= ld flash eprom bank is selected as destination for re - programming. 5 noe flash eprom output enable. 4 nce flash eprom chip enable. 3 - 0 ctrl the flash control signals . isp mode wfwin noe nce ctrl [ 3:0 ] sfrah, sfral sfrfd erase 4kb ld flash 1 1 0 0010 x x erase 64/32k ap flash0 0 1 0 0010 x x program 4kb ld flash 1 1 0 0001 address in data in program 64/32kb ap flash0 0 1 0 0001 addre ss in data in read 4kb ld flash 1 0 0 0000 address in data out read 64kb ap flash0 0 0 0 0000 address in data out port 3 bit: 7 6 5 4 3 2 1 0 p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 mnemonic: p3 address: b0h bit name function 7 - 0 p3 genera l purpose i/o port. each pin also has a n alternate input or output function that is controlled by other sfrs . the alternate function is enabled if the corresponding port latch bit is set to 1. alternate function p3.7 rd strobe for read from external ram . p3.6 w r strobe for write to external ram . p3.5 t1 /ic1/qe b ; timer/counter 1 external count input /input capture 1/qei input b .
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 40 - revision a 0. 2 p3.4 t0 /ic0/ qea ; timer/counter 0 external count input /input capture 0/qei in put a . p3.3 int0 external interrupt 1 . p3.2 int1 external interrupt 0 . p3.1 txd serial port output . p3.0 rxd serial port input . port 5 bit: 7 6 5 4 3 2 1 0 p5.7 p5.6 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 mnemonic: p5 address: b1h bit name function 7 - 0 p 5 general purpose i/o port. each pin also has an alternate in put or output function. this port can not support bit address able . alternate function p5[7:2] seg [15:10] p5.1 pwm7 output function p5.0 pwm6 output function port 6 bit: 7 6 5 4 3 2 1 0 p6.7 p6.6 p6.5 p6.4 p6.3 p6.2 p6.1 p6.0 mnemonic: p6 address : b2h bit name function 7 - 0 p 6 general purpose i/o port. the alternate function of p6[7:0] is seg[23:16]. this port can not support bit address able . alternate function p 6 [7: 0 ] seg [ 23:16 ] port 7 bit: 7 6 5 4 3 2 1 0 p7.7 p7.6 p7.5 p7.4 p7.3 p7.2 p7 .1 p7.0 mnemonic: p7 address: b3h bit name function 7 - 0 p 7 general purpose i/o port. the alternate function of p7[7:0] is seg[31:24]. this port can not support bit address able . alternate function
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 41 - revision a 0. 2 p 7 [7: 0 ] seg [ 31:24 ] timer 3 reload lsb bit: 7 6 5 4 3 2 1 0 rcap 3 l. 7 rcap 3 l. 6 rcap 3 l. 5 rcap 3 l. 4 rcap 3 l. 3 rcap 3 l. 2 rcap 3 l. 1 rcap 3 l. 0 mnemonic: rcap 3 l address: b4 h bit name function 7 - 0 rcap 3 l timer 3 reload lsb: this register is lsb of a 16 bit reload value when timer 3 is configured in reload mode. it se rved also as a compare register when timer 3 is configured as compare mode (see cmp/rl3 bit). timer 3 reload msb bit: 7 6 5 4 3 2 1 0 rcap 3 h. 7 rcap 3 h. 6 rcap 3 h. 5 rcap 3 h. 4 rcap 3 h. 3 rcap 3 h. 2 rcap 3 h. 1 rcap 3 h. 0 mnemonic: rcap 3 h address: b5 h bit name functio n 7 - 0 rcap 3 h timer 3 reload msb: this register is msb of a 16 bit reload value when timer 3 is configured in reload mode. it served also as a compare register when timer 3 is configured as compare mode (see cmp/rl3 bit). extended interrupt high priority 1 bit: 7 6 5 4 3 2 1 0 - - pnvmih pcptfh pt3h pbkfh ppwmf h pspih mnemonic: eip 1 address: b6 h bit name function 7 - 6 - reserved. 5 pnvmih nvm interrupt high priority. pnvmih = 1 sets it to highest priority level. 4 pcptfh capture/reload interrupt high priority. p cptfh = 1 sets it to highest priority level. 3 pt3h timer 3 interrupt high priority. p t3h = 1 sets it to highest priority level. 2 p bkfh pwm brake interrupt high priority. pbkfh = 1 sets it to highest priority level. 1 p pwmfh pwm period inter rupt high priority. ppwmfh = 1 sets it to highest priority level. 0 p spih spi interrupt high priority. p spih = 1 sets it to highest priority level. interrupt high priority bit: 7 6 5 4 3 2 1 0 - padch pt2 h ps hh pt1 h px1 h pt0 h px0 h mnemonic: ip h addres s: b 7 h bit name function
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 42 - revision a 0. 2 7 - reserved. 6 padch this bit defines the adc interrupt high priority. padch = 1 sets it to highest priority level. 5 pt2 h this bit defines the timer 2 interrupt high priority. pt2 h = 1 sets it to highe st priority level. 4 ps h this bit defines the serial port 0 interrupt high priority. ps h = 1 sets it to highe st priority level. 3 pt1 h this bit defines the timer 1 interrupt high priority. pt1 h = 1 sets it to highe st priority level. 2 px1 h this bit defines the external interrup t 1 high priority. px1 h = 1 sets it to highe st priority level. 1 pt0 h this bit defines the timer 0 interrupt high priority. pt0 h = 1 sets it to highe st priority level. 0 px0 h this bit defines the external interrupt 0 high priority. px0 h = 1 sets it to hi ghe st priority level. interrupt priority bit: 7 6 5 4 3 2 1 0 - padc pt2 ps pt1 px1 pt0 px0 mnemonic: ip address: b8h bit name function 7 - reserved. 6 padc this bit defines the adc interrupt priority. padc = 1 sets it to higher priority level. 5 pt 2 this bit defines the timer 2 interrupt priority. pt2 = 1 sets it to higher priority level. 4 ps this bit defines the serial port 0 interrupt priority. ps = 1 sets it to higher priority level. 3 pt1 this bit defines the timer 1 interrupt priority. pt1 = 1 sets it to higher priority level. 2 px1 this bit defines the external interrupt 1 priority. px1 = 1 sets it to higher priority level. 1 pt0 this bit defines the timer 0 interrupt priority. pt0 = 1 sets it to higher priority level. 0 px0 this bit defi nes the external interrupt 0 priority. px0 = 1 sets it to higher priority level. slave address mask enable bit: 7 6 5 4 3 2 1 0 saden .7 saden .6 saden .5 saden .4 saden .3 saden .2 saden .1 saden .0 mnemonic: saden address: b9h bit name function
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 43 - revision a 0. 2 7 - 0 saden this register enables the automatic address recognition feature of the serial port. when a bit in the saden is set to 1, the same bit location in saddr will be compared with the incoming serial port data. when saden.n is 0, then the bit becomes don' t care in the comparison. this register enables the automatic address recognition feature of the serial port. when all the bits of saden are 0, interrupt will occur for any incoming address. slave address mask enable 1 bit: 7 6 5 4 3 2 1 0 saden 1. 7 sad en 1. 6 saden 1. 5 saden 1. 4 saden 1. 3 saden 1. 2 saden 1. 1 saden 1. 0 mnemonic: saden 1 address: b a h bit name function 7 - 0 saden 1 this register enables the automatic address recognition feature of the serial port 1 . when a bit in the saden 1 is set to 1, the same bit location in saddr 1 will be compared with the incoming serial port data. when saden 1 .n is 0, then the bit becomes don't care in the comparison. this register enables the automatic address recognition feature of the serial port. when all the bits of saden 1 are 0, interrupt will occur for any incoming address. pwm output override control registers bit: 7 6 5 4 3 2 1 0 povm. 7 povm. 6 povm. 5 povm. 4 povm. 3 povm. 2 povm. 1 povm.0 mnemonic: p ovm address: bb h bit name function 7 - 0 povm pwm override mode e nable bits ; 0: the pwm output follows the corresponding pwm generator. 1: the pwm output is equal to corresponding bit in povd. pwm output state registers bit: 7 6 5 4 3 2 1 0 povd. 7 povd. 6 povd. 5 povd. 4 povd. 3 povd. 2 povd. 1 povd.0 mnemonic : p ovd addre ss: bc h bit name function 7 - 0 povd pwm override data represents the value of pwm[7:0] respectively in override mode. 1 = output on pwm i/o pin is active when the corresponding pwm output override bit is cleared. 0 = output on pwm i/o pin is inactive when the corresponding pwm output override bit is cleared . pwm pin output source select bit: 7 6 5 4 3 2 1 0 pio 7 pio 6 pio 5 pio 4 pio 3 pio 2 pio 1 pio0 mnemonic : p io address: b d h
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 44 - revision a 0. 2 bit name function 7 - 0 pio.x select pin output source from pwm or i/o register; x =0~7; pion is effective only when option bit pwmoe/pwmee /pwm6e/pwm7e is in enabled status. reset value=0; 1 = correspondent i/o pin with high source/sink current. 0 = pwmn output; n=0~7 with high source/sink current . pwm output enable register bit: 7 6 5 4 3 2 1 0 pwm 7 en pwm 6 en pwm 5 en pwm 4 en pwm 3 en pwm 2 en pwm 1 en pwm0en mnemonic: p wmen address: be h bit name function 6,4,2,0 pwmeen set high to enable even pwm output; e = 0,2,4,6; reset value=0; 1 = enable pwm output . 0 = disable pwm output . 7,5,3,1 pwmo en set high to enable odd pwm output; o = 1,3,5,7; reset value=0; 1 = enable pwm output . 0 = disable pwm output . pwm 4 high bits register bit: 7 6 5 4 3 2 1 0 - - - - pwm 4 . 11 pwm 4 . 10 pwm 4 .9 pwm 4 .8 mnemonic: pwm 4 h address: bfh bit name function 7~ 4 - r eserved 3 ~0 pwm 4 . 11 ~pwm 4 .8 the pwm 4 register bit 11 ~8. serial port control 1 bit: 7 6 5 4 3 2 1 0 sm0 _1 /f e _1 sm1 _1 sm2 _1 ren _1 tb8 _1 rb8 _1 ti _1 ri _1 mnemonic: scon1 address: c0 h bit name function 7 sm0 _1 / fe _1 serial port 1 m ode select bit 0 or fram ing error flag: this bit is controlled by t he smod0 bit in the pcon register. ( sm0 ) see table below. ( fe ) t his bit indicate s an invalid stop bit. it must be manually cleared by software. 6 sm1 _1 serial port 1 mode select bit 1. see table below.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 45 - revision a 0. 2 5 sm2_1 s erial port clock or multi - p rocessor c ommunication. (mode 0) this bit controls the serial port clock. if set to zero , the serial port runs at a divide - by - 12 clock of the oscillator. this is compatib le with the standard 8051/52. if set to one, the serial clo ck is a divide - by - 4 clock of the oscillator. (mode 1) if sm2 _1 is set to one, ri _1 is not activated if a valid stop bit is not received. (modes 2 / 3) this bit enables multi - processor communication. if sm2 _1 is set to one, ri _1 is not activated if rb8 _1 , t he ninth data bit, is zero. 4 ren_1 receive enable: 1 : enable serial reception . 0: disable serial reception . 3 tb8_1 (modes 2 / 3) this is the 9th bit to transmit . this bit is set by software. 2 rb8 _1 (mode 0) no function. (mode 1) if sm2 _1 = 0, rb8 _1 i s the stop bit that was received. (m odes 2 / 3 ) t his is the 9th bit that was received . 1 ti _1 transmit interrupt flag: this flag is set by the hardware at the end of the 8th bit in mode 0 or at the beginning of the stop bit in the other modes during seria l transmission. this bit must be cleared by software. 0 ri _1 receive interrupt flag: this flag is set by the hardware at the end of the 8th bit in mode 0 or halfway through the stop bits in the other modes during serial reception. however , sm2_1 can restr ict this behavior . this bit can only be cleared by software. s m1_1, s m0_1: mode select bits: s m0_1 s m1_1 mode description length baud rate 0 0 0 synchronous 8 tclk divided by 4 or 12 0 1 1 asynchronous 10 variable 1 0 2 asynchronous 11 tclk divided by 32 or 64 1 1 3 asynchronous 11 variable serial data buffer 1 bit: 7 6 5 4 3 2 1 0 sbuf _1 . 7 sbuf _1 . 6 sbuf _1 . 5 sbuf _1 . 4 sbuf _1 . 3 sbuf _1 . 2 sbuf _1 . 1 sbuf _1 . 0 mnemonic: sbuf1 address: c1 h bit name function 7 - 0 sbuf _1 for serial port 1. serial data is read from or written to this location. it actually consists of two separate 8 bit registers. on e is the receive buffer , and the other is the transmit buffer. any read access gets data from the receive data buffer, while write access is to the transmit data buf fer. timer 3 mode control bit: 7 6 5 4 3 2 1 0 enld icen2 icen1 icen0 t3cr - - - mnemonic: t3mod address: c2 h
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 46 - revision a 0. 2 bit name function 7 enld enable reloads from rcap3 registers to timer 3 counters. 6 icen2 capture 2 external enable. this bit enables the ca pture/reload function on the ic2 pin. an edge trigger (programmable by capcon0.cct2[1:0] bits) detected on the ic2 pin will result in capture from free running timer 3 counters to input capture 2 registers, or reload from rcap3 registers to timer 3 counter s. 1 = enable . 0 = disable . 5 ic en1 capture 1 external enable. this bit enables the capture/reload function on the ic 1 pin. an edge trigger (programmable by capcon0.cct1[1:0] bits) detected on the ic 1 pin will result in capture from free running timer 3 c ounters to input capture 1 registers, or reload from rcap 3 registers to timer 3 counters. 1 = enable . 0 = disable . 4 ic en0 capture 0 external enable. this bit enables the capture/reload function on the ic 0 pin. an edge trigger (programmable by capcon0.cct 0[1:0] bits) detected on the ic 0 pin will result in put capture from free running timer 3 counters to input capture 0 registers, or reload from rcap 3 registers to timer 3 counters. 1 = enable . 0 = disable . 3 t 3 cr timer 3 capture reset. in the timer 3 captu re mode this bit enables/disables hardware automatically reset timer 3 while the value in tl 3 and th 3 have been transferred into the input capture register (cclx, cchx). priority is given to t3cr to reset counter after capture . 2 - 0 - reserved. timer 3 co ntrol bit: 7 6 5 4 3 2 1 0 tf3 - - - - tr3 - cmp/rl3 mnemonic: t3con address: c3 h bit name function 7 tf3 timer 3 overflows flag. this bit is set when timer 3 overflows. it is cleared only by software and set by hardware. 6 - 3 - reserve d. 2 tr3 timer 3 run control. this bit enables/disables the operation of timer 3. halting this will preserve the current count in th3, tl3. 1 - reserved. 0 cmp/rl3 compare/reload select. this bit determines whether the timer 3 will be u se for compare or reload function. 0 = timer 3 as reload mode, tf3 indicates the overflow flag 1 = timer 3 as compare mode, tf3 indicates the c ompare match flag. power management register bit: 7 6 5 4 3 2 1 0
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 47 - revision a 0. 2 - - - - - aleoff - dme0 mnemonic: pmr addre ss: c4h bit name function 7 - 3 - reserved. 2 ale o ff this bit disables the expression of the ale signal on the device pin during all on board program and data memory accesses. external memory accesses will automatically enable ale independent of aleoff. al eoff=0: ale expression is enable d. aleoff=1: ale expression is disable d. 1 - reserved. 0 dme0 this bit determines the on chip movx sram to be enabled or disabled. set this bit to 1 will enable the on chip 2 kb movx sram. f ault sampling time register bit : 7 6 5 4 3 2 1 0 scmp1 scmp0 sfp1 sfp0 sfcen sfcst sfcdir lsbd mnemonic: fsplt address: c5h bit name function 7 - 6 scmp [1:0] smart fault comp are value selector (read/write) : 00 = 4 01 = 16 10 = 64 11 = 128 5 - 4 sfp [1:0] smart fault sampling frequency selector (read/write) : 00 = fosc/4 01 = fosc/8 10 = fosc/16 11 = fosc/128 3 sfcen smart fault/brake counter enable (read/write) : 0 = disable, and clear internal smart fault counter . 1 = enable smart fault detector . 2 sfcst smart fault/brake counter stat us (read only) : 0 = counter is non - active . 1 = counter is active . 1 sfcdir smart fault/brake counte rs direction status (read only) : 0 = down counting . 1 = up counting . 0 lsbd low level smart brake detector : 0 = disable low level smart brake detector . 1 = enable low level smart brake detector . it will be cleared by software. adc pin select bit: 7 6 5 4 3 2 1 0 adcps .7 adcps .6 adcps .5 adcps .4 adcps .3 adcps .2 adcps .1 adcps .0
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 48 - revision a 0. 2 mnemonic: adcps address: c 6 h bit name function 7 - 0 adcps adc input pin select . there are 8 adc input pins shared with p1.0~p1.7 . its? functions are controlled by the bit value in adcps. set the bit to switch the corresponding pin to adc input port; clear the bit to disable the pin to perform adc input port. the reset value is 00h. bit corresponding pin bit corresponding pin adcps .0 p1.0 adcps . 4 p1.4 adcps . 1 p1.1 adcps . 5 p1.5 adcps . 2 p1.2 adcps . 6 p1.6 adcps . 3 p1.3 adcps . 7 p1.7 timed access bit: 7 6 5 4 3 2 1 0 ta.7 ta.6 ta.5 ta.4 ta.3 ta.2 ta.1 ta.0 mnemonic: ta address: c7h bit name function 7 - 0 ta the timed access register controls the access to protected bits. to access protected bits, the user must first write aah to ta . this must be immediately followed by a write of 55h to ta. now a window is opened in the protected bi ts for three machine cycles, during which the user can write to these bits. for detail data, please refer "timed access protection" section. timer 2 control bit: 7 6 5 4 3 2 1 0 tf2 exf2 rclk tclk exen2 tr2 2 t c / 2 rl cp / mnemonic: t2con address: c8h bit name function 7 tf2 timer 2 overflows flag . this bit is set when timer 2 overflows. it is also set when the count is equal to the capture register in down count mode. it can be set only if rclk and tclk are both 0. it i s cleared only by software. software can also set this bit. 6 exf2 timer 2 external flag . a negative transition on the t2ex pin (p 4 .1) or timer 2 underflow/overflow will cause this flag to set based on 2 rl cp / , exen2 and dcen bits. if exf2 is set by a negative transition, this flag must be cleared by software. setting this bit in software or detection of a negative transition on t2ex pin will force a timer interrupt if enabled. 5 rclk receive clock flag . this bit determines the serial port time - base when receiving data in serial modes 1 or 3. if it is 0, then timer 1 overflow is used for baud rate generation, else timer 2 overflow is used. setting this bit forces timer 2 in baud rate generator mode. 4 tclk transmit clock flag: this bit det ermines the serial port time - base when transmitting data in mode 1 and 3. if it is set to 0, the timer 1 overflow is used to generate the baud rate clock; else timer 2 overflow is used. setting this bit forces
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 49 - revision a 0. 2 generate the baud rate clock; else timer 2 overflow is used. setting this bit forces timer 2 in baud rate generator mode. 3 exen2 timer 2 external enable . this bit enables the capture/reload function on the t2ex pin if timer 2 is not generating baud clocks for the serial port. if this bit is 0, then the t2ex pin will be ignored, else a negative transition detected on the t2ex pin wi ll result in capture or reload. 2 tr2 timer 2 run control . this bit enables/disables the operation of timer 2. h alting this will preserve the current count in th2, tl2. 1 2 t c / counter/timer select . this bit determines whether timer 2 will function as a timer or a counter. independent of this bit, the timer will run at 2 clocks per tick when used in baud rate generator mode. if it is set to 0, then timer 2 operates as a timer at a speed depending on t2m bit (ckcon.5), else, it will coun t negative edges on t2 pin. 0 2 rl cp / capture/reload select . this bit determines whether the capture or reload function will be used for timer 2. if either rclk or tclk is set, this bit will not function and the timer will function in an a uto - reload mode following each overflow. if the bit is 0 then auto - reload will occur when timer 2 overflows or a falling edge is detected on t2ex if exen2 =1. if this bit is 1, then timer 2 captures will occur when a falling edge is detected on t2ex if exe n2=1. timer 2 mode control bit: 7 6 5 4 3 2 1 0 hc5 hc4 hc3 hc2 t2cr - - dcen mnemonic: t2mod address: c9h bit name function 7 hc5 hardware clears int5 flag. setting this bit allows the flag of external interrupt 5 to be automatically cleared by hard ware while entering the interrupt service routine. 6 hc4 hardware clears int4 flag. setting this bit allows the flag of external interrupt 4 to be automatically cleared by hardware while entering the interrupt service routine. 5 hc3 hardware clears int 3 flag. setting this bit allows the flag of external interrupt 3 to be automatically cleared by hardware while entering the interrupt service routine. 4 hc2 hardware clears int 2 flag. setting this bit allows the flag of external interrupt 2 to be automat ically cleared by hardware while entering the interrupt service routine. 3 t2cr timer 2 capture reset. in the timer 2 capture mode this bit enables/disables hardware automatically reset timer 2 while the value in tl2 and th2 have been transferred into th e capture register. 2 - 1 - reserved. 0 dcen down count enable . this bit, in conjunction with the t2ex pin, controls the up/down direction that timer 2 counts in 16 - bit auto - reload mode. timer 2 capture lsb
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 50 - revision a 0. 2 bit: 7 6 5 4 3 2 1 0 rcap2l. 7 rcap2l. 6 rcap2l. 5 rcap2l. 4 rcap2l. 3 rcap2l. 2 rcap2l. 1 rcap2l. 0 mnemonic: rcap2l address: cah bit name function 7 - 0 rcap2l timer 2 capture lsb: this register is used to capture the tl2 value when a timer 2 is configured in capture mode. rcap2l is also used as the lsb of a 16 bit reload value when timer 2 is configured in auto reload mode. timer 2 capture msb bit: 7 6 5 4 3 2 1 0 rcap2h. 7 rcap2h. 6 rcap2h. 5 rcap2h. 4 rcap2h. 3 rcap2h. 2 rcap2h. 1 rcap2h. 0 mnemonic: rcap2h address: cbh bit name function 7 - 0 rcap2h timer 2 c apture hsb: this register is used to capture the th2 value when a timer 2 is configured in capture mode. rcap2h is also used as the hsb of a 16 bit reload value when timer 2 is configured in auto reload mode. timer 2 lsb bit: 7 6 5 4 3 2 1 0 tl2.7 tl2.6 tl2.5 tl2.4 tl2.3 tl2.2 tl2.1 tl2.0 mnemonic: tl2 address: cch tl2 timer 2 lsb timer 2 msb bit: 7 6 5 4 3 2 1 0 th2.7 th2.6 th2.5 th2.4 th2.3 th2.2 th2.1 th2.0 mnemonic: th2 address: cdh th2 timer 2 msb pwm control register 2 bit: 7 6 5 4 3 2 1 0 bk ch bkps bpen bken fp1 fp0 pmod1 pmod0 mnemonic: p wmcon2 address: ce h bit name function 7 bkch see table below for bk ch set tings . 6 bkps select which brake condition triggers brake flag . lsbd bit is described in sfr fsplt. bkps lsbd description 0 0 0 = brak e is asserted if p 1 . 1 is low. 1 0 1 = brak e is asserted if p 1 . 1 is high x 1 low level smart brake detector.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 51 - revision a 0. 2 5 b pen see table below for b p en set tings . 4 bken 0 = the brak e is never asserted. 1 = the brak e is enabled . 3 - 2 fp[1:0] select pwm frequ ency prescaler select bits. the clock source of prescaler , fpwm is in phase with fosc if pwmrun=1. fp[1:0] fpwm 00 f osc 01 f osc /2 10 f osc /4 11 f osc /16 1 - 0 pmod[1:0] pwm mode selects bits : pmod[1:0] description 00 edge - aligned mode. (up counter) 01 single - shot mode. (up counter) 10 center aligned mode (up - down counter) 11 reserved brake condition t able bpen bkch brake condition 0 0 brake on, (software brake and keeping brake) . software brake condition. when active (bpen=bkch=0, and bken=1), pwm output follows pwmnb setting. this brake has no effect on pwmrun bit; therefore, internal pwm generator continues to run. when the brake is released, the state of pwm output depends on the current state of pwm generator output during the release. 0 1 brake on, when pwm is not running ( pwmrun=0), the pwm output condition is follow pwmnb setting. when the brake is released (by disabling bken = 0), the pwm output resumes to the state when pwm generator stop running prior to enabling the brake. brake off, when pwm is running ( pwmrun=1). 1 0 brake on, when brake pin asserted, pwm output follows pwmnb setting. the pwmrun will be clear. external pin brake condition. when active (by external pin), pwm output follows pwmnb setting. pwmrun will be cleared by ha rdware. bkf flag will be set. when the brake is released (by de - asserting the external pin + disabling bken = 0), the pwm output resumes to the state of the pwm generator output prior to the brake. 1 1 this brake condition (by brake pin) causes bkf to be set, but pwm generator continues to run. the pwm output does not follow pwmnb, instead it output continuously as per normal without affected by the brake. pwm 4 low bits register
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 52 - revision a 0. 2 bit: 7 6 5 4 3 2 1 0 pwm4.7 pwm4.6 pwm4.5 pwm4.4 pwm4.3 pwm4.2 pwm4.1 pwm 4.0 mnemonic: pwm4l address: cfh pwm4 .7 - 0 pwm4 low bits register. program status word bit: 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov f1 p mnemonic: psw address: d0h bit name function 7 cy carry flag . set for an arithmetic operation which results in a carry being generated from the alu. it is also used as the accumulator for the bit operations. 6 ac auxiliary carry: set when the previous operation resulted in a carry (during addition) or a borrow (during subtraction) from the high order nibble. 5 f0 user f lag 0 . a general purpose flag that can be set or cleared by the by software. 4 - 3 rs.1 - 0 register bank selects bits: rs1 rs2 register bank address 0 0 0 00 - 07h 0 1 1 08 - 0fh 1 0 2 10 - 17h 1 1 3 18 - 1fh 2 ov overflow flag . set when a carry was generat ed from the seventh bit but not from the 8th bit as a result of the previous operation or vice - versa. 1 f1 user flag 1 . general purpose flag that can be set or cleared by the user by software . 0 p parity flag . set/cleared by hardware to indicate odd/even number of 1's in the accumulator. pwm p counter high bits register bit: 7 6 5 4 3 2 1 0 - - - - pwmp. 11 pwmp. 10 pwmp.9 pwmp.8 mnemonic: pwmp h address: d1h bit name function 7 - 4 - reserved . 3 - 0 pwmp.11~pwmp.8 the pwm counter register bits 11~8. pwm 0 high bits register bit: 7 6 5 4 3 2 1 0 - - - - pwm0. 11 pwm0. 10 pwm0.9 pwm0.8 mnemonic: pwm0h address: d2h
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 53 - revision a 0. 2 bit name function 7~ 4 - reserved . 3 ~0 pwm0. 11 ~pwm0.8 the pwm 0 register bit 11 ~8. nvm data bit: 7 6 5 4 3 2 1 0 nvmdat.7 nvmdat.6 nvmdat.5 nvmdat.4 nvmdat.3 nvmdat.2 nvmdat.1 nvmdat.0 mnemonic: nvmdat address: d3 h bit name function 7 ~0 nvmdat.7 ~nvmdat. 0 the nvm data write register. the read nvm data is by mov x instruction. qei control register bit: 7 6 5 4 3 2 1 0 - - - disidx dir qeim1 qeim0 qeien mnemonic: qeicon address: d4 h bit name function 7 - 5 - reserved. 4 disidx di sable indx function: 0 = enable indx function (default). 1 = disable indx function. indx input signal is ignored when qei operates counting function. 3 di r dire ction index of motion detection bit : 1 = forward (up - counting) . 0 = backward (down - counting) . this bit is writable. 2 - 1 qeim[1:0] qei mode select bits : qeim1 qeim0 descriptions 0 0 x 4 free - counting mode 0 1 x 2 free - counting mode 1 0 x 4 compare - c ounting mode 1 1 x 2 compare - counting mode 0 qeien input module mode select bit : 0 = input module performs input capture functions. (default value) . 1 = input module works as qei. pwm 2 high bits register bit: 7 6 5 4 3 2 1 0 - - - - pwm 2 . 11 pwm 2 . 10 pwm 2 .9 pwm 2 .8
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 54 - revision a 0. 2 mnemonic: pwm 2 h address: d 5 h bit name function 7~ 4 - reserved 3 ~0 pwm 2 . 11 ~pwm 2 .8 the pwm 2 register bit 11 ~8. pwm 6 high bits register bit: 7 6 5 4 3 2 1 0 - - - - pwm 6 . 11 pwm 6 . 10 pwm 6 .9 pwm6.8 mnemonic: pwm6h address : d6h bit name fu nction 7~ 4 - reserved 3 ~0 pwm6. 11 ~pwm6.8 the pwm 6 register bit 11 ~8. watchdog control 2 bit: 7 6 5 4 3 2 1 0 - - - - - - - strld mnemonic: wdcon2 address: d7h bit name function 7 - 6 - reserved. 0 strld set this bit, cpu will restart from ld flash eprom after watchdog reset. clear this bit, cpu will re start from ap flash eprom after watchdog reset. this register is protected by timer access ( ta ) register. watchdog control bit: 7 6 5 4 3 2 1 0 - por - - wdif wtrf ewt rwt mnemonic: wdcon address: d8h bit name function 7 - reserved. 6 por power - on r eset f lag . hardware will set this flag on a power up condition. this flag can be read or written by software. a write by software is the only way to clear this bit once it is set. 5 - 4 - reserved. 3 w dif watchdog timer interrupt flag . this bit is set by hardware to indicate that the time - out period has elapsed and invoke watch dog timer interrupt if enabled ( ewdi=1). this bit must be clear by software. 2 wtrf watchdog timer reset flag. hardwa re will set this bit when the watchdog timer causes a reset if ewt= 1. software can read it but must clear it manually. a power - on reset will also clear the bit. this bit helps software in determining the cause of a reset
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 55 - revision a 0. 2 1 ewt enable watchdog timer reset. setting this bit will enable the watchdog timer reset function after 512 clock s delay from time out and setting wtrf flag. 0 rwt reset watchdog timer. this bit restarts the watchdog timer and helps in putting the watchdog timer int o a know state. it also helps in resetting the watchdog timer before a time - out occurs. if ewdi (eie.4) is set, an interrupt will occur when time - out. if ewt is set, 512 clocks after the time - out, a system reset will occur and cpu starts from 0000h. this b it is self - clearing. the wdcon sfr is set to a 0x0x0xx0b on an external reset. wtrf is set to a 1 on a watchdog timer reset, but to a 0 on power on resets. wtrf is not altered by an external reset. por is set to 1 by a power - on reset. ewt is cleared to 0 o n a power - on reset and unaffected by other resets. the wdcon sfr is set to x0x x 0 00 0b on an external reset. wtrf is set to a 1 on a watchdog timer reset, but to a 0 on power on resets. por is set to 1 by a power - on reset. ewt is cleared to 0 on a power - o n reset , reset pin reset, watch dog timer reset and isp reset. all the bits in this sfr have unrestricted read access. the bits of por, wdif , ewt and rwt require timed access (ta) procedure to write. the remaining bits have unrestricted write accesses. pl ease refer ta register d e scription. pwm p counter low bits register bit: 7 6 5 4 3 2 1 0 pwmp.7 pwmp.6 pwmp.5 pwmp.4 pwmp.3 pwmp.2 pwmp.1 pwmp.0 mnemonic: pwmp l address: d9h bit name function 7~0 pwmp.7 ~pwmp.0 pwm counter low bits register. pwm0 low bits register bit: 7 6 5 4 3 2 1 0 pwm0.7 pwm0.6 pwm0.5 pwm0.4 pwm0.3 pwm0.2 pwm0.1 pwm0.0 mnemonic: pwm0l a ddress: dah bit name function 7~0 pwm0.7 ~pwm0.0 pwm 0 low bits register. nvm low byte address bit: 7 6 5 4 3 2 1 0 nvmaddr l.7 nvmaddr l.6 nvm addr l.5 nvmaddr l.4 nvmaddr l.3 nvmaddr l.2 nvmaddr l.1 nvmaddr l.0 mnemonic: nvmaddrl address: dbh bit name function 7~0 nvmaddr l .7 ~ nvmaddr l .0 the nvm low byte address .
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 56 - revision a 0. 2 pwm control register 1 bit: 7 6 5 4 3 2 1 0 pwmru n load pwmf clrpw m pwm 6 i pwm 4 i pwm 2 i pwm0i mnemonic : p wmcon1 address: dc h bit name function 7 pwmrun 0 = the pwm is not running. 1 = the pwm counter is running . 6 load this bit is auto cleared by hardware after the pwmp and pwmn are transferred to counter and compare register : 0 = the re gister s value of pwmp and pwmn is never loaded to counter and compar e register s . 1 = the pwmp and pwmn register s load value to counter and compare register s at the counter under flow /match . 5 pwmf 10 bit counter overflow flag: 0 = the 10 - bit counter is no t under flow/match. 1 = the 10 - bit counter is under flow/match. it will be set by hardware and cleared by soft ware . 4 clrpwm 1 = clear 1 2 - bit pwm counter to 000h . it will be automatically clear by hardware. 3 - 0 pwm x i 0 = pwm0 out put is non - inverted. 1 = pw m0 output is inverted. note: x = 0,2,4,6 . pwm 2 low bits register bit: 7 6 5 4 3 2 1 0 pwm2.7 pwm2.6 pwm2.5 pwm2.4 pwm2.3 pwm2.2 pwm2.1 pwm2.0 mnemonic: pwm2l address: ddh bit name function 7~0 pwm2.7 ~pwm2.0 pwm 2 low bits register. pwm 6 low bits register bit: 7 6 5 4 3 2 1 0 pwm6.7 pwm6.6 pwm6.5 pwm6.4 pwm6.3 pwm6.2 pwm6.1 pwm6.0 mnemonic: pwm6l address: deh bit name function 7~0 pwm6.7 ~pwm6.0 pwm 6 low bits register. pwm control register 3 bit: 7 6 5 4 3 2 1 0 pwm 7 b pwm 6 b pwm 5 b pwm4b pwm 3 b pwm 2 b pwm 1 b pwm 0 b mnemonic: p wmcon3 address: df h
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 57 - revision a 0. 2 bit name function 7 - 0 pwm x b 0 = the pwm0 output is low, when brak e is asserted. 1 = the pwm0 output is high, when brak e is asserted. note: x = 0~7 accumulator bit: 7 6 5 4 3 2 1 0 acc.7 acc.6 acc.5 ac c.4 acc.3 acc.2 acc.1 acc.0 mnemonic: acc address: e0h bit name function 7 - 0 acc the a or acc register is the standard 8032 accumulator adc control register bit: 7 6 5 4 3 2 1 0 adcen - ad c ex adci adcs aadr . 2 aadr . 1 aadr . 0 mn emonic: adccon address : e1 h bit name function 7 adcen enable a/d converter function. set adcen to logic high to enable adc block. 6 - reserved. 5 adcex enable external start control of adc conversion by a rising edge from p4.0. adcex=0: disable external start. adcex=1: enab le external start control. 4 adci a/d converting complete/interrupt flag. this flag is set when adc conversion is completed. the adc interrupt is requested if the interrupt is enabled. adci is set by hardware and cleared by software only. 3 adcs a/d con verting start. setting this bit by software starts the conversion of the selected adc input. adcs remains high while adc is converting signal and will be automatically cleared by hardware when adc conversion is completed. a new conversion may not be starte d while either adcs or adci is high. 2 - 0 aadr select and enable analog input channel from adc0 to adc7. aadr[2:0] adc selected input aadr[2:0] adc selected input 000 adcch0 (p1.0) 100 adcch4 (p1.4) 001 adcch1 (p1.1) 101 adcch5 (p1.5) 010 adcch2 (p1.2) 110 adcch6 (p1.6) 011 adcch3 (p1.3) 111 adcch7 (p1.7) the adci and adcs control the adc conversion as below: adci adcs adc status 0 0 adc not busy; a conversion can be started. 0 1 adc busy; start of a new conversion is blocked . 1 0 conversion compl eted; start of a new conversion requires adci = 0 .
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 58 - revision a 0. 2 1 1 this is an internal temporary state that user can ignore it. adc converter result high register bit: 7 6 5 4 3 2 1 0 adc.9 adc.8 adc.7 adc.6 adc.5 adc.4 adc.3 adc.2 mnemonic: adc h address: e 2 h bit name function 7 - 0 adc[9:2] 8 msb of 10 bit a/d conversion result. adch is a read only register. adc converter result low register bit: 7 6 5 4 3 2 1 0 adclk . 1 adclk . 0 - - - - adc. 1 adc. 0 mnemonic: adc l address: e 3 h bit name function 7 - 6 adclk adc c lock frequency select. the 10 bit adc needs a clock to drive the converting that the clock frequency may not over 4mhz. adclk[1:0] controls the frequency of the clock to adc block : adclk . 1 adclk . 0 adc clock frequency 0 0 crystal clock / 4 (default) 0 1 c rystal clock / 8 1 0 crystal clock / 16 1 1 reserved 1 - 0 adc 2 lsb of 1 0 - bit a/d conversion result. both bits are read only. lcd control register bit: 7 6 5 4 3 2 1 0 lcden clear duty pump - fs2 fs1 fs0 m nemonic: lcdc n address: e4h bit name functi on 7 lcden lcd enable bit. this bit is set and cleared by software. when the lcd is disabled, all segment and common pins output low . 0 = lcd disabled . 1 = lcd enabled . 6 clear refresh the lcd panel when is enable d and com pin goes low. 0: inactive . 1: a ctive . 5 duty select duty cycle : 0 = enable 1/4 duty for 32*4 dots . 1 = enable 1/3 duty for 32*3 dots . 4 pump select voltage pump type : 0 = voltage pump type a (default) . 1 = vo ltage pump type b (low power) .
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 59 - revision a 0. 2 3 - reserved. 2 - 0 fs frequency selection bit. these bits allow selection of the lcd frequency. it controls the ratio between the input clock (fosc) and the lcd output clock (flcd). these bits are set and cleared by software. refer to table 20 - 1 : divider selection table using fs bits . fs 2 fs 1 fs0 divider 0 0 0 /1 0 0 1 /2 0 1 0 /4 0 1 1 /8 1 x x /16 pwm dead - time control register 1 bit: 7 6 5 4 3 2 1 0 pdtc1. 7 pdtc1. 6 pdtc1.5 pdtc1.4 pdtc1.3 pdtc1.2 pdtc1.1 pdtc1.0 mnemonic: p dtc1 address: e5 h bi t name function 7 - 6 pdtc1 dead - time clock frequency (f dt ) prescale r select bits . pdtc1.7 pdtc1.6 f dt 0 0 f osc/2 0 1 f osc /4 1 0 f osc /8 1 1 f osc /16 5 - 0 pdtc1 dead time counter. unsigned 6 bit dead time value bits for dead time unit. dead - time = fdt * (pdtc1 [5:0]+1) pwm dead - time control register 0 bit: 7 6 5 4 3 2 1 0 pdtc0.7 pdtc0.6 pdtc0.5 pdtc0.4 pdtc0.3 pdtc0.2 pdtc0.1 pdtc0.0 mnemonic: p dtc0 address: e6 h bit name function 7 - 4 pdtc0 control complementary pwm to delay a dead - time at every ris in g edge or falling edge. reset value = 0. 1 = dead - time is inserted at falling edge. 0 = d ead - time is inserted at rising edge. pdtc0.4 - controls the pair of ( pwm0 , pwm1 ) . pdtc0.5 - controls the pair of ( pwm2 , pwm3 ) . pdtc0.6 - controls the pair of ( pwm4 , pwm5 ) . pdtc0.7 - controls the pair of ( pwm6 , pwm7 ) . 3 - 0 pdtc0 e nable dead - time insertion; dead - time insertion is only active w hen the pair of complementary pwm is enabled. reset value=0 . if dead - time insertion is inactive , the outputs of pin pair are comp lementary without any delay.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 60 - revision a 0. 2 inactive , the outputs of pin pair are comp lementary without any delay. 1 = p rogrammable dead - time is inserted into the pair signals of comparator output to delay the pair signals change from low to high. 0 = d isable dead - time insertion. pdtc 0 .0 - enables the dead - time insertion on the pin pair (pw m0, pwm1). pdtc0.1 - enables the dead - time insertion on the pin pair (pwm2, pwm3). pdtc0.2 - enables the dead - time inserti on on the pin pair (pwm4, pwm5) . pdtc0. 3 - enables the dead - time inserti on on the pin pair (pwm 6 , pwm 7 ) . pwm control register 4 bit: 7 6 5 4 3 2 1 0 pwmeo m pwmoo m pwm6o m pwm7o m - - - bkf mnemonic: p wmcon4 address: e7 h bit name function 7 pwmeom pwm channel 0, 2 and 4 output mode. 0 = disable pwm channel s 0, 2 and 4 to pwm output pins. 1 = enable pwm channel s 0, 2 and 4 to pwm output pins. 6 pwmoom pwm channel 1, 3 and 5 output mode. 0 = disable pwm channels 1, 3 and 5 to pwm output pins. 1 = enable pwm channels 1, 3 and 5 to pwm output pins. 5 pwm6om pwm channel 6 output mode. 0 = disable pwm channel 6 to pwm output pin. 1 = enable pwm channel 6 to pwm output pin. 4 pwm7om pwm channel 7 output mode. 0 = disable pwm channel 7 to pwm output pin. 1 = enable pwm channel 7 to pwm output pin. 3 - 1 - reserved. 0 bkf the external brake pin f lag. 0 = the pwm is not brake. 1 = the pwm is br ake by external brake pin. it will be cleared by software. together with option bits (pwmee and pwmoe), pwmeom, pwmoom, pwm6om and pwm7om control the pwm pin structure, as follow; pwmee/pwmoe (option bits) pwmeom/pwmoom/ pwm6om/pwm7om pin structure x 0 tr istate 0 1 push pull 1 1 quasi [b1] note: pwmeom/pwmoom/pwm6om/pwm7om are cleared to zero when cpu in reset state. thus , the port pins that multi - function with pwm will be tristated on default. user is required to set the bits to 1 to enable gpio/pwm outpu ts.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 61 - revision a 0. 2 extended interrupt enable bit: 7 6 5 4 3 2 1 0 es1 ex5 ex4 ewdi ex3 ex2 - ei2c mnemonic: eie address: e8h bit name function 7 e s1 enable serial port 1 interrupts . 6 ex5 enable external interrupt 5 . 5 ex4 enable external interrupt 4 . 4 ewdi ena ble watchdog timer interrupt . 3 ex3 enable external interrupt 3 . 2 ex2 enable external interrupt 2 . 1 - reserved. 0 ei2c enable i2c interrupt . i2c control register bit: 7 6 5 4 3 2 1 0 - ens sta sto si aa i2cin - mnemonic: i2con address: e 9 h bit na me function 7 - reserved. 6 ens i2c serial function block enable bit . when ens=1 the i2c serial function enables. the port latches of sda and scl must be set to logic high. 5 sta i2c start flag. setting sta to logic 1 to enter master mode, the i2c hardw are sends a start or r epeat start condition to bus when the bus is free. 4 sto i2c stop flag. in master mode, setting sto to transmit a stop condition to bus then i2c hardware will check the bus condition if a stop condition is detected this flag will be cleared by hardware automatically. in a slave mode, setting sto resets i2c hardware to the defined ? not addressed ? slave mode. 3 si i2c interrupt flag. when a new sio state is present in the s1sta register, the si flag is set by hardware, and if the ea a nd ei2c bits are both set, the i2c interrupt is requested. si must be cleared by software. 2 aa assert acknowledge flag. when aa=1 an acknowledge d ( low level to sda) will be returned during the acknowledge clock pulse on the scl line. when aa=0 an acknowl edged (high level to sda) will be returned during the acknowledge clock pulse on the scl line. 1 i2cin by default it is zero and input are allows to come in through sda pin. as when it is 1 input is disallow and to prevent leakage current. during power - do wn mode input is disallow. 0 - reserved. i2c address register
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 62 - revision a 0. 2 bit: 7 6 5 4 3 2 1 0 i2addr. 7 i2addr. 6 i2addr. 5 i2addr. 4 i2addr. 3 i2addr. 2 i2addr. 1 gc mnemonic: i2addr address: ea h bit name function 7 - 1 i2addr i2c slave address. the content s of the reg ister are irrelevant when i2c is in master mode. in the slave mode, the seven most significant bits must be loaded with the mcu?s own slave address. t he i2c hardware will react if the contents of i2addr are matched with the received slave address. 0 gc en able general call function. t he gc bit is set the i2c port hardware will respond to general call address (00h). clear gc bit to disable general call function. nvm high byte address bit: 7 6 5 4 3 2 1 0 - - - - - nvmaddr h.10 nvmaddr h.9 nvmaddr h.8 mnemon ic: nvmaddrh address: eb h bit name function 7 - 3 - reserved. 2 - 0 nvmaddrh.10 ~ nvmaddr h .8 the nvm high byte address i2c data register bit: 7 6 5 4 3 2 1 0 i2d at. 7 i2d at. 6 i2d at. 5 i2d at. 4 i2d at. 3 i2d at. 2 i2d at. 1 i2d at. 0 mnemonic: i2dat address: ec h i2d at.7 - 0 the data register of i2c channel. i2c status register bit: 7 6 5 4 3 2 1 0 b 7 b 6 b 5 b 4 b 3 0 0 0 mnemonic: i2status address: ed h bit name function 7 - 0 i2status the status register of i2c. the three least significant bits are always 0. the five m ost significant bits contain the status code. there are 23 possible status codes. when i2status contains f8h, no serial interrupt is requested. all other i2status values correspond to defined i2c states. when each of these states is entered, the i2c1 inter rupt is requested (si = 1). a valid status code is present in i2status one machine cycle after si is set by hardware and is still present one machine cycle after s i has been reset by software. in addition, states 00h stands for a bus error. a bus error occ urs when a start or stop condition is present at an illegal position in the formation frame. example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 63 - revision a 0. 2 i2c baud rate control register bit: 7 6 5 4 3 2 1 0 i2clk.7 i2clk.6 i2clk.5 i2clk.4 i2clk.3 i2clk.2 i2clk.1 i2clk.0 mnemonic: i2clk address: ee h bit name function 7 - 0 i2clk the i2c clock rate control i2c timer counter register bit: 7 6 5 4 3 2 1 0 - - - - - enti div4 tif mnemonic: i2 timer addres s: ef h bit name function 7 - 3 - reserved. 2 enti enable i2c 14 - bits time - out counter. setting enti to logic high will firstly reset the time - out counter and then start up counting. clearing enti disables the 14 - bit time - out counter. enti can be set to log ic high only when si=0. 1 div4 i2c time - out counter clock frequency selection. 0 = the clock frequency is coherent to the system clock fosc. 1 = the clock frequency is fosc/4. 0 tif i2c time - out flag. when the time - out counter overflows hardware will s et this flag and request the i2c interrupt if i2c interrupt is enabled (ei2c=1). this bit must be cleared by software. b register bit: 7 6 5 4 3 2 1 0 b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 mnemonic: b address: f0h bit name function 7 - 0 b the b register is t he standard 8032 accumulator . serial peripheral control register bit: 7 6 5 4 3 2 1 0 ssoe spe lsbfe mstr cpol cpha spr1 spr0 mnemonic: spcr address: f3 h bit name function 7 ssoe slave select output enable bit. the ss output featu re is enabled only in master mode by asserting the ssoe bit. i n slave mode ( /ss ) input is not a ffected by ssoe bit . see table below. 6 spe serial peripheral system enable bit . when the spe bit is set , spi block function s is enable. when modf is set, spe a lways reads 0.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 64 - revision a 0. 2 0 = spi system disabled . 1 = spi system enabled . 5 l sbfe lsb - first enable . this bit does not affect the position of the msb and lsb in the data register. reads and writes of the data register always have the msb in bit 7. in master mode, a change of this bit will abort a transmission in progress and force the spi system into idle state. 1 = data is transferred least significant bit first. 0 = data is transferred most significant bit first. 4 mstr master mode select bit . i t is customary to have an external pull - up resistor o n lines that are driven by open drain devices. 0 = slave mode . 1 = master mode . 3 cpol clock polarity bit . when the clock polarity bit is cleared and data is not being transferred, the spclk pin of the master device has a steady state low value. when cpol is set, spclk idles high. 2 cpha clock polarity bit . when the clock polarity bit is cleared and data is not being transferred, the spclk pin of the master device has a steady state low value. when cpol is set, spclk i dles high. 1 - 0 spr spi baud rate selection bits . these bits specify the spi baud rates. drss ssoe master mode slave mode 0 0 /ss input ( w ith mode fault ) /ss input ( not affected by ssoe ) 0 1 r eserved /ss input ( not affected by ssoe ) 1 0 /ss gene ral purpose i/o ( no mode fault ) /ss input ( not affected by ssoe ) 1 1 /ss output ( no mode fault ) /ss input ( not affected by ssoe ) note: in master mode, a change of lsbfe, mstr, cpol, cpha and spr [1:0] will abort a transmission in progress and for ce the spi system into idle state. serial peripheral status register bit: 7 6 5 4 3 2 1 0 spif wcol spiovf modf drss - - - mnemonic: spsr address: f4 h bit name function 7 spif spi interrupt complete flag . spif is set upon completion of data transfer be tween this device and external device or when new data has been received and copied to the spdr. if spif goes high, and if espi is set, a serial peripheral interrupt is generated. when spif is set; it must be clear by software and attempts to write spdr ar e inhibited if spif set. 6 wcol write collision flag. if a writer collision occurs on spi bus, wcol is set to high by hardware. wcol must be clear by software. 5 spiovf spi overrun flag . spiovf is set if a new character is received before a previously r eceived character is read from s p dr. once this bit is set it will prevent spdr register form excepting new data and must be clear ed first before any new data can be written. this flag is clear by software .
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 65 - revision a 0. 2 any new data can be written. this flag is clear by software . 0 = no overrun . 1 = overrun detected. 4 modf spi mode error interrupt status flag. modf is set when hardware detects mode fault. this bit is cleared by software. 3 drss data register slave select. refer to above table in spcr register. 2 - 0 - reserved. note: bits wcol, modf and spif are cleared by soft ware writing ? 0 ? to them. serial peripheral data i/o register bit: 7 6 5 4 3 2 1 0 spd.7 spd.6 spd.5 spd.4 spd.3 spd.2 spd.1 spd.0 mnemonic: spdr address: f5h bit name function 7 - 0 spd spdr is used when transmitting or receiving data on serial bu s. only a write to this register initiate s transmission or reception of a byte, and this only occurs in the master device. a read of the spdr is actually a read of a buffer. to prevent an overrun and the loss of the byte that c aused the overrun, the first spif must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated. i2c slave address mask enable bit: 7 6 5 4 3 2 1 0 i2csade n.7 i2csade n.6 i2csade n.5 i2csade n.4 i2csade n.3 i2csade n.2 i2csade n.1 i2csade n .0 mnemonic: i2csaden address: f6h bit name function 7 - 0 i2csaden this register enables the automatic address recognition feature of the i2c. when a bit in the i2csaden is set to 1, the same bit location in i2csaddr 1 will be compared with the incoming se rial port d ata. when i2csaden.n is 0, the bit becomes don't care in the comparison. this register enables the automatic address recognition feature of the i2c. when all the bits of i2csaden are 0, interrupt will occur for any incoming address. the default value is 0xf e . extended interrupt high priority bit: 7 6 5 4 3 2 1 0 ps1 h px5 h px4 h pwdi h px3 h px2 h - pi2c h mnemonic: eip h address: f 7 h bit name function 7 ps1h serial port 1 interrupt high priority. ps1h = 1 sets it to highest priority level. 6 px5h external interrupt 5 high priority . px5h = 1 sets it to highest priority level. 5 px4h external interrupt 4 high priority . px4h = 1 sets it to highest priority level.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 66 - revision a 0. 2 4 pwdi h watchdog timer interrupt high priority. pwdi h = 1 sets it to highest priority level. 3 px3h external interrupt 3 high priority . px3h = 1 sets it to highest priority level. 2 px2h external interrupt 2 high priority . px2h = 1 sets it to highest priority level. 1 - reserved. 0 pi2ch i2c interrupt high priority. pi2ch = 1 sets it to highest priority level. extended interrupt priority bit: 7 6 5 4 3 2 1 0 ps1 px5 px4 pwdi px3 px2 - pi2c mnemonic: eip address: f8h bit name function 7 ps1 serial port 1 interrupt priority. 6 px5 external interrupt 5 priority. 5 px4 external interr upt 4 priority. 4 pwdi watchdog timer interrupt priority . 3 px3 external interrupt 3 priority. 2 px2 external interrupt 2 priority. 1 - reserved. 0 pi2c i2c interrupt priority. extended interrupt enable 1 bit: 7 6 5 4 3 2 1 0 - - envm ecptf et3 ebk epwm espi mnemonic: e ie 1 address: f9 h bit name function 7 - 6 - reserved. 5 envm nvm interrupt enable bit . 0 = disable nvm interrupt . 1 = enable nvm interrupt . 4 ecptf capture interrupt enable bit . 0 = disable external capture/reload interrupt . 1 = enab le ex ternal capture/reload interrupt. 3 et3 timer 3 interrupt enable bit . 0 = disable timer 3 interrupt. 1 = enable timer 3 interrupt. 2 ebk brake interrupt enable bit . 0 = brake interrupt disable . 1 = brake interrupt enable . 1 epwm pwm period interrupt enable bit . 0 = pwm period system interrupts disabled . 1 = pwm period system interrupts enabled .
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 67 - revision a 0. 2 1 = pwm period system interrupts enabled . 0 e sp i serial peripheral interrupt enable bit . set the e sp i bit to 1 to request a hardware interrupt sequence each time the spif /modf status flag is set. 0 = spi system interrupts disabled . 1 = spi system interrupts enabled . extended interrupt priority 1 bit: 7 6 5 4 3 2 1 0 - - pnvmi pcptf pt3 pbkf ppwmf pspi mnemonic: eip 1 address: f a h bit name function 7 - 6 - reserved. 5 pnvmi nvm interrupt priority 4 pcptf capture/reload interrupt priority. 3 pt3 timer 3 interrupt priority. 2 pbkf pwm brake interrupt priority. 1 ppwmf pwm period interrupt priority. 0 pspi spi interrupt priority. input capture 0/pulse read counter l ow r egister bit: 7 6 5 4 3 2 1 0 ccl 0 . 7 / pcntl. 7 ccl 0 . 6 / pcntl. 6 ccl 0 . 5 / pcntl. 5 ccl 0 . 4 / pcntl. 4 ccl 0 . 3 / pcntl. 3 ccl 0 . 2 / pcntl. 2 ccl 0 . 1 / pcntl. 1 ccl0.0/ pcntl.0 mnemonic: ccl0/pcnt l address: fb h pcntl must be read first before reading at pcnth as readi ng pcntl will latch the plscnth automatically into pcnth; otherwise inaccurate result is read when reading pcnth first as it will not latch the plscntl data into pcntl. input capture 0/pulse read counter h igh r egister bit: 7 6 5 4 3 2 1 0 cch 0 . 7 / pcnth. 7 cch 0 . 6 / pcnth. 6 cch 0 . 5 / pcnth. 5 cch 0 . 4 / pcnth. 4 cch 0.3 / pcnth. 3 cch 0 . 2 / pcnth. 2 cch 0 . 1 / pcnth. 1 cch0.0/ pcnth.0 mnemonic: cch0/pcnt h address: fc h pcntl must be read first before reading at pcnth as reading pcntl will latch the plscnth automatically into pcnth. input capture 1/pulse cou nter l ow r egister bit: 7 6 5 4 3 2 1 0 ccl1.7/ plscnt l. 7 ccl1.6/ plscnt l. 6 ccl1.5/ plscnt l. 5 ccl1.4/ plscnt l. 4 ccl1.3/ plscnt l. 3 ccl1.2/ plscnt l. 2 ccl1.1/ plscnt l. 1 ccl1.0/ plscnt l.0 mnemonic: ccl1/plscnt l address: fd h input capture 1/pulse counter h igh r egister
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 68 - revision a 0. 2 bit: 7 6 5 4 3 2 1 0 cch 1 . 7 / plscnt h. 7 cch 1 . 6 / plscnt h. 6 cch 1 . 5 / plscnt h. 5 cch 1 . 4 / plscnt h. 4 cch 1.3 / plscnt h. 3 cch 1 . 2 / plscnt h. 2 cch 1 . 1 / plscnt h. 1 cch1.0/ plscnt h.0 mnemonic: cch1/plscnt h address: fe h interrupt control bit: 7 6 5 4 3 2 1 0 - - int 5 ct1 int 5 ct0 int 4 ct 1 int 4 ct0 int3ct 1 int3ct0 mnemonic: intctrl address: f f h bit name function 7 - 6 - reserved. 5 - 4 int 5 ct interrupt 5 edge select : int5ct 1 int5ct 0 description 0 0 rising edge trigger . 0 1 falling edge trigger . 1 0 rising and fall ing edge trigger . 1 1 reserved. 3 - 2 int 4 ct interrupt 4 edge select : int4ct 1 int4ct 0 description 0 0 rising edge trigger . 0 1 falling edge trigger . 1 0 rising and falling edge trigger . 1 1 reserved. 1 - 0 int3ct interrupt 3 edge select : int3ct 1 int 3ct 0 description 0 0 rising edge trigger . 0 1 falling edge trigger . 1 0 rising and falling edge trigger . 1 1 reserved.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 69 - revision a 0. 2 8 instruction set the w79e217 /217 executes all the instructions of the standard 8051/52 family . the operation s of these instruction s, as well as their effect s on flag and status bits , are exactly the same. however, the timing of these instructions is different in two ways . first ly , the w79e217 /217 machine cycle is four clock periods, while the standard - 8051/52 machine cycle is twelve clock periods. second ly , the w79e217 /217 can fetch only on c e per machine cycle ( i.e. , four clocks per fetch ) , while the standard 8051/52 can fetch twice per machine cycle (i.e. , six clocks per fetch ) . the timing difference s create an advantage for the w79e 217 /217 . t here is only one fetch per machine cycle, so the number of machine cycles is usually equal to the number of operands in the instruction. (j umps and calls do require an additional cycle to calculate the new address. ) as a result, the w79e217 /217 r educes the number of dummy fetches and wasted cycles , and therefore improv es overall efficiency , compared to the standard 8051/52. op - code hex code bytes w79e217 / 217 machine cycle w79e217 / 217 clock cycles 8032 clock cycles w79e217 /217 vs. 8032 speed ratio nop 00 1 1 4 12 3 add a, r0 28 1 1 4 12 3 add a, r1 29 1 1 4 12 3 add a, r2 2a 1 1 4 12 3 add a, r3 2b 1 1 4 12 3 add a, r4 2c 1 1 4 12 3 add a, r5 2d 1 1 4 12 3 add a, r6 2e 1 1 4 12 3 add a, r7 2f 1 1 4 12 3 add a, @r0 26 1 1 4 12 3 add a, @r 1 27 1 1 4 12 3 add a, direct 25 2 2 8 12 1.5 add a, #data 24 2 2 8 12 1.5 addc a, r0 38 1 1 4 12 3 addc a, r1 39 1 1 4 12 3 addc a, r2 3a 1 1 4 12 3 addc a, r3 3b 1 1 4 12 3 addc a, r4 3c 1 1 4 12 3 addc a, r5 3d 1 1 4 12 3 addc a, r6 3e 1 1 4 12 3 addc a, r7 3f 1 1 4 12 3 addc a, @r0 36 1 1 4 12 3 addc a, @r1 37 1 1 4 12 3 addc a, direct 35 2 2 8 12 1.5
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 70 - revision a 0. 2 addc a, #data 34 2 2 8 12 1.5 subb a, r0 98 1 1 4 12 3 subb a, r1 99 1 1 4 12 3 subb a, r2 9a 1 1 4 12 3 subb a, r3 9b 1 1 4 12 3 subb a, r4 9c 1 1 4 12 3 subb a, r5 9d 1 1 4 12 3 subb a, r6 9e 1 1 4 12 3 subb a, r7 9f 1 1 4 12 3 subb a, @r0 96 1 1 4 12 3 subb a, @r1 97 1 1 4 12 3 subb a, direct 95 2 2 8 12 1.5 subb a, #data 94 2 2 8 12 1.5 inc a 04 1 1 4 12 3 inc r0 08 1 1 4 12 3 inc r1 09 1 1 4 12 3 inc r2 0a 1 1 4 12 3 inc r3 0b 1 1 4 12 3 inc r4 0c 1 1 4 12 3 inc r5 0d 1 1 4 12 3 inc r6 0e 1 1 4 12 3 inc r7 0f 1 1 4 12 3 inc @r0 06 1 1 4 12 3 inc @r1 07 1 1 4 12 3 inc direct 05 2 2 8 12 1.5 inc dptr a3 1 2 8 24 3 d ec a 14 1 1 4 12 3 dec r0 18 1 1 4 12 3 dec r1 19 1 1 4 12 3 dec r2 1a 1 1 4 12 3 dec r3 1b 1 1 4 12 3 dec r4 1c 1 1 4 12 3 dec r5 1d 1 1 4 12 3 dec r6 1e 1 1 4 12 3 dec r7 1f 1 1 4 12 3 dec @r0 16 1 1 4 12 3 dec @r1 17 1 1 4 12 3 dec direct 15 2 2 8 12 1.5 mul ab a4 1 5 20 48 2.4
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 71 - revision a 0. 2 div ab 84 1 5 20 48 2.4 da a d4 1 1 4 12 3 anl a, r0 58 1 1 4 12 3 anl a, r1 59 1 1 4 12 3 anl a, r2 5a 1 1 4 12 3 anl a, r3 5b 1 1 4 12 3 anl a, r4 5c 1 1 4 12 3 anl a, r5 5d 1 1 4 12 3 anl a, r6 5e 1 1 4 12 3 anl a, r7 5f 1 1 4 12 3 anl a, @r0 56 1 1 4 12 3 anl a, @r1 57 1 1 4 12 3 anl a, direct 55 2 2 8 12 1.5 anl a, #data 54 2 2 8 12 1.5 anl direct, a 52 2 2 8 12 1.5 anl direct, #data 53 3 3 12 24 2 orl a, r0 48 1 1 4 12 3 orl a, r1 49 1 1 4 12 3 orl a, r2 4a 1 1 4 12 3 orl a, r3 4b 1 1 4 12 3 orl a, r4 4c 1 1 4 12 3 orl a, r5 4d 1 1 4 12 3 orl a, r6 4e 1 1 4 12 3 orl a, r7 4f 1 1 4 12 3 orl a, @r0 46 1 1 4 12 3 orl a, @r1 47 1 1 4 12 3 orl a, direct 45 2 2 8 12 1.5 orl a, #data 44 2 2 8 1 2 1.5 orl direct, a 42 2 2 8 12 1.5 orl direct, #data 43 3 3 12 24 2 xrl a, r0 68 1 1 4 12 3 xrl a, r1 69 1 1 4 12 3 xrl a, r2 6a 1 1 4 12 3 xrl a, r3 6b 1 1 4 12 3 xrl a, r4 6c 1 1 4 12 3 xrl a, r5 6d 1 1 4 12 3 xrl a, r6 6e 1 1 4 12 3 xrl a, r7 6f 1 1 4 12 3
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 72 - revision a 0. 2 xrl a, @r0 66 1 1 4 12 3 xrl a, @r1 67 1 1 4 12 3 xrl a, direct 65 2 2 8 12 1.5 xrl a, #data 64 2 2 8 12 1.5 xrl direct, a 62 2 2 8 12 1.5 xrl direct, #data 63 3 3 12 24 2 clr a e4 1 1 4 12 3 cpl a f4 1 1 4 12 3 rl a 23 1 1 4 12 3 rlc a 33 1 1 4 12 3 rr a 03 1 1 4 12 3 rrc a 13 1 1 4 12 3 swap a c4 1 1 4 12 3 mov a, r0 e8 1 1 4 12 3 mov a, r1 e9 1 1 4 12 3 mov a, r2 ea 1 1 4 12 3 mov a, r3 eb 1 1 4 12 3 mov a, r4 ec 1 1 4 12 3 mov a, r5 ed 1 1 4 12 3 mov a, r6 ee 1 1 4 12 3 mov a, r7 ef 1 1 4 12 3 mov a, @r0 e6 1 1 4 12 3 mov a, @r1 e7 1 1 4 12 3 mov a, direct e5 2 2 8 12 1.5 mov a, #data 74 2 2 8 12 1.5 mov r0, a f8 1 1 4 12 3 mov r1, a f9 1 1 4 12 3 mov r2, a fa 1 1 4 12 3 mov r3, a fb 1 1 4 12 3 mov r4, a fc 1 1 4 12 3 mov r5, a fd 1 1 4 12 3 mov r6, a fe 1 1 4 12 3 mov r7, a ff 1 1 4 12 3 mov r0, direct a8 2 2 8 12 1.5 mov r1, direct a9 2 2 8 12 1.5 mov r2, direct aa 2 2 8 12 1.5 mov r3, direct ab 2 2 8 12 1.5 mov r4, direct ac 2 2 8 12 1.5 mov r5, di rect ad 2 2 8 12 1.5
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 73 - revision a 0. 2 mov r6, direct ae 2 2 8 12 1.5 mov r7, direct af 2 2 8 12 1.5 mov r0, #data 78 2 2 8 12 1.5 mov r1, #data 79 2 2 8 12 1.5 mov r2, #data 7a 2 2 8 12 1.5 mov r3, #data 7b 2 2 8 12 1.5 mov r4, #data 7c 2 2 8 12 1.5 mov r5, #data 7 d 2 2 8 12 1.5 mov r6, #data 7e 2 2 8 12 1.5 mov r7, #data 7f 2 2 8 12 1.5 mov @r0, a f6 1 1 4 12 3 mov @r1, a f7 1 1 4 12 3 mov @r0, direct a6 2 2 8 12 1.5 mov @r1, direct a7 2 2 8 12 1.5 mov @r0, #data 76 2 2 8 12 1.5 mov @r1, #data 77 2 2 8 12 1 .5 mov direct, a f5 2 2 8 12 1.5 mov direct, r0 88 2 2 8 12 1.5 mov direct, r1 89 2 2 8 12 1.5 mov direct, r2 8a 2 2 8 12 1.5 mov direct, r3 8b 2 2 8 12 1.5 mov direct, r4 8c 2 2 8 12 1.5 mov direct, r5 8d 2 2 8 12 1.5 mov direct, r6 8e 2 2 8 12 1. 5 mov direct, r7 8f 2 2 8 12 1.5 mov direct, @r0 86 2 2 8 12 1.5 mov direct, @r1 87 2 2 8 12 1.5 mov direct, direct 85 3 3 12 24 2 mov direct, #data 75 3 3 12 24 2 mov dptr, #data 16 90 3 3 12 24 2 movc a, @a+dptr 93 1 2 8 24 3 movc a, @a+pc 83 1 2 8 24 3 movx a, @r0 e2 1 2 - 9 8 - 36 24 3 - 0.66 movx a, @r1 e3 1 2 - 9 8 - 36 24 3 - 0.66 movx a, @dptr e0 1 2 - 9 8 - 36 24 3 - 0.66 movx @r0, a f2 1 2 - 9 8 - 36 24 3 - 0.66 movx @r1, a f3 1 2 - 9 8 - 36 24 3 - 0.66 movx @dptr, a f0 1 2 - 9 8 - 3 6 24 3 - 0.66
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 74 - revision a 0. 2 push direct c0 2 2 8 24 3 pop direct d0 2 2 8 24 3 xch a, r0 c8 1 1 4 12 3 xch a, r1 c9 1 1 4 12 3 xch a, r2 ca 1 1 4 12 3 xch a, r3 cb 1 1 4 12 3 xch a, r4 cc 1 1 4 12 3 xch a, r5 cd 1 1 4 12 3 xch a, r6 ce 1 1 4 12 3 xch a, r7 cf 1 1 4 12 3 xch a, @r0 c6 1 1 4 12 3 xch a, @r1 c7 1 1 4 12 3 xchd a, @r0 d6 1 1 4 12 3 xchd a, @r1 d7 1 1 4 12 3 xch a, direct c5 2 2 8 12 1.5 clr c c3 1 1 4 12 3 clr bit c2 2 2 8 12 1.5 setb c d3 1 1 4 12 3 setb bit d2 2 2 8 12 1.5 cpl c b3 1 1 4 12 3 cpl bit b2 2 2 8 12 1.5 anl c, bit 82 2 2 8 24 3 anl c, /bit b0 2 2 6 24 3 orl c, bit 72 2 2 8 24 3 orl c, /bit a0 2 2 6 24 3 mov c, bit a2 2 2 8 12 1.5 mov bit, c 92 2 2 8 24 3 acall addr11 71, 91, b1, 11, 31, 51, d1, f1 2 3 12 24 2 lcall addr16 12 3 4 16 24 1.5 ret 22 1 2 8 24 3 reti 32 1 2 8 24 3 ajmp addr11 01, 21, 41, 61, 81, a1, c1, e1 2 3 12 24 2 ljmp addr16 02 3 4 16 24 1.5 jmp @a+dptr 73 1 2 6 24 3 sjmp rel 80 2 3 12 24 2 jz rel 60 2 3 12 24 2
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 75 - revision a 0. 2 jnz rel 70 2 3 12 24 2 jc rel 40 2 3 12 24 2 jnc rel 50 2 3 12 24 2 jb bit, rel 20 3 4 16 24 1.5 jnb bit, rel 30 3 4 16 24 1.5 jbc bit, rel 10 3 4 16 24 1.5 cjne a, direct, rel b5 3 4 16 24 1.5 cjne a, #data, rel b4 3 4 16 24 1.5 cjne @r0, #data, rel b6 3 4 16 24 1.5 cjne @r1, #data, rel b7 3 4 16 24 1.5 cjne r0, #data, rel b8 3 4 16 24 1.5 cjne r1, #data, rel b9 3 4 16 24 1.5 cjne r2, #data, rel ba 3 4 16 24 1.5 cjne r3, #data, rel bb 3 4 16 24 1.5 cjne r4, #data, rel bc 3 4 16 24 1.5 cjne r5, #data, rel bd 3 4 16 24 1.5 cjne r6, #data, rel be 3 4 16 24 1.5 cjne r7, #data, rel bf 3 4 16 24 1.5 djnz r0, rel d8 2 3 12 24 2 djnz r1, rel d9 2 3 12 24 2 djnz r5, rel dd 2 3 12 24 2 djnz r2, rel da 2 3 12 24 2 djnz r3, rel db 2 3 12 24 2 djnz r4, rel dc 2 3 12 24 2 djnz r6, rel de 2 3 12 24 2 djnz r7, rel df 2 3 12 24 2 djnz direct, rel d5 3 4 16 24 1.5 table 8 - 1 : instruction set for w79e217 /217
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 76 - revision a 0. 2 8.1 i nstruction t iming th is section is important because some applications use so ftware instructions to generate timing delays. i t also provides more information about timing differences between the w79e217 /217 and the standard 8051/52. in w79e217 /217 , each machine cycle is four clock periods long. each clock period is called a state , and each machine cycle consists of four states : c1, c2 c3 and c4, in order. b oth clock edges are used for internal timing , so the duty cycle of the clock should be as close to 50% as possible. t he w79e217 /217 does one op - code fetch per machine cycle , so , i n most instructions, the number of machine cycles required is equal to the number of bytes in the instruction. there are 256 available op - codes . 128 of them are single - cycle instructions , so many op - codes are executed in just four clock periods. some of th e other op - codes are two - cycle instructions , and most of these have two - byte op - codes. however , there are some instructions that have one - byte instructions yet take two cycle s to execute . one important example is the movx instruction. in the standard 8051/ 52, the movx instruction is always two machine cycles long. however , in the w79e217 /217 , the duration of this instruction is controlled by the software. it can vary from two to nine machine cycles long, and , rd and wr strobe lines are elongated proportionally . this is called stretching, and it gives a lot of flexibility when accessing fast and slow peripherals . it also reduces the amount of external circuitry and software overhead . the rest of the instructions are th ree - , four - or five - cycle instructions. at the end of this section, there are timing diagrams that provide an example of each type of instruction (single - cycle, two - cycle, ? ). in summary, there are five types of instructions in the w79e217 /217 , based on th e number of machine cycles , and each machine cycle is four clock periods long. the standard 8051/52 has only three types of instructions, based on the number of machine cycles, but each machine cycle is twelve clock periods long . as a result , even though t he number of categories is higher , each instruction in the w79e217 /217 runs 1.5 to 3 times faster , based on the number of clock periods, than it does in the standard 8051/52. single cycle c4 c3 c2 c1 clk ale psen ad7-0 port 2 a7-0 address a15-8 data_ in d7-0 figure 8 - 1 : sin gle cycle instruction timing
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 77 - revision a 0. 2 instruction fetch c4 c3 c2 c1 op-code address a15-8 address a15-8 ale psen pc ad7-0 port 2 clk operand fetch c4 c3 c2 c1 operand pc+1 figure 8 - 2 : two cycle s instruction timing operand operand a7-0 a7-0 a7-0 op-code address a15-8 address a15-8 address a15-8 operand fetch operand fetch instruction fetch c2 c3 c4 c2 c3 c4 c4 c3 c2 c1 c1 c1 clk ale psen ad7-0 port 2 figure 8 - 3 : three cycle s instruction timing
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 78 - revision a 0. 2 operand operand operand op-code address a15-8 address a15-8 address a15-8 address a15-8 a7-0 a7-0 a7-0 a7-0 operand fetch operand fetch operand fetch instruction fetch c2 c1 c4 c3 c2 c1 clk ale psen ad7-0 port 2 c4 c3 c2 c1 c4 c3 c2 c1 c4 c3 figure 8 - 4 : four cycle s instruction timing operand operand operand op-code address a15-8 address a15-8 address a15-8 address a15-8 a7-0 a7-0 a7-0 a7-0 operand fetch operand fetch operand fetch operand fetch instruction fetch c2 c1 c4 c3 c2 c1 clk ale psen ad7-0 port 2 c4 c3 c2 c1 c4 c3 c2 c1 c4 c3 c2 c1 c4 c3 operand a7-0 address a15-8 figure 8 - 5 : five cycle s instruction timing 8.1.1 external data memory access timing the timi ng for the movx instruction is another feature of the w79e217 /217 . in the standard 8051/52, the movx instruction has a fixed execution time of 2 machine cycles. however , in w79e217 /217 , the duration of the access can be controlled by the user. the instruct ion starts off as a normal op - code fetch that takes four clocks. in the next machine cycle, w79e217 /217 puts out the external memory address , and the actual access occurs. the user can control the duration of this access by setting the stretch value in ckc on , bits 2 ? 0. as shown in the table below, t hese three bits can range from zero to seven , resulting in movx instructions that take two to nine machine cycles. the default value is one , resulting in a movx instruction of three machine cycles. s tretching o nly affects the movx instruction . t here is no effect on any other instruction or its timing; it is as if the state of the cpu is held for the desired period. the timing waveforms when the stretch
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 79 - revision a 0. 2 value is zero, one, and two are shown below. m2 m1 m0 machi ne cycles rd or wr strobe width in clocks rd or wr strobe width @ 25 mhz rd or wr strobe width @ 40 mhz 0 0 0 2 2 80 ns 50 ns 0 0 1 3 (default) 4 160 ns 100 ns 0 1 0 4 8 320 ns 200 ns 0 1 1 5 12 480 ns 300 ns 1 0 0 6 16 640 ns 400 ns 1 0 1 7 20 800 ns 500 ns 1 1 0 8 24 960 ns 600 ns 1 1 1 9 28 1120 ns 700 ns table 8 - 2 : data memory cycle stretch values next instruction machine cycle second machine cycle first machine cycle last cycle of previous instruction c4 port 2 port 0 wr psen ale clk c3 c2 d0-d7 a0-a7 d0-d7 a0-a7 d0-d7 a0-a7 d0-d7 a15-a8 a15-a8 a15-a8 a15-a8 a0-a7 c1 c4 c3 c2 c1 c4 c3 c2 c1 c4 c3 c2 c1 movx instruction cycle next inst. read next inst. address movx data out movx data address movx inst. address movx inst . figure 8 - 6 : data memory write with stretch value = 0
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 80 - revision a 0. 2 next instruction machine cycle third machine cycle second machine cycle first machine cycle last cycle of previous instruction c4 port 2 port 0 wr psen ale clk c3 c2 d0-d7 a0-a7 d0-d7 a0-a7 d0-d7 a0-a7 d0-d7 a15-a8 a15-a8 a15-a8 a15-a8 a0-a7 c1 c4 c3 c2 c1 c4 c3 c2 c1 c4 c3 c2 c1 movx instruction cycle next inst. read next inst. address movx data out movx data address movx inst. address movx inst. c4 c3 c2 c1 figure 8 - 7 : data memory write with stretch value = 1 next instruction machine cycle fourth machine cycle third machine cycle second machine cycle first machine cycle last cycle of previous instruction c4 port 2 port 0 wr psen ale clk c3 c2 d0-d7 a0-a7 d0-d7 a0-a7 d0-d7 a0-a7 d0-d7 a15-a8 a15-a8 a15-a8 a15-a8 a0-a7 c1 c4 c3 c2 c1 c4 c3 c2 c1 c4 c3 c2 c1 movx instruction cycle next inst. read next inst. address movx data out movx data address movx inst. address movx inst. c4 c3 c2 c1 c4 c3 c2 c1 figure 8 - 8 : data memory write with stretch value = 2
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 81 - revision a 0. 2 9 p ower m anagement the w79e217 /217 provides idle mode and power - down mode to control power consumption. these modes are discussed in the next two sections. 9.1 idle mode the user can put the device into idle mode by writing 1 to the bit pcon.0. the instruction that sets the idle bit is the last instruction that will be executed before the device goes into idle mode. in the idle mode, the clock to the cpu is halted, but not to the interrupt, timer, watchdog timer , pwm, adc and serial port s blocks. this forces the cpu state to be frozen; the program counter, the stack pointer, the program status word, the accumulator and the other registers hold their contents. the ale and psen pins are held high during the idle state. the port pins hold the logical states they had at the time idle was activated. the idle mode can be terminated in two ways. since the interrupt controller is still active, the activation of an y enabled interrupt can wake up the processor. this will automatically clear the idle bit, terminate the idle mode, and the interrupt service routine ( isr) will be executed. after the isr, execution of the program will continue from the instruction which p ut the device into idle mode. the idle mode can also be exited by activating the reset. the device can be put into reset either by applying a high on the external rst pin, a power on reset condition or a watchdog timer reset. the external reset pin has to be held high for at least two machine cycles i.e. 8 clock periods to be recognized as a valid reset. in the reset condition the program counter is reset to 0000h and all the sfrs are set to the reset condition. since the clock is already running there is n o delay and execution starts immediately. in the idle mode, the watchdog timer continues to run, and if enabled, a time - out will cause a watchdog timer interrupt which will wake up the device. the software must reset the watchdog timer in order to preempt the reset which will occur after 512 clock periods of the time - out. when the device is exiting from an idle mode with a reset, the instruction following the one which put the device into idle mode is not executed. so there is no danger of unexpected writes . 9.2 power down mode the device can be put into power down mode by writing 1 to bit pcon.1. the instruction that does this will be the last instruction to be executed before the device goes into power down mode. in the power down mode, all the clocks are stop ped and the device comes to a halt. all activity is completely stopped and the power consumption is reduced to the lowest possible value. in this state the ale and psen pins are pulled low. the port pins output the values held by their r espective sfrs. the device will exit the power down mode with a reset or by an external interrupt pin enabled as level detect. an external reset can be used to exit the power down state. the high on rst pin terminates the power down mode, and restarts the clock. the program execution will restart from 0000h. in the power down mode, the clock is stopped, so the watchdog timer cannot be used to provide the reset to exit power down mode. the device can be woken from the power down mode by forcing an external i nterrupt pin activated, provided the corresponding interrupt is enabled, while the global enable(ea) bit is set and the external input has been set to a level detect mode. if these conditions are met, then the low level on the external pin re - starts the os cillator. then device executes the interrupt service routine for the corresponding external interrupt. after the interrupt service routine is completed, the program execution returns to the instruction after the one which put the device into power down mod e and continues from there. mode program memory ale psen port0 port1 port2 port3 port4 port5 port6 port7 idle internal 1 1 data data data data data data data data idle external 1 1 float data address data data data data data power dow n internal 0 0 data data data data data data data data
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 82 - revision a 0. 2 dow n power down external 0 0 float data data data data data data data table 9 - 1 : status of external pins during idle and power down
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 83 - revision a 0. 2 10 r eset c onditions the use r has several hardware related options for placing the w79e217 /217 into reset condition. in general, most register bits go to their reset value irrespective of the reset condition, but there are a few flags whose state depends on the source of reset. the u ser can use these flags to determine the cause of res et using software. there are three ways of putting the device into reset sta te. they are external reset, power - on reset and watchdog reset . in general, most register s return to their default value s regar dless of the source of the reset, but a couple flags depend on the source. as a result, t he user can use these flags to determine the cause of the reset. the rest of this section discusses the three causes of reset and then elaborates on the reset state. 10.1 s ources of reset 10.1.1 external reset the device samples the rst pin every machine cycle during state c4. the rst pin must be held high for at least two machine cycles before t he reset circuitry applies an internal reset signal. thus , this reset is a synchronous operation and requires the clock to be running. t he device remains in the reset state as long as rst is one and remains there up to two machine cycles after rst is deactivated . t hen , the device begin s program execution at 0000h. there are no flag s associat ed with the external reset , but, since the other two reset sources do have flags, the external reset is the cause if those flags are clear. 10.1.2 power - on reset (por) if the power supply falls below v rst , the device go es into the reset state. when the power supp ly returns to proper levels, the device perform s a power - on reset and set s the por flag. the software should clear the por flag , or it will be difficult to determine the source of future reset s . 10.1.3 watchdog timer reset the watchdog t imer is a free - running tim er with programmable time - out intervals. the program must clear the watchdog timer before the time - out interval is reached to restart the count. if the time - out interval is reached, an interrupt flag is set. 512 clocks later, i f the watchdog r eset is enabl ed and the watchdog timer has not been cleared, the w atchdog t imer generate s a reset. the reset condition is maintained by the hardware for two machine cycles , and the wtrf bit in wdcon is set. afterwards, the device begin s program execution at 0000h. 10.2 r ese t s tate when the device is reset, m ost registers return to their initial state . the watchdog t imer is disabled if the reset source was a power - on reset . the port registers are set to ffh , which puts most of the port pins in a high state and makes port 0 fl oat ( as it does not have on - chip pull - up resistors) . t he program counter is set to 0000h , and the stack pointer is reset to 07h. after this, the device remains in the reset state as long as the reset condition s are satisfied . r eset does not affect the on - c hip ram , however, so ram is preserved as long as v dd remains above approximately 2 v, the minimum operating voltage for the ram. if v dd falls below 2 v, the ram contents are also lost. in either case, the stack pointer is always reset, so the stack content s are lost. the wdcon sfr bits are set/cleared in reset condition depend s on the source of the reset. the wdcon sfr is set to a 0x0x0xx0b on an external reset. wtrf is set to a 1 on a watchdog timer reset, but to a 0 on power on/down resets. wtrf is not al tered by an external reset. por is set to 1 by a power - on reset. ewt is cleared to 0 on a power - on reset and unaffected by other resets. all the bits in this sfr have unrestricted read access. por, wdif , ewt and rwt bits require timed access (ta) procedure to write. the remaining bits have unrestricted write accesses. please refer ta register d e scription. table below l ists the different reset values for wdcon due to different sources of reset . wdcon watch - dog control d8h (df) - (de) por (dd) - (dc) - (db) w dif (da) wtrf (d9) ewt (d8) rwt x0xx 0000b external reset x0xx 0100b watchdog reset
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 84 - revision a 0. 2 x 1 xx 0000b power on reset
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 85 - revision a 0. 2 11 interrupts the device has a four priority level interrupt structure with 20 interrupt sources. each of the interrupt sources has an individual p riority bit, flag, interrupt vector and enable bit. in addition, all the interrupts can be globally enabled or disabled. 11.1 interrupt sources the external interrupts int0 and int1 can be either edge triggered or level t riggered, depending on bits it0 and it1. the bits ie0 and ie1 in the tcon register are the flags which are checked to generate the interrupt. in the edge triggered mode, the intx inputs are sampled in every machine cycle. if the sample is high in one cycle and low in the next, then a high to low transition is detected and the interrupts request flag iex in tcon is set. the flag bit requests the interrupt. since the external interrupts are sampled every machine cycle, they have to be held high or low for at least one complete machine cycle. the iex flag is automatically cleared when the service routine is called. if the level triggered mode is selected, then the requesting source has to hold the pin low till the interrupt is serviced. the iex flag will not be cleared by the hardware on entering the service routine. if the interrupt continues to be held low even after the service routine is completed, then the processor may acknowledge another interrupt request from the same source. note that the external inter rupts int2 are edge trigger only . by default, the individual interrupt flag corresponding to external interrupt 2 to 5 must be cleared manually by software. it can be configured with hardware cleared by setting the corresponding bit hcx in t2mod register. for instance, if hc2 is set hardware will clear ie2 flag after program enters the interrupt 2 service routine. while for int3 to int5 can detect the rising, falling or both edges which function are selectable by software located in intctrl [5:0] register. the timer 0 and 1 interrupts are generated by the tf0 and tf1 flags. these flags are set by the overflow in the timer 0 and timer 1. the tf0 and tf1 flags are automatically cleared by the hardware when the timer interrupt is serviced. the timer 2 interrupt is generated by a logical or of the tf2 and the exf2 flags. these flags are set by overflow or capture/reload events in the timer 2 operation. the hardware does not clear these flags when a timer 2 interrupt is executed. software has to resolve the cause of the interrupt between tf2 and exf2 and clear the appropriate flag. when adc conversion is completed hardware will set flag adci to logic high to request adc interrupt if bit eadc (ie.6) is in high state. adci is cleared by software only. the i2c functi on can generate interrupt , if ei2c and ea bits are enabled, when si flag is set due to a new i2c status code is generated , si flag is generated by hardware and must be cleared by software. the watchdog timer can be used as a system monitor or a simple time r. in either case, when the time - out count is reached, the watchdog timer interrupt flag wdif (wdcon.3) is set. if the interrupt is enabled by the enable bit eie.4, then an interrupt will occur. all the bits that generate interrupts can be set or reset by hardware, and thereby software initiated interrupts can be generated. each of the individual interrupts can be enabled or disabled by setting or clearing a bit in the ie sfr. ie also has a global enable/disable bit ea, which can be cleared to disable all i nterrupts. 11.2 priority level structure there are four priority levels for the interrupts ; high est, high, low and low est . the other interrupt source can be individually set to either high or low levels. naturally, a higher priority interrupt cannot be interrup ted by a lower priority interrupt. however there exists a predefined hierarchy amongst the interrupts themselves. this hierarchy comes into play when the interrupt controller has to resolve simultaneous requests having the same priority level. this hierarc hy is defined as shown below; the interrupts are numbered starting from the highest priority to the lowest.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 86 - revision a 0. 2 source flag vector address flag cleared by priority level external interrupt 0 ie0 0003h hardware, follow the inverse of pin 1 (highest) timer 0 overflow tf0 000bh hardware, software 2 external interrupt 1 ie1 0013h hardware, follow the inverse of pin 3 timer 1 overflow tf1 001bh hardware, software 4 serial port ri + ti 0023h s oftware 5 timer 2 overflow tf2 + exf2 002bh s oftware 6 a/d conve rter adci 0033h s oftware 7 i2c channel i2c1 si 003bh s oftware 8 serial port 1 ri_1 + ti_1 00 7 bh software 9 spi interrupt spif + modf + spiovf 0083h software 1 0 external interrupt 2 ie2 0043h hardware, software 1 1 external interrupt 3 ie3 004bh har dware, software 1 2 external interrupt 4 ie 4 0053h hardware, software 1 3 external interrupt 5 ie 5 005bh hardware, software 1 4 pwm period pwm f 0073h software 1 5 pwm brake bkf 00 6 bh software 1 6 timer 3 overflow tf3 008bh software 1 7 capture input /direc tion interrupt/qei cptf0 /qeif + cptf1 /drif + cptf 2 0093h software 1 8 nvm interrupt nvmf 009bh software 19 watchdog timer wdif 0063h s oftware 20 table 11 - 1 : priority structure of interrupts the interrupt flags are sampled every machine cycle. in the same machine cycle, the sampled interrupts are polled and their priority is resolved. if certain conditions are met , the hardware will execute an internally generated lcall instruction which will vector the process to the approp riate interrupt vector address. the conditions for generating the lcall are ; 1. an interrupt of equal or higher priority is not currently being serviced. 2. the current polling cycle is the last machine cycle of the instruction currently being executed. 3. the current instruction does not involve a write to ie, e ie, eie1, ip, e ip , eip1 , iph, eiph or eip1h registers and is not a reti. if any of these conditions are not met, then the lcall will not be generated. the polling cycle is repeated every machine cyc le, with the interrupts sampled in the same machine cycle. if an interrupt flag is active in one cycle but not responded to, and is not active when the above conditions are met, the denied interrupt will not be serviced. this means that active interrupts a re not remembered; every
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 87 - revision a 0. 2 polling cycle is new. the processor responds to a valid interrupt by executing an lcall instruction to the appropriate service routine. this may or may not clear the flag which caused the interrupt. in case of timer interrupts, the tf0 or tf1 flags are cleared by hardware whenever the processor vectors to the appropriate timer service routine. in case of external interrupt, int0 and int1, the flags are cleared only if they are edge triggered. in case of serial interrupts, the flags are not cleared by hardware. in the case of timer 2 interrupt, the flags are not cleared by hardware. the watchdog timer interrupt flag wdif has to be cleared by software. the hardware lcall behaves exactly like the software lcall instruction. this instruc tion saves the program counter contents onto the stack, but does not save the program status word psw. the pc is reloaded with the vector address of that interrupt which caused the lcall. these address of vector for the different sources are shown in table 11 - 1 : priority structure of interrupts . priority bits iph/eiph/eip1h ip/eip/eip1 interrupt priority level 0 0 level 0 (lowest priority) 0 1 level 1 1 0 level 2 1 1 level 3 (highest priority) table 11 - 2 : four - level interrupt p riority each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the ip, iph, eip, eiph, eip1 and eip1h registers. an interrupt service routine in progress can be i nterrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. the highest priority interrupt service cannot be interrupted by any other interrupt source. so, if two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. this is called the arbitration ranking. note that the arbitration ranking is only used to resolve simultaneous requests of the same priority level. as below table summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits, arbitration ranking, and whether each interrupt may wake up the cpu from power down mode. source flag vector a ddre ss interrupt enable bits interrupt priority control bits arbitration ranking power down wakeup external interrupt 0 ie0 0003h ex0 (ie.0) iph.0,ip.0 1 (highest) yes timer 0 overflow tf0 000bh et 0 (ie.1) iph.1,ip.1 2 no external interrupt 1 ie1 0013h ex1 (ie.2) iph.2,ip.2 3 yes timer 1 overflow tf1 001bh et1 (ie.3) iph.3,ip.3 4 no serial port ri + ti 0023h es (ie.4) iph.4,ip.4 5 no timer 2 overflow tf2 + exf2 002bh et2 (ie.5) iph.5,ip.5 6 no a/d converter adci 0 033h eadc (ie.6) iph.6,ip.6 7 no i2c channel i2c si 003bh ei2c (eie.0) eiph.0, eip.0 8 no serial port 1 ri_1 + ti_1 007bh es1 (eie.7) eiph.7, eip.7 9 no spi interrupt spif /modf/s piovf 0083h espi (eie1.0) eip 1 h. 0 , eip 1 . 0 1 0 no
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 88 - revision a 0. 2 piovf eip 1 . 0 exte rnal interrupt 2 ie2 0043h ex2 (eie.2) eiph.2, eip.2 1 1 no external interrupt 3 ie3 004bh ex3 (eie.3) eiph.3, eip.3 1 2 no external interrupt 4 ie 4 0053h ex4 (eie.5) eiph.5, eip.5 1 3 no external interrupt 5 ie 5 005bh ex5 (eie.6) eiph.6, eip.6 1 4 no pwm period pwm f 0073h epwm (eie1.1) eip1h. 1 , eip1. 1 1 5 no pwm brake bkf 006bh ebk (eie1.2) eip1h. 2 , eip1. 2 1 6 no timer 3 overflow tf3 008bh et3 (eie1.3) eip1h. 3 , eip1. 3 17 no capture input /direction interrupt/qei cptf0/qeif + cptf1/drif+ cptf2 0093h ecptf (eie1.4) eip1h. 4 , eip1. 4 1 8 no nvm interrupt nvmf 009bh envmi (eie1.5) eip1h.5, eip1.5 19 no watchdog timer wdif 0063h ewdi (eie.4) eiph.4, eip.4 20 no table 11 - 3 : vector location for interrupt sources and power down wakeup 11.2.1 response time the response time for each interrupt source depends on several factors like nature of the interrupt and the instruction under progress. in the case of external interrupt int0 to int5, they are sampled at c3 of every machine cycle and then t heir corresponding interrupt flags ie0 and ie1 will be set or reset. similarly, the serial port flags ri/ri_1 and ti/ti_1 are set in c4 of last machine cycle. the timer 0 and 1 overflow flags are set at c3 of the machine cycle in which overflow has occurre d. these flag values are polled only in the next machine cycle. if a request is active and all three conditions are met, then the hardware generated lcall is executed. this call itself takes four machine cycles to be completed. thus there is a minimum time of five machine cycles between the interrupt flag being set and the interrupt service routine being executed. a longer response time should be anticipated if any of the three conditions are not met. if a higher or equal priority is being serviced, then t he interrupt latency time obviously depends on the nature of the service routine currently being executed. if the polling cycle is not the last machine cycle of the instruction being executed, then an additional delay is introduced. the maximum response ti me (if no other interrupt is in service) occurs if the device is performing a write to ie, ip , iph , eie , eip , eiph, eie1, eip1 or eip1h and then executes a mul or div instruction. from the time an interrupt source is activated, the longest reaction time is 12 machine cycles. this includes 1 machine cycle to detect the interrupt, 2 machine cycles to complete the ie, ip , iph , eie , eip , eiph, eie1, eip1 or eip1h access, 5 machine cycles to complete the mul or div instruction and 4 machine cycles to complete th e hardware lcall to the interrupt vector location. thus in a single - interrupt system the interrupt response time will always be more than 5 machine cycles and not more than 12 machine cycles. the maximum latency of 12 machine cycle is 48 clock cycles. not e that in the standard 8051 the maximum latency is 8 machine cycles which equals 96 machine cycles. this is a 50% reduction in terms of clock periods.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 89 - revision a 0. 2 12 programmable timers/ counters the w79e217 /217 has three 16 - bit programmable timer/counters. 12.1 t imer /c ounte rs 0 & 1 tm0 and tm1 are 16 - bit timer/counters , and there are nearly identical . each of these timer/counters has two 8 bit registers which form the 16 bit s counting register. for timer/counter 0 , it consists of th0, the upper 8 bits register, and tl0, the lower 8 bit register. similarly timer/counter 1 has two 8 bit s registers ; th1 and tl1. the two timers can be configured to operate either as timers, counting machine cycles or as counters counting external inputs. when configured as a "timer", the timer co unts clock cycles. in "counter" mode, the register is incremented on the falling edge of the corresponding external input pin s , t0 for timer 0 and t1 for timer 1. the t0 and t1 inputs are sampled in every machine cycle at c4. if the sampled value is high i n one machine cycle and low in the next, then a valid high to low transition on the pin is recognized and the count register is incremented. since it takes two machine cycles to recognize a negative transition on the pin , therefore the maximum counting rat e is 1/ 8 of the master clock frequency [lp2] . in both "timer" and "counter" mode, the count register is updated at c3. therefore, in the "timer" mode, the recognized negative transition on pin t0 and t1 can cause the count register value to be updated only in t he machine cycle following the one in which the negative edge was detected. the "timer" or "counter" function is selected by the " t c / " bit in the tmod special function register. each timer/counter has one selection bit for its own; bit 2 of tmod selects the function for timer/counter 0 and bit 6 of tmod selects the function for timer/counter 1. in addition each timer/counter can be set to operate in any one of four possible modes. the mode selection is done by bits m0 and m1 in the tmod sfr. 12.1.1 time - base selection the w79e217 /217 can operate like the standard 8051/52 family, counting at the rate of 1/12 of the clock speed , or in turbo mode, counting at the rate of 1/4 clock speed. th e speed is controlled by the t0m and t1m bits in ckcon , and the default value is zero, which uses the standard 8051/52 speed . 12.1.2 m ode 0 in mode 0, the timer/counter is a 13 - bit counter. the 13 - bit counter consists of thx (8 msb) and the five lower bits of tlx (5 lsb) . the upper three bits of tlx are ignored. the time r/counter is enabled when trx is set and either gate is 0 or intx is 1. when t c / is 0, the timer/counter count s clock cycles ; when t c / is 1, it count s falling edges on t0 (p3.4 for t imer 0 ) or t1 ( p3.5 for t imer 1 ) . for clock cycles, the time base may be 1/12 or 1/4 clock speed, and t he falling edge of the clock increments the count er . when the 13 - bit value moves from 1fffh to 0000h , t he timer overflow flag tfx is set , and an interrupt occur s if ena bled . this is illustrated in next figure below. 12.1.3 m ode 1 mode 1 is the same as mode 0 , except that the timer/counter is 16 bits, instead of 13 bits.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 90 - revision a 0. 2 1/4 1/12 fosc t0=p3.4 (t1=p3.5) 0 1 0 1 tr0=tcon.4 (tr1=tcon.6) gate=tmod.3 (gate=tmod.7) int0 =p3.2 ( int1 =p3.3) t0m=ckcon.3 (t1m=ckcon.4) c/ t =tmod.2 (c/ t =tmod.6) 0 7 0 7 tfx interrupt tl0 (tl1) th0 (th1) tf0 (tf1) timer1 functions are shown in parentheses 4 m1, m0=tmod.1, tmod.0 (m1, m0=tmod.5, tmod.4) 00 11 figure 12 - 1 : timer/counter s 0 & 1 in mode 0 and mode 1 12.1.4 m ode 2 in mode 2, the timer/counter is in the auto reload mode. in this mode, tlx acts as an 8 bit s count register, while thx holds the reload value. when the tlx register overflows from ffh to 00h, the tfx bit in tcon is set and tl x is reloaded with the contents of thx, and the counting process continues. the reload operation leaves the contents of the thx register unchanged. counting is enabled by the trx bit and proper setting of gate and intx pins. as in the ot her two modes 0 and 1 , mode 2 allows counting of either clock cycles (clock/12 or clock/4) or pulses on pin tn. 1/4 1/12 fosc t0=p3.4 (t1=p3.5) 0 1 0 1 tr0=tcon.4 (tr1=tcon.6) gate=tmod.3 (gate=tmod.7) int0 =p3.2 ( int1 =p3.3) t0m=ckcon.3 (t1m=ckcon.4) c/ t =tmod.2 (c/ t =tmod.6) 0 7 0 7 tfx interrupt tl0 (tl1) th0 (th1) tf0 (tf1) timer1 functions are shown in parentheses figure 12 - 2 : timer/counter 0 & 1 in mode 2
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 91 - revision a 0. 2 12.1.5 m ode 3 mode 3 is used when an extra 8 - bit timer is needed. it has different effect on t imer 0 and timer 1 . tl0 and th0 become two separate 8 bits count ers . tl0 uses the timer 0 control bits t c / , gate, tr0, int0 and tf0 , and it can be used to count clock cycles (clock/12 or clock/4) or falling edges on pin t0 , as determined by t c / (tmod.2). th0 becomes a clock - cycle counter (clock/12 or clock/4) and takes over the timer 1 enable bit tr1 and overflow flag tf1 . in contrast, mode 3 simply freezes t imer 1. if timer 0 is in mode 3, timer 1 can still be used in m odes 0, 1 and 2, but it no longer has control over tr1 and tf1 . therefore when timer 0 is in mode 3, timer 1 can only count oscillator cycles, and it does not have an in terrupt or flag. with these limitations, baud rate generation is its most practical application, but other time - base functions may be achieved by reading the registers. 1/4 1/12 fosc t0=p3.4 0 1 0 1 tr0=tcon.4 gate=tmod.3 int0 =p3.2 t0m=ckcon.3 c/ t =tmod.2 0 7 0 7 tf0 interrupt tl0 th0 tr1=tcon.6 tf1 interrupt figure 12 - 3 : timer/counter mode 3 12.2 t imer /c ounter 2 timer/counter 2 is a 16 - bit up/down - counter equipped with a capture/reload capability. the clock source for timer/counter 2 may be the external t2 pin ( t2 c / = 1) or the crystal oscillator ( t2 c / = 0), divided by 12 or 4. the clock is enabled and disabled by tr2. timer/counter 2 runs in one of four operating modes, each of which is discussed below.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 92 - revision a 0. 2 12.2.1 c apture m ode c apture mode is enabled by setting rl2 cp / in t2con t o 1. in capture mode, timer/counter 2 is a 16 - bit up - counter. when the counter rolls over from ffffh to 0000h, the timer overflow flag tf2 is set, and an interrupt is generated, if enabled . if the exen2 bit is set, a negative transition on the t2ex pin cap tures the current value of tl2 and th2 in the rcap2l and rcap2h registers . it also sets the exf2 bit in t2con, which generate s an interrupt if enabled . in addition, if the t2cr bit in t2mod is set , the w79e217 /217 reset s t imer 2 automatically after each ca pture . this is illustrated below. (rclk,tclk, rl2 cp / )= (0,0,1) 1 / 4 1 / 12 fosc t 2 = p 1 . 0 0 1 0 1 t 2 ex = p 1 . 1 t 2 m = ckcon . 5 c / t 2 = t 2 con . 1 exf 2 timer 2 interrupt t 2 con . 6 tr 2 = t 2 con . 2 exen 2 = t 2 con . 3 tl 2 th 2 rcap 2 l rcap 2 h tf 2 t 2 con . 7 figure 12 - 4 : timer2 16 - bit capture mode 12.2.2 a uto - reload m ode , c ounting up this mode is enabled by cl earing rl2 cp / in t2con register and dcen in t2mod. in this mode, timer/counter 2 is a 16 - bit up - counter. when the counter rolls over from ffffh to 0000h , the timer overflow flag tf2 is set, and tl2 and th2 capture the contents of rcap2l an d rcap2h , respectively . alternatively, i f exen2 is set, a negative transition on the t2ex pin cause s a reload , which also sets the exf2 bit in t2con.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 93 - revision a 0. 2 (rclk, tclk , rl2 cp / )= (0,0,0) & dcen= 0 1 / 4 1 / 12 fosc t 2 = p 1 . 0 0 1 0 1 t 2 ex = p 1 . 1 t 2 m = ckcon . 5 c / t 2 = t 2 con . 1 exf 2 timer 2 interrupt t 2 con . 6 tr 2 = t 2 con . 2 exen 2 = t 2 con . 3 tl 2 th 2 rcap 2 l rcap 2 h tf 2 t 2 con . 7 figure 12 - 5 : 16 - bit auto - reload mode, counting up 12.2.3 a uto - reload m ode , c ounting up /d own this mode is enabled by clearing cp rl / 2 in t2con and setting dcen in t2mod. in this mode, timer/counter 2 is a 16 - bit up/down - cou nter , whose direction is controlled by the t2ex pin (1 = up, 0 = down) . if timer/counter 2 is counting up, a n overflow reload s tl2 and th2 with the contents of the capture registers rcap2l and rcap2h. if timer/counter 2 is counting down, tl2 and th2 are lo aded with ffffh when the contents of timer/counter 2 equal the capture registers rcap2l and rcap2h. regardless of direction, reload ing set s the tf2 bit. it also toggle s the exf2 bit , but the exf2 bit can not generate an interrupt in this mode. this is illu strated below. (rclk,tclk, rl2 cp / )= (0,0,0) & dcen= 1 1 / 4 1 / 12 fosc t 2 = p 1 . 0 0 1 0 1 t 2 ex = p 1 . 1 t 2 m = ckcon . 5 c / t 2 = t 2 con . 1 exf 2 timer 2 interrupt t 2 con . 6 tr 2 = t 2 con . 2 tl 2 th 2 rcap 2 l rcap 2 h tf 2 t 2 con . 7 0 ffh 0 ffh down counting reload value up counting reload value figure 12 - 6 : 16 - bit auto - reload up/down counter
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 94 - revision a 0. 2 12.2.4 b aud r ate g enerator m ode b aud rate generator mode is ena bled by setting either rclk or tclk in t2con. i n baud rate generator mode, timer/counter 2 is a 16 - bit counter with auto - reload when the count rolls over from ffffh. however, rolling - over does not set tf2. if exen2 is set, then a negative transition on the t2ex pin set s exf2 bit in the t2con register and cause s an interrupt request. rclk+tclk=1, rl2 cp / =0 fosc t 2 = p 1 . 0 0 1 t 2 ex = p 1 . 1 c / t 2 = t 2 con . 1 exf 2 timer 2 interrupt t 2 con . 6 tr 2 = t 2 con . 2 exen 2 = t 2 con . 3 tl 2 th 2 rcap 2 l rcap 2 h 1 / 16 1 / 16 1 1 0 0 rclk = t 2 con . 5 tclk = t 2 con . 4 1 / 2 0 1 timer 1 overflow smod = pcon . 7 rx clock tx clock timer 2 overflow 1 / 2 figure 12 - 7 : baud rate generator mode
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 95 - revision a 0. 2 13 w atchdog t imer the wa tchdog t imer is a free - running timer that can be programmed to serve as a system monitor, a time - base generator or an event timer. it is basically a set of dividers that divide the system clock to determine the time - out interval. when the time - out occurs , a flag is set, which can generate an interrupt or a system reset , if enabled. the interrupt will occur if its interrupt and global interrupt enable s are set. the interrupt and reset functions are independent of each other and may be used separately or toge ther. the main use of the watchdog timer is as a system monitor. in case of power glitches or electromagnetic interference, the processor may begin to execute errant code. t he w atchdog t imer helps w79e217 /217 recover s from these states. d uring development , t he code is first written without the watchdog interrupt or reset. then , the watchdog interrupt is enabled to identify code locations where the interrupt occurs , and instructions are inserted to reset the w atchdog t imer in these locations . in the final ve rsion, the watchdog interrupt is disabled , and the watchdog reset is enabled . if errant code is executed, the watchdog timer is not reset at the required times, so a watchdog timer reset occur s . w hen used as a simple timer, the reset and interrupt function s are disabled . t he watchdog timer can be started by rwt and set s the wdif flag after the selected time interval. meanwhile, t he program poll s the wdif flag to find out when the selected time interval has passed. alternatively, t he watchdog timer can also be used as a very long timer. in this case, t he interrupt feature is enabled. reset fosc 16 time - out wdif ewdi ( eie . 4 ) interrupt 512 clock delay 00 01 10 11 0 19 17 22 20 25 23 reset watchdog rwt ( wdcon . 0 ) enable watchdog timer reset ewt ( wdcon . 1 ) ( wd 1 , wd 0 ) wtrf figure 13 - 1 : watchdog timer the watchdog timer should be started by rwt because t his ensures that t he timer starts from a known state. the rwt bit is self - clearing ; i.e. , after writing a 1 to this bit , the bit is automatically cleared . after setting rwt, t he watchdog timer begins count ing clock cycles. the time - out interval is selected by wd1 and wd0 (c kcon.7 and ckcon.6). wd1 wd0 interrupt time - out reset time - out number of clocks time @ 10 mhz time @ 11.0592 mhz time @ 25 mhz 0 0 2 17 2 17 + 512 131072 13.11 ms 11.85 ms 5.24 ms 0 1 2 20 2 20 + 512 1048576 104.86 ms 94.81 ms 41.94 ms 1 0 2 23 2 23 + 512 8388608 838.86 ms 758.52 ms 335.54 ms 1 1 2 26 2 26 + 512 67108864 6710.89 ms 6068.15 ms 2684.35 ms table 13 - 1 : time - out values for the watchdog timer when the selected time - out occurs, the w atchdog interrupt flag wdif (wdcon.3) is set. after watchdog time - out , and if watchdog timer r eset ewt (wdcon.1) is enabled, the watchdog timer
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 96 - revision a 0. 2 will cause a reset 512 clocks later . this reset last s two machine cycles, and the watchdog timer reset flag wtrf (wdcon.2) is set , which indicates that the watchdog timer cause d the reset. rwt can be used to clear watchdog timer before a time - out occurs. the watchdog t imer is disabled by a power - on/fail reset . the external reset and watchdog timer reset can not disable watchdog time r , instead it only restart the timer. the control bits that support the watchdog t imer are described as below : w atchdog timer c ontrol (wdcon) bit name function 7 - reserved. 6 por power - on reset flag. the h ardware set s this flag during power ? up , and it c an only be cleared by software . this flag can also be written by software. 5 - 4 - reserved. 3 wdif watchdog timer interrupt flag. if the watchdog interrupt is enabled, the hardware set s this bit to indicate that the watchdog interrupt has occurred. if the interrupt is not enabled, this bit indicates that the time - out period has elapsed. this bit must be cleared by software. 2 wtrf watchdog timer reset flag. if ewt is 0, the watchdog timer ha s no affect on this bit. otherwise, the h ardware set s this bit wh en the watchdog timer causes a reset. it can be cleared by s oftware o r a power - fail reset . it can be also read by software, which helps determin e the cause of a reset. 1 ewt enable watchdog - t imer reset. set this bit to enable the watchdog t imer reset fun ction. 0 rwt reset watchdog timer. set t his bit to reset the watchdog timer before a time - out occurs. this bit is automatically cleared by the hardware. the por, ewt, wdif and rwt bits are protected by the timed access procedure. this procedure prevents software , especially errant code, from accidentally enabling or disabling the w atchdog t imer. an example is provided below. org 63h mov ta,#aah mov ta,#55h clr wdif jnb execute_reset_flag,by pass_reset ; test if cpu need to reset. jmp $ ; wait to reset bypass_reset: mov ta,#aah mov ta,#55h setb rwt reti org 300h start: mov ckcon,#01h ; s elect 2 ^ 17 timer ; mov ckcon,#61h ; s elect 2 ^ 20 timer ; mov ckcon ,#81h ; s elect 2 ^ 23 timer
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 97 - revision a 0. 2 ; mov ckcon,#c1h ; s elect 2 ^ 26 timer mov ta,#aah mov ta,#55h mov wdcon,#00000011b setb ewdi setb ea jmp $ ; w ait time out c loc k c ontrol wd1, wd0: ckcon.7, ckcon.6 - watchdog timer mode select bits. these two bits select the time - out interval for the watchdog timer. the reset interval is 512 clock s longer than the selected interval . t he default time - out is 2 17 clocks, the shortest time - out period.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 98 - revision a 0. 2 14 pulse - width - modulated (pwm) outputs 14.1 pwm features the pwm block supports the following features ; ? ? four 12 - bit pwm channels or complementary pairs : ? ? 4 independent pwm output s : pwm0, pwm2, pwm4 & pwm6 . ? ? 4 complementary pwm pairs with insertio n of programmable dead - time: (pwm0,pwm1), (pwm2,pwm3), (pwm4,pwm5), (pwm6,pwm7) ? ? three operation mode: edge aligned mode, center aligned mode and single shot mode . ? ? programmable dead - time insertion between paired p wms. ? ? output override control for electrica lly commutated motor operation . ? ? hardware/software brake protection . ? ? support 2 independent interrupts : ? ? interrupt request when up/down counter comparison matched or underflow . ? ? interrupt request when external brake asserted . ? ? flexible operation in debug mode . ? ? high source/sink current. the output s for pwm0 to pwm7 are on p 2 [ 5:0] ( pwm[5:0]) and p5[1:0] (pwm [7:6]) respectively . after cpu reset , the internal output of each pwm channel depend s on the output controls and polarity setting s . the interval between succ essive outputs is controlled by a 1 2 ? bit up/ down counter which uses the oscillator frequency with configurable internal clock prescaler as its input. t he pwm counter clock, has the frequency as the clock source f pwm = f osc /prescaler . the following figure 14 - 1 : pwm block diagram below is the block diagram for pwm. pwm 0 generator pwm 0 & pwm 1 dead time generator output control pwm i / o pin drive block pwm 6 generator pwm 4 generator pwm 2 generator pwm 2 & pwm 3 dead time generator output control pwm 6 & pwm 7 dead time generator output control pwm 4 & pwm 5 dead time generator output control pwm 0 pwm 1 pwm 2 pwm 3 pwm 4 pwm 5 pwm 6 pwm 7 pwm time base control pwm logic control brake control brake condition figure 14 - 1 : pwm block diagram 14.2 pwm control registers the overall functioning of the pwm mod ule is controlled by the contents of the pwmcon1 register. the operation of most of the control bits is straightforward. for example pwm0i is an invert bit for each output which causes results in the output to have the opposite value compared to its non - in verted
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 99 - revision a 0. 2 output. the transfer of the data from the counter and compare registers to the control registers is controlled by the pwmcon1.6 (load) while pwmcon1.7 (pwmrun) allows the pwm to be either in the run or idle state. if the brake pin is not used to c ontrol the brake function, the ?brake when pwm is not running? function can be used to cause the outputs to have a given state when the pwm is halted. this approach should be used only in time critical situations when there is not sufficient time to use th e approach outlined above , since going from the brake state to run without causing an undefined state on the outputs is not straightforward. a discussion on this topic is included in the section on pwmcon2. the brake function, which is controlled by the co ntents of the pwmcon2 register, is somewhat unique. in general , when brake is asserted , the eight pwm outputs are forced to a user selected state, namely the state selected by pwmcon 3 . as shown in the description of the operation of the pwmcon2 register , i f pwmcon2.4 , bken, is a ?1? brake is asserted under the control pwmcon2.7, bkch, and pwmcon2.5, bpen. as shown , if both are a ?0? , b rake is asserted. if pwmcon2.7 is a ?1? , brake is asserted when the pwmrun bit, pwmcon1.7, is a ?0? . if pwmcon2.6 , bkps, is a ?1? , brake is asserted when the brake pin, p 1.1 , has the same polarity as pwmcon2.6. when brake is asserted in response to this pin , the pwm run bit in pwmcon1.7 is automatically cleared , and bkf (pwmcon 4 .0) flag will be set . when both bkch and bpen are ? 1? , bkf will be set when brake pin is asserted, but pwm generator continues to run. with this special condition, the pwm output does not follow pwmnb, instead it output continuously as per normal without affected by the brake. since the brake pin being ass erted will automatically clear the pwmrun ( pwmcon1.7 ) and bkf (pwmcon 4 .0) flag will be set , the user program can poll this bit or enable pwm ? s brake interrupt to determine when the brake pin causes a brake to occur. the other method for detecting a brake c aused by the brake pin would be to tie the brake pin to one of the external interrupt pins. this latter approach is needed if the brake signal is of insufficient length to ensure that it can be captured by a polling routine. when, after being asserted, the condition causing the brake is removed, the pwm outputs go to whatever state that had immediately prior to the brake. this means that in order to go from brake being asserted to having the pwm run without going through an indeterminate state, care must be taken. if the brake pin causes brake to be asserted, the following prototype code will allow the pwm to go from brake to run smoothly by software polling bkf flag or enable pwm ? s interrupt . ? rewrite pwmcon2 to change from brake pin enabled to s/w brake. ? write pwm (0 , 2, 4, 6 ) compare register to always ?1?, 3ff h, or always ?0? , 0 00h, to initialize pwm output to a low or high . ? clear bkf flag. ? set pwmcon1 to enable pwmrun and load. ? poll brake pin until it is no longer active. when no longer active: ? poll pwmcon1 to find that load bit pwmcon1.6 is ?0?. when ?0?: ? write pwmp (0 , 2, 4, and 6 ) counter register for desired pulse widths and counter reload values. ? set pwmcon1 to run and transfer. note that if a narrow pulse on the brake pin causes bra ke to be asserted, it may not be possible to go through the above code before the end of the pulse. in this case, in addition to the code shown, an external latch on the brake pin may be required to ensure that there is a smooth transition in going from br ake to run. a compare value greater than the counter reloaded value resulted in the pwm output being high. in addition there are two special cases. a compare value of all zeroes, 000h , causes the output to remain permanently low [jk3] . a compare value of all on es, f ffh , results in the pwm output remaining permanently high [jk4] .
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 100 - revision a 0. 2 12-bits up/down counter control block compare register0 pwm0 register pwmrun fosc - + pwm2 register - + pwm4 register - + pwm6 register - + pwm2i pwm4i pwm6i pwm0i - + pwmf x x x x y y y y > > > > load bken brake control block bpen bkch clrpwm clear counter bkps brake pin p1.1 bkfn 0 1 brake flag enable external brake pin (bpen,bkch) = (1,0) pin=0 pin=1 output brake condition compare register2 compare register4 compare register6 (pmod1, pmod0) prescaler (1/1, 1/2, 1/4, 1/16 ) pwmrun fpwm pwmp register pwm mode (fp1, fp0) posc pwm brake interrupt pwm period interrupt q q set clr d s/w clear counter match pwmp/ underflow dead-time insertion & override control pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7 figure 14 - 2 : pwm time - base generator and brake function the pwmp register fact that writes are not into the cou nter register that controls the counter; rather they are into a holding register. as described below the transfer of data from this holding register, into the register which contains the actual reload value, is controlled by the user?s program. the width o f each pwm output pulse is determined by the value in the appropriate compare register. each pwm register pair of (pwmph,pwmpl), (pwm0h,pwm0l), (pwm2h,pwm2l), (pwm4h,pwm4l) and ( pwm6h,pwm6l ),in the format of 12 - bit width by combining 4 lsb of high byte and 8 msb bits of low byte, decides the pwm period and each channel ? s duty cycle.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 101 - revision a 0. 2 0 1 pwmee pion vdd i/o pwme output pwm0, 2, 4 pwmeom pwmee pwme/pion: n,e = 0,2,4 pwmee: pwm channel 0, 2 & 4 enable (option bit) pwmeom: pwm channel 0, 2 & 4 output mode (sfr pwmcon4.7 bit) quasi driver 1=open 0=short figure 14 - 3 : pwm 0, 2 & 4 i/o pin s 0 1 pwmoe pion vdd i/o pwmo output pwm1, 3, 5 pwmoom pwmoe pwmo/pion: o,n = 1,3,5 pwmoe: pwm channel 1, 3 & 5 enable (option bit) pwmoom: pwm channel 1, 3 & 5 output mode (sfr pwmcon4.6 bit) quasi driver 1=open 0=short figure 14 - 4 : pwm 1, 3 & 4 i/o pin s 0 1 pwm6e pio6 vdd i/o pwm6 output pwm6 pwm6om pwm6e pwm6e: pwm channel 6 enable (option bit) pwm6om: pwm channel 6 output mode (sfr pwmcon4.5 bit) quasi driver 1=open 0=short figure 14 - 5 : pwm 6 i/o pin
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 102 - revision a 0. 2 0 1 pwm7e pio7 vdd i/o pwm7 output pwm7 pwm7om pwm7e pwm7e: pwm channel 7 enable (option bit) pwm7om: pwm channel 7 output mode (sfr pwmcon4.4 bit) quasi driver 1=open 0=short figure 14 - 6 : pwm 7 i/o pi n [j5] epol ( option bit ) pwm initial state 0 1 0 1 0 1 low high pwmeb pwmeen pwm output ( pwm 0 , 2 , 4 , 6 ) in brake condition b note : e = 0 , 2 , 4 , 6 figure 14 - 7 : even pwm output pwm output (pwm1,3,5,7) opol (option bit) pwm initial state 0 1 0 1 0 1 low high pwmob pwmoen in brake condition b note: o = 1,3,5,7 figure 14 - 8 : odd pwm output
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 103 - revision a 0. 2 14.3 complementary pwm with dead - time a nd override functions in this module there are four duty - cycle generators, from 0 through 3. the total of eight pwm output pins in this module, from 0 through 7. the eight pwm outputs are grouped into output pairs of even and odd numbered outputs. in compl imentary modes, the odd pwm pins must always be the complement of the corresponding even pwm pin. for example, pwm1 will be the complement of pwm0. pwm3 will be the complement of pwm2, pwm5 will be the complement of pwm4 and pwm7 will be the complement of pwm6. complementary mode is enabled only when both pwmeen and the corresponding pwmoen are set to high. the time base for the pwm module is provided by its own 12 - bit timer, which also incorporates selectable prescaler options. note: pwm pairs of (pwm2 , 3 ), (pwm4 , 5 ) and (pwm6 , 7 ) are in the same structure as pair of (pwm0 , 1 ). ( refer to figure 14 - 9 ). dead time control 0 1 0 1 pdtc 0 . 0 pdtc 0 . 4 rising / falling dt enable pwm 0 b povd . 1 c pwm 1 povm . 1 pdtc 1 [ 7 : 0 ] posc povd . 0 povm . 0 pwm 0 i x y + > - pwm 0 generator figure 14 - 9 : complementary pwm with dead - time and o verride functions 14.4 dead - time insertion the dead time generator inserts an ?off? period called ?dead time? between the turnings off of one pin to the turning on of the complementary pin of the paired pins. this is to prevent damage to the power switching dev ices that will be connected to the pwm output pins. each complementary output pair for the pwm module has 6 - bits counter used to produce the dead time insertion . e ach dead time unit has a rising and falling edge detector connected to the duty cycle compari son output. the dead time is loaded into the timer on the detected pwm edge event. depending on whether the edge is rising or falling, one of the transitions on the complementary outputs is delayed until the timer counts down to zero. a timing diagram indi cating the dead time insertion for one pair of pwm outputs is shown in figure 14 - 10 and figure 14 - 11 .
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 104 - revision a 0. 2 pwm 0 without dead - time pwm 1 without dead - time pwm 0 with dead - time pwm 1 with dead - time dead - time interval note : pdtc 0 . 4 selects insertion at rising edge figure 14 - 10 : effect o f dead - time for complementary pairs (rising edge) pwm 0 without dead - time pwm 1 without dead - time pwm 0 with dead - time pwm 1 with dead - time dead - time interval note : pdtc 0 . 4 selects insertion at falling edge figure 14 - 11 : effect of dead - time for complementary pairs (falling edge) note: user need to take care that power switches shou ld not be use when pwm pair is asserted (high) at the same time. pdtco and pdtc1 have time access protection in writing access. in power inverter application, a dead time insertion avoids the upper and lower switches of the half bridge from being active at the same time. h ence the dead time control is crucial to proper operation of a system. some amount of time must be provided between turning off of one pwm output in a complementary pair and turning on the other transistor as the power output devices can not switch instantaneously.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 105 - revision a 0. 2 14.5 pwm output override start pwm0en = 1? even override (povm.0 = 1?) odd override (povm.1 = 1?) odd override (povm.1 = 1?) (pwm0 = povd.0) if pwm1en = 1 {//override mode pwm1 = povd .1 } else pwm1 = initial state (pwm0 = povd.0) if pwm1en = 1 {//complementary + override mode pwm1 = /pwm0 } else pwm1 = initial state if pwm1en = 1 {//complementary mode pwm0 = normal pwm output pwm1 = /pwm0 } else { independent mode pwm0 = normal pwm output pwm1 = initial state } pwm0 = normal pwm output if pwm1en = 1 pwm1 = povd.1 else pwm1 = initial state odd override (povm.1 = 1?) pwm0 = pwm initial state if pwm1en = 1 pwm1 = /pwm0 else pwm1 = initial state pwm0 = pwm initial state if pwm1en = 1 pwm1 = povd.1 else pwm1 = initial state yes no yes yes no no no yes yes no figure 14 - 12 : override flow diagram each of the pwm output channels can be manually overridden by using the appropriate bits in t he p ovd and povm registers . this function allow user to drive the pwm i/o pins to specified logic states independent of the duty cycle comparison units. the pwm override bits are useful when controlling various types of e lectrically c ommutated m otor (ecm) like a bldc motor . the povd register contains eight bits, povd[7:0] . it determine s which pwm i/o pins will be overridden. on reset , povd is 00h. the povm register contains eight bits, povm[7:0] . it determine s the state of the pwm i/o pins when a particula r output is overridden via the povd bits. on reset , povm is 00h. the pov m[7:0] bits are active - high . when the pov m[7:0] bits are set, the corresponding p ovd[7:0 ] bit will have effect on the pwm output . when one of the pov m bits is set , the output on the co rresponding pwm i/o pin will be determined by the state of corresponding p ovd bit. when a p ovm bit is clear , the pwm pin will be driven to its active state. the odd channel is always the complement of the even channel with dead time inserted, . figure 14 - 13 demonstrates the override function in complementary mode.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 106 - revision a 0. 2 a b c d e f g povd 1 povd 0 pwm 1 pwm 0 figure 14 - 13 : o verride bit in complementary mode assume rising edge dead time insertion ; re fer to figure 14 - 12 : override flow diagram . example: povm0 = 1 and povm1 = 0 ; pwm0en and pwm1en = 1; a. odd override bits have no effect in complementary mode. b. even override bit is activated, which causes the odd pwm to deactivate. c. d ead - time insertion. d. even pwm activated after the dead - time. e. even override bit is deactivated, which causes the even pwm to deactivate . f. dead - time insertion. g. odd pwm is activated after the dead time. 1 2 3 4 6 5 pwm 0 pwm 1 pwm 2 pwm 3 pwm 4 pwm 5 pwm 6 pwm 7 figure 14 - 14 : example 1 of output even & odd override
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 107 - revision a 0. 2 state povm pwmeen = 1 pwmoen = 1 povd 1 1111 1111b 0110 0100b 2 1111 1111b 1010 0001b 3 1111 1111b 0000 1001b 4 1111 1111b 0001 1000b 5 1111 1111b 1001 0010b 6 1111 1111b 0100 0110b table 14 - 1 : example 1 of output even & odd override 1 2 3 4 pwm 0 pwm 1 pwm 2 pwm 3 pwm 4 pwm 5 pwm 6 pwm 7 pwm initial state pwm initial state pwm initial state pwm initial state # 1 : povm 1 2 3 4 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7 #2: povm 1 2 3 4 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7 #3: povm figure 14 - 15 : example 2 of output override state #1: povm (odd not override not in complementary ) (pwmeen = 1, pwmoen = 0) # 2 : povm (odd not override in complementary ) (pwmeen = 1, pwmoen = 1) # 3 : povm (odd with override not in complementary ) (pwmeen = 1, p wmoen = 1) povd 1 0001 0100b 0001 0100b 1011 1110 0000 0000b 2 0000 0101b 0000 0101b 1010 1111 0000 0000b
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 108 - revision a 0. 2 3 0100 0001b 0100 0001b 1110 1011 0000 0000b 4 0101 0000b 0101 0000b 1111 1010 0000 0000b table 14 - 2 : example 2 of output override 14.6 edge aligned pwm (up - counter) pwm 0 ( old ) pwm 0 ( new ) pwmp ( old ) pwmp ( new ) pwm 0 waveform 1 . 12 - bit up counter matches pwmp 2 . update new duty cycle register ( pwm 0 , 2 , 4 and 6 ) if load = 1 3 . update new pwm period register ( pwmp ) if load = 1 new pwm period new duty cycle pwm period new pwm 0 is written new pwmp is written figure 14 - 16 : edge - aligned pwm in edge - aligned pwm output mode, the 12 bits counter will starts counting from 0 to match with the value of the duty cycle pwm0 (old) . w hen th e match occur s , it will toggle the pwm0 output waveform to low. after cpu resets, the value of pwm0 waveform at starts of counter depend on the polarity setting located in the option bits. at th is point a new pwm0 (new) is written. the counter will continue counting to match with the value of the period register, pwmp (old) and toggle the pwm0 waveform to high. please take note that pwm0 and pwmp is a double - buffered register used to set the duty cycle and counting period for t he pwm time base respectively. for the 1 st buffer it is accessible by user while the 2 nd buffer holds the actual compare value used in the present period. load bit must be set to 1 to enable the value to be loaded in to the 2 nd buffer register when counter underflow/match . when the counter matches the pwmp (old) it will automatically update the new duty cycle register and the counter will again starts counting upwards to match the value pwm0 (new). at this point it will toggl e the pwm0 waveform to low. new pwmp is written at this point. when the counter continues counting to match the pwmp (old), again the pwm0 waveform will be toggle to high. the counter starts counting from 0 again; at this point the value is pwm0 (new) and pwmp (new) to be match by the counter and once the counter matches these values it will be toggle at the pwm output.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 109 - revision a 0. 2 set pmod [ 1 : 0 ] = 00 start : load = 1 pwmrun = 1 , clrpwm = 1 load pwmn and pwmp to working registers ?load? auto clear by hardware ( h / w ) pwmni = 1 ? ( output inverted ? ) pwmn output : inverted 0 if counter < pwmn 1 if counter > pwmn pwmn output : non inverted 1 if counter < pwmn 0 if counter > pwmn counter counting up counter = pwmn ? pwmn output toggle counter continues counting up counter = pwmp ? pwmn output toggle reset counter to zero ( h / w ) pwmf flag set load = 1 ? load new pwmp / pwmn value to working register no yes no no no yes figure 14 - 17 : edge - aligned flow diagram
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 110 - revision a 0. 2 start initialize sfr ; pwmp = 7ffh; pwm0 = 3ffh; configure sfr ; pwmcon2 = 1100 0000b; // pwm clock source = fosc // edge-aligned mode // brake not asserted // brake no any activity {set pwmcon2 = 1100 0001b; // single shot mode} {set pwmcon2 = 1100 0010b; // center aligned mode} pwmen = 0000 0001b; // enable pwm0 output ie = 1000 0000b; // enable ea eie1 = 0000 0010; // enable pwm interrupt note: option bit pwmee = enable start pwm pwmcon1 = 1101 0000b; // pwmrun counter starts running // load pwmp & pwmn value to counter // clear counter to 0 // clear pwm flag // pwm output non inverted user monitor output pwm0 output pin using scope. refer figure 12-16 to figure 12-19 and figure 12-22 figure 14 - 18 : program flow for edge - aligned mode pwmp ( 7 ff ) pwm 0 ( 3 ff ) pwm 0 waveform pwm period pwm period pwm period pwm period pwm period figure 14 - 19 : pwm0 edge aligned waveform output
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 111 - revision a 0. 2 14.7 center aligned pw m (up/down counter) pwm 0 ( old ) pwm 0 ( new ) pwmp ( old ) pwmp ( new ) pwm 0 waveform pwm period pwm period new pwm period new pwm 0 is written new pwmp is written new duty cycle 1 . 12 - bit up counter matches pwmp 2 . update new duty cycle register ( pwm 0 , 2 , 4 and 6 ) if load = 1 3 . update new pwm period register ( pwmp ) if load = 1 figure 14 - 20 : center - aligned mode center - aligned pwm signals are produced by the module when the pwm time base is configured in an up/down counting mode (s ee figure 14 - 20 ). the counter will start counting - up from 0 to match the value of pwm0 (old) ; this will cause the toggling of the pwm0 output to low. the cpu reset states determine the starts value of pwm0 waveform at starts of co unter lies on the polarity setting located in the option bits. at this time the new pwm0 is written to the register. counter continue to count and match with the pwmp (old). upon reaching this states counter is configured automatically to down counting an d toggle the pwm0 output when counter matches the pwm0 (old) value. interrupt request when up/down counter underflow . once the counter reaches 0 it will update the duty cycle register with load = 1. up - counting is continues with the matching at pwm0 (new) follow by a low toggle at the pwm0 output. by this time the pwmp buffer is still consist of the pwmp (old) value. a new pwmp is written. so the counter will still matches with this value and continues with down counting and matched the pwm0 (new) and toggl e the pwm0 output. again updates on the pwm period register is reflected on the 3 rd cycle of the diagram by starts counting from 0 to match the pwm0 (new) and toggle at the pwm0 output to low. counter is continuing up - counting, upon reaching the pwmp (new ) it is matched. then counter is down counting automatically to match at the pwm0 (new) to get a toggle high at pwm0 output.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 112 - revision a 0. 2 set pmod [ 1 : 0 ] = 10 start : load = 1 pwmrun = 1 , clrpwm = 1 load pwmn and pwmp to working registers ?load? auto clear by hardware ( h / w ) pwmni = 1 ? ( output inverted ? ) pwmn output : inverted 0 if counter < pwmn 1 if counter > pwmn pwmn output : non inverted 1 if counter < pwmn 0 if counter > pwmn counter counting up counter = pwmn ? pwmn output toggle counter continues counting up counter = pwmp ? counter counting down from pwmp pwmf flag set load = 1 ? load new pwmp / pwmn value to working register no yes no no no yes yes counter = pwmn ? pwmn output toggle counter continues counting down counter = 0 ? no no yes yes figure 14 - 21 : center - aligned flow diagram
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 113 - revision a 0. 2 pwmp ( 7 ff ) pwm 0 ( 3 ff ) pwm 0 waveform pwm period pwm period pwm period figure 14 - 22 : pwm0 center aligned waveform output 14.8 single shot (up - counter) pwm period pwmrun is cleared by hardware pwmp pwm 0 0 figure 14 - 23 : single shot m ode the single shot mode pwm module will produce single pulse output. single - pulse operation is configured when the pmod1:pmod0 bits are set to ?01? in p wm con 3 register. this mode of operation is useful for driving certain types of ecms . in this mode, the pwm counter will start counting upwards when the pwmrun is set to 1. when the counter value matches with the pwmp register, pwm interrupt will be generated if it is enable and pwmf is set and counter will reset to zero on the following input clock edge an d pwmrun will be cleared by hardware. duty cycle of pwm channels are determined by the respective pwmx registers, where x = 0,2,4,6 example steps of setting up single shot: - 1. s et initial state = 0 (controlled by epol option bit) 2. pwm0en=0, povm.0=0, pwm0i= 0, pwm0=0000h(for keep comparator output in low state), pwmp=0001h(let the period as short as possible) 3. pwmrun=1(do a dummy pwmrun for loading pwm 0 to compare register0, which make comparator output low always. 4. pwm0en=1, now the pwm0 pin should be still in 0 state. 5. pwmp=xxxxh(controls a period), pwm0=yyyyh(controls duty or pulse width)
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 114 - revision a 0. 2 6. pwmrun=1(this time a real pwm single shot signal user wanted. the wave form should be the upper one. note: in single shot mode, it?s important that user sets clrpwm together with pwmrun and load in order to have pwmn and pwmp loaded into working registers immediate ly .
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 115 - revision a 0. 2 set pmod[1:0] = 01 start : load = 1 pwmrun = 1, clrpwm = 1 load pwmn and pwmp to working registers ?load? auto clear by hardware (h/w) pwmni = 1? (output inverted?) pwmn output : inverted 0 if counter < pwmn 1 if counter > pwmn pwmn output : non inverted 1 if counter < pwmn 0 if counter > pwmn counter counting up counter = pwmn? pwmn output toggle counter continues counting up counter = pwmp? reset counter to zero (h/w) pwmf flag set pwmrun clear to zero (h/w) no yes no no end initialize set initial state = 0 by epol option bit pwmxen=0, povm.x=0, pwmxi=0, pwmx=0000h, pwmp=0000h set pwmxen=1, pwmp=xxxxh, pwmx=yyyyh figure 14 - 24 : single - shot flow diagram
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 116 - revision a 0. 2 14.9 smart fault detector this is a brake detec tion logic that is new to support external brake conditions that already exist. a dedicated sfr fsplt is added for this function. the sfr consists of smart fault detector control and status bits. it basically consists of a clock divider, 8 bits counter, co mparator and 4 selectable compare value s . the following diagram show the general block diagram. fosc / 4 fosc / 8 fosc / 16 fosc / 128 sfp [ 1 : 0 ] 8 - bit fault counter fcnt clr 4 16 64 128 scmp [ 1 : 0 ] comp brake interrupt flag ( bkf ) sfcst ( read only ) sfcdir ( read only ) lsbd bkfn ( see note ) 0 1 2 3 0 1 2 3 1 0 bkf sfcen bpen bken lsbd bkfs note : bkfn is a another brake flag generated without smart detector enabled . figure 14 - 25 : smart fault detector the smart fault detector is enabled when bi t lsbd = 1 (fsplt.0). this logic detects low level brake pin. the 8 bits counter is enabled by sfcen bit located in sfr fsplt.3. the counter is clock by fosc divider selectable by sfp1 - 0 control bits (fsplt.5 - 4). the comparator compares the 8 bits counter value with the compare value selectable with scmp1 - 0 (fsplt1 - 0). upon initial detection of low level at brake pin, the 8 bits counter will be active. this will cause the counter to increment. while the counter is active and there is high level detected a t brake pin, the counter will decrement. see next figure for timing diagram. when the counter value reaches compare value, bkf will be asserted.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 117 - revision a 0. 2 sfcst=0 (stop counting) bkf fcnt = 0 external brake signal fcnt incr. fcnt incr. fcnt decr. compare value sfcst=1 (start counting) sfcst sfcen set by h/w clr by s/w set by h/w clr by h/w set by s/w clr by s/w figure 14 - 26 : smart fault dete ctor timing diagram the smart fault detector consists of 2 status bits; sfcst and sfcdir. a sfcst sh ow status of 8 bits counter is active or in - active, while sfcdir shows the counter?s counting direction. when sfcst = 0, sfcdir keeps its? state. the s/w ca n manually disable and clear the 8 bits counter, by clearing sfcen to 0. the following tables show the tabulate accumulated low level brake time with various fosc/x dividers and compares value, at 40mhz and 20mhz. fosc/x 1/4 1/8 1/16 1/128 scmp[1:0] 10, 000,000 5,000,000 2,500,000 312,500 4 0.40us 0.80us 1.60us 12.80us 16 1.60us 3.20us 6.40us 51.20us 64 6.40us 12.80us 25.60us 204.80us 128 12.80us 25.60us 51.20us 409.60us table 14 - 3 : example the accumulat ed low level time at 40 mhz fosc/x 1/4 1/8 1/16 1/128 scmp[1:0] 5,000,000 2,500,000 1,250,000 156,250 4 0.80us 1.60us 3.20us 25.60us 16 3.20us 6.40us 12.80us 102.40us 64 12.80us 25.60us 51.20us 409.60us 128 25.60us 51.20us 102.40us 819.20us table 14 - 4 : example the accumulated low level time at 2 0 mhz
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 118 - revision a 0. 2 15 motion feedback module motion feedback module is a peripheral module designed for motion feedback applications. this module includes two sub - modules: ? ? input capture module (ic). ? ? quadrature encoder interface (qei). there are three 16 - bit registers cascaded by two 8 - bit sfr in motion feedback module, but with different definitions in each sub - module . together with timer 3, these modules provide a number of optio ns for motion and control applications. most of the features for the qei and ic sub - modules are fully programmable thus making a flexible peripheral structure that can accommodate a wide range of uses. a simplified block diagram of the entire motion feedba ck module is shown in figure 15 - 2 . note: the input pins are common to the ic and qei sub - modules, only one of these two sub - modules may be used at any given time. ic sub - module is the default value upon reset . 15.1 input capture mod ule (ic) the capture modules are function to detect and measure pulse width and period of a square wave. it supports 3 capture inputs and digital noise rejection filter. the modules are configured by capcon0 and capcon1 sfr registers. input c apture 0, 1 & 2 have their own edge detector but share with one timer i.e. timer 3. the input capture pin s structure are schmitt trigger . for this operation it basically consists of; ? ? 3 capture module function blocks . ? ? timer 3 block . each capture module block consists of 2 bytes of capture registers, noise filter and programmable edge triggers. noise filter is used to filter the unwanted glitch or pulse on the trigger input pin. the noise filter can be enabled through bit enfx (capcon1). if enabled, the capture logic req uired to sample 4 consecutive same capture input value in order to recognize an edge as a capture event. a possible implementation of digital noise filter is as follow; the interval between pulse s requirement for input capture is 1 machine cycle width, whi ch is the same as the pulse width required to guarantee a trigger for all trigger edge mode. for less than 3 system clocks, anything less than 3 clocks will not have any trigger and pulse width of 3 or more but less than 4 clocks will trigger but will not g u ara n tee 100% because input sampling is at stage c3 of the machine cycle . q q set clr d q q set clr d q q set clr d q q set clr d j q q k set clr tx filtered clk tx figure 15 - 1 : noise filter the trigger option is programmable through cctx [1:0] (capcon0). it suppor ts positive edge, negative edge and both edge triggers. each capture module consists of an enable, icen 0 ~ 2 . [note: x=0 , 1, 2 for capture 0 , 1, 2 block]. capture blocks are trigger ed by external pins ic 0, ic 1 and ic 2, respectively. if ic en x is enabled, each
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 119 - revision a 0. 2 time the external pin trigger s , the content of the free running 16 bits counter, tl 3 & th 3 (from timer 3 block) will be captured/transferred into the corresponding capture registers, cclx and cchx . th is action also causes the corresponding cptfx flag bit in capcon1 to be set, and generate an interrupt (if enabled by ecptf bit in sfr, eie1.4 ) . the cptf0 - 2 flags are logical ?or? to the interrupt module. input capture 0~2 share one interrupt named capture interrupt. flag is set by hardware and cleared by soft ware. setting the t 3 cr bit (t 3 mod.3), will allow hardware to reset timer 3 automatically after the value of tl 3 and th 3 have been captured. priority is given to t3cr to reset counter after capture the timer value into the capture register. when rl3 cmp/ = 0 ( reload mode, with t3cr=0 and enld=1 ) , rcap3 will be loaded into timer 3 counter upon overflow. while the rest of the condition of combination of setting for t3cr and enld will reset the counter to 0000h.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 120 - revision a 0. 2 noise filter cptf0 ccl0 cch0 capture 0 block [00] [01] [10] icen0 ic0 cct0[1:0] enf0 [1] capture 1 block capture 2 block ic1 ic2 cptf1 cptf2 with schmitt trigger fosc div by 1,4,16,32 tl3 th3 rcap3l rcap3h 00 01 10 11 tr3 ccdiv[1:0] cptf0 cptf1 cptf2 ccld[1:0] cmp/rl3 enld timer 3 block = 0 1 tf3 cmp/rl3 tmf3 tmf3 cmp/rl3 tovf3 reset timer3 t3cr cptf0 cptf1 cptf2 not e: tovf3 = timer 3 overflow tmf3 = internal timer 3 flag signal. figure 15 - 2 : timer 3 /capture/compare/reload modules
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 121 - revision a 0. 2 xx 00 01 02 100 00 01 02 1 m/c 100h unknown 0000h keeps 0000h ic0 cptf0 tm3 counter capture 0 register rcap3 ex1: falling edge detection, reload mode read capture counter to get period width r e l o a d r e l o a d xx 00 01 02 100 00 01 02 1 m/c 100h unknown 0000h keeps 0000h ic0 cptf0 tm3 counter capture 0 register rcap3 ex2: rising edge detection, reload mode read capture counter to get period width r e l o a d r e l o a d xx 00 01 02 fc 00 01 02 1 m/c fch 0000h keeps 0000h ic0 cptf0 tm3 counter capture 0 register rcap3 ex3: rising and falling edge detection, reload mode read capture counter to get pulse width r e l o a d r e l o a d 01 r e l o a d 00 02 legend: m/c = machine cycle 02h figure 15 - 3 : timing diagram for input capture
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 122 - revision a 0. 2 start initialize sfr/acc; rcap3l = rcap3h = 0; acc = 0; configure sfr ; ckcon1 = 0000 0000b; // timer3 clk = fosc capcon0 = 0000 0101b; // falling edge ic0 and reload by capture 0 block capcon1 = 0000 1000b; // enable digital filter for ic0 t3mod = 1001 0000b; // icen0 = enld = 1 ie = 1000 0000b; // enable ea eie1 = 0001 0000b; // enable ic0 interrupt, ecptf = 1 start timer 3 t3con = 0000 0100b; // tr3 = 1. acc = 2? user read the capture register (should be 100h), and calculate the period base on frequency selected. end no figure 15 - 4 : program flow for measurement with ic0 between pulses with falling edge detection (acc is incremented in interrupt service routine).
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 123 - revision a 0. 2 start initialize sfr/acc; rcap3l = rcap3h = 0; acc = 0; configure sfr ; ckcon1 = 0000 0000b; // timer3 clk = fosc capcon0 = 0000 0001b; // rising edge ic0 and reload by capture 0 block capcon1 = 0000 1000b; // enable digital filter for ic0 t3mod = 1001 0000b; // icen0 = enld = 1 ie = 1000 0000b; // enable ea eie1 = 0001 0000b; // enable ic0 interrupt, ecptf = 1 start timer 3 t3con = 0000 0100b; // tr3 = 1. acc = 2? user read the capture register (should be 100h), and calculate the period base on frequency selected. end no figure 15 - 5 : program flow for measurement with ic0 between pulses with rising edge detection (acc is incremented in interrupt service routine).
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 124 - revision a 0. 2 start initialize sfr/acc; rcap3l = rcap3h = 0; acc = 0; configure sfr ; ckcon1 = 0000 0000b; // timer3 clk = fosc capcon0 = 0000 1001b; // rising and falling edge ic0 and // reload by capture 0 block capcon1 = 0000 1000b; // enable digital filter for ic0 t3mod = 1001 0000b; // icen0 = enld = 1 ie = 1000 0000b; // enable ea eie1 = 0001 0000b; // enable ic0 interrupt, ecptf = 1 start timer 3 t3con = 0000 0100b; // tr3 = 1. acc = 2? user read the capture register (should be 02h), and store the value in the register. end no figure 15 - 6 : program flow for measurement with ic0 pulse width with rising and falling edge detection (acc is incremented in interrupt service routine).
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 125 - revision a 0. 2 reload mode enld = 1 reload/compare value compare mode ffffh 0000h rcap3 tf3 set when overflow (if enld = 0, timer reload from 0) tf3 set when compare match figure 15 - 7 : compare/reload function tl3/th3 value ccl0/cch0 registers icen0 = 1 cptf0 flag set input capture 0 trigger 0000h ffffh timer 3 external input capture 0 figure 15 - 8 : input capture 0 triggers 15.1.1 compare mode timer 3 can be configured for compare mode. the compare mode is e nabled by setting the rl3 cmp/ bit to 1 in the t3con register. rcap3 will serves as a compare register. as timer 3 counting up, upon matching with rcap3 value, tf3 will be set ( which will generate an interrupt request if enable timer 3
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 126 - revision a 0. 2 inter rupt et3 is enabled) and the timer reload from 0 and starts counting again. 15.1.2 reload mode timer 3 can be also be configured for reload mode. the reload mode is enabled by clearing the rl3 cmp/ bit to 0 in the t 3 con register. in this mode, rc ap serves as a reload register. when timer 3 overflows, a reload is generated that causes the contents of the rcap 3 l and rcap 3 h registers to be reloaded into the tl 3 and th 3 registers, if enld is set. tf3 flag is set, and interrupt request is generated if enable timer 3 interrupt et3 is enabled. however, if enld = 0, timer 3 will be reload with 0, and count up again. alternatively, other reload source is also possible by the input capture pins by configuring the ccld [1:0] bit. if the ic en x bit is set, the n a trigger of external ic 0, ic 1 or ic 2 pin (respectively) will also cause a reload. this action also sets the cptf0, cptf1 or cptf2 flag bit in sfr capcon1, respectively. 15.2 quadrature encoder interface (qei) the quadrature encoder interface (qei) decodes s peed of rotation and motion sensor information. it can be used in any application that uses quadrature encoder for feedback. the qei block supports the features as below : ? ? two qei phase inputs: qea and qeb . ? ? one qei index input: indx . ? ? 16 - bit up/down pulse c ounter (plscnt) with 16 - bit read access latched buffer (pcnt) . ? ? four pulse counter update modes : ? ? mode0: x4 free - counting mode . ? ? mode1: x2 free - counting mode . ? ? mode2: x4 compare - counting mode . ? ? mode3: x2 compare - counting mode . ? ? two interrupt sources: ? ? pulse count er interrupt (qeif/cptf2) . ? ? direction index of motion detection with direction interrupt ( dirf ) . ? ? the three 16 - bit sfrs in qei share the same addresses with the capture counter registers. input capture mode qei mode capture0 counter register (cch0, ccl0) p ulse read counter register (pcnth, pcntl) capture1 counter register (cch1, ccl1) pulse counter register (plscnth, plscntl) capture2 counter register (cch2, ccl2) maximum counter register (maxcnth, maxcntl) in qei mode, ic1 and ic0 work as qeb and qea i nputs respectively while ic2 works as indx input . qea and qeb accept the outputs from a quadrature encoded source, such as incremental optical shaft encoder. two channels, a and b, nominally 90 degrees out of phase, are required.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 127 - revision a 0. 2 qei control logic maxcnt / capture 2 register plscnt / capture 1 register pcnt / capture 0 register latch 16 - bit counter read access to low byte of pcnt compare / reload control logic direction clock dir qeif / cptf 2 drif / cptf 1 mode select bits noise filter ic 0 / qea noise filter ic 1 / qeb cha* noise filter ic 2 / indx chb* indx figure 15 - 9 : qei block diagram the qei control logic detects the relation of phase lead/lag between qea and qeb to produce direction index (dir) and clock to control pulse counter. the comparator/reloa d logic compares the pulse counter and maximum count and control the function of reloading pulse counter in c ompare - counting mode. in free - counting mode , the pulse counter will counts until the 65535 value . in compare - counting mode , the pulse counter will counts to maxcnt value. the value of the pulse counter is not affected during qei mode changes, nor when the qei is disabled altogether. when encoder is traveling in the forward direction, the pulse counter will resets on qea or qeb edge once indx rising edge has been detected . qeif will be set , and it is cleared by software. when encoder is traveling in the reverse direction, the value of maxcnt is loaded into pulse counter on qea or qeb edge after the falling edge of indx has been detected . r eset is gene rated in the next qea or qeb edge and qeif will be set and need to be clear by software. interrupt request wil l be generated if ecptf is set. note: disidx bit in qeicon can be used to disable indx function. 15.2.1 free - counting mo d e pulse counter up or down c ounts acc ording to direction index (dir). when overflow or underflow occurs, it sets fl ag qeif. 15.2.2 compare - counting mode pulse counter up or down counts according to direction index (dir). when counter up counts, if plscnt=maxcnt, it sets qeif high and reset plscnt to zero on the next qea edge for x2 counting mode, and on qea/qeb edge for x4 counting mode. when counter down counts to zero the comparator control logic reload plscnt with maxcnt and sets qeif high on the next qea edge for x2 counting mode, and o n qea/qeb edge for x4 counting mode . this mode provides the position of a rotor to user. if a quadrature encoder output 1024 pulses to qea per round, user can
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 128 - revision a 0. 2 write maxcnt with 4095 in x4 mode or 2047 in x2 mode and reset plscnt at initial before rotor run s. when the plscnt reaches maxcnt, it means rotor r uns one round on next qea edge. 15.2.3 x2/x 4 counting modes in x 2 counting mode , the pulse counter increases or decreases one on every qea edge based on the phase relationship of qea and qeb signals, however: - i n x 4 counting mode , the pulse counter increases or decreases one on every qea and qeb edge based on the phase relat ionship of qea and qeb signals. 15.2.4 direction of count if qea lead qeb, the pulse counter is increased by 1. if qea lags qeb, the pulse counter is decreased by 1. the qei control logic generates a signal that sets the dir bit (qeicon .3 ); this in turn determines the direction of the count. when qea leads qeb, dir is set (= 1), and the position counter increments on every active edge. when qea lags qeb, dir is cleared, and the position counter decrements on every active edge . refer to below table . previous signal detected rising falling current signal detected qea qeb qea qeb counting control (dir) ? inc (1) qea rising ? dec (0) ? dec (0) qea falling ? inc (1) ? inc (1) qeb rising ? dec (0) ? inc (1) qeb falling ? dec (0) table 15 - 1 : direction of count
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 129 - revision a 0. 2 cha chb * * dir qeif cleared by software drif up-counting down-counting cleared by software n n 0 1 2 3 4 5 6 7 8 9 10 9 8 7 6 5 4 3 2 1 0 pulse counter reload pulse counter reload mode0/2: x4 counting mode note: mode0: 4x free-counting mode, n=65535 mode2: 4x compare-counting mode, n=max_cnt cha* & chb* are output signals of digital filter pulse counter (plscnt) figure 15 - 10 : x4 counting mode qei x4 counting mode provides for a finer resolution of the rotor position, since the counter increments or decrements more frequently for each qea/qeb input pulse pair than in qei x2 mode. this mode is sel ected by setting the qei mode select bits to ? 00b? or ?10b?. in this mode, the qei logic detects every edge on every qea and qeb input edges.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 130 - revision a 0. 2 cha chb * * dir qeif cleared by software drif up-counting down-counting cleared by software n n 0 0 pulse counter reload pulse counter reload mode1/3: x2 counting mode note: mode1: 2x free-counting mode, n=65535 mode3: 2x compare-counting mode, n=max_cnt cha* & chb* are output signals of digital filter 1 2 3 4 5 4 3 2 1 pulse counter (plscnt) figure 15 - 11 : x2 counting mode qei x2 counting mode is selected by setting the qei mode select bits (qeim 1 :qeim0) to ?01b? or ?1 1b ?. in this mode, the qei logic detects every edge on the qea input only. every rising and falling edge on the qea signal clocks the p ulse counter. 15.2.5 up - counting under the forward direction the dir bit is 1 when up - counting. software needs to clear the qeif flag. for the free - counting mode counter will counts until it matches 65535 and next edges on the forward direction will set the qeif high and reset the plscnt to zero. for compare - counting mode counter counts until the max_cnt value and reload the counter to zero and starts counting up. changes of direction trigger a down - count and plscnt decreasing in counter value. for x2 mode, only cha edge will set qeif whi le for x4 mode both cha and chb edges will set qeif. 15.2.6 down - counting a change of direction will causes the counter to down - count for x2/x4 counting mode. it is indicated with the dir bit as 0 and dirf flag is set to 1. at this stage the plscnt will starts to down - count from the max_cnt value for compare - counting mode and while in free - counting mode it will starts to down - count from 65535. the p ulse counter will reload with maxcnt when it down counts to zero in compare - counting mode and sets qeif to high in the next edge. in free - counting mode the counter will count to 16 bits value before it reload the pulse counter with the value 65535 and set the qeif high in the next edge. for x2 mode, only cha edge will set qeif while for x4 mode both cha and chb edges w ill set qeif.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 131 - revision a 0. 2 qea qeb +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 count(+/-) plscnt max_cnt 1 2 3 4 5 1 7 9 8 1 7 9 9 0 0 0 4 0 0 0 3 0 0 0 2 0 0 0 1 0 0 0 0 1 8 0 5 1 8 0 4 1 8 0 3 1 8 0 2 1 8 0 1 1 8 0 0 1 8 0 3 1 8 0 4 1 8 0 5 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 3 up-counting down-counting clear by software indx dir qeif reverse direction forward direction figure 15 - 12 : qei timing with indx input in free counting mode 1: plscnt register shown at figure 15 - 12 diagram is in qei x 4 counting - m odes (plscnt increments on every rising and every falling edge of qea and qeb input signals) . 2: when indx pulse is detected, plscnt is reset to ?0? on the next qea or qeb edge. plscnt is set to maxcnt when plscnt = 0 (when decrementing), which occurs on the next qea or qeb edge. similar reset sequence occurs for the reverse direction except that the indx signal is recognized on its falling edge. the reset is generated on the next qea or qeb edge. 3: position counter is loaded with ?0000h? (i.e., reset) o n the next qea or qeb edge when indx is high. 4: position counter is loaded with maxcnt value (e.g., 1 805 h) on the next qea or qeb edge following the indx falling edge input signal detect). 5: qeif must be cleared in software.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 132 - revision a 0. 2 16 s erial p ort the w79e217 / 217 has two enhanced serial ports that are functionally similar to the serial port of the original 8052 family . both the s erial port s are full - duplex port s , and t he w79e217 /217 provides additional features , such as frame error detection and automatic addre ss recognition. the serial port s are capable of synchronous and asynchronous communication. in s ynchronous mode , the w79e217 /217 generates the clock and operates in half - duplex mode. in asynchronous mode, the serial port s can simultaneously transmit and re ceive data. the transmit register s and the receive buffer s are both addressed as sbuf ( sbuf1 for the second serial port) , but any write to sbuf /sbuf1 writes to the transmit register while a ny read from sbuf /sbuf1 reads from the receive buffer. both serial port s can operate in four modes , as described below. the description s are for serial port 0, however, it also apply to the second serial port . 16.1 m ode 0 this mode provides half - duplex, synchronous communication with external devices. in this mode , serial data is transmitted and received on the rxd line , and the w79e217 /217 provides the shift clock on txd , whether the device is transmitting or receiving. eight bits are transmitted or received per frame , lsb first. the baud rate is 1/12 or 1/4 of the oscillator frequency , as determined by the sm2 bit (scon.5 ; 0 = 1/12 ; 1 = 1/4 ) . this programmable baud rate is the only difference between the standard 8051/52 and the w79e217 /217 in mode 0. any write to sbuf start s transmission. the shift clock is activated , and dat a is shifted out on rxd until all eight bits are transmitted. if sm2 is 1, the data appear s on rxd one clock period before the falling edge of the shift clock on txd . then, t he clock remains low for two clock periods before go ing high again. if sm2 is 0, t he data appear s on rxd three clock periods before the falling edge of the shift clock on txd , and t he clock on txd remains low for six clock periods before go ing high again. this ensures that , at the receiving end , the data on the rxd line can be clocked o n the rising edge of the shift clock or latched when the clock is low. the ti flag is set high in c1 following the end of transmission. the functional block diagram is shown below. 1 / 12 fosc 0 tx clock rx clock ti ri tx shift tx start rx shift load sbuf shift clock ri ren sm 2 clock sin parout sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus write to sbuf sout transmit shift register serial interrupt rxd txd rxd p 3 . 0 alternate input function p 3 . 0 alternate output function p 3 . 1 alternate output function 1 / 4 1 receive shift register figure 16 - 1 serial port mode 0 the serial port receive s data when ren is 1 and ri is zero. the shift clock (txd) is activated , and the
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 133 - revision a 0. 2 serial port latch es data on the rising edge of the shift clock. the external device should , therefore , present data o n the falling edge of the shift clock. this process continues until all eight bits have been received. the ri flag is set in c1 following the last rising edge of the shift clock , which stop s reception until ri is cleared by the software. 16.2 m ode 1 in mode 1, full - duplex asynchronous communication is used. f rames consist of ten bits transmitted on txd and received on rxd. the ten bits consist of a start bit (0), eight data bits (lsb first), and a stop bit (1). when receiv ing , the stop bit goes into rb8 in scon. the baud rate in this mode is 1/16 or 1/32 of the timer 1 overflow , and s ince timer 1 can be set to a wide range of values, a wide variation of baud rates is possible. transmission begins with a write to sbuf but is synchronized with the divide - by - 16 coun ter, not the write to sbuf. the start bit is put on txd at c1 following the first roll - over of the divide - by - 16 counter , and t he next bit is placed at c1 following the next rollover. after all eight bits are transmitted, the stop bit is transmitted. the ti flag is set in the next c1 state , or the tenth rollover of the divide - by - 16 counter after the write to sbuf. reception is enabled when ren is high , and t he serial port starts receiving data when it detect s a falling edge on rxd. the falling - edge detector monitors the rxd line at 16 times the selected baud rate. when a falling edge is detected, the divide - by - 16 counter is reset to align the bit boundaries with the rollovers of the c ounter. the 16 states of the counter divide the bit time into 16 slices. b it detection is done on a best - of - three bas i s using samples at the 8th, 9th and 10th counter states. if the first bit after the falling edge is not 0, the start bit is invalid , reception is aborted immediately, and t he serial port resumes look ing for a falli ng edge on rxd. if a valid start bit is detected, the rest of the bits are shifted into sbuf. after shifting in eight data bits, the stop bit is received. then, if ; 1. ri is 0 , and 2. sm2 is 0 or the received stop bit is 1 , the stop bit goes in to rb8, th e eight data bits go into sbuf , and ri is set. otherwise , the received frame is lost. in the middle of the stop bit, the receiver resumes looking for a falling edge on rxd. 1 / 2 1 / 16 tx clock rx clock ti ri tx shift tx start rx shift load sbuf smod clock sin d 8 sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus write to sbuf sout transmit shift register serial interrupt txd rxd parout rb 8 start stop 0 1 bit detector 1 - to - 0 detector sample 1 / 16 0 timer 1 overflow 1 receive shift register 0 1 0 1 tclk rclk timer 2 overflow figure 16 - 2 serial port mode 1
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 134 - revision a 0. 2 16.3 m ode 2 in mode 2, full - duplex asynchronous communication is used. frames consist of eleven bits : one start bit (0), eight data bits (lsb first), a programmable ninth bit (tb8) and a stop bit (0). when receiving, t he ninth bit is p ut into rb8. the baud rate is 1/ 16 or 1/ 32 of the oscillator frequency, as determined by smod in pcon. transmission begins with a write to sbuf but is synchronized with the divide - by - 16 counter, not the write to sbuf . the start bit is put on txd pin at c1 following the first roll - over of the divide - by - 16 counter, and t he next bit is placed on txd at c1 following the next rollover. after all nine bits of data are transmitted, the stop bit is transmitted. the ti flag is set in the next c1 state , or the 11th r ollover of the divide - by - 16 counter after the write to sbuf. reception is enabled when ren is high , and t he serial port starts receiving data when it detect s a falling edge on rxd. the falling - edge detector monitors the rxd line at 16 times the selected ba ud rate. when a falling edge is detected, the divide - by - 16 counter is reset to align the bit boundaries with the rollovers of the c ounter. the 16 states of the counter divide the bit time into 16 slices. b it detection is done on a best - of - three bas i s using samples at the 8th, 9th and 10th counter states. if the first bit after the falling edge is not 0, the start bit is invalid , reception is aborted , and t he serial port resumes look ing for a falling edge on rxd. if a valid start bit is detected, the rest of the bits are shifted into sbuf. after shifting in nine data bits, the stop bit is received. then, if ; 1. ri is 0 , and 2. sm2 is 0 or the received stop bit is 1 , the stop bit goes in to rb8, the eight data bits go into sbuf , and ri is set. otherwise , the received frame may be lost. in the middle of the stop bit, the receiver resumes looking for a falling edge on rxd. the functional description is shown in the figure below. 1 / 2 1 / 16 tx clock rx clock ti ri tx shift tx start rx shift load sbuf smod clock sin d 8 sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus write to sbuf sout transmit shift register serial interrupt txd rxd parout rb 8 start stop 0 1 bit detector 1 - to - 0 detector sample 1 / 16 0 fosc / 2 1 d 8 tb 8 receive shift register figure 16 - 3 serial port mode 2
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 135 - revision a 0. 2 16.4 m ode 3 this mode is the same as mode 2, except that the baud rate is programmable. the program must select the m ode and baud rate in scon before any communication can take place. timer 1 should be initialized if mode 1 or mode 3 w ill be used. tx clock rx clock ti ri tx shift tx start rx shift load sbuf clock sin d 8 sbuf read sbuf internal data bus serial controllor clock load parin tx start internal data bus write to sbuf sout transmit shift register serial interrupt txd rxd parout rb 8 start stop 0 1 bit detector 1 - to - 0 detector d 8 tb 8 receive shift register 1 / 2 1 / 16 smod sample 1 / 16 0 timer 1 overflow 1 0 1 0 1 tclk rclk timer 2 overflow figure 16 - 4 serial port mode 3 sm0 sm1 mode type baud clock frame size start bit stop bit 9th bit function 0 0 0 synch. 4 or 12 osc 8 bits no no none 0 1 1 asynch . timer 1 or 2 10 bits 1 1 none 1 0 2 asynch. 32 or 64 osc 11 bits 1 1 0, 1 1 1 3 asynch. timer 1 or 2 11 bits 1 1 0, 1 table 16 - 1 : serial ports modes 16.5 framing error detection a f rame e rror occurs when a va lid stop bit is not detected. this could indicate incorrect serial data communication. typically , a frame error is due to noise or contention on the serial communication line. the w79e217 /217 has the ability to detect framing errors and set a flag that can be checked by software. the f rame e rror fe (fe_1) bit is located in scon.7. this bit is sm0 in the standard 8051/52 family , but, in the w79e217 /217 , it serves a dual function and is called sm0/fe. there are actually two separate flags, sm0 and fe. the fla g that is actually accessed as scon.7 is determined by smod0 (pcon.6). when smod0 is set to 1, the fe flag is accessed . when smod0 is set to 0, the sm0 flag is accessed .
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 136 - revision a 0. 2 the fe bit is set to 1 by the hardware , but it must be cleared by the software. once f e is set, any frames received afterwards, even those without error s, do not clear the fe flag. the flag has to be cleared by the software. note that smod0 must be set to 1 while reading or writing fe. 16.6 multiprocessor communications multiprocessor communica tion is available in modes 1, 2 and 3 and makes use of the 9th data bit and the automatic address recognition feature . this approach eliminates the software overhead required to check every received address and greatly simplifies the program. in modes 2 an d 3 , address bytes are distinguished from data bytes by 9th bit set , which is set high in address bytes . when the master processor wants to transmit a block of data to one of the slaves, it first sends the address of the target slave(s). t he slave processo rs have already set their sm2 bit s high so that they are only interrupted by a n address byte. the a utomatic address recognition feature then ensures that only the addressed slave is actually interrupted. this feature compar es the received byte to the slave ? s given or broadcast address and only sets the ri flag if the byte s match . th is slave then clears the sm2 bit, clearing the way to receive the data bytes. the unaddressed slaves are not affected, as they are still waiting for their address. in m ode 1, the 9th bit is the stop bit, which is 1 in valid frame s . therefore, i f sm2 is 1, ri is only set if a valid frame is received and if the received byte matches the given or broadcast address. the m aster processor can selectively communicate with groups of slave s using the given address or a ll the slaves can be addressed together using the broadcast address. the addresses for each slave are defined by the saddr and saden registers . the slave address is the 8 - bit value specified in saddr. saden is a mask for the v alue in saddr. if a bit position in saden is 0, then the corresponding bit position in saddr is a don't - care condition in the address comparison . only those bit positions in saddr whose corresponding bits in saden are 1 are used to obtain the given address . this provides flexibility to address multiple slaves without changing address es in saddr. the following example shows how to setup the given address es to address different slaves. slave 1: saddr 1010 0100 saden 1111 1010 given 1010 0x0x slave 2: sadd r 1010 0111 saden 1111 1001 given 1010 0xx1 the given a ddress for slave s 1 and 2 differ in the lsb. in slave 1, it is a d on't - care, while , in slave 2 , it is 1. thus , to communicate with only slave 1, the master must send an address with lsb = 0 (1010 000 0). similarly , bit 1 is 0 for slave 1 and don't - care for slave 2. hence , to communicate only with slave 2 , the master has to transmit an address with bit 1 = 1 (1010 0011). if the master wishes to communicate with both slaves simultaneously, then the addre ss must have bit 0 = 1 and bit 1 = 0. since b it 3 is don't - care for both slaves , two different addresses can address both slaves (1010 0001 and 1010 0101). the master can communicate with all the slaves simultaneously using the broadcast address. the broad cast a ddress is formed from the logical or of the saddr and saden registers . the zeros in the result are don't ? care values. in most cases , the broadcast address is ffh. in the previous case, the broadcast address is (1111111x) for slave 1 and (11111111) fo r slave 2. the saddr and saden registers are located at address es a9h and b9h , respectively. t hese two registers default to 00h , so the given address and broadcast address default to xxxx xxxx (i.e. , all bits don't - care) , which effectively removes the mult iprocessor communications feature
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 137 - revision a 0. 2 17 i2c serial ports the i 2 c bus uses two wires (scl and sda) to transfer information between devices connected to the bus. the main features of the i2c bus are: ? bi - directional data transfer between masters and slaves . ? mu lti - master bus (no central master) . ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus . ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus . ? serial c lock synchronization can be used as a handshake mechanism to suspend and resume serial transfer . ? the i 2 c bus may be used for test and diagnostic purposes . t buf stop sda scl start t hd ; sta t low t hd ; dat t high t f t su ; dat repeated start t su ; sta t su ; sto stop t r figure 17 - 1 : i2c bus timing the device?s on - chip i 2 c logic provides the serial interface that meet s the i 2 c bus standard mode specification. the i2c logic handles bytes transfer autonomously. it also keeps track of serial transfers, and a status register ( i2status ) reflects t he status of the i 2 c bus. the i2c port, scl and sda are at p2.6 and p2. 7 . when the i/o pins are used as i2c port, user must set the pins to logic high in advance. when i2c port is enabled by setting ens to high, the internal states will be controlled by i2 con and i2c logic hardware. once a new status code is generated and stored in i2status , the i2c interrupt flag (si) will be set automatically . i f both ea and ei2c are also in logic high, the i2c interrupt is requested . the 5 most significant bits of i2stat us stores the internal state code, the lowest 3 bits are always zero and the content keeps stable until si is cleared by software.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 138 - revision a 0. 2 17.1 sio port the sio port is a serial i/o port, which supports all transfer modes from and to the i2c bus. the sio port handles byte transfers autonomously. to enable this port, the bit ens1 in i2con should be set to '1'. the cpu interfaces to the sio port through the s even special function registers. the detail description of these registers can be found in the i2c control regist ers section. the sio h/w interfaces to the i2c bus via two pins: sda (p2.7, serial data line) and scl (p2.6, serial clock line). pull up resistor is needed for pin p 2.6 and p2.7 for i2c operation as these are 2 open drain pins. 17.2 the i2c control registers t he i2c has 1 control register (i2con) to control the transmit/receive flow, 1 data register (i2dat) to buffer the tx/rx data, 1 status regist er (i2status) to catch the state of tx/rx, recognizable slave address register for slave mode use and 1 clock rate control block for master mode to generate the variable baud rate. symbol definition address msb bit _ address, symbol lsb reset i2timer i2c timer counter register efh - - - - - enti div4 tif xxxx x 000 b i2clk i2c clock rate ee h i2clk.7 i2clk.6 i2clk.5 i2 clk.4 i2clk.3 i2clk.2 i2clk.1 i2clk.0 0000 0000b i2status i2c status register ed h i2statu s .7 i2statu s .6 i2statu s .5 i2statu s .4 i2statu s .3 - - - 1111 1000b i2dat i2c data ec h i2d at. 7 i2d at. 6 i2d at. 5 i2d at. 4 i2d at. 3 i2d at. 2 i2d at. 1 i2d at. 0 0000 0000b i2add r i2c slave address ea h addr.7 addr.6 addr.5 addr.4 addr.3 addr.2 addr.1 gc 0000 000 0 b i2con i2c control register e9 h - ens sta sto si aa i2cin - x000 00 0 xb i2csaden i2c maskable slave address f6h i2csade n.7 i2csade n.6 i2csade n.5 i2csade n.4 i2csade n.3 i2 csade n.2 i2csade n.1 i2csade n.0 1111 1110b table 17 - 1 : contro l registers of i2c ports 17.2.1 slave address registers, i2addr i2c port is equipped with one slave address register . the content s of the register are irr elevant when i2c is in master mode. in the slave mode, the seven most significant bits must be loaded with the mcu?s own slave address. t he i2c hardware will react if the contents of i2addr are matched with the received slave address. the i2c ports support the ? general call ? function. if the gc bit is set the i2c port1 hardware will respond to general call address (00h). clear gc bit to disable general call function. when gc bit is set, the device is in slave mode which can receive the general call address( 00h) sent by master on the i2c bus. this special slave mode is referred to as gc mode. 17.2.2 data register, i2 dat this register contains a byte of serial data to be transmitted or a byte which has just been received. the cpu can read from or write to this 8 - bit directly addressable sfr while it is not in the process of shifting a byte. data in i2 dat remains stable as long as si is set. the msb is shifted out first. while data is being shifted out, data on the bus is simultaneously being shifted in; i2 dat alwa ys contains the last data byte present on the bus. thus, in the event of arbitration lost, the transition from master transmitter to slave receiver is made with the correct data in i2 dat. i2 dat and the acknowledge bit form a 9 - bit shift register which shif ts in or out an 8 - bit byte, followed by an acknowledge bit. t he acknowledge bit is controlled by the hardware and cannot be accessed by the cpu. serial data is shifted into i2 dat on the rising edges of serial clock pulses on the scl line. when a byte has b een shifted into i2 dat, the serial data is available in i2 dat, and the acknowledge bit (ack or nack) is returned by the control logic during the ninth clock pulse. serial data is shifted out from i2 dat on the fal ling edges of scl clock pulses , and is shift ed into i2dat on the rising edges of scl clock pulses .
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 139 - revision a 0. 2 i 2 dat . 7 i 2 dat . 6 i 2 dat . 5 i 2 dat . 4 i 2 dat . 3 i 2 dat . 2 i 2 dat . 1 i 2 dat . 0 i 2 c data register : shifting direction figure 17 - 2 : i2c data shift 17.2.3 control register, i2con the cpu can read from and write to this 8 - bit, directly addressable sf r . two bits are affected by hardware: the si bit is set when the i2c hardware requests a serial interrupt, and the sto bit is cleared when a stop condition is present on the bus. the sto bit is also cleared when ens = "0". ens i2c serial function block ena ble bit . when ens=1 the i2c serial function enables. the port latches of sda1 and scl1 must be set to logic high. [j6] st a i2c start flag. setting sta to logic 1 to enter master mode, the i2c hardware sends a start or r epeat start condition to bus when the bus is free. sto i2c stop flag. in master mode, setting sto to transmit a stop condition to bus then i2c hardware will check the bus condition if a stop condition is detected this flag will be cleared by hardware automatically. in a slave mode, setting sto r esets i2c hardware to the ?not addressed slave mode? . si i2c port 1 interrupt flag. when a new sio state is present in the s1sta register, the si flag is set by hardware, and if the ea and ei2c1 bits are both set, the i2c1 interrupt is requested. si mu st be cleared by software. aa assert acknowledge control bit [lp7] . when aa=1 prior to address or data received [lp8] , an acknowledge d ( low level to sda) will be returned during the acknowledge clock pulse on the scl line when ; 1.) a slave is acknowledging the addre ss sent from master, 2.) the receiver devices are acknowledging the data sent by transmitter. when aa=0 prior to address or data received , a n ot [lp9] acknowledged (high level to sda) will be returned during the acknowledge clock pulse on the scl line. i2cin by default it is zero and input are allows to come in through sda pin. as when it is 1 input is disallow and to prevent leakage current. during power - down mode input is disallow. 17.2.4 status register, i2status i2status is an 8 - bit read - only register. the three l east significant bits are always 0. the five most significant bits contain the status code. there are 23 possible status codes. when i2status contains f8h, no serial interrupt is requested. all other i2status values correspond to defined i2c ports states. when each of these states is entered, a status interrupt is requested (si = 1). a valid status code is present in i2status one machine cycle after si is set by hardware and is still present one machine cycle after si has been reset by software. in addition , state 00h stands for a bus error. a bus error occurs when a start or stop condition is present at an illegal position in the format frame. examples of illegal positions are during the serial transfer of an address byte, a data byte or an acknowledge bit. 17.2.5 i2c clock baud rate control , i2clk the data baud rate of i2c is determines by i2clk register when i2c port is in a master mode. it is not important when i2c port is in a slave mode. in the slave modes, sio will automatically synchronize with any clock fr equency up to 400 khz from master i2c device. the data baud rate of i2c setting conforms to the following equation. data baud rate of i2c = f cpu / (i2clk + 1), where f cpu = f osc / 4.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 140 - revision a 0. 2 for example, if f osc =16mhz, the i2clk=40(28h), the data baud rate of i2c = ( 16mhz /4) /(40+1) = 97.56k bits/sec. 17.2.6 i2c time - out counter, i2timer in w79e217 /217 , the i2c logic block provides a 14 - bit timer - out counter that helps user to deal with bus pending problem. when si is cleared user can set enti=1 to start the time - out cou nter. if i2c bus is pended too long to get any valid signal from devices on bus, the time - out counter overflows cause tif=1 to request an i2c interrupt. the i2c interrupt is requested in the condition of either si=1 or tif=1. flags si and tif must be clear ed by software. 17.2.7 i2c maskable slave address this register enables the automatic address recognition feature of the i2c. when a bit in the i2csaden is set to 1, the same bit location in i2csaddr 1 will be compared with the incoming serial port data. when i2c saden.n is 0, then the bit becomes a don't - care in the comparison. this register enables the automatic address recognition feature of the i2c. when all the bits of i2csaden are 0, interrupt will occur for any incoming address. 1 0 fosc 1 / 4 14 - bits counter tif clear counter enti si div 4 ens 1 to i 2 c interrupt enable si figure 17 - 3 : i2c t ime - out block diagram 17.3 modes of operation the on - chip i2c ports support five operation modes, master transmitter , master receiver, slave transmitter , slave receiver , and gc cal l . in a given application, i2c port may operate as a maste r or as a slave. in the slave mode, the i2c port hardware looks for its own slave address and the general call address. if one of these addresses is detected, and if the slave is willing to receive or transmit data from/to master(by setting the aa bit), ac knowledge pulse will be transmi t ted out on the 9 th clock, hence an interrupt is requested on both master and slave devices if interrupt is enabled. when the microcontroller wishes to become the bus master, the hardware waits until the bus is free before th e master mode is entere d so that a possible slave action is not interrupted. if bus arbitration is lost in the master mode, i2c port switches to the slave mode immediately and can detect its own slave addr ess in the same serial transfer . 17.3.1 master transmitter mode serial data output through sda while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. in this case the data direction bit (r/w) will be logic 0, and we sa y that a ?w? is transmitted. thus the first byte transmitted is sla+w. serial data is transmitted 8 bits at a time. after each byte is transmitted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end o f a serial
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 141 - revision a 0. 2 transfer. 17.3.2 master receiver mode in this case the data direction bit (r/w) will be logic 1, and we say that an ?r? is transmitted. thus the first byte transmitted is sla+r. serial data is received via sda while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are output to indicate the beginning and end of a serial transfer. 17.3.3 slave receiver mode serial data and the serial clock are receiv ed through sda and scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave addres s and direction bit. 17.3.4 slave transmitter mode the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit will indicate that the transfer direction is reversed. serial data is transmitted via sda while the s erial clock is input through scl. start and stop conditions are recognized as the beginning and end of a serial transfer. 17.4 data transfer flow in five operating modes the five operating modes are: master/transmitter, master/receiver, slave/transmitter, slav e/receiver and gc call. bits sta, sto and aa in i2con register will determine the next state of the sio hardware after si flag is cleared. upon complexion of the new action, a new status code will be updated and the si flag will be set. if the i2c interrup t control bits (ea and ei2) are enable d , appropriate action or software branch of the new status code can be performed in the interrupt service routine. data transfers in each mode are shown in the following figures. 08h a start has been transmitted. (sta,sto,si,aa)=(0,0,0,x) sla+w will be transmitted; ack bit will be received. 18h sla+w has been transmitted; ack has been received. last state last action is done expected next action next action is done new state software should load the data byte (to be transmitted) into i2 dat before new i2 con setting is done. (1) data byte will be transmitted: (2) sla+w (r) will be transmitted: software should load the sla+w/r (to be transmitted) into i2 dat before new i2 con setting is done. (3) data byte will be received: software can read the received data byte from i2 dat while a new state is entered. next setting in i2con figure 17 - 3 : l egend for i2c f low charts
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 142 - revision a 0. 2 17.4.1 master/transmitter mode 08h a start has been transmitted. (sta,sto,si,aa)=(0,0,0,x) sla+w will be transmitted; ack bit will be received. set sta to generate a start. 18h sla+w will be transmitted; ack bit will be received. or 20h sla+w will be transmitted; not ack bit will be received. (sta,sto,si,aa)=(1,0,0,x) a repeated start will be transmitted; (sta,sto,si,aa)=(0,0,0,x) data byte will be transmitted; ack will be received. (sta,sto,si,aa)=(0,1,0,x) a stop will be transmitted; sto flag will be reset. send a stop (sta,sto,si,aa)=(1,1,0,x) a stop followed by a start will be transmitted; sto flag will be reset. send a stop followed by a start 28h data byte in s1dat has been transmitted; ack has been received. or 30h data byte in s1dat has been transmitted; not ack has been received. 10h a repeated start has been transmitted. (sta,sto,si,aa)=(0,0,0,x) sla+r will be transmitted; ack bit will be transmitted; sio1 will be switched to mst/rec mode. 38h arbitration lost in sla+r/w or data byte. (sta,sto,si,aa)=(0,0,0,x) i2c bus will be release; not address slv mode will be entered. (sta,sto,si,aa)=(1,0,0,x) a start will be transmitted when the bus becomes free. send a start when bus becomes free enter naslave from slave mode (c) to master/receiver (a) from master/receiver (b) figure 17 - 4 : master transmitter mode
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 143 - revision a 0. 2 17.4.2 master/receiver mode 08h a start has been transmitted. (sta,sto,si,aa)=(0,0,0,x) sla+r will be transmitted; ack bit will be received. set sta to generate a start. 40h sla+r has been transmitted; ack has been received. (sta,sto,si,aa)=(0,1,0,x) a stop will be transmitted; sto flag will be reset. (sta,sto,si,aa)=(1,1,0,x) a stop followed by a start will be transmitted; sto flag will be reset. (sta,sto,si,aa)=(0,0,0,0) data byte will be received; not ack will be returned. send a stop (sta,sto,si,aa)=(0,0,0,1) data byte will be received; ack will be returned. 10h a repeated start has been transmitted. (sta,sto,si,aa)=(0,0,0,x) sla+r will be transmitted; ack bit will be transmitted; sio1 will be switched to mst/tx mode. (sta,sto,si,aa)=(1,0,0,x) a start will be transmitted; when the bus becomes free (sta,sto,si,aa)=(0,0,0,x) i2c bus will be release; not address slv mode will be entered. enter naslave from master/transmitter (a) to master/transmitter (b) from slave mode (c) 48h sla+r has been transmitted; not ack has been received. 58h data byte has been received; not ack has been returned. 50h data byte has been received; ack has been returned. send a stop followed by a start 38h arbitration lost in not ack bit. send a start when bus becomes free (sta,sto,si,aa)=(1,0,0,x) a repeated start will be transmitted; figure 17 - 5 : master receiver mode
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 144 - revision a 0. 2 17.4.3 slave/transmitter mode set aa a8h own sla+r has been received; ack has been return. or b0h arbitration lost sla+r/w as master; own sla+r has been received; ack has been return. (sta,sto,si,aa)=(1,0,0,1) switch to not address slv mode; own sla will be recognized; a start will be transmitted when the bus becomes free. (sta,sto,si,aa)=(0,0,0,0) last data will be transmitted; ack will be received. (sta,sto,si,aa)=(0,0,0,1) data byte will be transmitted; ack will be received. send a start when bus becomes free c8h last data byte in s1dat has been transmitted; ack has been received. (sta,sto,si,aa)=(1,0,0,0) switch to not addressed slv mode; no recognition of own sla; a start will be transmitted when the becomes free. (sta,sto,si,aa)=(0,0,0,1) switch to not addressed slv mode; own sla will be recognized. (sta,sto,si,aa)=(0,0,0,0) switch to not addressed slv mode; no recognition of own sla. enter naslave to master mode (c) (sta,sto,si,aa)=(0,0,0,0) last data byte will be transmitted; ack will be received. (sta,sto,si,aa)=(0,0,0,1) data byte will be transmitted; ack will be received. c0h data byte or last data byte in s1dat has been transmitted; not ack has been received. b8h data byte in s1dat has been transmitted; ack has been received. a0h a stop or repeated start has been received while still addressed as slv/rec. figure 17 - 6 : slave transmitter mode
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 145 - revision a 0. 2 17.4.4 slave/receiver mode set aa 60h own sla+w has been received; ack has been return. or 68h arbitration lost sla+r/w as master; own sla+w has been received; ack has been return. (sta,sto,si,aa)=(1,0,0,1) switch to not address slv mode; own sla will be recognized; a start will be transmitted when the bus becomes free. (sta,sto,si,aa)=(0,0,0,0) data will be received; not ack will be returned. (sta,sto,si,aa)=(0,0,0,1) data will be received; ack will be returned. send a start when bus becomes free 88h previously addressed with own sla address; not ack has been returned. (sta,sto,si,aa)=(1,0,0,0) switch to not addressed slv mode; no recognition of own sla; a start will be transmitted when the becomes free. (sta,sto,si,aa)=(0,0,0,1) switch to not addressed slv mode; own sla will be recognized. (sta,sto,si,aa)=(0,0,0,0) switch to not addressed slv mode; no recognition of own sla. enter naslave to master mode (c) (sta,sto,si,aa)=(0,0,0,0) data byte will be received; not ack will be returned. (sta,sto,si,aa)=(0,0,0,1) data byte will be received; ack will be returned. 80h previously addressed with own sla address; data has been received; ack has been returned. a0h a stop or repeated start has been received while still addressed as slv/rec. figure 17 - 7 : slave receiver mode
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 146 - revision a 0. 2 17.4.5 gc mode set aa 70h reception of the general call address and one or more data bytes; ack has been return. or 78h arbitration lost sla+r/w as master; and address as sla by general call; ack has been return. (sta,sto,si,aa)=(1,0,0,1) switch to not address slv mode; own sla will be recognized; a start will be transmitted when the bus becomes free. (sta,sto,si,aa)=(x,0,0,0) data will be received; not ack will be returned. (sta,sto,si,aa)=(x,0,0,1) data will be received; ack will be returned. send a start when bus becomes free 98h previously addressed with general call; data byte has been received; not ack has been returned. (sta,sto,si,aa)=(1,0,0,0) switch to not addressed slv mode; no recognition of own sla; a start will be transmitted when the becomes free. (sta,sto,si,aa)=(0,0,0,1) switch to not addressed slv mode; own sla will be recognized. (sta,sto,si,aa)=(0,0,0,0) switch to not addressed slv mode; no recognition of own sla. enter naslave to master mode (c) (sta,sto,si,aa)=(x,0,0,0) data byte will be received; not ack will be returned. (sta,sto,si,aa)=(x,0,0,1) data byte will be received; ack will be returned. 90h previously addressed with general call; data has been received; ack has been returned. a0h a stop or repeated start has been received while still addressed as slv/rec. figure 17 - 8 : general call address
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 147 - revision a 0. 2 18 serial peripheral interf ace (spi) 18.1 general descriptions this device consists of spi block to support high speed serial communication. it?s capable of supporting data transfer rates 5 m bit/s . this device?s spi support the following features; ? ? master and slave mode . ? ? slave select outpu t . ? ? programmable serial clock?s polarity and phase . ? ? receive double buffered data register . ? ? lsb first enable . ? ? write collision detection . ? ? transfer complete interrupt . 18.2 block descriptions the figure 18 - 1 shows spi block diagram. it pr ovide s an overview of spi architecture in this device. the main blocks of spi are the register blocks, control logics, baud rate control and pin control logics; a. shift register and read data buffer. it is single buffered in the transmit direction and doubl e buffered in the receive direction. transmit data cannot be written to the shifter until the previous transfer is complete. receive logics consist of parallel read data buffer so the shifter is free to accept a second data, as the first received data will be transferred to the read data buffer. b. spi control block. this provide control functions to configure the device for spi enable, master or slave, clock phase and polarity, lsb access first selection, and slave select output enable. c. baud rate control. these control logics divide cpu clock to 4 different selectable clocks 1/8, 1/32, 1/128 and 1/256. its? selection is controllable through spr [ 1 : 0 ] bits. spr1 spr0 divider baud rate 0 0 8 5mhz 0 1 32 1.25mhz 1 0 128 312.50khz 1 1 256 156.25khz table 18 - 1 spi baud rate selection ( f osc @ 40 mhz) d. spi registers. there are three spi registers to support its operations, they are; ? spi control registers (spcr) ? spi status registers (spsr) ? spi data regi ster (spdr) these registers provide control, status, data storage functions and baud rate selection control. detail bits descriptions are found at sfr section. when using spi pull - up must be apply at bit pup0 = 1. e. pin control logic. controls behavior of s pi interface pins.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 148 - revision a 0. 2 divider /8, /32, /128, /256 select 8-bit shift register read data buffer msb lsb p i n c o n t r o l l o g i c miso mosi spclk ss spi control spi status register spi control register clock logic s m m s clock s p i f w c o l s p i o v f m o d f d r s s spi interrupt request s p e mstr m s t r s s o e d r s s s p r 0 s p r 1 s p r 0 s p r 1 c p h a c p o l m s t r l s b f e s p e s s o e spe internal data bus internal mcu clock figure 18 - 1 : spi block diagram
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 149 - revision a 0. 2 18.3 functional descriptions 18.3.1 master mode the device can configure the spi to operate as a master or as a slave, through mstr bit . when the mstr bit is set, master mode is selected, when mstr bit is cleared, slave mode is selected. during master mode, only master spi device can initiate transmission. a transmission begins by writing to the master spdr register. the byte s begin shift ing out on mosi pin under the control of spclk. the master places data on mosi line a half - cycle before spclk edge that the slave device uses to latch the data bit. the ss must stay low before data transactions and stay low for the dur ation of the transactions . 1 2 8 7 6 5 4 3 lsb 1 2 3 4 5 6 msb spclk spclk ( output ) ( cpol = 0 ) mosi / miso ss ( output to slave ) spif master transfer in progress 1 2 3 4 1 . ss asserted 2 . master writes to spdr 3 . during master transmit , data is shifting out through mosi . during master receive , data is shifting in through miso . 4 . spif set at the end of transmission . 5 . ss negated note : when cpha = 0 , ss output must go high between successive spi character . when cpol = 0 , spclk idle low . spclk cycle 5 [lp10] [j11] [j12] [jk13] [j14] figure 18 - 2 : master mode transmission (cpol = 0, cpha = 0)
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 150 - revision a 0. 2 1 2 8 7 6 5 4 3 lsb 1 2 3 4 5 6 msb spclk spclk ( output ) ( cpol = 1 ) mosi / miso ss ( output to slave ) spif master transfer in progress 1 2 3 4 1 . ss asserted 2 . master writes to spdr 3 . during master transmit , data is shifting out through mosi . during master receive , data is shifting in through miso . 4 . spif set at the end of transmission . 5 . ss negated note : when cpha = 0 , ss output must go high between successive spi character . when cpol = 1 , spclk idle high . spclk cycle 5 figure 18 - 3 : master mode transmission (cpol = 1, cpha = 0) 1 2 8 7 6 5 4 3 lsb 1 2 3 4 5 6 msb spclk spclk ( output ) ( cpol = 0 ) mosi / miso ss ( output to slave ) spif master transfer in progress 1 2 3 4 1 . ss asserted 2 . master writes to spdr 3 . during master transmit , data is shifting out through mosi . during master receive , data is shifting in through miso . 4 . spif set at the end of transmission . 5 . ss negated note : when cpha = 1 , ss output can stay low between successive spi character . when cpol = 0 , spclk idle low . spclk cycle 5 figure 18 - 4 : master mode transmission (cpol = 0, cpha = 1)
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 151 - revision a 0. 2 1 2 8 7 6 5 4 3 lsb 1 2 3 4 5 6 msb spclk spclk ( output ) ( cpol = 0 ) mosi / miso ss ( output to slave ) spif master transfer in progress 1 2 3 4 1 . ss asserted 2 . master writes to spdr 3 . during master transmit , data is shifting out through mosi . during master receive , data is shifting in through miso . 4 . spif set at the end of transmission . 5 . ss negated note : when cpha = 1 , ss output can stay low between successive spi character . when cpol = 1 , spclk idle high . (cpol = 1) spclk cycle 5 figure 18 - 5 : master mode transmission (cpol = 1, cpha = 1) 18.3.2 slave mode when in slave mode, the spclk pin becomes input and it will be clock by another master spi device. the ss pin also becomes input. similarly, before dat a transmissions occurs, and remain low until the transmission completed. if ss goes high, the spi is forced in to idle state. if the ss is force d to high at the middle of transmission , the transmission will be abort ed and the receiving shifter buffer will be high and goes into idle states. data flows from master to slave on mosi pin and flows from slave to master on miso pin. the spdr is used when transmitting or receiving data on the serial bus. only a write to this register initiates transmission or reception of a byte, and this only occurs in the master device. at the completion of transferring a byte of data, the spif status bit is set in both the master and slave devices. a read of the spdr is actually a read of a buffer. to prevent an overrun and the loss of the byte that caused the overrun, the first spif must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 152 - revision a 0. 2 1 2 8 7 6 5 4 3 lsb 1 2 3 4 5 6 msb spclk spclk ( input ) ( cpol = 0 ) mosi / miso ss ( input ) spif slave transfer in progress 1 2 3 5 1 . ss asserted 2 . slave writes to spdr 3 . during slave transmit , data is shifting out through mis 0 . during slave receive , data is shifting in through mosi . 4 . spif set at the last sampling bit. 5 . ss negated note : when cpha = 0 , ss output must go high between successive spi character . when cpol = 0 , spclk idle low . spclk cycle 4 figure 18 - 6 : slave mode transmission (cpol = 0, cpha = 0) 1 2 8 7 6 5 4 3 lsb 1 2 3 4 5 6 msb spclk spclk ( input ) ( cpol = 1 ) mosi / miso ss ( input ) spif slave transfer in progress 1 2 3 5 1 . ss asserted 2 . slave writes to spdr 3 . during slave transmit , data is shifting out through miso . during slave receive , data is shifting in through mosi . 4 . spif set at the last sampling bit. 5 . ss negated note : when cpha = 0 , ss output must go high between successive spi character . when cpol = 1 , spclk idle high . spclk cycle 4 figure 18 - 7 : slave mode transmission (cpol = 1, cpha = 0)
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 153 - revision a 0. 2 1 2 8 7 6 5 4 3 lsb 1 2 3 4 5 6 msb spclk spclk ( input ) ( cpol = 0 ) mosi / miso ss ( input ) spif slave transfer in progress 1 2 3 5 1 . ss asserted 2 . slave writes to spdr 3 . during slave transmit , data is shifting out through miso . during slave receive , data is shifting in through mosi . 4 . spif set at the last sampling bit. 5 . ss negated note : when cpha = 1 , ss output can stay low between successive spi character . when cpol = 0 , spclk idle low . spclk cycle 4 f igure 18 - 8 : slave mode transmission (cpol = 0, cpha = 1) 1 2 8 7 6 5 4 3 lsb 1 2 3 4 5 6 msb spclk spclk ( input ) ( cpol = 0 ) mosi / miso ss ( input ) spif slave transfer in progress 1 2 3 5 1 . ss asserted 2 . slave writes to spdr 3 . during slave transmit , data is shifting out through miso . during slave receive , data is shifting in through mosi . 4 . spif set at the last sampling bit. 5 . ss negated note : when cpha = 1 , ss output can stay low between successive spi character . when cpol = 1 , spclk idle high . (cpol = 1) spclk cycle 4 figure 18 - 9 : slave mode transmission (cpol = 1, cpha = 1)
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 154 - revision a 0. 2 18.3.3 slave select the slave select ( ss ) input of a slave device must be externally asserted before a master device can exchange data with the slave device. ss must be low before data transactions and must stay low for the duration o f the transaction. the ss line of the master must be held high. the other three lines are dedicated to the spi whenever the serial peripheral interface is on. the state of the master and slave cpha bits affects the operation of ss . cpha settings should be identical for master and slave. when cpha = 0, the shift clock is the or of ss with spclk. in this clock phase mode, ss must go high between successive characters in an spi message. when cpha = 1, ss can be left low between successive spi characters. in cases where there is only one spi slave mcu, its ss line can be tied to vss as long as only cpha = 1 clock mode is used. 18.3.4 /ss output available in master mode only, ss output is enabled with the ssoe bit in the spcr register and drss bit in the spsr register . the ss output pin is connected to the ss input pin of the slave de vice. the ss output automatically goes low for each transmission when selecting external device and it goes high during each idling state to deselect external devices. drss ssoe master mode slave mode 0 0 ss inpu t ( w ith mode fault ) ss input ( not affected by ssoe ) 0 1 r eserved ss input ( not affected by ssoe ) 1 0 ss general purpose i/o ( no mode fault ) ss input ( not affecte d by ssoe ) 1 1 ss output ( no mode fault ) ss input ( not affected by ssoe ) during master mode (with ssoe =drss = 0), mode fault will be set if ss pin is detected low. when mode fault is det ected hardware will clear mstr bit and spe bit in the meantime it will also generated interrupt request, if espi is enabled. modf spif ssoe mstr ea espi spi interrupt request ss drss spiovf figure 18 - 10 : spi interrupt request
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 155 - revision a 0. 2 18.3.5 spi i/o pins mo de when spi is disabled (spe = 0) the corresponding i/o is following the original setting and act as a normal i/o. in the case of spi is enabled (spe = 1) the spi pins i/o mode follow the below table. for /ss pin it is always at quasi - bidirectional mode wh ether it is configured as master or slave. miso mosi clk /ss master input output output output *: drss=0,ssoe=0 input: drss=1, ssoe=1 slave output ** during /ss = low else input mode input input input input = quasi - bidirectional mode output = push - pul l mode output* = this output mode in /ss is quasi - bidirectional output mo de. master needs to detect mode fault during master outputs /ss low. output** = in slave mode, miso is in output mode only during the time o f /ss=low, otherwise it must keep in inpu t mode ( quasi - bidirectional ). 18.3.6 programmable serial clock?s phase and polarity the clock polarity cpol control bit selects active high or active low spclk clock, and has no significant effect on the transfer format. the clock phase cpha control bit selects one of two different transfer protocols by sampling data on odd numbered spclk edges or on even numbered spclk edges. thus, both these bits enable selection of four possible clock formats to be used by spi system. the clock phase and polarity should be id entical for the master spi device and the communicating slave device. when cpha equals 0, the ss line must be negated and reasserted between each successive serial byte. also, if the slave writes data to the spi data register (spdr) w hile ss is low, a write collision error results. when cpha equals 1, the ss line can remain low between successive transfers. the figures from figure 18 - 2 to figure 18 - 9 show the spi transfer format, with different cpol and cpha. when cpha = 0, data is sample on the first edge of spclk and when cpha = 1 data is sample on the second edge of the spclk. prior to changing cpol setting, spe must be disabled first . 18.3.7 rece ive double buffered data register this device is single buffered in the transmit direction and double buffered in the receive direction. this means that new data for transmission cannot be written to the shifter until the previous transfer is complete; how ever, received data is transferred into a parallel read data buffer so the shifter is free to accept a second serial byte. as long as the first byte is read out of the read data buffer before the next byte is ready to be transferred, no o verrun condition occurs . if overrun occur, spiovf is set. second byte serial data cannot be transferred successfully into the data register during overrun condition and the data register will remains the value of the previous byte. the fi gure below shows the receive data timing waveform when overrun occur.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 156 - revision a 0. 2 data ( n ) progressing data ( n + 1 ) progressing spif data ( n ) data ( n ) spi data register spi shift register data ( n + 2 ) progressing spiovf data ( n + 2 ) data ( n ) receiving data ( n + 1 ) receiving data ( n + 2 ) receiveing if spif is not clear , the spiovf will be set , data ( n ) will be kept . the data ( n + 1 ) will be lost . when data ( n ) is received , the spif will be set . to clear this bit by software . when data ( n + 2 ) is received , the spif will be set . the spi receive data timing waveform figure 18 - 11 : spi overrun timing waveform 18.3.8 lsb first enable by default, this device transfer the spi data most significant bit first. this d evice provides a control bit spcr.lsbfe to allow support of transfer of spi data in least significant bit first. 18.3.9 write collision detection write collision indicates that an attempt was made to write data to the spdr while a transfer was in progress. spdr i s not double buffered in the transmit direction, any writes to spdr cause data to be written directly into the spi shift register. this write corrupts any transfer in progress, a write collision error is generated (wcol will be set). the transfer continues undisturbed, and the write data that caused the error is not written to the shifter. a write collision is normally a slave error because a slave has no control over when a master initiates a transfer. a master knows when a transfer is in progress, so ther e is no reason for a master to generate a write - collision error, although the spi logic can detect write collisions in both master and slave devices. wcol flag is clear by software. 18.3.10 transfer complete interrupt this device consists of an interrupt flag at s pif. this flag will be set upon completion of data transfer with external device, or when a new data have been received and copied to spdr. if interrupt is enable (through espi ) , the spi interrupt request will be generated, if global enable bit ea is also enabled. spif is software clear. 18.3.11 mode fault e rror arises in a multiple - master system when more than one spi device simultaneously tries to be a master. this error is called a mode fault . when the spi system is configured as a master and the / ss input line goes to active low, a mode fault error has occurred ? usually because two devices have attempted to act as master at the same time. in cases where more than one device is concurrently configured as a master, there is a chance of contention between two pin drivers. for push - pull cmos drivers, this contention can cause permanent damage. the mode fault mechanism attempts to protect the device by disabling the drivers. the mstr and spe control bits in the spcr associated with the spi are cleared by hardware and an interrupt is generated subject to masking by the espi control bit . other precautions may need to be taken to prevent driver damage. if two devices are made masters at the same time, mode fault does not help protect either one unless one of them select s the other as
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 157 - revision a 0. 2 slave. the amount of damage possible depends on the length of time both devices attempt to act as master. modf bit is set automatically by spi hardware, if the mstr control bit is set and the slave select input pin becomes 0. this condition is not permitted in normal operation. in the case where /ss is set , it is an output pin rather than being dedicated as the / ss input for the spi system. in this special case, the mode fault function is inhibited and modf remains cleared. this flag is clea red by software. the following shows the sample hardware connection and s/w flow for multi - master/slave environment. it shows how s/w handles mode fault. miso mosi sck /ss i/o port 0 1 2 3 i/o port 0 1 2 3 m i s o m o s i s c k / s s slave mcu 0 master/slave mmcu1 master/slave mmcu2 m i s o m o s i s c k / s s slave mcu 1 m i s o m o s i s c k / s s slave mcu 2 miso mosi sck /ss figure 18 - 12 : spi mult i - master slave environment
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 158 - revision a 0. 2 start configuration (master); mstr = 1, spe = 1 ssoe = 0, drss = 0 s/w should configure spr0-1, cpha, cpol, lsbfe accordingly. spi intr? modf? send data? write spdr spif n n n n y y y y ok to reconfigure? spiovf read spdr n missing data. s/w should take appropriate actions here. y a a mmcu1/2 clear spif flag read spdr clear modf flag y n eg. checking /ss line . configure p0[3:0] to fh (input). missing data. s/w should take appropriate actions here. clear spif & spiovf flag mode fault detected spi overflow figure 18 - 13 : spi multi - master slave s/w flow diagram
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 159 - revision a 0. 2 19 analog - to - digital co nverter the adc contains a digital - to - analog converter ( dac ) that converts t he contents of a successive approximation register to a voltage ( v dac ) , which is compared to the analog input voltage ( vin ). the output of the comparator is then fed back to the successive approximation control logic that controls the successive approximat ion register. this is illustrated in the figure below. dac msb lsb successive approximation register vin + - comparator start ready (stop) successive approximation control logic v dac figure 19 - 1 : successive approximation adc 19.1 operation of adc a conversion can be initiated by software only or by either hard ware or software . the software only start mode is selected when control bit ad c con.5 (ad c ex) =0. a conversion is then started by setting control bit ad c con.3 (adcs) to 1. the hardware or software start mode is selected when ad c con.5 =1, and a conversion m ay be started by setting ad c con.3 = 1 as above or by applying a rising edge to external pin stadc (p4.0) . when a conversion is started by applying a rising edge, a low level must be applied to stadc for at least one machine cycle followed by a high level f or at least one machine cycle. user sets adcs to start converting then adcs remains high while adc is converting signal and will be automatically cleared by hardware when adc conversion is completed. the end of the 10 - bit conversion is flagged by control b it adccon.4 (adci). the upper 8 bits of the result are held in special function register adch, and the two remaining bits are held in adcl . 1 (adc.1) and adcl . 0 (adc.0). the user may ignore the two least significant bits in adcl and use the adc as an 8 - bit converter (8 upper bits in adch). in any event, the total actual conversion time is 50 adc clock input cycles. control bits from adccon.0 to adccon.2 are used to control an analog multiplexer which selects one of eight analog channels. an adc conversion in progress is unaffected by an external or software adc start. the result of a completed conversion remains unaffected provided adci = logic 1 . the result of a completed conversion (adci = logic 1) remains unaffected when entering the idle mode. the devi ce supports maximum 8 analog input ports. 8 analog input ports share the i/o pins from p1.0 to p1.7. these i/o pins are switched to analog input ports by setting the bits of adc input pin select register (ddio) to logic 1.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 160 - revision a 0. 2 10-bits adc block adcps adc.0 adc.9 adci adcs av dd vref+ av ss aadr[2:0] analog input multiplexer | 0 1 p4.0 adcex adcclk[1:0] adc conversion block adcen adcs start conversion adc clock input enable adc 00 01 10 11 fosc/4 fosc/8 fosc/16 reserved p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 adcch.0 adcch.1 adcch.2 adcch.3 adcch.4 adcch.5 adcch.6 adcch.7 fig ure 19 - 2 : adc block diagram 19.2 adc resolution and analog supply the adc circuit has its own supply pins (av dd and av ss ) and one pins (vref+) connected to each end of the dac?s resistance - ladder that the av dd an d vref+ are connected to v dd and av ss is connected to v ss . the ladder has 1023 equally spaced taps, separated by a resistance of ?r?. the first tap is located 0.5 r above av ss , and the last tap is located 0 .5 r below vref+. this gives a total ladder resist ance of 1024 r. this structure ensures that the dac is monotonic and results in a symmetrical quantization error. for input voltages between av ss and [(vref+) + ? lsb], the 10 - bit result of an a/d conversion will be 0000000000b = 000h. for input voltages b etween [(vref+) ? 3/2 lsb] and vref+, the result of a conversion will be 1111111111b = 3ffh. avref+ and av ss may be between av dd + 0.2v and av ss ? 0.2 v. avref+ should be positive with respect to av ss , and the input voltage (vin ) should be between avref+ a nd av ss . the result can always be calculated from the following formula: result = avref vin 1024 ? ? or result = v ss v dd 1024 ?
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 161 - revision a 0. 2 20 lcd display 20.1 lcd f eatures the lcd has the following features ; ? ? selectable lcd frequency by frequency divider . ? ? two operation modes; normal (default) and power saving mode . ? ? 1/3 bias voltage . ? ? two display modes; 1/3 duty or 1/4 duty ? ? segment/com pins: o dedicated 10 s egment pins o segment 10 - 31 share with gpio pins. o dedicated 4 com pins. the device can directly drive a lcd w ith 32 segment outputs pins and 4 or 3 common output pins for a total of 32*4 dots or 32*3 dots by direct lcd pointer (lcdpt) and lcd data (lcddata) mapping. lcd pt can be written by ( mov lcdpt , a). if lcden is set, data written in the lcd data will autom atically display on the lcd pins. lcddata can be written by mov lcddata, a instruction.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 162 - revision a 0. 2 frequency divider (fs[2:0]) com drivers seg drivers lcd data voltage pump a/b lcd controller com3 com2 com1 com0 seg[31:24] / p7[7:0] seg0 vdd vlcd1 vlcd2 vss dh1 dh2 vdd vss to seg and com drivers flcd seg[31:0] flcd fosc flcd com[3:0] duty & bias address bus data bus lcd pointer seg[23:16] / p6[7:0] seg[15:10] / p5[7:2] seg9 figure 20 - 1 : lcd driver block diagram lcd frequency is set by the lcdcn.fs [ 2 :0] register bits . lcden ( lcdcn. 7 ) can enable or disable the lcd by software. if lcden is set, voltage pump supplies voltage to segment and com drivers and lcd panel will be displayed according lcddata. see below section for explanation . when lcden is clear, voltage p ump is turn off and all lcd pins will be output at low . pump (lcdcn. 4 ) can select which voltage pump (type a or b) to drive s egments and c om. default is pump type a which is normal mode, while pump type b is power saving mode. the duty cycle s are selectabl e at lcdcn.5 for 32*4 dots is ? duty and 32*3 dots is 1/3 duty. there is a clear bit (lcdcn.6) for clearing the lcd display and by default it is inactive. upon activating this clear bit the com pin will goes low that will directly clear the lcd display ed . however, when the clea r bit is deactivated again by software , the lcd display will resume previous display prior to clear. 20.2 lcd frequency lcd frequency can be set by fs [ 2 :0] bits . setting a correct frequency according to the lcd panel requirement will get a good contrast. structure of the lcd frequency selection block (flcd) is shown in the following diagram figure 20 - 2 .
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 163 - revision a 0. 2 fosc fs2 fs1 fs0 /1,/2,/4,/8,/16 flcd 14 bits figure 20 - 2 : lcd frequency selec tion block diagram (flcd) fs 2 fs 1 fs0 divider 0 0 0 /1 0 0 1 /2 0 1 0 /4 0 1 1 /8 1 x x /16 table 20 - 1 : divider selection table using fs bits user is free to select any lcd frequency by selecting the d ivider. the lcd frequency can be calculated by following equation: lcd frequency (flcd) = ( fosc /2* 14) x ( d ivider) each common signal is selected sequentially according to the specified number of time slices of its frame period . for example, in 1/3 duty, com0 to com2 will output waveforms, com3 will be tied to low. whereas for 1/ 4 duty, com0 to com3 will output waveform s . refer to the figure below .
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 1 64 - revision a 0. 2 vdd vlcd 2 vlcd 1 vss f f = frame frequency t f = 4 * t 1 / 3 bias , ? duty 1 / 3 bias , 1 / 3 duty vdd vlcd 2 vlcd 1 vss f f = frame frequency t f = 3 * t note : t = one clock period figure 20 - 3 : common signal wa veform the segment signal corresponds to lcd display data memory. each byte of data is read synchronized with com0, com1, com2 and com3 . if the contents of the each bit are 1, that bit is converted to the select voltage. if the contents of the each bit are 0, that bit is converted to the deselect voltage. the conversion results are output to segment pins. refer to the figure below . t note : t = one clock period select deselect common signal segment signal vdd vlcd 2 vlcd 1 vss vdd vlcd 2 vlcd 1 vss figure 20 - 4 : segment signal waveforms
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 165 - revision a 0. 2 com0 ? duty flcd vdd vlcd2 vlcd1 vss vdd vlcd2 vlcd1 vss com1 vdd vlcd2 vlcd1 vss com2 vdd vlcd2 vlcd1 vss com3 figure 20 - 5 : lcd com output pins configured using voltage pump a type with ? dut y .
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 166 - revision a 0. 2 flcd 1/3 duty com0 vdd vlcd2 vlcd1 vss com1 com2 vdd vlcd2 vlcd1 vss vdd vlcd2 vlcd1 vss figure 20 - 6 : lcd com outp ut pins configured using voltage pump a type with 1/3 duty .
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 167 - revision a 0. 2 com0 vdd vlcd2 vlcd1 vss 1/4 duty flcd com1 vdd vlcd2 vlcd1 vss com2 vdd vlcd2 vlcd1 vss vdd vlcd2 vlcd1 vss com3 figure 20 - 7 : lcd com output pins configured using voltage pump b type with ? duty .
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 168 - revision a 0. 2 com0 vdd vlcd2 vlcd1 vss 1/3 duty flcd com1 vdd vlcd2 vlcd1 vss com2 vdd vlcd2 vlcd1 vss figur e 20 - 8 : lcd com output pins configured using voltage pump b type with 1/3 duty. 20.3 lcd power connection the lcd power connection for 1/3 bias is shown figure below. lcd voltage amplification uses regulator type . 3 bias voltages; vdd, vlcd2 = 2/3vdd and vlcd1=1/3vdd.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 169 - revision a 0. 2 dh 1 dh 2 vss vdd vlcd 1 vlcd 2 0 . 1 uf uc 0 . 1 uf 1 / 3 bias figure 20 - 9 : 1/3 bias lcd power connection example output waveform of lcd driving mode in next diagram .
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 170 - revision a 0. 2 vdd vlcd2 vlcd1 vss com0 vdd vlcd2 vlcd1 vss com1 vdd vlcd2 vlcd1 vss com2 vdd vlcd2 vlcd1 vss com3 lcd driver outputs for only seg on com0 side being lit. lcd driver outputs for only seg on com1 side being lit. lcd driver outputs for only seg on com0, com1 side being lit. lcd driver outputs for only seg on com1,com2,com3 side being lit. lcd driver outputs for only seg on com1,com2 side being lit. lcd driver outputs for only seg on com0,com2,com3 side being lit. lcd driver outputs for only seg on com0,1,2,3 side being lit. vdd vlcd2 vlcd1 vss vdd vlcd2 vlcd1 vss vdd vlcd2 vlcd1 vss vdd vlcd2 vlcd1 vss vdd vlcd2 vlcd1 vss vdd vlcd2 vlcd1 vss vdd vlcd2 vlcd1 vss figure 20 - 10 : 1/4 duty, 1/3 bias of lighting system
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 171 - revision a 0. 2 20.4 lcd option bits there are two option bits for lcd, lcd [1:0] for selection of lcd segment pin as per the table below. when option bit lcd [1 :0] = 00 the entire segment pins are active and p5, p6 & p7 cannot work as general purpose i/o. when lcd [1:0] = 01, p6 & p7 can work as general purpose i/o but only seg15~seg0 can be use for lcd display. where as lcd [1:0] = 10, only p7 can work as genera l purpose i/o and seg23~0 is use for lcd display. when lcd [1:0] = 11 only seg9~0 can be use for lcd display. see section 24 for location of these bits. lcd1 lcd0 active 0 0 seg31~0 0 1 p7 & p6 & seg15~0 1 0 p7 & seg23~0 1 1 gpio pin s (p5, p6, p7) 20.5 l cd display each number is control by 4 common pins and 2 segment pins. to display a number, data is written into the lcddata to display out into the lcd panel. there are total of 16 lcd characters pointed by lcdpt. com0 com2 com3 com1 00 01 02 03 10 11 12 13 lcdpt [3:0] seg[31:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh figure 20 - 11 : lcd segment and com mapping
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 172 - revision a 0. 2 seg0 seg1 com0 00 10 com1 01 11 com2 02 12 com3 com2 com1 com0 seg0 seg1 10 01 02 03 00 11 12 13 com3 03 13 figure 20 - 12 : relation of seg [1: 0] and com [3:0] pins. lcdpt[3:0] name bit7 - b it4 bit3 - b it0 0000 lcddata_0 s01c[3:0] s00c[3:0] 0001 lcddata_1 s03c[3:0] s02c[3:0] 00 10 lcddata_2 s05c[3:0] s04c[3:0] 00 11 lcddata_3 s07c[3:0] s06c[3:0] 0 100 lcddata_4 s09c[3:0] s08c[3:0] 0 101 lcddata_5 s11c[3:0] s10c[3:0] 0 110 lcddata_6 s13c[3:0] s12c[3:0] 0 111 lcddata_7 s15c[3:0] s14c[3:0] 1 00 0 lcddata_8 s17c[3:0] s16c[3:0] 1 001 lcddata_9 s19c[3:0] s18c[3:0] 1 0 10 lcddata_10 s21c[3:0] s20c[3:0] 1 0 1 1 lcddata_11 s23c[3:0] s22c[3:0] 11 0 0 lcddata_12 s25c[3:0] s24c[3:0] 11 01 lcddata_13 s27c[3:0] s26c[3:0] 1110 lcddata_14 s29c[3:0] s28c[3:0] 1111 lcddata_15 s31c[3:0] s30c[3:0] table 20 - 2 : registers associated with lcd operation .
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 173 - revision a 0. 2 lcd display lcddata [7 :0] lcd display lcddata [7:0] lcd display lcddata [7:0] 0000 1010b 1111 0110b 1110 1110b 1011 1100b 1000 1010 b 1111 0000b 1001 1110b 1111 1110b 1111 0100b 0100 1110b 1101 1110b 1110 0100b 1101 0110b 1111 1010b 0000 0001b table 20 - 3 : example of writing lcddata example: ; --------- --------------------------------------------------------- ; example writing a number 3 to the lcd display. ; ------------------------------------------------------------------ .chip 8052 .symbols .ramchk off ; ------------------------------------------------ ------------------ lcdcn equ e4h lcdpt equ abh lcddata e qu 86 h ; ------------------------------------------------------------------ org 0000h jmp start ; ------------------------------------------------------------------ org 0100h start: mov lcdcn, #9e h ; enable lcd, duty = 1/4, pump a, freq = 1/16 mov lcdpt, #0ah ; select location to write mov lcddata, #4eh ; number ? 3 ? is display in lcd panel jmp $ ; ------------------------------------------------------------------ end
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 174 - revision a 0. 2 21 timed access protect ion t he w79e217 /217 has features like the watchdog t imer, wait - state control signal and p ower - on/fail reset flag that are crucial to the proper operation of the system. if these features are unprotected, errant code may write critical control bits , resulting in incorrect operation and loss of control. t o prevent this, the w79e217 /217 provides has a timed - access protection scheme that controls write access to critical bits. in this scheme , protected bits have a timed write - enable window. a write is successful onl y if this window is active ; otherwise , the write is discarded. the write - enable window is opened in two steps. first, the software writes aah to the timed access (ta) register. this starts a counter , which expires in three machine cycles. then, i f the soft ware write s 55h to the ta register before the counter expires , the write - enable window is opened for three machine cycles. after three machine cycles, the window automatically closes , and the procedure must be repeated again to access protected bits. the s uggested code for opening the write - enable window is ; ta reg 0c7h ; d efine new register ta, located at 0c7h mov ta, #0aah mov ta, #055h five e xamples , some correct and some incorrect, of using timed - access protection are shown below. example 1: vali d access mov ta, #0aah ; 3 m/c ; note: m/c = machine cycles mov ta, #055h ; 3 m/c mov wdcon, #00h ; 3 m/c example 2: valid access mov ta, #0aah ; 3 m/c mov ta, #055h ; 3 m/c nop ; 1 m/c setb ewt ; 2 m/c example 3: valid access mov ta, #0aah ; 3 m/c mov ta, #055h ; 3 m/c orl wdcon, #00000010b ; 3m /c example 4: invalid access mov ta, #0aah ; 3 m/c mov ta, #055h ; 3 m/c nop ; 1 m/c nop ; 1 m/c clr por ; 2 m/c
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 175 - revision a 0. 2 example 5: invalid access mov ta, #0aah 3 m/c nop 1 m/c mov ta, #055h 3 m/c setb ewt 2 m/c in the first three examples, the protected bits are written before the window closes. in example 4 , however, the writ e occurs after the window has closed, so there is no chang e in the protected bit. in example 5 , the second write to ta occurs four machine cycles after the first write, so the timed access window in not opened at all, and the write to the protected bit fails.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 176 - revision a 0. 2 22 port 4 structure port 4 is a multi - function port tha t performs general purpose i/o port and chip - select strobe signals including read strobe, write strobe and read/write strobe signals. the 4 alternate modes are selected by p4xm1 and p4xm0. the function of chip - select strobe output provides that user can ac tivate external devices by access to some specific address region. p ort 4 c ontrol r egister a bit: 7 6 5 4 3 2 1 0 p41m1 p41m0 p41c1 p41c0 p40m1 p40m0 p40c1 p40c0 mnemonic: p4cona address: 92h p ort 4 c ontrol r egister b bit: 7 6 5 4 3 2 1 0 p43m1 p43 m0 p43c1 p43c0 p42m1 p42m0 p42c1 p42c0 mnemonic: p4conb address: 93h bi t name function p4xm1, p4xm0 port 4 alternate modes. =00 : mode 0. p4.x is a general purpose i/o port which is the same as port 1. =01 : mode 1. p4.x is a read strobe signal for chip select purpose. the address range depends on the sfr p4xah, p4xal and bits p4xc1, p4xc0. =10 : mode 2. p4.x is a write strobe signal for chip select purpose. the address range depends on the sfr p4xah, p4xal and bits p4xc1, p4xc0. =11 : mode 3. p4.x is a rea d/write strobe signal for chip select purpose. the address range depends on the sfr p4xah, p4xal and bits p4xc1, p4xc0 p4xc1, p4xc0 port 4 chip - select mode address comparison: =0 0 : compare the full address (16 bits length) with the base address registers p4xah and p4xal. =01 : compare the 15 high bits (a15 - a1) of address bus with the base address registers p4xah and p4xal. =10 : compare the 14 high bits (a15 - a2) of address bus with the base address registers p4xah and p4xal. =11 : compare the 8 high bits (a1 5 - a8) of address bus with the base address registers p4xah and p4xal. p40ah, p40al: the base address registers for comparator of p4.0. p40ah contains the high - order byte of address; p40al contains the low - order byte of address. p41ah , p41al : the base add ress registers for comparator of p4.1. p41ah contains the high - order byte of address; p41al contains the low - order byte of address. p42ah, p42al: the base address registers for comparator of p4.2. p42ah contains the high - order byte of address; p42al contai ns the low - order byte of address. p43ah, p43al: the base address registers for comparator of p4.3. p43ah contains the high - order byte of address; p43al contains the low - order byte of address.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 177 - revision a 0. 2 port 4 bit: 7 6 5 4 3 2 1 0 - - - - p4.3 p4.2 p4.1 p4.0 mnem onic: p4 address: a5h p4.3 - 0 port 4 is a bi - directional i/o port with internal pull - ups. p ort 4 c hip - select p olarity bit: 7 6 5 4 3 2 1 0 p43inv p42inv p42inv p40inv - pwdnh rmwfp pup0 mnemonic: p4csin address: a2h p4xinv the active polarity of p4.x w hen it is set as a chip - select strobe output . high = active high. low = active low. pwdnh set pwdnh to logic 1 then ale and psen will keep high state, clear this bit to logic 0 then ale and psen will output low during power down mode. rmwfp control read pa th of instruction ? read - modify - write ? . when this bit is set, the read path of executing ? read - modify - write ? instruction is from port pin otherwise from sfr. pup0 enable port 0 weak pull up.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 178 - revision a 0. 2 address bus bit length selectable comparator register p4xal p4xah equal p4.x mux 4->1 p4 register p4.x read write data i/o rd_cs wr_cs rd/wr_cs p4xc0 p4xc1 p4xm0 p4xm1 p4xcsinv p4.x input data bus register pin figure 22 - 1 port 4 structure diagram here is an example to program the p4.0 as a write strobe signal at the i/o port address 1234h ~1237h and positive polarity, and p4.1 ~ p4.3 are used as general i/o ports. mov p40ah , # 12h mov p40al , # 34h ; define t he base i/o address 1234h for p4.0 as an special function mov p4cona , # 00001010b ; define the p4.0 as a write strobe signal pin and the compared address is [a15:a2] mov p4conb , # 00h ; p4.1 ~p4.3 as general i/o port which are the same as port1 mov p4csin , # 10h ; write the p40csinv =1 to inverse the p4.0 write strobe polarity then any instruction writes data to address from 1234h to 1237h, for example movx @dptr,a (with dptr=1234h~1237h) , will generate the positive polarity write strobe signal at pin p 4.0. and the instruction of ? mov p4 , # xx ? will output the bit3 to bit1 of data #xx to pin p4.3~ p4.1.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 179 - revision a 0. 2 23 in - system programmin g 23.1 the loader program l ocates at ldflash m emory cpu is free run at apflash memory. chpcon register had been set #03h value before cp u has entered idle state. cpu will switch to ldflash memory and execute a reset action. h/w reboot mode will switch to ldflash memory, too. set sfrcn register where it locates at user's loader program to update apflash bank 0 or bank 1 memory. set a swrese t (chpcon =#83h) to switch back apflash after cpu has updated apflash program. cpu will restart to run program from reset state. 23.2 the loader program l ocates at apflash m emory cpu is free run at apflash memory. chpcon register had been set #01h value before cpu has entered idle state. set sfrcn register to update ldflash or another bank of apflash program. cpu will continue to run user's apflash program after cpu has updated program. please refer demonstrative code to understand other detail description.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 180 - revision a 0. 2 24 o ption bits this device has two config bits (config0, config1) that must be define at power up and can not be set after the program start of execution. those features are configured through the use of two flash eprom bytes, and the flash eprom can be progra mmed and verified repeatedly. until the code inside the flash eprom is confirmed ok, the code can be protected. the protection of flash eprom and those operations of the configuration bits are described below. 24.1 config0 bit description b0 =0: lock data out b1 =0: movc inhibited b2 reserved b3 reserved b4 =1: disable h/w reboot by p 3 .6 and p 3 .7 =0: enable h/w reboot by p 3 .6 and p 3 .7 b5 =1: disable h/w reboot by p4.3 =0: enable h/w reboot by p4.3 b6 reserved b7 =1: crystal > 24mhz =0: crystal < 24mhz t able 24 - 1 config 0 option bits b0: lock bit this bit is used to protect the customer's program code in the w79e217 /217 . a fter the programmer finishes the programming and verifies sequence b0 can be cleared to logic 0 to protect code from reading by any access path . once this bit is set to logic 0, both the flash eprom data and special setting regis ters can not be accessed again. b1: movc inhibit this bit is used to restrict the accessible region of the movc i nstruction. it can prevent the movc instruction in external program memory from reading the internal program code. when this bit is set to logic 0, a movc instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. a movc instruction in internal program memory space will always be able to access the rom data in both internal and external memory. if this bit is logic 1, there are no restrictions on the movc instruction. b4: h/w reboot with p 3 .6 and p 3 .7 if this bit is set to logic 0, enable to reboot 4k ld flash mode while rst =h, p 3 .6 = l and p 3 .7 = l state. cpu will start from ld flash to update the user?s program. b5: h/w reboot with p4.3 if this bit is set to logic 0, enable to reboot 4 k ld flash mode while rst =h and p4.3 = l state. cpu will start from ld flash to update the user?s program b7: select clock freq u ency. if clock freq u ency is over 24m h z, then set this bit is h. if c lock frequency is less than 24m h z, then clear this bit.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 181 - revision a 0. 2 24.2 co nfig1 b its n ame function bit0 pwmoe pwm odd channel 1, 3 and 5 enable . 1: disable (default). 0: enable odd pwm outputs to corresponding pins. bit1 pwmee pwm even channel 0, 2 and 4 enable . 1: disable (default ) 0: enable odd pwm outputs to corresponding pins. bit2 opol define the polarity of pwm output after cpu reset, opol controls odd pwm outputs . 1: initial output high 0: initial output low bit3 epol define the polarity of pwm output after cpu reset, epol control even pwm outputs . 1: initial output high 0: initial output low bit 4 lcd0 ( r efer lcd config table below ) . bit 5 lcd1 ( r efer lcd config table below ) . bit 6 pwm6e pwm channel 6 output enable . 1: disable (default). 0: enable pwm 6 output to corresponding pin . bit 7 pwm7e pwm channel 7 output enable. 1: disable (default) . 0: enable pwm 7 output to corresponding pin . table 24 - 2 : config 1 option bits lcd 1 lcd 0 lcd pin define 0 0 seg31~0 0 1 p7 & p6 & seg15~0 1 0 p7 & seg23~0 1 1 gpio pin s (p5 , p6, p7) table 24 - 3 : lcd config bits definition table
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 182 - revision a 0. 2 25 electrical character istics 25.1 absolute maximum ratings symbol parameter condition rating unit dc power supply v dd ? v ss - 0.3 +7.0 v input voltage v in v s s - 0.3 v dd +0.3 v operating temperature t a 0 +70 ? c storage temperature t st - 55 +150 ? c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. 25.2 dc c haracteristics (v dd ? v ss = 5v ? 10%, ta = 25 ? c, fosc = 20 mhz, unless otherwise specified.) parameter symbol specification unit test conditions min typ max operating voltage v dd 2.7 5 5.5 v v dd =4.5v ~ 5.5v @ 4 0mhz v dd =2.7v ~ 5.5v @ 20 mhz i dd 1 - 36 50 ma run nop v dd =5.5v at 40mhz i dd 2 28 35 ma v dd =5.5v at 20mhz operating current i dd 3 12 16 ma v dd = 3.0 v at 20mhz i idle 1 - - 35 ma idle mode v dd =5.5v at 40mhz i idle 2 20 ma v dd =5.5v at 20mhz idle current i idle 3 10 ma v dd = 3.0 v at 20mhz power down current i pw dn - - 10 ua power - down mode v dd = 2.7v~5.5v input current p1, p2, p3, p4, p5, p6, p7 i in1 - 50 - +10 ua v dd =5.5v v in =0v or v dd input current rst i in2 - 10 50 +300 ua v dd =5.5v 0 p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 183 - revision a 0. 2 input high voltage p0, p1, p2, p3, p4, p5, p6, p7 ea (schmitt input) v ih1 0.7 v dd - v dd +0. 2 v hysteresis voltage v hy 0.2 v dd v v il2 1 - - 1.6 v dd =4.5v input low voltage rst, v il2 2 - - 0.8 v v dd = 2.7 v v ih2 1 3.5 - v dd +0.2 v dd =5.5v i nput high voltage rst [ *1 ] v ih2 2 2.0 v dd +0.2 v v dd = 2.7 v v il3 1 0 - 0.8 v dd =4.5v input low voltage xtal1 [ * 3 ] v il3 2 0 - 0.4 v v dd = 2.7 v v ih3 1 3.5 - v dd +0.2 v dd =5.5v input high volta ge xtal1 [ * 3 ] v ih3 2 2.0 - v dd +0.2 v v dd = 2.7 v v ol1 1 - 0.9 v dd = 4.5 v, i ol = 20 ma output low voltage p2.0~p2.5, p5.0~p5.1 ( push - pull mode ) v ol1 2 - 0.4 v v dd = 2.7v, i ol = 3.2 ma v ol 21 - 0.5 v dd = 4.5 v, i ol = 4.0 ma output low voltage p0, p1, p2 , p3, p4, p5, p6, p7 ( quasi - bidirectional mode ) v ol 22 - 0.4 v v dd = 2.7v, i ol = 3.0 ma v oh 11 2.4 - v dd = 4.5 v, i oh = - 16 - 20 ma output high voltage p2.0~p2.5, p5.0~p5.1 ( push - pull mode ) v o h 12 1.9 - v v dd = 2.7v, i oh = - 3.2 ma v oh 21 3.2 - v dd = 4.5 v, i oh = - 80 - 100 ua output high voltage p1, p2 , p3, p4, p5, p6, p7 ( quasi - bidirection al mode ) v oh 22 2.1 - v v dd = 2.7v, i oh = - 25 - 30 ua isk 3 1 8 16 v dd =4.5v , vs = 0.45v sink current [ * 2 ] p0, p2 , ale, psen isk 3 2 4.5 9 ma v dd = 2.7 v, v s = 0 .4 5 v isr3 1 - 8 - 14 vdd=4.5v , vs = 2.4v source current [ * 2 ] p0, p2, ale, psen isr3 2 - 3 - - 6 ma v dd = 2.7 v, v s = 2.0 v lcd supply current i lcd - - 6 ua all seg on 0.9 1.2 - m a v dd = 5.0v; v ol = 0.4v seg0 - seg31 sink current(used as lcd output) i ol1 0.7 1.0 v dd = 3.0v; v ol = 0.4v 0.8 1.1 - m a v dd = 5. 0v; v o h = 4 .4v seg0 - seg31 drive current(used as lcd output) i oh1 0.5 0.8 v dd = 3.0v; v o h = 2 .4v notes: *1. rst pin is a schmitt trigger input. rst has internal pull - low resistors about 60k ? . * 2 . p0, p2, ale and / psen are tested in the external access mode. * 3 . xtal1 is a cmos input. * 4 . pins of p1, p2, p3, p4, p5, p6, p7 can source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when vin approximates to 2v.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 184 - revision a 0. 2 25.3 ac c haracteristics t clcl t clcx t chcx t clch t chcl clock note: duty cycle is 50%. 25.3.1 e xterna l c lock c haracteristics parameter symbol min. typ. max. units notes clock high time t chcx 12 - - ns clock low time t clcx 12 - - ns clock rise time t clch - - 10 ns clock fall time t chcl - - 10 ns 25.3.2 ac s pecification (v dd ? v ss = 5v ? 10%, ta = 25 ? c, fo sc = 20 mhz, unless otherwise specified. ) parameter symbol variable clock min. variable clock max. units oscillator frequency 1/t clcl 0 40 1 mhz oscillator frequency 1/t clcl 0 33 2 mhz ale pulse width t lhll 1.5t clcl - 5 ns address valid to ale low t avll 0.5t clcl - 5 ns address hold after ale low t llax1 0.5t clcl - 5 ns address hold after ale low for movx write t llax2 0.5t clcl - 5 ns ale low to valid instruction in t lliv 2.5t clcl - 20 ns ale low to psen low t llpl 0.5t clcl - 5 ns psen pulse width t plph 2.0t clcl - 5 ns psen low to valid instruction in t pliv 2.0t clcl - 20 ns input instruction hold after psen t pxix 0 ns input instruction float after psen t pxiz t clcl - 5 ns port 0 address to valid instr. in t aviv1 3.0 t clcl - 20 ns port 2 address to valid instr. in t aviv2 3.5t clcl - 20 ns psen low to address float t plaz 0 ns data hold after read t rhdx 0 ns data float after read t rhdz t clcl - 5 ns
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 185 - revision a 0. 2 rd low to address float t rlaz 0.5t cl cl - 5 ns note: 1. cpu executes the program stored in the internal apflash at v dd =5.0v 2. cpu executes the program stored in the external memory at v dd =5.0v 25.3.3 movx c haracteristics u sing s tre t ch m emory c ycle parameter symbol variable clock min. variable cl ock max. units strech data access ale pulse width t llhl2 1.5t clcl - 5 2.0t clcl - 5 ns t mcs = 0 t mcs >0 address hold after ale low for movx write t llax2 0.5t clcl - 5 ns rd pulse width t rlrh 2.0t clcl - 5 t mcs - 10 ns t mcs = 0 t mcs >0 wr pulse width t wlwh 2.0t clcl - 5 t mcs - 10 ns t mcs = 0 t mcs >0 rd low to valid data in t rldv 2.0t clcl - 20 t mcs - 20 ns t mcs = 0 t mcs >0 data hold after read t rhdx 0 ns data float after read t rhdz t clcl - 5 2.0t clcl - 5 ns t mcs = 0 t mcs >0 ale low to valid data in t lldv 2.5t clcl - 5 t mcs + 2t clcl - 40 ns t mcs = 0 t mcs >0 port 0 address to valid data in t avdv1 3.0t clcl - 20 2.0t clcl - 5 ns t mcs = 0 t mcs >0 ale low to rd or wr low t llwl 0.5t cl cl - 5 1.5t clcl - 5 0.5t clcl + 5 1.5t clcl + 5 ns t mcs = 0 t mcs >0 port 0 address to rd or wr low t avwl t clcl - 5 2.0t clcl - 5 ns t mcs = 0 t mcs >0 port 2 address to rd or wr low t avwl2 1.5t clcl - 5 2.5t clcl - 5 ns t mcs = 0 t mcs >0 data valid to wr transition t qvwx - 5 1.0t clcl - 5 ns t mcs = 0 t mcs >0 data hold after write t whqx t clcl - 5 2.0t clcl - 5 ns t mcs = 0 t mcs >0 rd low to address float t rlaz 0.5t clcl - 5 ns rd or wr high to ale high t whlh 0 1.0t clcl - 5 10 1.0t clcl + 5 ns t mcs = 0 t mcs >0 note: t mcs is a time period related to the stretch memory cycle selection. the following table shows the time period of t mcs for each selection of the st retch value.
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 186 - revision a 0. 2 m2 m1 m0 movx cycles t mcs 0 0 0 2 machine cycles 0 0 0 1 3 machine cycles 4 t clcl 0 1 0 4 machine cycles 8 t clcl 0 1 1 5 machine cycles 12 t clcl 1 0 0 6 machine cycles 16 t clcl 1 0 1 7 machine cycles 20 t clcl 1 1 0 8 machine cycles 24 t clcl 1 1 1 9 machine cycles 28 t clcl e xplanation of l ogics s ymbols in order to maintain compatibility with the original 8051 family, this device specifies the same parameter for each device, using the same symbols. the explanation of the symbols is as follows. t time a address c clock d input data h logic level high l logic level low i instruction p psen q output data r rd signal v valid w wr signal x no longer a valid state z tri - state 25.4 the adc converter dc electrical characteristics (v dd ? v ss = 3.0~5v ? 10%, t a = - 40~85 ? c, fosc = 20mhz, unless otherwise specified.) specification parameter symbol min. typ. max. unit test conditions analog input avin v ss - 0.2 v dd +0.2 v adc clock adcclk 200khz - 5mhz hz adc block circuit input clock conversion time t c 5 2 t adc 1 us t adc is adc block circuit input clock differential non - linearity dnl - 1 - +1 lsb integral non - linearity inl - 2 - +2 lsb offset error ofe - 1 - + 1 lsb gain error ge - 1 - +1 % absolute voltage error ae - 3 - + 3 lsb notes: 1. t adc : the period time of adc input clock.
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 187 - revision a 0. 2 25.5 i2c bus timing characteristics standard mode i2c bus parameter symbol min. max. unit scl clock frequency f scl 0 100 khz bus free time between a sto p and start condition t buf 4.7 - us hold time (repeated) start condition. after this period, the first clock pulse is generated t hd;sta 4.0 - us low period of the scl clock t low 4.7 - us high period of the scl clock t high 4.0 - us set - up time for a rep eated start condition t su;sta 4.7 - us data hold time t hd;dat 5.0 - us data set - up time t su;dat 250 - ns rise time of both sda and scl signals t r - 1000 ns fall time of both sda and scl signals t f - 300 ns set - up time for stop condition t su;sto 4.0 - us capacitive load for each bus line c b - 400 pf t buf stop sda scl start t hd ; sta t low t hd ; dat t high t f t su ; dat repeated start t su ; sta t su ; sto stop t r figure 25 - 1 : i2c bus timing
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 188 - revision a 0. 2 25.6 p rogram m emory r ead c ycle t llax1 t pxiz t plaz t llpl t pxix t pliv t aviv2 t aviv1 t plph t avll address a8-a15 address a8-a15 address a0-a7 instruction in address a0-a7 port 2 port 0 psen ale t lliv t lhll 25.7 d ata m emory r ead c ycle t avll t avwl1 t llax1 t whlh t rldv t rlrh t rlaz t rhdz t rhdx t avdv2 t avdv1 t llwl address a8-a15 address a0-a7 instruction in data in address a0-a7 port 2 port 0 psen rd ale t lldv
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 189 - revision a 0. 2 25.8 d ata m emo ry w rite c ycle t avll t avwl1 t llax2 t whlh t wlwh t qvwx t whqx t avdv2 t llwl address a8-a15 address a0-a7 instruction in data out address a0-a7 port 2 port 0 psen wr ale
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 190 - revision a 0. 2 26 typical application circuits 26.1 expanded external program memory and crystal vcc vcc ad13 a15 a5 ad3 ad5 ad7 ad4 ad4 a3 a11 a1 ad0 a6 ad5 ad1 ad3 a12 ad1 a2 ad1 a7 a2 ad5 ad6 a5 ad14 ad0 ad10 ad2 ad0 a13 a8 a3 a6 ad15 ad2 ad7 ad11 ad2 a9 ad9 ad6 a7 a14 ad4 a4 ad8 a0 ad6 ad7 ad3 a10 ad12 a0 a1 a4 pin-diagram of standard 8051 ea/vp x1 x2 reset int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd wr psen ale/p txd rxd 74f373 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 8.2k c2 c1 crystal 27512 a0 10 a1 9 a2 8 a3 7 a4 6 a5 5 a6 4 a7 3 a8 25 a9 24 a10 21 a11 23 a12 2 a13 26 a14 27 a15 1 ce 20 oe 22 o0 11 o1 12 o2 13 o3 15 o4 16 o5 17 o6 18 o7 19 10u r figure 26 - 1 : typical external program memory and crystal connections crystal c1 c2 r 16 mhz 20p 20p - 24 mhz 12p 12p - 33 mhz 10p 10p 3.3k 40 mhz 1p 1p 3.3k the above table shows the reference values for crystal applications. note: c1, c2, r components refer to figure above. 26.2 expanded external d ata memory and oscillator vcc vcc vcc oscillator ad0 ad3 ad3 a10 a4 ad5 a6 ad4 a1 ad1 a11 a5 a0 ad4 ad7 ad9 ad7 a7 ad6 ad12 a2 ad1 ad7 ad2 a6 ad5 a12 ad6 a8 a1 ad6 ad1 a3 ad0 ad14 ad10 a13 ad3 a2 a7 ad0 ad5 a4 a9 ad8 ad4 a14 a3 ad2 ad13 a5 ad11 a0 ad2 20256 cs 20 oe 22 we 27 i/o0 11 i/o1 12 i/o2 13 i/o3 15 i/o4 16 i/o5 17 i/o6 18 i/o7 19 a0 10 a1 9 a2 8 a3 7 a4 6 a5 5 a6 4 a7 3 a8 25 a9 24 a10 21 a11 23 a12 2 a13 26 a14 1 vcc 28 pin-diagram of standard 8051 ea/vp x1 x2 reset int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd wr psen ale/p txd rxd 74f373 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 10u 8.2k figure 26 - 2 : typical external data memory and oscillator connections
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 191 - revision a 0. 2 27 package dimension 27.1 100l qfp ( 14x20x2.75mm footprint 4.8mm) e h y a a2 seating plane l l 1 see detail f ? a1 e d h d e b c 0.10 0 7 0 0.004 2.40 1.40 19. 0 0 1.20 18.80 1.00 18. 6 0 0.064 0.055 0.9 84 0.7 48 0.047 0.976 0.740 0.039 0.969 0. 732 0.65 20.10 14.10 0.20 0.40 2.90 20.00 14.00 ----- 19.90 13.90 0.10 0.20 2.50 0.791 0.555 0.008 0.016 0.114 0.787 0.551 ----- 0.026 0.783 0.547 0.004 0.008 0.098 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.012 0.006 0.15 0.30 24. 6 0 24.80 25. 0 0 7 0.020 0.032 0.498 0.802 0.01 0.004 0 .020 0.50 ? controlling dimension : millimeters
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 192 - revision a 0. 2 28 application note in - system programming software examples this appl ication note illustrates the in - system progra mmability of the winbond w79e217 /217 flash ep rom microcontroller. in this example, microcontroller will boot from apflash bank and waiting for a key to enter in - system programming mode for re - programming the con tents of 64 kb apflash. while entering in - system programming mode, microcontroller executes the loader program in 4kb ldflash bank. the loader program erases the 64 kb apflash then reads the new code data from external sram buffer (or through other interfa ces) to update the apflash. if the customer uses the reboot mode to update his program, please enable this b3 or b4 of security bits from the writer. please refer security bits for detail description. example 1: ;**************************************** *************************************************************************** ;* example of apflash program: program will scan the p1.0. if p1.0 = 0, enters in - system ;* programming mode for updating the content of apflash code else executes the current rom code. ;* xtal = 24 mhz ;******************************************************************************************************************* .chip 8052 .ramchk off .symbols chpcon equ 9fh ta equ c7h sfral equ ach sfrah equ adh sfrfd equ aeh sfrcn equ afh org 0h ljmp 100h ; jump to main program ;************************************************************************ ;* timer0 service vector org = 000bh ;******************************************************** **************** org 00bh clr tr0 ; tr0 = 0, stop timer0 mov tl0, r6 mov th0,r7 reti ;************************************************************************ ;* apflash main program ;********************************************** ************************** org 100h main_ apflash : mov a, p1 ; scan p1.0
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 193 - revision a 0. 2 anl a, # 01h cjne a, # 01h , program _ apflash ; if p1.0 = 0, enter in - system programming mode jmp normal _mode program_64: mov ta , #aah ; chpcon register is written protect by ta r egister. mov ta , #55h mov chpcon , #03h ; chpcon = 03h, enter in - system programming mode mov sfrcn , #0h mov tcon , #00h ; tr = 0 timer0 stop mov ip , #00h ; ip = 00h mov ie , #82h ; timer0 interrupt enable for wake - up from idle mode mov r6 , #f0h ; tl0 = f0h mov r7 , #ffh ; th0 = ffh mov tl0 , r6 mov th0 , r7 mov tmod , #01h ; tmod = 01h, set timer0 a 16 - bit timer mov tcon , #10h ; tcon = 10h, tr0 = 1 , go mov pcon , #01h ; enter idle mode for launching the in - system programmin g ;************** ****************************************************************** ;* normal mode apflash b apflash program: depending user's application ;******************************************************************************** normal_mode: . ; user's application program . . . example 2: ;******************************************************************************************************************** ********* ;* example of 4kb ldflash program: this loader program w ill erase the apflash b apflash first, then reads the new ;* code from external sram and program them into apflash b apflash bank. xtal = 24 mhz ;**************************************************************************************************************** **** ********* .chip 8052 .ramchk off .symbols chpcon equ 9fh ta equ c7h sfral equ ach
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 194 - revision a 0. 2 sfrah equ adh sfrfd equ aeh sfrcn equ afh org 000h ljmp 100h ; jump to main program ;*************************************************************** ********* ;* 1. timer0 service vector org = 0bh ;************************************************************************ org 000b clr tr0 ; tr0 = 0, stop timer0 mov tl0 , r6 mov th0 , r7 reti ;*************************************************** ********************* ;* 4kb ldflash main program ;***************************************** ******************************* org 100h main_4k: mov ta, # aah mov ta, # 55h mov chpcon, # 03h ; chpcon = 03h, enable in - system programming. mov sfrcn, # 0h mov tcon, # 00h ; tcon = 00h, tr = 0 timer0 stop mov tmod, # 01h ; tmod = 01h, set timer0 a 16bit timer mov ip, # 00h ; ip = 00h mov ie, # 82h ; ie = 82h, timer0 interrupt enabled mov r6, # f0h mov r7, # ffh mov tl0, r6 mov th0, r7 mov tcon, # 10h ; tcon = 10h, tr0 = 1, go mov pcon, # 01h ; enter idle mode update_ apflash : mov tcon, # 00h ; tcon = 00h, tr = 0 tim0 stop mov ip, # 00h ; ip = 00h mov ie, # 82h ; ie = 82h, timer0 interrupt enabled mov tmod, # 01h ; tmod = 01h, mode1 m ov r6,#d0h ; set wake - up time for erase operation, about 15 ms depending on user's system clock rate. mov r7, # 8ah
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 195 - revision a 0. 2 mov tl0, r6 mov th0, r7 erase_p_4k: mov sfrcn, # 22h ; sfrcn = 22h, erase apflash apflash0 ; sfrcn = a2h, erase apflash 1 mov tcon, # 10h ; tcon = 10h, tr0 = 1 , go mov pcon, # 01h ; enter idle mode (for erase operation) ;********************************************************************* ;* blank check ;************************************ ********************************* mov sfrcn, # 0h ; sfrcn = 00h, read apflash b apflash0 ; sfrcn = 80h, read apflash b apflash1 mov sfrah, # 0h ; start address = 0h mov sfral, # 0h mov r6, # fdh ; set timer f or read operation, about 1.5 ? s. mov r7, # ffh mov tl0, r6 mov th0, r7 blank_check_loop: setb tr0 ; e nable timer 0 mov pcon, # 01h ; e nter idle mode mov a, sfrfd ; r ead one byte cjne a, # ffh , blank _check_error inc sfral ; n ext address mov a, sfra l jnz blank_check_loop inc sfrah mov a, sfrah cjne a, # 0h , blank _check_loop ; e nd address = ffffh jmp program _ apflash rom blank_check_error: jmp $ ;******************************************************************************* ;* re - programming apflash b apflash bank ;******************************************************************************* program_ apflash rom: mov r2, #00h ; target low byte address mov r1, #00h ; target high byte address mov dptr, #0h
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 196 - revision a 0. 2 mov sfrah, r1 ; sfrah, targ et high address mov sfrcn, #21h ; sfrcn = 21h, program apflash 0 ; sfrcn = a1h, program apflash 1 mov r6, #9ch ; set timer for programming, about 50 ? s. mov r7, #ffh mov tl0, r6 mov th0, r7 prog_d_ apflash : mov sfral, r2 ; sfral = low by te address call get_byte_from_pc_to_acc ; this pr ogram is based on user?s circuit. mov @dptr, a ; save data into sram to verify code. mov sfrfd, a ; sfrfd = data in mov tcon, #10h ; tcon = 10h, tr0 = 1,go mov pcon, #01h ; enter idle m ode (prorgamming) inc dptr inc r2 cjne r2, #0h, prog_d_ apflash inc r1 mov sfrah, r1 cjne r1, #0h, prog_d_ apflash ;***************************************************************************** ; * verify apflash b apflash bank ;************ ***************************************************************** mov r4, #03h ; error counter mov r6, #fdh ; set timer for read verify, about 1.5 ? s. mov r7, #ffh mov tl0, r6 mov th0, r7 mov dptr, #0h ; the start address of sample code mov r2, #0h ; target low byte address mov r1, #0h ; target high byte address mov sfrah, r1 ; sfrah, target high address mov sfrcn, #00h ; sfrcn = 00h, read apflash0 ; sfrcn = 80h, read apflash1 read_verify_ a pflash : mov sfral,r2 ; sfral = low address mov tcon,#10h ; tcon = 10h, tr0 = 1,go mov pcon,#01h inc r2 movx a,@dptr inc dptr
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 197 - revision a 0. 2 cjne a,sfrfd,error_ apflash cjne r2,#0h,read_verify_ apflash inc r1 mov sfrah,r1 cjne r1,#0h,read_verify_ apflash ;****************************************************************************** ;* programming completly, software reset cpu ;****************************************************************************** mov ta, #aah mov ta, #55h mov chpcon, #83h ; software reset. cpu will restart from apflash0 error_ apflash : djnz r4, update_ apflash ; if error occurs, repeat 3 times. . ; in - syst programming fail, user's process to deal with it. . . .
preliminary W79E217A/21 6 a data sheet publication release date: december , 20 06 - 198 - revision a 0. 2 29 revi sion history revi sion date page description
p reliminary w79e217 a/21 6 a data sheet publicati on release date: december , 20 06 - 199 - revision a 0. 2 important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully i ndemnify winbond for any damages resulting from such improper use or sales.

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