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functional block diagram calibration memory and controller 2.5v reference av dd agnd dv dd clkin convst busy c ref2 c ref1 ref in / ref out ain(? ain(+) dgnd db11?b0 wr hben rd cs parallel interface/control register ad7854/ad7854l charge redistribution dac t/h comp sar + adc control buf rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 3 v to 5 v single supply, 200 ksps 12-bit sampling adcs ad7854/ad7854l features specified for v dd of 3 v to 5.5 v read-only operation ad7854?00 ksps; ad7854l?00 ksps system and self-calibration low power normal operation ad7854: 15 mw (v dd = 3 v) ad7854l: 5.5 mw (v dd = 3 v) automatic power-down after conversion (25 w) ad7854: 1.3 mw 10 ksps ad7854l: 650 w 10 ksps flexible parallel interface 12-bit parallel/8-bit parallel (ad7854) 28-lead dip, soic and ssop packages (ad7854) applications battery-powered systems (personal digital assistants, medical instruments, mobile communications) pen computers instrumentation and control systems high speed modems product highlights 1. operation with either 3 v or 5 v power supplies. 2. flexible power management options including automatic power-down after conversion. by using the power manage- ment options a superior power performance at slower throughput rates can be achieved: ad7854: 1 mw typ @ 10 ksps ad7854l: 1 mw typ @ 20 ksps 3. operates with reference voltages from 1.2 v to av dd . 4. analog input ranges from 0 v to av dd . 5. self-calibration and system calibration. 6. versatile parallel i/o port. 7. lower power version ad7854l. general description the ad7854/ad7854l is a high speed, low power, 12-bit adc that operates from a single 3 v or 5 v power supply, the ad7854 being optimized for speed and the ad7854l for low power. the adc powers up with a set of default conditions at which time it can be operated as a read-only adc. the adc contains self-calibration and system calibration options to en- sure accurate operation over time and temperature and has a number of power-down options for low power applications. the ad7854 is capable of 200 khz throughput rate while the ad7854l is capable of 100 khz throughput rate. the input track-and-hold acquires a signal in 500 ns and features a pseudo- differential sampling scheme. the ad7854 and ad7854l input voltage range is 0 to v ref (unipolar) and Cv ref /2 to +v ref /2, centered at v ref /2 (bipolar). the coding is straight binary in unipolar mode and twos complement in bipolar mode. input signal range is to the supply and the part is capable of convert- ing full-power signals to 100 khz. cmos construction ensures low power dissipation of typically 5.4 mw for normal operation and 3.6 w in power-down mode. the part is available in 28-lead, 0.6 inch wide dual-in-line pack- age (dip), 28-lead small outline (soic) and 28-lead small shrink outline (ssop) packages. see page 27 for data sheet index. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ?analog devices, inc., 2000
parameter a version 1 b version 1 s version 1 units test conditions/comments dynamic performance signal to noise + distortion ratio 3 70 71 70 db min typically snr is 72 db (snr) v in = 10 khz sine wave, f sample = 200 khz (l version: f sample = 100 khz @ f clkin = 2 mhz) total harmonic distortion (thd) e78 e78 e78 db max v in = 10 khz sine wave, f sample = 200 khz (l version: f sample = 100 khz @ f clkin = 2 mhz) peak harmonic or spurious noise e78 e78 e78 db max v in = 10 khz sine wave, f sample = 200 khz (l version: f sample = 100 khz @ f clkin = 2 mhz) intermodulation distortion (imd) second order terms e78 e78 e78 db typ fa = 9.983 khz, fb = 10.05 khz, f sample = 200 khz (l version: f sample = 100 khz @ f clkin = 2 mhz) third order terms e78 e78 e78 db typ fa = 9.983 khz, fb = 10.05 khz, f sample = 200 khz (l version: f sample = 100 khz @ f clkin = 2 mhz) dc accuracy resolution 12 12 12 bits integral nonlinearity 1 0.5 1 lsb max 5 v reference v dd = 5 v differential nonlinearity 1 1 1 lsb max guaranteed no missed codes to 12 bits unipolar offset error 3 3 4 lsb max 2 2 2 lsb typ unipolar gain error 4 4 4 lsb max 2 2 2 lsb typ bipolar positive full-scale error 4 4 5 lsb max 2 2 2 lsb typ negative full-scale error 4 4 5 lsb max 2 2 2 lsb typ bipolar zero error 4 4 5 lsb max analog input input voltage ranges 0 to v ref 0 to v ref 0 to v ref volts i.e., ain(+) e ain(e) = 0 to v ref , ain(e) can be biased up but ain(+) cannot go below ain(e). v ref /2 v ref /2 v ref /2 volts i.e., ain(+) e ain(e) = ev ref /2 to +v ref /2, ain(e) should be biased to +v ref /2 and ain(+) can go below ain(e) but cannot go below 0 v. leakage current 1 1 1 a max input capacitance 20 20 20 pf typ reference input/output ref in input voltage range 2.3/v dd 2.3/v dd 2.3/v dd v min/max functional from 1.2 v input impedance 150 150 150 k typ ref out output voltage 2.3/2.75 2.3/2.7 2.3/2.7 v min/max ref out tempco 20 20 20 ppm/ c typ logic inputs input high voltage, v inh 3 3 3 v min av dd = dv dd = 4.5 v to 5.5 v 2.1 2.1 2.1 v min av dd = dv dd = 3.0 v to 3.6 v input low voltage, v inl 0.4 0.4 0.4 v max av dd = dv dd = 4.5 v to 5.5 v 0.6 0.6 0.6 v max av dd = dv dd = 3.0 v to 3.6 v input current, i in 10 10 10 a max typically 10 na, v in = 0 v or v dd input capacitance, c in 4 10 10 10 pf max logic outputs output high voltage, v oh i source = 200 a 4 4 4 v min av dd = dv dd = 4.5 v to 5.5 v 2.4 2.4 2.4 v min av dd = dv dd = 3.0 v to 3.6 v output low voltage, v ol 0.4 0.4 0.4 v max i sink = 0.8 ma floating-state leakage current 10 10 10 a max floating-state output capacitance 4 10 10 10 pf max output coding straight (natural) binary unipolar input range twos complement bipolar input range conversion rate t clkin 18 conversion time 4.6 (10) 4.6 (9) 4.6 (9) s max (l versions only, 0 c to +70 c, 1.8 mhz clkin) track/hold acquisition time 0.5 (1) 0.5 (1) 0.5 (1) s min (l versions only, e40 c to +85 c, 1 mhz clkin) ad7854/ad7854lespecifications 1, 2 (av dd = dv dd = +3.0 v to +5.5 v, ref in /ref out = 2.5 v external reference, f clkin = 4 mhz (for l version: 1.8 mhz (0 c to +70 c) and 1 mhz (e40 c to +85 c)); f sample = 200 khz (ad7854), 100 khz (ad7854l); t a = t min to t max , unless otherwise noted.) specifications in () apply to the ad7854l. e2e rev. b
parameter a version 1 b version 1 s version 1 units test conditions/comments power requirements av dd, dv dd +3.0/+5.5 +3.0/+5.5 +3.0/+5.5 v min/max i dd normal mode 5 5.5 (1.8) 5.5 (1.8) 6 (1.8) ma max av dd = dv dd = 4.5 v to 5.5 v. typically 4.5 ma (1.5 ma); 5.5 (1.8) 5.5 (1.8) 6 (1.8) ma max av dd = dv dd = 3.0 v to 3.6 v. typically 4.0 ma (1.5 ma). sleep mode 6 with external clock on 10 10 10 a typ full power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 0. 400 400 400 a typ partial power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 1. with external clock off 5 5 5 a max typically 1 a. full power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 0. 200 200 200 a typ partial power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 1. normal mode power dissipation 30 (10) 30 (10) 30 (10) mw max v dd = 5.5 v: typically 25 mw (8) 20 (6.5) 20 (6.5) 20 (6.5) mw max v dd = 3.6 v: typically 15 mw (5.4) sleep mode power dissipation with external clock on 55 55 55 w typ v dd = 5.5 v 36 36 36 w typ v dd = 3.6 v with external clock off 27.5 27.5 27.5 w max v dd = 5.5 v: typically 5.5 w 18 18 18 w max v dd = 3.6 v: typically 3.6 w system calibration offset calibration span 7 +0.05 v ref /e0.05 v ref v max/min allowable offset voltage span for calibration gain calibration span 7 +0.025 v ref /e0.025 v ref v max/min allowable full-scale voltage span for calibration notes 1 temperature ranges as follows: a, b versions, e40 c to +85 c; s version, e55 c to +125 c. 2 specifications apply after calibration. 3 not production tested. guaranteed by characterization at initial product release. 4 sample tested @ +25 c to ensure compliance. 5 all digital inputs @ dgnd except for convst convst o s o s o s
ad7854/ad7854l e4e rev. b limit at t min , t max (a, b, s versions) parameter 5 v 3 v units description f clkin 2 500 500 khz min master clock frequency 4 4 mhz max 1.8 1.8 mhz max l version t 1 3 100 100 ns min convst convst t c c rd rd cs rd cs rd rd rd rd wr wr cs wr cs wr wr wr wr cs t rtr v convst convst
ad7854/ad7854l rev. b e5e ordering guide linearity power temperature error dissipation package model range 1 (lsb) (mw) option 2 ad7854aq e40 c to +85 c 1 15 q-28 ad7854sq e55 c to +125 c 1 15 q-28 ad7854ar e40 c to +85 c 1 15 r-28 ad7854br e40 c to +85 c 1/2 15 r-28 ad7854ars e40 c to +85 c 1 15 rs-28 ad7854laq 3 e40 c to +85 c 1 5.5 q-28 ad7854lar 3 e40 c to +85 c 1 5.5 r-28 ad7854lars 3 e40 c to +85 c 1 5.5 rs-28 eval-ad7854cb 4 eval-control board 5 notes 1 linearity error refers to the integral linearity error. 2 q = cerdip; r = soic; rs = ssop. 3 l signifies the low power version. 4 this can be used as a stand-alone evaluation board or in conjunction with the eval-control board for evaluation/demonstration purposes. 5 this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in the cb designator. for more information on analog devices products and evaluation boards visit our world wide web home page at http://www.analog.com. to output pin +2.1v i oh 1.6ma 200a i ol c l 50pf figure 1. load circuit for digital output timing specifications absolute maximum ratings 1 (t a = +25 c unless otherwise noted) av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +7 v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +7 v av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +0.3 v analog input voltage to agnd . . . . e0.3 v to av dd + 0.3 v digital input voltage to dgnd . . . . e0.3 v to dv dd + 0.3 v digital output voltage to dgnd . . . e0.3 v to dv dd + 0.3 v ref in /ref out to agnd . . . . . . . . . e0.3 v to av dd + 0.3 v input current to any pin except supplies 2 . . . . . . . . . 10 ma operating temperature range commercial (a, b versions) . . . . . . . . . . . e40 c to +85 c commercial (s version) . . . . . . . . . . . . . . e55 c to +125 c storage temperature range . . . . . . . . . . . e65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c cerdip package, power dissipation . . . . . . . . . . . . . . 450 mw ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . 75 c/w lead temperature, (soldering, 10 secs) . . . . . . . . . +300 c soic, ssop package, power dissipation . . . . . . . . . 450 mw ja thermal impedance . . . 75 c/w (soic) 115 c/w (ssop) jc thermal impedance . . . 25 c/w (soic) 35 c/w (ssop) lead temperature, soldering vapor phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . +220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latchup. pin configuration for dip, soic and ssop 14 13 12 11 10 9 8 1 2 3 4 7 6 5 top view (not to scale) 17 16 15 20 19 18 28 27 26 25 24 23 22 21 ad7854 db10 db11 clkin busy dv dd dgnd db9 ref in /ref out av dd agnd c ref1 c ref2 ain(+) db6 db7 db8 ain( e ) hben db0 db1 db5 db2 db3 db4
ad7854/ad7854l e 6 e rev. b pin function descriptions pin mnemonic description 1 convst wr cs rd cs cs c c cs rd wr cs rd n convst
ad7854/ad7854l rev. b e 7 e total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7854/ad7854l, it is defined as: thd ( db ) 20 log ( v 2 2 v 3 2 v 4 2 v 5 2 v 6 2 ) v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa fb), while the third order terms include (2fa + fb), (2fa fb), (fa + 2fb) and (fa 2fb). testing is performed using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in fre- quency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the end- points of the transfer function are zero scale, a point 1/2 lsb below the first code transition, and full scale, a point 1/2 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. unipolar offset error this is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal ain(+) voltage (ain( ) + 1/2 lsb) when operating in the unipolar mode. unipolar gain error this is the deviation of the last code transition (111 . . . 110 to 111 . . . 111) from the ideal, i.e., ain( ) +v ref /2 1.5 lsb, after the unipolar offset error has been adjusted out. bipolar positive full-scale error this applies to the bipolar modes only and is the deviation of the last code transition from the ideal ain(+) voltage. for bipolar mode, the ideal ain(+) voltage is (ain( ) +v ref /2 1.5 lsb). negative full-scale error this applies to the bipolar mode only and is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal ain(+) voltage (ain( ) v ref /2 + 0.5 lsb). bipolar zero error this is the deviation of the midscale transition (all 0s to all 1s) from the ideal ain(+) voltage (ain( ) 1/2 lsb). track/hold acquisition time the track/hold amplifier returns into track mode and the end of conversion. track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion. signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental sig- nals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantiza- tion noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to ( noise + distortion ) = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74 db.
ad7854/ad7854l e 8 e rev. b ad7854/ad7854l on-chip registers the ad7854/ad7854l powers up with a set of default conditions, and the user need not ever write to the device. in this case the ad7854/ad7854l will operate as a read-only adc. the wr pin should be tied to dv dd for operating the ad7854/ad7854l as a read-only adc. extra features and flexibility such as performing different power-down options, different types of calibrations including syste m cali- bration, and software conversion start can be selected by writing to the part. the ad7854/ad7854l contains a control register, adc output data register, status register, test register and 10 calibra- tion registers . the control register is write-only, the adc output data register and the status register are read-only, and the test and calibration registers are both read/write registers. the test register is used for testing the part and should not be written t o. addressing the on-chip registers writing to write to the ad7854/ad7854l, a 16-bit word of data must be transferred. this transfer consists of two 8-bit writes. the firs t 8 bits of data that are written must consist of the 8 lsbs of the 16-bit word and the second 8 bits that are written must consist of the 8 msbs of the 16-bit word. for each of these 8-bit writes, the data is placed on pins db0 to db7, pin db0 being the lsb of eac h transfer and pin db7 being the msb of each transfer. the two msbs of the 16-bit word, addr1 and addr0, are decoded to determine which register is addressed, and the 14 lsbs are written to the addressed regist er. table i shows the decoding of the address bits, while figure 2 shows the overall write register hierarchy. table i. write register addressing addr1 addr0 comment 0 0 this combination does not address any register. 0 1 this combination addresses the test register . the 14 lsbs of data are written to the test register. 1 0 this combination addresses the calibration register . the 14 least significant data bits are writ- ten to the selected calibration register. 1 1 this combination addresses the control register . the 14 least significant data bits are written to the control register. reading to read from the various registers the user must first write to bits 6 and 7 in the control register, rdslt0 and rdslt1. these bits are decoded to determine which register is addressed during a read operation. table ii shows the decoding of the read addr ess bits while figure 3 shows the overall read register hierarchy. the power-up status of these bits is 00 so that the default read will be from the adc output data register. note: when reading from the calibration registers, the low byte must always be read first. once the read selection bits are set in the control register all subsequent read operations that follow are from the selected r egister until the read selection bits are changed in the control register. table ii. read register addressing rdslt1 rdslt0 comment 0 0 all successive read operations are from the adc output data register . this is the default power- up setting. there is always four leading zeros when reading from the adc output data register. 0 1 all successive read operations are from the test register . 1 0 all successive read operations are from the calibration registers . 1 1 all successive read operations are from the status register . test register calibration registers control register addr1, addr0 decode 01 10 11 gain(1) offset(1) dac(8) gain(1) offset(1) offset(1) gain(1) calslt1, calslt0 decode 00 01 10 11 figure 2. write register hierarchy/address decoding test register calibration registers control register rdslt1, rdslt0 decode 01 10 11 gain(1) offset(1) dac(8) gain(1) offset(1) offset(1) gain(1) calslt1, calslt0 decode 00 01 10 11 adc output data register 00 figure 3. read register hierarchy/address decoding
ad7854/ad7854l rev. b e 9 e control register the arrangement of the control register is shown below. the control register is a write only register and contains 14 bits of data. the control register is selected by putting two 1s in addr1 and addr0. the function of the bits in the control register is described below. the power-up status of all bits is 0. msb zero zero zero zero pmgt1 pmgt0 rdslt1 rdslt0 amode convst calmd calslt1 calslt0 stcal lsb control register bit function description bit mnemonic comment 13 zero these four bits must be set to 0 when writing to the control register. 12 zero 11 zero 10 zero 9 pmgt1 power management bits. these two bits are used for putting the part into various power-down modes 8 pmgt0 (see power-down section for more details). 7 rdslt1 theses two bits determine which register is addressed for the read operations. see table ii. 6 rdslt0 5 amode analog mode bit. this pin allows two different analog input ranges to be selected. a logic 0 in this bit position selects range 0 to v ref (i.e., ain(+) ain( ) = 0 to v ref ). in this range ain(+) cannot go below ain( ) and ain( ) cannot go below agnd and data coding is straight binary. a logic 1 in this bit position selects range v ref /2 to +v ref /2 (i.e., ain(+) ain( ) = v ref /2 to +v ref /2). ain(+) cannot go below agnd, so for this range, ain( ) needs to be biased to at least +v ref /2 to allow ain(+) to go as low as ain( ) v ref /2 v. data coding is twos complement for this range. 4 convst conversion start bit. a logic one in this bit position starts a single conversion, and this bit is automati- cally reset to 0 at the end of conversion. this bit may also used in conjunction with system calibration (see calibration section). 3 calmd calibration mode bit. a 0 here selects self-calibration and a 1 selects a system calibration (see table iii). 2 calslt1 calibration selection bits and start calibration bit. these bits have two functions. 1 calslt0 with the stcal bit set to 1, the calslt1 and calslt0 bits determine the type of calibration per- 0 stcal formed by the part (see table iii). the stcal bit is automatically reset to 0 at the end of calibration. with the stcal bit set to 0, the calslt1 and calslt0 bits are decoded to address the calibration register for read/write of calibration coefficients (see section on the calibration registers for more details). table iii. calibration selection calmd calslt1 calslt0 calibration type 00 0 a full internal calibration is initiated. first the internal dac is calibrated, then the internal gain error and finally the internal offset error are removed. this is the default setting. 0 0 1 first the internal gain error is removed, then the internal offset error is removed. 0 1 0 the internal offset error only is calibrated out. 0 1 1 the internal gain error only is calibrated out. 10 0 a full system calibration is initiated. first the internal dac is calibrated, followed by the system gain error calibration, and finally the system offset error calibration. 1 0 1 first the system gain error is calibrated out followed by the system offset error . 1 1 0 the system offset error only is removed. 1 1 1 the system gain error only is removed.
ad7854/ad7854l e 10 e rev. b status register the arrangement of the status register is shown below. the status register is a read-only register and contains 16 bits of data . the status register is selected by writing to the control register and putting two 1s in rdslt1 and rdslt0. the function of the bit s in the status register are described below. the power-up status of all bits is 0. start read status register write to control register setting rdslt0 = rdslt1 = 1 figure 4. flowchart for reading the status register msb zero zero zero zero zero zero pmgt1 pmgt0 one one amode busy calmd calslt1 calslt0 stcal lsb status register bit function description bit mnemonic comment 15 zero these six bits are always 0. 14 zero 13 zero 12 zero 11 zero 10 zero 9 pmgt1 power management bits. these bits will indicate if the part is in a power-down mode or not. see table vi 8 pmgt0 in power-down section for description. 7 one both these bits are always 1. 6 one 5 amode analog mode bit. when this bit is a 0, the device is set up for the unipolar analog input range. when this bit is a 1, the device is set up for the bipolar analog input range. 4 busy conversion/calibration busy bit. when this bit is 1, this indicates that there is a conversion or calibration in progress. when this bit is 0, there is no conversion or calibration in progress. 3 calmd calibration mode bit. a 0 in this bit indicates a self-calibration is selected, and a 1 in this bit indicates a system calibration is selected (see table iii). 2 calslt1 calibration selection bits and start calibration bit. the stcal bit is read as a 1 if a calibration is in 1 calslt0 progress and as a 0 if there is no calibration in progress. the calslt1 and calslt0 bits indicate 0 stcal which of the calibration registers are addressed for reading and writing (see section on the calibration registers for more details).
ad7854/ad7854l rev. b e 11 e calibration registers the ad7854/ad7854l has 10 calibration registers in all, 8 for the dac, 1 for offset and 1 for gain. data can be written to or r ead from all 10 calibration registers. in self- and system calibration, the part automatically modifies the calibration registers; only if the user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers. addressing the calibration registers the calibration selection bits in the control register calslt1 and cals lt0 determine which of the calibration regist ers are addressed (see table iv). the addressing applies to both the read and write operations for the calibration registers. the user should not attempt to read from and write to the calibration registers at the same time. table iv. calibration register addressing calslt1 calslt0 comment 0 0 this combination addresses the gain (1) , offset (1) and dac registers (8) . ten registers in total. 0 1 this combination addresses the gain (1) and offset (1) registers. two registers in total. 1 0 this combination addresses the offset register . one register in total. 1 1 this combination addresses the gain register . one register in total. writing to/reading from the calibration registers when writing to the calibration registers a write to the control register is required to set the calslt0 and calslt1 bits. when reading from the calibration registers a write to the con- trol register is required to set the calslt0 and calslt1 bits and also to set the rdslt1 and rdslt0 bits to 10 (this addresses the calibration registers for reading). the calibration register pointer is reset on writing to the control register setting the calslt1 and calslt0 bits, or upon completion of all the calibration register write/read operations. when reset it points to the first calibration register in the selected write/read sequence. the calibration register pointer points to the gain calibration register upon reset in all but one case, this case being w here the offset calibration register is selected on its own (calslt1 = 1, calslt0 = 0). where more than one cali- bration register is being accessed, the calibration register pointer is automatically incremented after each full calibration register write/read operation. the calibration register address pointer is incremented after the high byte read or write operation in byte mode. therefore when reading from or writing to the calibra- tion registers, the low byte transfer must be carried out first, i.e., hben is at logic zero. the order in which the 10 calibration registers are arranged is shown in figure 5. read/write opera- tions may be aborted at any time before all the calibration registers have been accessed, and the next control register write operation resets the calibration register pointer. the flowchart in figure 6 shows the sequence for writing to the calibration registers. figure 7 shows the sequence for reading from the cali- bration registers. calibration registers gain register offset register dac 1st msb register (1) (2) (3) dac 8th msb register (10) cal register address pointer calibration register address pointer position is determined by the number of calibration registers addressed and the number of read/write operations. figure 5. calibration register arrangement when reading from the calibration registers there are always two leading zeros for each of the registers. write to control register setting stcal = 0 and calslt1, calslt0 = 00, 01, 10, 11 start cal register pointer is automatically reset write to cal register (addr1 = 1, addr0 = 0) cal register pointer is automatically incremented last register write operation or abort ? finished no yes figure 6. flowchart for writing to the calibration registers
ad7854/ad7854l e 12 e rev. b write to control register setting stcal = 0, rdslt1 = 1, rdslt0 = 0, and calslt1, calslt0 = 00, 01, 10, 11 start cal register pointer is automatically reset read cal register cal register pointer is automatically incremented last register read operation or abort ? finished no yes figure 7. flowchart for reading from the calibration registers adjusting the offset calibration register the offset calibration register contains 16 bits. the two msbs are zero and the 14 lsbs contain offset data. by changing the contents of the offset register, different amounts of offset on the analog input signal can be compensated for. decreasing the number in the offset calibration register compensates for nega- tive offset on the analog input signal, and increasing the number in the offset calibration register compensates for positive offset on the analog input signal. the default value of the offset cali- bration register is 0010 0000 0000 0000 approximately. this is not the exact value, but the value in the offset register should be close to this value. each of the 14 data bits in the offset register is binary weighted; the msb has a weighting of 5% of the refer- ence voltage, the msb-1 has a weighting of 2.5%, the msb-2 has a weighting of 1.25%, and so on down to the lsb which has a weighting of 0.0006%. this gives a resolution of 0.0006% of v ref approximately. the resolution can also be expressed as (0.05 v ref )/2 13 volts. this equals 0.015 mv, with a 2.5 v reference. the maximum offset that can be compensated for is 5% of the reference voltage, which equates to 125 mv with a 2.5 v reference and 250 mv with a 5 v reference. q. if a +20 mv offset is present in the analog input signal and the reference voltage is 2.5 v, what code needs to be written to the offset register to compensate for the offset ? a. 2.5 v reference implies that the resolution in the offset reg- ister is 5% 2.5 v/2 13 = 0.015 mv. +20 mv/0.015 mv = 1310.72; rounding to the nearest number gives 1311. in binary terms this is 00 0101 0001 1111, therefore increase the offset register by 00 0101 0001 1111. this method of compensating for offset in the analog input sig- nal allows for fine tuning the offset compensation. if the offset on the analog input signal is known, there is no need to apply the offset voltage to the analog input pins and do a system cali- bration. the offset compensation can take place in software. adjusting the gain calibration register the gain calibration register contains 16 bits. the two msbs are zero and the 14 lsbs contain gain data. as in the offset cali- bration register the data bits in the gain calibration register are binary weighted, with the msb having a weighting of 2.5% of the reference voltage. the gain register value is effectively multi- plied by the analog input to scale the conversion result over the full range. increasing the gain register compensates for a smaller analog input range and decreasing the gain register com- pensates for a larger input range. the maximum analog input range that the gain register can compensate for is 1.025 times the reference voltage, and the minimum input range is 0.975 times the reference voltage.
ad7854/ad7854l rev. b e 13 e when using the software conversion start for maximum throughput, the user must ensure the control register write operation extends beyond the falling edge of busy. the falling edge of busy resets the convst bit to 0 and allows it to be reprogrammed to 1 to start the next conversion. typical connection diagram figure 8 shows a typical connection diagram for the ad7854/ ad7854l. the agnd and the dgnd pins are connected together at the device for good noise suppression. the first convst applied after power-up starts a self-calibration sequence. this is explained in the calibration section of the data sheet. applying the rd and cs signals causes the conversion result to be output on the 12 data pins. n ote that after power is applied to av dd and dv dd , and the convst signal is applied, the part requires (70 ms + 1/sample rate) for the internal refer- ence to settle and for the self-calibration to be completed. 4mhz/1.8mhz oscillator av dd dv dd ain(+) ain( e ) c ref1 c ref2 db11 db0 agnd dgnd clkin ref in /ref out ad7854/ ad7854l analog supply +3v to +5v 0.1 f 0.1 f 10 f 0.1 f 0.01 f conversion start signal 0.1nf external reference 0.1 f on-chip reference 0v to 2.5v input optional external reference busy ad780/ ref192 c/ p
figure 8. typical circuit for applications where power consumption is a major concern, the power-down options can be programmed by writing to the part. see power-down section for more detail on low power applications. circuit information the ad7854/ad7854l is a fast, 12-bit single supply a/d con- verter. the part requires an external 4 mhz/1.8 mhz master clock (clkin), two c ref capacitors, a convst signal to start conversion and power supply decoupling capacitors. the part provides the user with track/hold, on-chip reference, calibration features, a/d converter and parallel interface logic functions on a single chip. the a/d converter section of the ad7854/ ad7854l consists of a conventional successive-approximation converter based around a capacitor dac. the ad7854/ ad7854l accepts an analog input range of 0 to +v ref. v ref can be tied to v dd . the reference input to the part connected via a 150 k resistor to the internal 2.5 v reference and to the on-chip buffer. a major advantage of the ad7854/ad7854l is that a conver- sion can be initiated in software as well as applying a signal to the convst pin. the part is available in a 28-lead ssop package, and this offers the user considerable sp ace saving advan- tages over alternative solutions. the ad7854l version typically consumes only 5.5 mw making it ideal for battery-powered applications. converter details the master clock for the part is applied to the clkin pin. conversion is initiated on the ad7854/ad7854l by pulsing the convst input or by writing to the control register and setting the convst bit to 1. on the rising edge of convst (or at the end of the control register write operation), the on-chip track/ hold goes from track to hold mode. the falling edge of the clkin signal which follows the rising edge of convst initates the conversion, provided the rising edge of convst (or wr when converting via the control register) occurs typically at least 10 ns before this clkin edge. the conversion takes 16.5 clkin periods from this clkin falling edge. if the 10 ns setup time is not met, the conversion takes 17.5 clkin periods. the time required by the ad7854/ad7854l to acquire a signal depends upon the source resistance connected to the ain(+) input. please refer to the acquisition time section for more details. when a conversion is completed, the busy output goes low, and the result of the conversion can be read by accessing the data through the data bus. to obtain optimum performance from the part, read or write operations should not occur during the conversion or less than 200 ns prior to the next convst rising edge. reading/writing during conversion typically de- grades the signal to (noise + distortion) by less than 0.5 dbs. the ad7854 can operate at throughput rates of over 200 ksps (up to 100 ksps for the ad7854l). with the ad7854l, 100 ksps throughput can be obtained as follows: the clkin and convst signals are arranged to give a conversion time of 16.5 clkin periods as described above and 1.5 clkin periods are allowed for the acquisition time. with a 1.8 mhz clock, this gives a full cycle time of 10 s, which equates to a throughput rate of 100 ksps.
ad7854/ad7854l e 14 e rev. b input frequency e khz e 72 e 92 0 100 20 thd e db 40 60 80 e 76 e 80 e 84 e 88 r in = 1k r in = 50 , 10nf as in figure 13 thd vs. frequency for different source impedances figure 10. thd vs. analog input frequency the maximum source impedance depends on the amount of total harmonic distortion (thd) that can be tolerated. the thd increases as the source impedance increases. figure 10 shows a graph of the total harmonic distortion vs. analog input signal frequency for different source impedances. with the setup as in figure 11, the thd is at the 90 db level. with a source impedance of 1 k and no capacitor on the ain(+) pin, the thd increases with frequency. in a single supply application (both 3 v and 5 v), the v+ and v of the op amp can be taken directly from the supplies to the ad7854/ad7854l which eliminates the need for extra external power supplies. when operating with rail-to-rail inputs and out- puts at frequencies greater than 10 khz, care must be taken in selecting the particular op amp for the application. in particular, for single supply applications the input amplifiers should be connected in a gain of 1 arrangement to get the optimum per- formance. figure 11 shows the arrangement for a single supply application with a 50 and 10 nf low-pass filter (cutoff fre- quency 320 khz) on the ain(+) pin. note that the 10 nf is a capacitor with good linearity to ensure good ac performance. recommended single supply op amps are the ad820 and the ad820-3v. v e v+ 10k 10k v in ( e v ref /2 to +v ref /2) v ref /2 0.1 f 10 f 50 10nf (npo) ad820 ad820-3v to ain(+) of ad7854/ad7854l +3v to +5v 10k ic1 10k figure 11. analog input buffering analog input the equivalent analog input circuit is shown in figure 9. dur- ing the acquisition interval the switches are both in the track position and the ain(+) charges the 20 pf capacitor through the 125 resistance. on the rising edge of convst switches sw1 and sw2 go into the hold position retaining charge on the 20 pf capacitor as a sample of the signal on ain(+). the ain( ) is connected to the 20 pf capacitor, and this unbalances the voltage at node a at the input of the comparator. the capacitor dac adjusts during the remainder of the conversion cycle to restore the voltage at node a to the correct value. this action transfers a charge, representing the analog input signal, to the capacitor dac which in turn forms a digital representation of the analog input signal. the vo ltage on the ain( ) pin directly influences the charge transferred to the capacitor dac at the hold instant. if this v oltage changes during the con version period, the dac representation of the analog input voltage is a ltered. therefore it is most important that the voltage on the ain( ) pin remains constant during the conversion period. further- more, it is recommended that the ain( ) pin is always connected to agnd or to a fixed dc voltage. capacitor dac comparator 20pf hold track sw2 track sw1 hold 125 ain(+) 125 ain( e ) agnd node a figure 9. analog input equivalent circuit acquisition time the track-and-hold amplifier enters its tracking mode on the falling edge of the busy signal. the time required for the track-and-hold amplifier to acquire an input signal depends on how quickly the 20 pf input capacitance is charged. there is a minimum acquisition time of 400 ns. for large source imped- ances, >2 k , the acquisition time is calculated using the formula: t acq = 9 (r in + 125 ) 20 pf where r in is the source impedance of the input signal, and 125 , 20 pf is the input r, c. dc/ac applications for dc applications, high source impedances are acceptable, provided there is enough acquisition time between conversions to charge the 20 pf capacitor. for example with r in = 5 k , the required acquisition time is 922 ns. for ac applications, removing high frequency components from the analog input signal is recommended by use of an rc low- pass filter on the ain(+) pin, as shown in figure 11. in applica- tions where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances significantly affect the ac per- formance of the adc. they may require the use of an input buffer amplifier. the choice of the amplifier is a function of the particular application.
ad7854/ad7854l rev. b e 15 e transfer functions for the unipolar range the designed code transitions occur midway between successive integer lsb values (i.e., 1/2 lsb, 3/2 lsbs, 5/2 lsbs . . . fs 3/2 lsbs). the output coding is straight binary for the unipolar range with 1 lsb = fs /4096 = 3.3 v/ 4096 = 0.8 mv when v ref = 3.3 v . the ideal input/ output transfer characteristic for the unipolar range is shown in figure 14. output code 111...111 111...110 111...101 111...100 000...011 000...010 000...001 000...000 0v 1lsb +fs e 1lsb v in = (ain(+) e ain( e )), input voltage 1lsb = fs 4096 figure 14. ad7854/ad7854l unipolar transfer characteristic figure 13 shows the ad7854/ad7854l s v ref /2 bipolar ana- log input configuration. ain(+) cannot go below 0 v, so for the full bipolar range, ain( ) should be biased to at least +v ref /2. once again the designed code transitions occur midway between successive integer lsb values. the output coding is twos complement with 1 lsb = 4096 = 3.3 v /4096 = 0.8 mv . the ideal input/output transfer characteristic is shown in figure 15. output code 011...111 011...110 000...001 111...111 000...000 000...010 000...001 000...000 v in = (ain(+) e ain( e )), input voltage 1lsb = fs 4096 0v (v ref /2) e 1lsb (v ref /2) + 1 lsb v ref /2 + fs e 1lsb fs = v ref v figure 15. ad7854/ad7854l bipolar transfer characteristic input ranges the analog input range for the ad7854/ad7854l is 0 v to v ref in both the unipolar and bipolar ranges. the only difference between the unipolar range and the bipolar range is that in the bipolar range the ain( ) should be biased up to at least +v ref /2 and the output coding is twos comple- ment (see table v and figures 14 and 15). table v. analog input connections analog input input connections connection range ain(+) ain() diagram 0 v to v ref 1 v in agnd figure 12 v ref /2 2 v in v ref /2 figure 13 notes 1 output code format is straight binary. 2 range is v ref /2 biased about v ref /2. output code format is twos complement. note that the ain( ) pin on the ad7854/ad7854l can be biased up above agnd in the unipolar mode, or above v ref /2 in bipolar mode if required. the advantage of biasing the lower end of the analog input range away from agnd is that the analog input does not have to swing all the way down to agnd. thus, in single supply applications the input amplifier does not have to swing all the way down to agnd. the upper end of the analog input range is shifted up by the same amount. care must be taken so that the bias applied does not shift the upper end of the analog input above the av dd supply. in the case where the ref- erence is the s upply, av dd , the ain( ) should be tied to agnd in unipolar mode or to av dd /2 in bipolar mode. . . . ain(+) ain( e ) v in = 0 to v ref track and hold amplifier db0 db11 straight binary format ad7854/ad7854l figure 12. 0 to v ref unipolar input configuration 2 ? s complement format v ref /2 . . . ain(+) ain( e ) v in = 0 to v ref track and hold amplifier db0 db11 ad7854/ad7854l figure 13. v ref /2 about v ref /2 bipolar input configuration
ad7854/ad7854l e 16 e rev. b reference section for specified performance, it is recommended that when using an external reference, this reference should be between 2.3 v and the analog supply av dd . the connections for the reference pins are shown below. if the internal reference is being used, the ref in /ref out pin should be decoupled with a 100 nf capacitor to agnd very close to the ref in /ref out pin. these connections are shown in figure 16. if the internal reference is required for use external to the adc, it should be buffered at the ref in /ref out pin and a 100 nf capacitor should be connected from this pin to agnd. the typical noise performance for the internal reference, with 5 v supplies is 150 nv/ hz @ 1 khz and dc noise is 100 v p-p. av dd dv dd c ref1 c ref2 ref in /ref out ad7854/ ad7854l analog supply +3v to +5v 0.1 f 0.1 f 10 f 0.1 f 0.01 f 0.1 f figure 16. relevant connections using internal reference the ref in /ref out pin may be overdriven by connecting it to an external reference. this is possible due to the series resis- tance from the ref in /ref out pin to the internal reference. this external reference can be in the range 2.3 v to av dd . when using av dd as the reference source, the 10 nf capacitor from the ref in /ref out pin to agnd should be as close as possible to the ref in /ref out pin, and also the c ref1 pin should be connected to av dd to keep this pin at the same volt- age as the reference. the connections for this arrangement are shown in figure 17. when using av dd it may be necessary to add a resistor in series with the av dd supply. this has the effect of filtering the noise associated with the av dd supply. note that when using an external reference, the voltage present at the ref in /ref out pin is determined by the external refer- ence source resistance and the series resistance of 150 k from the ref in /ref out pin to the internal 2.5 v reference. thus, a low source impedance external reference is recommended. av dd dv dd c ref1 c ref2 ref in /ref out ad7854/ ad7854l analog supply +3v to +5v 0.1 f 0.1 f 10 f 0.1 f 0.01 f 0.01 f figure 17. relevant connections, av dd as the reference ad7854/ad7854l performance curves figure 18 shows a typical fft plot for the ad7854 at 200 khz sample rate and 10 khz input frequency. frequency e khz 0 e 20 e 120 0 100 20 snr e db 40 60 e 40 e 60 e 80 80 e 100 av dd = dv dd = 3.3v f sample = 200khz f in = 10khz snr = 72.04db thd = e 88.43db figure 18. fft plot figure 19 shows the snr versus frequency for different supplies and different external references. input frequency e khz 74 73 69 0 100 20 s(n+d) ratio e db 40 80 72 71 70 60 av dd = dv dd with 2.5v reference unless stated otherwise 5.0v supplies, with 5v reference 5.0v supplies 5.0v supplies, l version 3.3v supplies figure 19. snr vs. frequency figure 20 shows the power supply rejection ratio versus fre- quency for the part. the power supply rejection ratio is defined as the ratio of the power in adc output at frequency f to the power of a full-scale sine wave: psrr (db) = 10 log (pf/pfs) pf = power at frequency f in adc output, pfs = power of a full- scale sine wave. here a 100 mv peak-to-peak sine wave is coupled onto the av dd supply while the digital supply is left unaltered. both the 3.3 v and 5.0 v supply performances are shown.
ad7854/ad7854l rev. b e 17 e power-up times using an external reference when the ad7854/ad7854l are powered up, the parts are powered up from one of two conditions. first, when the power supplies are initially powered up and, secondly, when the parts are powered up from a software power-down (see last section). when av dd and dv dd are powered up, the ad7854/ad7854l enters a mode whereby the convst signal initiates a timeout followed by a self-calibration. the total time taken for this time- out and calibration is approximately 70 ms see calibration on power-up in the c alibration section of this data sheet. the power- up calibration mode can be disabled if the user writes to the control register before a convst signal is applied. if the timeout and self-calibration are disabled, then the user must take into account the time required by the ad7854/ad7854l to power up before a self-calibration is carried out. this power-up time is the time taken for the ad7854/ad7854l to power up when power is first applied (300 s typ) or the time it takes the external refer- ence to settle to the 12-bit level whichever is the longer. the ad7854/ad7854l powers up from a full software power- down in 5 s typ. this limits the throughput which the part is capable of to 100 ksps for the ad7854 and 60 ksps for the ad7854l when powering down between conversions. figure 21 shows how a full power-down between conversions is implemented using the convst pin. the user first selects the power-down between conversions option by setting the power management bits, pmgt1 and pmgt0, to 0 and 1 respectively in the control register (see last section). in this mode the ad 7854/ad7854l automatically enters a full power-down at the end of a conver- sion, i.e., when busy goes low. the falling edge of the next convst pulse causes the part to power up. assuming the external reference is left powered up, the ad7854/ad7854l should be ready for normal operation 5 s after this falling edge. the rising edge of convst initiates a conversion so the convst pulse should be at least 5 s wide. the part auto- matically p owers down on completion of the conversion. where the software convert start is used, the part may be powered up in software before a conversion is initiated. t convert 5 s 4.6 s power-up time normal operation full power-down power-up time power-up on falling edge start conversion on rising edge busy figure 21. using the convst pin to power up the ad7854 for a conversion input frequency e khz e 78 e 80 e 90 0 100 20 psrr e db 40 60 e 82 e 84 e 86 e 88 80 av dd = dv dd = 3.3v/5.0v, 100mv pk-pk sine wave on av dd 3.3v 5.0v figure 20. psrr vs. frequency power-down options the ad7854/ad7854l provides flexible power management to allow the user to achieve the best power performance for a given throughput rate. the power management options are selected by programming the power management bits, pmgt1 and pmgt0, in the control register. table vi summarizes the power- down options that are available and how they can be selected by programming the power management bits in the control register. the ad7854/ad7854l can be fully or partially powered down. when fully powered down, all the on-chip circuitry is powered down and i dd is 10 a typ. if a partial power-down is selected, then all the on-chip circuitry except the reference is powered down and i dd is 400 a typ with the external clock running. additional power savings may be made if the external clock is off. the choice of full or partial power-down does not give any significant improvement in the throughput rate which can be achieved with a power-down between conversions. this is dis- cussed in the next section power-up times . but a partial power-down does allow the on-chip reference to be used exter- nally even though the rest of the ad7854/ad7854l circuitry is powered down. it also allows the ad7854/ad7854l to be pow- ered up faster after a long power-down period when using the on-chip reference (see power-up times section using the internal (on-chip) reference ). as can be seen from table vi, the ad7854/ad7854l can be programmed for normal operation, a full power-down at the end of a conversion, a partial power-down at the end of a conversion and finally a full power-down whether converting or not. the full and partial power-down at the end of a conversion can be used to achieve a superior power performance at slower through- put rates, in the order of 50 ksps (see power vs. throughput rate section of this data sheet). table vi. power management options pmgt1 pmgt0 bit bit comment 0 0 normal operation 0 1 full power-down after a conversion 1 0 full power-down 1 1 partial power-down after a conversion
ad7854/ad7854l e 18 e rev. b using the internal (on-chip) reference as in the case of an external reference the ad7854/ad7854l can power up from one of two conditions, power-up after the sup- plies are connected or power-up from a software power-down. when using the on-chip reference and powering up when av dd and dv dd are first connected, it is recommended that the power- up calibration mode be disabled as explained above. when using the on-chip reference, the power-up time is effectively the time it takes to charge up the external capacitor on the ref in / ref out pin. this time is given by the equation: t up = 9 r c where r 150k and c = external capacitor. the recommended value of the external capacitor is 100 nf; this gives a power-up time of approximately 135 ms before a calibration is initiated and normal operation should commence. when c ref is fully charged, the power-up time from a software power-down reduces to 5 s. this is because an internal switch opens to provide a high impedance discharge path for the refer- ence capacitor during power-down see figure 22. an added advantage of the low charge leakage from the reference capacitor during power-down is that even though the reference is being powered down between conversions, the reference capacitor holds the reference voltage to within 0.5 lsbs with throughput rates of 100 samples/second and over with a full power-down between conversions. a high input impedance op amp like the ad707 should be used to buffer this reference capacitor if it is being used externally. note, if the ad7854/ad7854l is left in its powered-down state for more than 100 ms, the charge on c ref will start to leak away and the power-up time will increase. if this longer power-up time is a problem, the user can use a partial power-down for the last conversion so the reference remains powered up. switch opens during power-down to other circuitry ref in/out external capacitor on-chip reference buf ad7854/ ad7854l figure 22. on-chip reference during power-down power vs. throughput rate the main advantage of a full power-down after a conversion is that it significantly reduces the power consumption of the part at lower throughput rates. when using this mode of operation, the ad7854/ad7854l is only powered up for the duration of the conversion. if the power-up time of the ad7854/ad7854l is taken to be 5 s and it is assumed that the current during power-up is 4.5 ma/1.5 ma typ, then power consumption as a function of throughput can easily be calculated. the ad7854 has a conversion time of 4.6 s with a 4 mhz external clock, and the ad7854l has a conversion time of 9 s with a 1.8 mhz clock. this means the ad7854/ad7854l consumes 4.5 ma/ 1.5 ma typ for 9.6 s/14 s in every conversion cycle if the parts are powered down at the end of a conversion. the four graphs, figures 24, 25, 26 and 27, show the power consumption of the ad7854 and ad7854l for v dd = 3 v as a function of through- put. table vii lists the power consumption for various throughput rates. table vii. power consumption vs. throughput power power throughput rate ad7854 ad7854l 1 ksps 130 w65 w 10 ksps 1.3 mw 650 w 20 ksps 2.6 mw 1.25 mw 50 ksps 6.48 mw 3.2 mw 4mhz/1.8mhz oscillator av dd dv dd ain(+) ain( e ) c ref1 c ref2 db11 db0 agnd dgnd clkin ref in /ref out ad7854/ ad7854l analog supply +3v to +5v 0.1 f 0.1 f 10 f 0.1 f 0.01 f conversion start signal 0.1nf external reference 0.1 f on-chip reference 0v to 2.5v input optional external reference busy ad780/ ref192 c/ p hben full power-down after a conversion pmgt1 = 0 pmgt0 = 1 figure 23. typical low power circuit
ad7854/ad7854l rev. b e 19 e power e mw throughput rate e ksps 1 0.1 0.01 0 10 2468 ad7854 full power-down v dd = 3v clkin = 4mhz on-chip reference figure 24. power vs. throughput ad7854 power e mw throughput rate e ksps 1 0.1 0.01 0 20 4 8 12 16 ad7854l full power-down v dd = 3v clkin = 1.8mhz on-chip reference figure 25. power vs. throughput ad7854l power e mw throughput rate e ksps 0.01 050 10 20 30 40 0.1 1 10 ad7854 full power-down v dd = 3v clkin = 4mhz on-chip reference figure 26. power vs. throughput ad7854 power e mw throughput rate e ksps 0.01 050 10 20 30 40 0.1 1 10 ad7854l full power-down v dd = 3v clkin = 1.8mhz on-chip reference figure 27. power vs. throughput ad7854l
ad7854/ad7854l e 20 e rev. b calibration section calibration overview the autom atic calibration that is performed on power-up ensures that the calibration options covered in this section are not required in a significant number of applications. a calibration does not have to be initiated unless the operating conditions change (clkin frequency, analog input mode, reference volt- age, temperature, and supply voltages). the ad7854/ad7854l has a number of calibration features that may be required in some a pplications, and there are a number of advantages in per- forming these different types of calibration. first, the internal errors in the adc can be reduced significantly to give superior dc performance; and second, system offset and gain errors can be removed. this allows the user to remove reference errors (whether it be internal or external reference) and to make use of the full dynamic range of the ad7854/ad7854l by adjusting the analog input range of the part for a specific system. there are two main calibration modes on the ad7854/ad7854l, self-calibration and system calibration. there are various op- tions in both self-calibration and system calibration as outlined previously in table iii. all the calibration functions are initi- ated by writing to the control register and setting the stcal bit to 1. the duration of each of the different types of calibration is given in table ix for the ad7854 with a 4 mhz master clock. these calibration times are master clock dependent. therefore the calibration times for the ad7854l (clkin = 1.8 mhz) are larger than those quoted in table viii. table viii. calibration times (ad7854 with 4 mhz clkin) type of self-calibration or system calibration time full 31.25 ms gain + offset 6.94 ms offset 3.47 ms gain 3.47 ms automatic calibration on power-on the automatic calibration on power-on is initiated by the first convst pulse after the av dd and dv dd power on. from the convst pulse the part internally sets a 32/72 ms (4 mhz/ 1.8 mhz clkin) timeout. this time is large enough to ensure that the internal reference has settled before the calibration is performed. however, if an external reference is being used, this reference must have stabilized before the automatic calibration is initiated. this first convst pulse also triggers the busy signal high, and once the 32/72 ms has elapsed, the busy signal goes low. at this point the next convst pulse that is applied initiates the automatic full self-calibration. this convst pulse again triggers the busy signal high, and after 32/72 ms (4 mhz/ 1.8 mhz clkin), the calibration is completed and the busy signal goes low. this timing arrangement is shown in figure 28. the times in figure 28 assume a 4 mhz/1.8 mhz clkin signal. av dd = dv dd busy power on 32/72 ms timeout period automatic calibration duration 32/72 ms conversion is initiated on this edge figure 28. timing arrangement for autocalibration on power-on the convst signal is gated with the busy internally so that as soon as the timeout is initiated by the first convst pulse all subsequent convst pulses are ignored until the busy signal goes low, 32/72 ms later. the convst pulse that follows after the busy signal goes low initiates an automatic full self- calibration. t his takes a further 32/72 ms. after calibration, the part is accurate to the 12-bit level and the specifications quoted on the data sheet apply, and all subsequent convst pulses initiate conversions. there is no need to perform another calibration unless the operating conditions change or unless a system calibration is required. this autocalibration at power-on is disabled if the user writes to the control register before the autocalibration is initiated. if the control register write operation occurs during the first 32/72 ms timeout period, then the busy signal stays high for the 32/72 ms and the convst pulse that follows the busy going low does not initiate an automatic full self-calibration. it initiates a con- version and all subsequent convst pulses initiate conversions as well. if the control register write operation occurs when the automatic full self-calibration is in progress, then the calibration is not be aborted; the busy signal remains high until the auto- matic full self-calibration is complete. self-calibration description there are four different calibration options within the self- calibration mode. there is a full self-calibration where the dac, internal offset, and internal gain errors are removed. there is the (gain + offset) self-calibration which removes the internal gain error and then the internal offset errors. the inter- nal dac is not calibrated here. finally, there are the self-offset and self-gain calibrations which remove the internal offset errors and the internal gain errors respectively. the internal capacitor dac is calibrated by trimming each of the capacitors in the dac. it is the ratio of these capacitors to each other that is critical, and so the calibration algorithm ensures that this ratio is at a specific value by the end of the calibration routine. for the offset and gain there are two separate capacitors, one of which is trimmed during offset calibra tion and one of which is trimmed during gain calibration. in bipolar mode the midscale error is adjusted by an offset cali- bration and the positive full-scale error is adjusted by the gain calibration. in unipolar mode the zero-scale error is adjusted by the offset calibration and the positive full-scale error is adjusted by the gain calibration.
ad7854/ad7854l rev. b e 21 e self-calibration timing figure 29 shows the timing for a software full self-calibration. here the busy line stays high for the full length of the self- calibration. a self-calibration is initiated by writing to the con- trol register and setting the stcal bit to 1. the busy line goes high at the end of the write to the control register, and busy goes low when the full self-calibration is complete after a time t cal as show in figure 29. t 23 data latched into control register hi-z hi-z data valid t cal data busy figure 29. timing diagram for full self-calibration for the self-(gain + offset), self-offset and self-gain calibrations, the busy line is triggered high at the end of the write to the control register and stays high for the full duration of the self- calibration. the length of time for which busy is high depends on the type of self-calibration that is initiated. typical values are given in table viii. the timing diagram for the other self- calibration options is similar to that outlined in figure 29. system calibration description system calibration allows the user to remove system errors exter nal to the ad7854/ad7854l, as well as remove the errors of the ad7854/ad7854l itself. the maximum calibration range for the system offset errors is 5% of v ref , and for the system gain errors it is 2.5% of v ref . if the system offset or system gain errors are outside these ranges, the system calibration algorithm reduces the errors as much as the trim range allows. figures 30 through 32 illustrate why a specific type of system calibration might be used. figure 30 shows a system offset cali- bration (assuming a positive offset) where the analog input range has been shifted upwards by the system offset after the system offset calibration is completed. a negative offset may also be removed by a system offset calibration. max system offset is 5% of v ref analog input range system offset calibration sys offset agnd v ref + sys offset v ref e 1lsb max system full scale is 2.5% from v ref analog input range max system offset is 5% of v ref v ref e 1lsb sys offset agnd figure 30. system offset calibration figure 31 shows a system gain calibration (assuming a system full scale greater than the reference voltage) where the analog input range has been increased after the system gain calibration is completed. a system full-scale voltage less than the reference voltage may also be accounted for a by a system gain calibration. analog input range system offset calibration agnd sys full s. v ref e 1lsb max system full scale is 2.5% from v ref analog input range v ref e 1lsb sys full s. agnd max system full scale is 2.5% from v ref figure 31. system gain calibration finally in figure 32 both the system offset error and gain error are removed by the system offset followed by a system gain cali- bration. first the analog input range is shifted upwards by the positive system offset and then the analog input range is adjusted at the top end to account for the system full scale. max system full scale is 2.5% from v ref max system offset is 5% of v ref analog input range system offset calibration followed by system gain calibration sys offset agnd v ref + sys offset v ref e 1lsb analog input range max system offset is 5% of v ref v ref e 1lsb sys offset agnd sys f.s. sys f.s. max system full scale is 2.5% from v ref figure 32. system (gain + offset) calibration
ad7854/ad7854l e 22 e rev. b system gain and offset interaction the architecture of the ad7854/ad7854l leads to an interac- tion between the system offset and gain errors when a system calibration is performed. therefore it is recommended to perform the cycle of a system offset calibration followed by a system gain calibration twice. when a system offset calibration is performed, the system offset error is reduced to zero. if this is followed by a system gain calibration, then the system gain error is now zero, but the system offset error is no longer zero. a second sequence of system offset error calibration followed by a system gain cali- bration is necessary to reduce system offset error to below the 12-bit level. the advantage of doing separate system offset and system gain calibrations is that the user has more control over when the analog inputs need to be at the required levels, and the convst signal does not have to be used. alternatively, a system (gain + offset) calibration can be per- formed. at the end of one system (gain + offset) calibration, the system offset error is zero, while the system gain error is reduced from its initial value. three system (gain + offset) calibrations are required to reduce the system gain error to below the 12-bit error level. there is never any need to perform more than three system (gain + offset) calibrations. in bipolar mode the midscale error is adjusted for an offset cali- bration and the positive full-scale error is adjusted for the gain calibration; in unipolar mode the zero-scale error is adjusted for an offset calibration and the positive full-scale error is adjusted for a gain calibration. system calibration timing the timing diagram in figure 33 is for a software full system calibration. it may be easier in some applications to perform separate gain and offset calibrations so that the convst bit in the control register does not have to be programmed in the middle of the system calibration sequence. once the write to the control register setting the bits for a full system calibration is completed, calibration of the internal dac is initiated and the busy line goes high. the full-scale system voltage should be applied to the analog input pins, ain(+) and ain( ) at the start of calibration. the busy line goes low once the dac and system gain calibration are complete. next the system offset voltage should be applied across the ain(+) and ain( ) pins for a m inimum setup time (t setup ) of 100 ns before the rising edge of cs . this second write to the control register sets the convst bit to 1 and at the end of this write operation the busy signal is triggered high (note that a convst pulse can be applied instead of this second write to the control register). the busy signal is low after a time t cal2 when the system offset calibration section is complete. the full system calibration is now complete. the timing for a system (gain + offset) calibration is very similar to that of figure 33, the only difference being that the time t cal1 is replaced by a shorter time of the order of t cal2 as the in ternal dac is not calibrated. the busy signal signifies when the gain calibration is finished and when the part is ready for the offset calibration. convst bit set to 1 in control register t 23 data latched into control register hi-z hi-z hi-z t cal1 t 23 t setup v offset v system full scale data valid data busy ain data valid t cal2 figure 33. timing diagram for full system calibration the timing diagram for a system offset or system gain calibra- tion is shown in figure 34. here again a write to the control register initiates the calibration sequence. at the end of the con- trol register write operation the busy line goes high and it stays high until the calibration sequence is finished. the analog input should be set at the correct level for a minimum setup time (t setup ) of 100 ns before the cs rising edge and stay at the cor- rect level until the busy signal goes low. t 23 hi-z hi-z data latched into control register t setup t cal2 data valid v system full scale or v offset data busy ain figure 34. timing diagram for system gain or system offset calibration
ad7854/ad7854l rev. b e 23 e parallel interface reading the timing diagram for a read cycle is shown in figure 35. the convst and busy signals are not shown here as the read cycle may occur while a conversion is in progress or after the conversion is complete. the hben signal is low for the first read and high for the sec- ond read. this ensures that it is the lower 12 bits of the 16-bit word are output in the first read and the 8 msbs of the 16-bit word are output in the second read. if required, the hben signal may be high for the first read and low for the second read to ensure that the high byte is output in the first read and the lower byte in the second read. the cs and rd sig- nals are gated together internally and level triggered active low. both cs and rd may be tied together as the timing speci- fication for t 5 and t 6 are both 0 ns min. the data is output a time t 8 after both cs and rd go low. the rd rising edge should be used to latch the data by the user and after a time t 9 the data lines will go into their high impedance state. in figure 35, the first read outputs the 12 lsbs of the 16-bit word on pins db0 to db11 (db0 being the lsb of the 12-bit read). the second read outputs the 8 msbs of the 16-bit word on pins db0 to db7 (db0 being the lsb of the 8-bit read). if the system has a 12-bit or a 16-bit data bus, only one read operation is necessary to obtain the 12-bit conversion result (12 bits are output in the first read). a s econd read operation is not required. if the system has an 8-bit data bus then two reads are needed. pins db0 to db7 should be connected the 8-bit data bus. pins db8 to db11 should be tied to dgnd or dv dd via 10 k resistors. with this arrangement, hben is pulled low for the first read and the 8 lsbs of the 16-bit word are output on pins db0 to db7 (data on pins db8 to db11 will be ignored). hben is pulled high for the second read and now the 8 msbs of the 16-bit word are output on pins db0 to db7. data valid t 3 = 15ns min, t 4 = 5ns min, t 5 = t 6 = 0ns min, t 8 = 50ns max, t 9 = 5/40ns min/max, t 10 = 70ns min t 3 t 4 t 3 t 4 t 5 t 6 t 9 t 8 hben data t 10 data valid t 7 figure 35. read cycle timing diagram using cs and rd in the case where the ad7854/ad7854l is operated as a read- only adc, the wr pin can be tied permanently high. the read operation need only consist of one read if the system has a 12- bit or a 16-bit data bus. when both the cs and rd signals are tied permanently low a different timing arrangement results, as shown in figure 36. here the data is output a time t 20 before the falling edge of the busy signal. this allows the falling edge of busy to be used for latching the data. again if hben is low during the conver- sion the 12 lsbs of the 16-bit word will be output on pins db0 to db11. bringing hben high causes the 8 msbs of the 16-bit word to be output on pins db0 to db7. note that with this arrangement the data lines are always active. t 1 = 100ns min, t 20 = 70ns min, t 19 = t 20 = 70ns min, t 21 = t 22 = 60ns max t 1 t 2 t convert conversion is initiated on this edge t 19 t 20 t 18 t 21 t 22 old data valid new data valid (db0 e db11) new data valid (db8 e db11) new data valid (db0 e db11) new data valid (db8 e db11) on pins db0 to db11 on pins db0 to db7 busy hben data figure 36. read cycle timing diagram with cs and rd tied low writing the timing diagram for a write cycle is shown in figure 37. the convst and busy signals are not shown here as the write cycle may occur while a conversion is in progress or after the conversion is complete. to write a 16-bit word to the ad7854/ad7854l, two 8-bit writes are required. the hben signal must be low for the first write and high for the second write. this ensures that it is the lower 8 bits of the 16-bit word are latched in the first write and the 8 msbs of the 16-bit word are latched in the second write. for both write operations the 8 bits of data should be present on pins db0 to db7 (db0 being the lsb of the 8-bit write). any data on pins db8 to db11 is i gnored when writing to the device. the cs and wr signals are gated together internally. both cs and wr may be tied together as the timing specification for t 13 and t 14 are both 0 ns min. the data is latched on the rising edge of wr . the data needs to be set up a time t 16 before the wr rising edge and held for a time t 17 after the wr rising edge. data valid t 11 t 12 t 11 t 12 t 13 t 14 t 10 t 15 t 16 t 17 hben data data valid t 11 = 0ns min, t 12 = 5ns min, t 13 = t 14 = 0ns min, t 15 = 70ns min, t 16 = 10ns min, t 17 = 5ns min figure 37. write cycle timing diagram resetting the parallel interface if random data has been inadvertently written to the test regis- ter, it is necessary to write the 16-bit word 0100 0000 0000 0010 (in two 8-bit bytes) to restore the test register to its default value.
ad7854/ad7854l e 24 e rev. b microprocessor interfacing the parallel port on the ad7854/ad7854l allows the device to be interfaced to microprocessors or dsp processors as a memory mapped or i/o mapped device. the cs and rd inputs are common to all memory peripheral interfacing. typical inter- faces to different processors are shown in figures 38 to 41. in all the interfaces shown, an external timer controls the convst input of the ad7854/ad7854l and the busy out- put interrupts the host dsp. also, the hben pin is connected to address line a0 (xa0 in the case of the tms320c30). this maps the ad7854/ad7854l to two locations in the processor memory space, adcaddr and adcaddr+1. thus when writing to the adc, first the 8 lsbs of the 16-bit are written to address location adcaddr and then the 8 msbs to location adcaddr+1. all the interfaces use a 12-bit data bus, so only one read is needed from location adcaddr to access the adc output data register or the status register. to read from the other registers, the 8 msbs must be read from location adcaddr+1. interfacing to 8-bit bus systems is similar, except that two reads are required to obtain data from all the registers. ad7854/ad7854l to adsp-21xx figure 38 shows the ad7854/ad7854l interfaced to the adsp-21xx series of dsps as a memory mapped device. a single wait state may be necessary to interface the ad7854/ ad7854l to the adsp-21xx depending on the clock speed of the dsp. this wait state can be programmed via the data memory w aitstate control register of the adsp-21xx (please see adsp-2100 family users manual for details). the following instruction reads data from the ad7854/ad7854l: ax 0 = dm(adcaddr) data can be written to the ad7854/ad7854l using the instructions: dm (adcaddr) = ay 0 dm (adcaddr+ 1 ) = ay 1 where adcaddr is the address of the ad7854/ad7854l in adsp-21xx data memory, ax 0 contains the data read from the adc, and ay 0 contains the 8 lsbs and ay 1 the 8 msbs of data written to the ad7854/ad7854l. adsp-21xx* a13 e a1 a0 d23 e d8 hben busy db11 e db0 ad7854/ ad7854l* addr decode address bus data bus *additional pins omitted for clarity figure 38. ad7854/ad7854l to adsp-21xx parallel interface ad7854/ad7854l to tms32020, tms320c25 and tms320c5x a parallel interface between the ad7854/ad7854l and the tms32020, tms320c25 and tms320c5x family of dsps are shown in figure 39. the memory mapped addresses chosen for the ad7854/ad7854l should be chosen to fall in the i/o memory space of the dsps. the parallel interface on the ad7854/ad7854l is fast enough to interface to the tms32020 with no extra wait states. in the tms320c25 interface, data accesses may be slowed sufficiently when reading from and writing to the part to require the inser- tion of one wait state. in such a case, this wait state can be generated using the single or gate to combine the cs and msc signals to drive the ready line of the tms320c25, as shown in figure 39. extra wait states are necessary when using the tms320c5x at their fastest clock speeds. wait states can be programmed via the iowsr and cwsr registers (please see tms320c5x user guide for details). data is read from the adc using the following instruction: in d,adcaddr where d is the memory location where the data is to be stored and adcaddr is the i/o address of the ad7854/ad7854l. data is written to the adc using the following two instructions: out d 8 lsb, adcaddr out d 8 msb, adcaddr +1 where d 8 lsb is the memory location where the 8 lsbs of data are stored, d 8 msb is the location where the 8 msbs of data are stored and adcaddr and adcaddr +1 are the i/o memory spaces that the ad7854/ad7854l is mapped into. tms32020/ tms320c25/ tms320c50* a15 e a1 ready a0 r/ x d23 e d0 tms320c25 only hben busy db11 e db0 ad7854/ ad7854l* addr decode address bus data bus *additional pins omitted for clarity figure 39. ad7854/ad7854l to tms32020/c25/c5x parallel interface
ad7854/ad7854l rev. b e 25 e ad7854/ad7854l to dsp5600x figure 41 shows a parallel interface between the ad7854/ ad7854l and the dsp5600x series of dsps. the ad7854/ ad7854l should be mapped into the top 64 locations of y data memory. if extra wait states are needed in this interface, they can be programmed using the port a bus control register (please see dsp5600x user? manual for details). data can be read from the dsp5600x using the following instruction: move y:adcaddr, x 0 data can be written to the ad7854/ad7854l using the follow- ing two instructions: move x0, y:adcaddr move x1, y:adcaddr+ 1 where adcaddr is the address in the dsp5600x address space to which the ad7854/ad7854l has been mapped. dsp56000/ dsp56002* a15 e a1 x/ a0 d23 e d0 hben busy db11 e db0 ad7854/ ad7854l* addr decode address bus data bus *additional pins omitted for clarity figure 41. ad7854/ad7854l to dsp5600x parallel interface ad7854/ad7854l to tms320c30 figure 40 shows a parallel interface between the ad7854/ ad7854l and the tms320c3x family of dsps. the ad7854/ad7854l is interfaced to the expansion bus of the tms320c3x. two wait states are required in this interface. these can be programmed using the wtcnt bits of the expansion bus control register (see tms320c3x users guide for details). data from the ad7854/ad7854l can be read using the following instruction: ldi *arn,rx data can be loaded into the ad7854/ad7854l using the instructions: sti ry,*arn++ sti rz,*arn-- where arn is an auxiliary register containing the lower 16 bits of the address of the ad7854/ad7854l in the tms320c3x memory space, rx is the register into which the adc data is loaded during a load operation, ry contains the 8 lsbs of data and rz contains the 8 msbs of data to be written to the ad7854/ad7854l. tms320c30* xa12 e xa1 xa0 xr/ x xd23 e xd0 hben busy db11 e db0 ad7854/ ad7854l* addr decode expansion address bus expansion data bus *additional pins omitted for clarity figure 40. ad7854/ad7854l to tms320c30 parallel interface
ad7854/ad7854l e 26 e rev. b application hints grounding and layout the analog and digital supplies of the ad7854/ad7854l are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the part has very good immunity to noise on the power supplies as can be seen by the psrr versus frequency graph. however, care should still be taken with regard to grounding and layout. the printed circuit board on which the ad7854/ad7854l is mounted should be designed such that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should only be joined in one place. if the ad7854/ad7854l is the only device requiring an agnd to dgnd connection, then the ground planes should be connected at the agnd and dgnd pins of the ad7854/ ad7854l. if the ad7854/ad7854l is in a system where multiple devices require agnd to dgnd connections, the connection should still be made at one point only, a star ground point which should be established as close as possible to the ad7854/ad7854l. avoid running digital lines under the device as these couple noise onto the die. the analog ground plane should be allowed to run under the ad7854/ad7854l to avoid noise coupling. the power supply lines to the ad7854/ad7854l should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks and the data inputs should be shielded with digital ground to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with a 10 f tantalum capacitor in parallel with 0.1 f disc ceramic capacitor to agnd. all digital supplies should have a 0.1 f disc ceramic capacitor to dgnd. to achieve the best performance from these decoupling compo- nents, they must be placed as close as possible to the device, ideally right up against the device. in systems where a common supply voltage is used to drive both the av dd and dv dd of the ad7854/ad7854l, it is recommended that the system s av dd supply is used. in this case an optional 10 resistor between the av dd pin and dv dd pin can help to filter noise from digital circuitry. this supply should have the recommended analog supply decoupling capacitors between the av dd pin of the ad7854/ad7854l and agnd and the recommended digital supply decoupling capacitor between the dv dd pin of the ad7854/ad7854l and dgnd. evaluating the ad7854/ad7854l performance the recommended layout for the ad7854/ad7854l is outlined in the evaluation board for the ad7854/ad7854l. the evalua- tion board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the pc via the eval-control board. the eval-control board can be used in conjunction with the ad7854/ad7854l evaluation board, as well as many other analog devices evaluation boards ending in the cb desig- nator, to demonstrate/evaluate the ac and dc performance of the ad7854/ad7854l. the software allows the user to perform ac (fast fourier trans- form) and dc (histogram of codes) tests on the ad7854/ ad7854l. it also gives full access to all the ad7854/ad7854l on-chip registers allowing for various calibration and power- down options to be programmed. ad785x family all parts are 12 bits, 200 ksps, 3.0 v to 5.5 v. ad7853 single channel serial ad7854 single channel parallel ad7858 eight channel serial ad7859 eight channel parallel
ad7854/ad7854l rev. b e 27 e page index topic page features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . 1 product highlights . . . . . . . . . . . . . . . . . . . . . . . . . 1 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 timing specifications . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . 5 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin function description . . . . . . . . . . . . . . . . . . . 7 ad7854/ad7854l on-chip registers . . . . . . . . . . . . 8 addressing the on-chip registers . . . . . . . . . . . . . . . . . . . 8 writing/reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 calibration registers . . . . . . . . . . . . . . . . . . . . . . 11 addressing the calibration registers . . . . . . . . . . . . . . . . 11 writing to/reading from the calibration registers . . . . . . 11 adjusting the offset calibration register . . . . . . . . . . . . . 12 adjusting the gain calibration register . . . . . . . . . . . . . . 12 circuit information . . . . . . . . . . . . . . . . . . . . . . . . 13 converter details . . . . . . . . . . . . . . . . . . . . . . . . . . 13 typical connection diagram . . . . . . . . . . . . . . 13 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 acquisition time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 dc/ac applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 input ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 transfer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 reference section . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ad7854/ad7854l performance curves . . . . . . . . 16 power-down options . . . . . . . . . . . . . . . . . . . . . . . . 17 power-up times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 using an external reference . . . . . . . . . . . . . . . . . . . . . . 17 using the internal (on-chip) reference . . . . . . . . . . . . . 18 power vs. throughput rate . . . . . . . . . . . . . . . . 18 topic page calibration section . . . . . . . . . . . . . . . . . . . . . . . . 20 calibration overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 automatic calibration on power-on . . . . . . . . . . . . . . . . 20 self-calibration description . . . . . . . . . . . . . . . . . . . . . . . 20 self-calibration timing . . . . . . . . . . . . . . . . . . . . . . . . . . 21 system calibration description . . . . . . . . . . . . . . . . . . . . 21 system gain and offset interaction . . . . . . . . . . . . . . . . . 22 system calibration timing . . . . . . . . . . . . . . . . . . . . . . . 22 parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . 23 reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 resetting the parallel interface . . . . . . . . . . . . . . . . . . . . . 23 microprocessor interfacing . . . . . . . . . . . . . . . 24 ad7854/ad7854l to adsp-21xx . . . . . . . . . . . . . . . . . . 24 ad7854/ad7854l to tms32020, tms320c25 and tms320c5x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ad7854/ad7854l to tms320c30 . . . . . . . . . . . . . . . . 25 ad7854/ad7854l to dsp5600x . . . . . . . . . . . . . . . . . . 25 applications hints . . . . . . . . . . . . . . . . . . . . . . . . . . 26 grounding and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 evaluating the ad7854/ad7854l performance . . . . . . . 26 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 28 table index # title page i write register addressing . . . . . . . . . . . . . . . . . . . . . . . 8 ii read register addressing . . . . . . . . . . . . . . . . . . . . . . . 8 iii calibration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 iv calibrating register addressing . . . . . . . . . . . . . . . . . 11 v analog input connections . . . . . . . . . . . . . . . . . . . . . 15 vi power management options . . . . . . . . . . . . . . . . . . . . 17 vii power consumption vs. throughput . . . . . . . . . . . . . 18 viii calibration times (ad7854 with 4 mhz clkin) . . . 20
ad7854/ad7854l e 28 e rev. b c2117 e 0 e 3/00 (rev. b) printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 28-lead cerdip (q-28) 28 114 15 0.610 (15.49) 0.500 (12.70) pin 1 0.005 (0.13) min 0.100 (2.54) max 15 ? 0 ? 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20) seating plane 0.225 (5.72) max 1.490 (37.85) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.015 (0.38) min 0.026 (0.66) 0.014 (0.36) 0.110 (2.79) 0.090 (2.29) 0.070 (1.78) 0.030 (0.76) 28-lead small outline package (r-28) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 ? 0 ? 0.0291 (0.74) 0.0098 (0.25) 45 ? 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 28 15 14 1 28-lead shrink small outline package (rs-28) 28 15 14 1 0.407 (10.34) 0.397 (10.08) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 8 ? 0 ?

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