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1 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications ace1202 arithmetic controller engine (acex?) for low power applications general description the ace1202 (arithmetic controller engine) is a dedicated pro- grammable monolithic integrated circuit for applications requiring high performance, low power, and small size. it is a fully static part fabricated using cmos technology. the ace1202 has an 8-bit microcontroller core, 64 bytes of ram, 64 bytes of data eeprom and 2k bytes of code eeprom. its on- chip peripherals include a multi-function 16-bit timer, watchdog/ idle timer, and programmable undervoltage detection circuitry. on-chip clock and reset functions reduce the number of required external components. the ace1202 is available in 8- and 14-pin so and dip packages. features arithmetic controller engine 2k bytes on-board code eeprom 64 bytes data eeprom 64 bytes ram watchdog multi-input wake-up on all i/o pins block and connection diagram january 2000 16-bit multifunction timer with difference capture on-chip oscillator ?no external components ?1 s instruction cycle time instruction set geared for block encryption on-chip power on reset programmable read and write disable functions memory mapped i/o multilevel low voltage detection fully static cmos ?low power halt mode (100na @3.3v) ?single supply operation (2.0-5.5v, 2.2-5.5v, 2.7-5.5v) software selectable i/o options ?push-pull outputs with tri-state option ?weak pull-up or high impedance inputs 40 years data retention 1,000,000 data changes packages available: 8- and 14-pin so, 8- and 14-pin dip in-circuit programming power-on reset v cc gnd g0 (cko) g1 (cki) g2 (t1) g3(input only) g4 g5 g6 g7 internal oscillator g port general purpose i/o with multi- input wakeup low battery/brown-out detect * 100nf decoupling capacitor recommended watchdog/ 12-bit timer 0 16-bit timer 1 with difference capture halt power saving mode acex control unit 64 bytes of data eeprom programming interface 2k bytes of code eeprom ram block 64 bytes external reset ? 1999 fairchild semiconductor corporation
2 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications absolute maximum ratings ambient storage temperature -65 c to +150 c input voltage not including g3 -0.3v to v cc +0.3v g3 input voltage 0.3v to 13v lead temperature (10s max) +300 c electrostatic discharge on all pins 2000v min operating conditions ambient operating temperature: ace1202 0 c to 70 c ace1202e -40 c to +85 c operating supply voltage: from -40 c to 85 c: 2.2v to 5.5v see table for eeprom write limits relative humidity (non-condensing) 95% ace1202 dc electrical characteristics for v cc = 2.2 to 5.5v all measurements valid for ambient operating temperature range unless otherwise stated. symbol parameter conditions min typ max units i cc supply current 2.2v 0.5 1.0 ma no eeprom write in 3.3v 1.0 1.5 ma progress 5.5v 1.6 2.0 ma i cch halt mode current 3.3v, -40 c to 25 c 10 100 na 5.5v, -40 c to 25 c 200 1000 na 3.3v, 25 c to +85 c 50 1000 na 5.5v, 25 c to +85 c 400 2500 na 3.3v, -40 c to +125 c 350 5000 na 5.5v, -40 c to +125 c 1200 8000 na i cci idle mode current 5.5v 120 250 a* 3.3v 100 150 a* v ccw eeprom write voltage code eeprom in 4.5 5.0 5.5 v programming mode data eeprom in 2.4 5.5 v operating mode s vcc power supply slope 1 s/v 10ms/v inputs v ih logic high 0.8v cc v v il logic low 0.2 v cc v i ip input pull-up current v cc =5.5v, v in =0v 30 65 350 a i tl tri-state leakage v cc =5.5v 2 200 na v ol output low voltage - v ol v cc = 3.3v 5.5v g0, g1, g2, g4, g6, g7 5.0 ma sink 0.2 v cc v g5 10.0 ma sink 0.2 v cc v v cc = 2.2v 3.3v 3.0 ma sink 0.2 v cc v 5.0 ma sink 0.2 v cc v v oh output high voltage - v oh v cc = 3.3v 5.5v g0, g1, g2, g4, g6, g7 0.4 ma source 0.8 v cc v g5 1.0 ma source 0.8 v cc v v cc = 2.2v 3.3v 0.4 ma source 0.8 v cc v 0.8 ma source 0.8 v cc v * based on continuous idle looping.
3 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications preliminary ace1202 ac electrical characteristics for v cc = 2.2 to 5.5v parameter conditions min typ max units instruction cycle time from 5.0v at 25 c 0.9 1.00 1.1 s internal clock - setpoint internal clock voltage dependent 3.0v to 5.5v, 5% frequency variation constant temperature internal clock temperature 3.0v to 5.5v, 10% dependent frequency variation full temperature range internal clock frequency 3.0v to 4.5v for 2% deviation for 0.5v drop ace1202e, t=constant crystal oscillator frequency (note 1) 4 mhz external clock frequency (note 2) 4 mhz eeprom write time 3 10 ms internal clock start up time (note 2) 2 ms oscillator start up time (note 2) 2400 cycles note 1: the maximum permissible frequency is guaranteed by design but not 100% tested. note 2: the parameter is guaranteed by design but not 100% tested. ace1202 electrical characteristics for programming all data valid at ambient temperature between 4.5v and 5.5v. see eeprom write time in the ac characteristics for definition of the programming ready time. the following characteristics are guaranteed by design but are not 100% tested. parameter description min max units t hi clock high time 500 dc ns t lo clock low time 500 dc ns t dis shift_in setup time 100 ns t dih shift_in hold time 100 ns t dos shift_out setup time 100 ns t doh shift_out hold time 900 ns t sv1 , t sv2 load supervoltage timing 50 us t load1 , t load2 , t load3 , t load4 load timing 5 us v supervoltage supervoltage level 11.5 12.5 v
4 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications absolute maximum ratings ambient storage temperature -65 c to +150 c input voltage not including g3 -0.3v to v cc +0.3v g3 input voltage 0.3v to 13v lead temperature (10s max) +300 c electrostatic discharge on all pins 2000v min operating conditions ambient operating temperature: ace1202b 0 c to 70 c ace1202be -40 c to +85 c ace1202bv -40 c to +125 c operating supply voltage: from -40 c to 125 c: 2.7v to 5.5v see table for eeprom write limits relative humidity (non-condensing) 95% ace1202b dc electrical characteristics for v cc = 2.7 to 5.5v all measurements valid for ambient operating temperature range unless otherwise stated. symbol parameter conditions min typ max units i cc supply current 2.7v 0.7 1.2 ma no eeprom write in 3.3v 1.0 1.5 ma progress 5.5v 1.6 2.0 ma i cch halt mode current 3.3v, -40 c to 25 c 10 100 na 5.5v, -40 c to 25 c 200 1000 na 3.3v, 25 c to +85 c 50 1000 na 5.5v, 25 c to +85 c 400 2500 na 3.3v, -40 c to +125 c 350 5000 na 5.5v, -40 c to +125 c 1200 8000 na i cci idle mode current 5.5v 120 250 a* 3.3v 100 150 a* v ccw eeprom write voltage code eeprom in 4.5 5.0 5.5 v programming mode data eeprom in 2.7 5.5 v operating mode s vcc power supply slope 1 s/v 10ms/v inputs v ih logic high 0.8v cc v v il logic low 0.2 v cc v i ip input pull-up current v cc =5.5v, v in =0v 30 65 350 a i tl tri-state leakage v cc =5.5v 2 200 na v ol output low voltage - v ol v cc = 3.3v 5.5v g0, g1, g2, g4, g6, g7 5.0 ma sink 0.2 v cc v g5 10.0 ma sink 0.2 v cc v v cc = 2.7v 3.3v 3.0 ma sink 0.2 v cc v 5.0 ma sink 0.2 v cc v v oh output high voltage - v oh v cc = 3.3v 5.5v g0, g1, g2, g4, g6, g7 0.4 ma source 0.8 v cc v g5 1.0 ma source 0.8 v cc v v cc = 2.7v 3.3v 0.4 ma source 0.8 v cc v 0.8 ma source 0.8 v cc v * based on continuous idle looping.
5 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications preliminary ace1202b ac electrical characteristics for v cc = 2.7 to 5.5v parameter conditions min typ max units instruction cycle time from 5.0v at 25 c 0.9 1.00 1.1 s internal clock - setpoint internal clock voltage dependent 3.0v to 5.5v, 5% frequency variation constant temperature internal clock temperature 3.0v to 5.5v, 10% dependent frequency variation full temperature range internal clock frequency 3.0v to 4.5v for 2% deviation for 0.5v drop ace1202be, t=constant crystal oscillator frequency (note 1) 4 mhz external clock frequency (note 2) 4 mhz eeprom write time 3 10 ms internal clock start up time (note 2) 2 ms oscillator start up time (note 2) 2400 cycles note 1: the maximum permissible frequency is guaranteed by design but not 100% tested. note 2: the parameter is guaranteed by design but not 100% tested. ace1202b electrical characteristics for programming all data valid at ambient temperature between 4.5v and 5.5v. see eeprom write time in the ac characteristics for definition of the programming ready time. the following characteristics are guaranteed by design but are not 100% tested. parameter description min max units t hi clock high time 500 dc ns t lo clock low time 500 dc ns t dis shift_in setup time 100 ns t dih shift_in hold time 100 ns t dos shift_out setup time 100 ns t doh shift_out hold time 900 ns t sv1 , t sv2 load supervoltage timing 50 us t load1 , t load2 , t load3 , t load4 load timing 5 us v supervoltage supervoltage level 11.5 12.5 v
6 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications absolute maximum ratings ambient storage temperature -65 c to +150 c input voltage not including g3 -0.3v to vcc+0.3v g3 input voltage 0.3v to 13v lead temperature (10s max) +300 c electrostatic discharge on all pins 2000v min operating conditions operating supply voltage excluding eeprom write: 0 c to +70 c 2.0v to 5.5v (based on preliminary data) relative humidity (non-condensing) 95% preliminary ace1202l dc electrical characteristics for v cc = 2.0 to 5.5v all measurements valid for ambient operating temperature range unless otherwise stated. symbol parameter conditions min typ max units i cc supply current 2.0v 0.4 0.5 ma no eeprom write in progress i cch halt mode current 2.0v, 0 c to 70 c 10 100 na i cci idle mode current 2.0v 30 50 a v ccw eeprom write voltage write not allowed for v v cc < 2.4v s vcc power supply slope 1us/v 10ms/v inputs v ih logic high 0.8 v cc v v il logic low 0.2 v cc v i ip input pull-up current v cc =5.5v, v in =0v 30 65 350 a i tl tri-state leakage v cc =5.5v 2 200 na v ol output low voltage v cc = 3.3v 5.5v g0, g1, g2, g4, g6, g7 5.0 ma sink 0.2 v cc v g5 10.0 ma sink 0.2 v cc v v cc = 2.0v 3.3v g0, g1, g2, g4, g6, g7 0.8 ma sink 0.36 v cc v g5 10.0 ma sink 0.36 v cc v v oh output high voltage v cc = 3.3v 5.5v g0, g1, g2, g4, g6, g7 0.4 ma source 0.8 v cc v g5 1.0 ma source 0.8 v cc v v cc = 2.0v 3.3v g0, g1, g2, g4, g6, g7 0.1 ma source 1.44 v cc v g5 0.2 ma source 1.44 v cc v
7 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications preliminary ace1202l ac electrical characteristics for v cc = 2.0 to 5.5v parameter conditions min typ max units instruction cycle time from 5.0v at 25 c 0.9 1.00 1.1 s internal clock - setpoint internal clock voltage dependent 3.0v to 5.5v, 5% frequency variation constant temperature internal clock temperature 3.0v to 5.5v, 10% dependent frequency variation full temperature range internal clock frequency 3.0v to 4.5v for 2% deviation for 0.5v drop ace1202e, t=constant crystal oscillator frequency (note 1) 4 mhz external clock frequency (note 2) 4 mhz eeprom write time 5 10 ms internal clock start up time (note 2) 2 ms oscillator start up time (note 2) 2400 cycles note 1: the maximum permissible frequency is guaranteed by design but not 100% tested. note 2: the parameter is guaranteed by design but not 100% tested.
8 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 3.0 ace1202 ac & dc characteristic graphs the graphs in this section are for design guidance and are based on prelimintest data figure 2: rc oscillator frequency (v cc =5.0v) figure 3: rc oscillator frequency (v cc =2.5v) figure 4: internal oscillator frequency 1600 1800 2000 2200 -45 -5 25 90 130 temperature [ c] 5.0v 5.5v 4.5v 4.0v 3.5v 2.2v 1.000 1.200 1.400 1.600 1.800 2.000 2.200 2.400 2.600 3.3k/82pf 5.6k/100pf 6.8k/100pf resistor & capacitor values [k & pf] avg min max 0.600 0.800 1.000 1.200 1.400 1.600 3.3k/82pf 5.6k/100pf 6.8k/100pf resistor & capacitor values [k & pf] avg min max frequency (mhz) frequency (mhz) frequency (khz)
9 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications name parameter unit v cc supply voltage [v] v batt battery voltage (nominal operating voltage) [v] t s min minimum time for v cc to rise by 1v [ms] t s actual actual time for v cc to rise by 1v [ms] t s max maximum time for v cc to rise by 1v [ms] s vcc power supply slope [ms/v] t s min t s actual t s max time v cc v batt 1v figure 5: power supply rise time
10 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 0.380 0.400 0.420 0.440 0.460 0.480 0.500 0.520 130 95 25 -5 -20 -45 temperature [ c] vcc=3.0v 1.040 1.050 1.060 1.070 1.080 1.090 1.100 1.110 130 95 25 -5 -20 -45 temperature [ c] vcc=4.5v 1.240 1.260 1.280 1.300 1.320 1.340 130 95 25 -5 -20 -45 temperature [ c] vcc=5.0v 1.440 1.460 1.480 1.500 1.520 1.540 1.560 1.580 1.600 130 95 25 -5 -20 -45 temperature [ c] vcc=5.5v figure 6: i cc active current (ma) current (ma) current (ma) current (ma)
11 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 0 50 100 150 200 250 300 350 130 95 25 -5 temperature [ c] vcc=3.3v 0 200 400 600 800 1000 1200 1400 130 95 25 -5 temperature [ c] vcc=5.5v figure 7: halt current halt current (na) halt current (na)
12 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications v cc v cc optional led rf stage rf interface g0 g1 g5 g2 gnd g4 g3 figure 8: ace1202 application example (remote keyless entry) v cc gnd g2 g3 g4 nc g6 g7 g5 g0 1 2 3 4 5 6 7 14 13 12 11 10 9 8 nc nc reset g1 v cc gnd g1 g3 g4 g5 g0 1 2 3 4 8 7 6 5 g2 v cc gnd sft_o load sft_i nc g6 g7 g5 go 1 2 3 4 5 6 7 14 13 12 11 10 9 8 nc nc reset cki v cc gnd cki load sft_i g5 go 1 2 3 4 8 7 6 5 sft_o figure 9: ace1202 pinout C normal operation figure 10: ace1202 pinout C programming mode
13 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 4.0 arithmetic controller core the ace1202 core is specifically designed for low cost applica- tions involving bit manipulation, shifting and block encryption. it is based on a modified harvard architecture meaning peripheral, i/o, and ram locations are addressed separately from instruction data. the core differs from the traditional harvard architecture by aligning the data and instruction memory sequentially. this allows the x-pointer (12-bits) to point to any memory location in either figure 11: programming model 8-bit accumulator register 12-bit x pointer register 11-bit program counter 4-bit stack pointer 8-bit status register negative flag half carry flag (from bit 3) carry flag (from msb) zero flag global interrupt mask ready flag (from eeprom) a x pc sp sr 0 0 0 0 n h c z g 0 0 r 7 11 10 3 segment of the memory map. this modification improves the overall code efficiency of the ace1202 and takes advantage of the flexibility found on von neumann style machines. 4.1 cpu registers the ace1202 has five general purpose registers. they are the a, x, pc, sp, and sr. the x, sp and sr are memory mapped registers.
14 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 4.1.1 accumulator accumulator a is general-purpose 8-bit register that holds oper- ands and results of arithmetic calculations or data manipulations. 4.1.2 x pointer the x register provides an 12-bit indexing value that can be added to an 8-bit offset provided in an instruction to create an effective address. the x register can also be used as a counter or as a temporary storage register. 4.1.3 program counter (pc) the program counter, a 11-bit register, contains the address of the next instruction to be executed. after reset, the program counter is initialized to 0x800 in normal mode. 4.1.4 stack pointer (sp) the ace1202 has an automatic program stack. this stack can be initialized to any location between addresses 0x30-0x3f. by default, the stack is initialized to 0x3f. normally, the sp is initialized by one of the first instructions in an application program. the stack is configured as a data structure that decrements from high memory to low memory. each time a new address is pushed onto the stack, the sp is decremented by two. each time an address is pulled from the stack, the sp is incremented by two. at any given time, the sp points to the next free location in the stack. when a subroutine is called by a jump to subroutine (jsr), the address of the instruction, after the jsr instruction, is automati- cally pushed onto the stack least significant byte first. when the subroutine is finished, a return from subroutine (ret) instruction is executed. the ret pulls the previously stacked return address from the stack, and loads it into the program counter. execution then continues at this recovered return address. 4.1.5 status register (sr) this 8-bit register contains four condition code indicators (c, h, z, and n), one interrupt masking bit (g), and an eeprom write flag (r). in the ace1202, condition codes are automatically updated by most instructions. carry/borrow (c) the c bit is set if the arithmetic logic unit (alu) performs a carry or borrow during an arithmetic operation. the rotate instruction operates with and through the carry bit to facilitate multiple-word shift operations. the ldc and invc instructions facilitate direct bit manipulation using the carry flag. half carry (h) the half carry flag indicates whether an overflow has taken place on the boundary between the two nibbles in the accumulator. it is primarily used for bcd arithmetic calculation. zero (z) the z bit is set if the result of an arithmetic, logic, or data manipulation operation is zero. otherwise, the z bit is cleared. negative (n) the n bit is set if the result of an arithmetic, logic, or data manipulation operation is negative (msb = 1). otherwise, the n bit is cleared. a result is said to be negative if its most significant bit (msb) is a one. interrupt mask (g) the interrupt request mask (g) is a global mask that disables all maskable interrupt sources. until the g bit is set, interrupts can become pending, but the operation of the cpu continues uninterrupted. after any reset, the g bit is cleared by default and can only be set by a software instruction. when an interrupt is recognized, the g bit is cleared after the pc is stacked and the interrupt vector is fetched. after the interrupt is serviced, a return from interrupt instruction is normally executed to restore the pc to the value that was present before the interrupt occurred. the g bit is set after a return from interrupt is executed. although the g bit can be set within an interrupt service routine, nesting interrupts in this way should only be done when there is a clear understanding of latency and of the arbitration mechanism. 4.2 interrupt handling when an interrupt is recognized, the current instruction completes its execution. the return address (the current value in the program counter) is pushed onto the stack and execution continues at the address specified by the unique interrupt vector (see table 9). this process takes five instruction cycles. at the end of the interrupt service routine, a reti instruction is executed. the reti instruction causes the saved address to be pulled off the stack in reverse order. the g bit is set and program execution resumes at the return address. the ace1202 is capable of supporting four interrupts. three are maskable through the g bit of the status register and the fourth (software interrupt) is not inhibited by the g bit (see figure 12). (see table 6 for the interrupt priority sequence.) the software interrupt instruction is executed in a manner similar to other maskable interrupts in that the program counter registers are stacked. how- ever, with a software interrupt, the g bit is not effected. this means, when returning from a software interrupt, a ret instruction should be used rather than using the reti instruction. the reti instruction will set the g bit. 4.3 addressing modes the ace1202 has seven addressing modes. indexed in this addressing mode, a 8-bit unsigned offset value is added to the x-pointer yielding a new effective address. this mode can be used to address any memory location (instruction or data). indirect this is the normal addressing mode. the operand is the data memory addressed by the x-pointer. table 6: interrupt priority sequence interrupt priority (4 highest, 1 lowest) miw 4 timer0 3 timer1 2 software 1
15 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications figure 12: ace1202 basic interrupt structure sw t1 int. pend. flags int. source & priority int. enable bits global int. enable gie t0 miwu
16 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications direct the instruction contains an 8-bit address field that directly points to the data memory for the operand. immediate the instruction contains an 8-bit immediate field as the operand. inherent this instruction has no operand associated with it. absolute this mode is used with the jmp and jsr instructions, with the instruction field replacing the 11-bits in the program counter. this allows jumping to any location in the memory map. relative this mode is used for the jp and the bit manipulation instructions, where the instruction field being added to the program counter to get the new program location. table 7: instruction addressing modes instruction immediate direct indexed indirect inherent relative absolute adc a, # a, m a, [x] add a, # a, m a, [x] and a, # a, m a, [x] or a, # a, m a, [x] subc a, # a, m a, [x] xor a, # a, m a, [x] clr max inc max dec max ifeq a, # x, # m,# a, m a, [00,x] a, [x] ifgt a, # x, # a, m a, [00,x] a, [x] ifne a, # a, m a, [00,x] a, [x] iflt x, # sc no-op rc no-op ifc no-op ifnc no-op invc no-op ldc #, m stc #, m rlc ma rrc ma ld a, # x, # m, # a, m a, [00,x] a, [x] st a, m a, [00,x] a, [x] ld m, m nop no-op ifbit #, a #, m sbit #, m #, [x] rbit #, m #, [x] jp rel jsr a, [00,x] m,m+1 jmp a, [00,x] m,m+1 ret no-op reti no-op intr no-op
17 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications table 8: instruction addressing modes mnemonic operand bytes cycles flags affected adc a, [x] 1 1 c,h,z,n adc a, m 2 2 c,h,z,n adc a, # 2 2 c,h,z,n add a, [x] 1 1 z,n add a, m 2 2 z,n add a, # 2 2 z,n and a, # 2 2 z,n and a, m 2 2 z,n and a, [x] 1 1 z,n clr x 1 1 z clr a 1 1 c,z,n clr m 2 1 c,z,n dec a 1 1 z,n dec m 2 2 z,n dec x 1 1 z ifbit #, a 1 1 none ifbit #, m 2 2 none ifc 1 1 none ifeq a, [00,x] 2 2 none ifeq a, [x] 1 1 none ifeq a, # 2 2 none ifeq a, m 2 2 none ifeq m, # 3 3 none ifeq x, # 3 3 none ifgt a, # 2 2 none ifgt a, [00,x] 2 2 none ifgt a, [x] 1 1 none ifgt a, m 2 2 none ifgt x, # 3 3 none ifne a, # 2 2 none ifne a, [00,x] 2 2 none ifne a, [x] 1 1 none ifne a, m 2 2 none iflt x, # 3 3 none ifnc 1 1 none inc a 1 1 z,n inc m 2 2 z,n inc x 1 1 z intr 1 5 none invc 1 1 c mnemonic operand bytes cycles flags affected jmp [00,x] 2 3 none jmp m, m+1 3 4 none jp 1 1 none jsr m, m+1 3 5 none jsr [00,x] 2 5 none ld a, # 2 2 none ld a, [00,x] 2 3 none ld a, [x] 1 1 none ld a, m 2 2 none ld m, # 3 3 none ld x, # 3 3 none ldc #, m 2 2 c ld m, m 3 3 none nop 1 1 none or a, # 2 2 z,n or a, [x] 1 1 z,n or a, m 2 2 z,n rbit #, [x] 1 2 z,n rbit #, m 2 2 z,n rc 1 1 c ret 1 5 none reti 1 5 none rlc a 1 1 c,z,n rlc m 2 2 c,z,n rrc a 1 1 c,z,n rrc m 2 2 c,z,n sbit #, [x] 1 2 z,n sbit #, m 2 2 z,n sc 1 1 c st a, [00,x] 2 3 none st a, [x] 1 1 none st a, m 2 2 none stc #, m 2 2 z,n subc a, # 2 2 c,h,z,n subc a, [x] 1 1 c,h,z,n subc a, m 2 2 c,h,z,n xor a, # 2 2 z,n xor a, [x] 1 1 z,n xor a, m 2 2 z,n
18 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 4.4 memory map all i/o ports, peripheral registers and core registers, except the accumulator and the program counter are mapped into memory s pace. table 9: memory map address block contents 0x00 - 0x3f sram data ram 0x40 - 0x7f data eeprom non-volatile parameters 0xaa timer1 t1ralo register 0xab timer1 t1rahi register 0xac timer1 tmr1lo register 0xad timer1 tmr1hi register 0xae timer1 t1cntrl register 0xaf miwu wkedg register 0xb0 miwu wkpnd register 0xb1 miwu wken register 0xb2 i/o portgd register 0xb3 i/o portgc register 0xb4 i/o portgp register 0xb5 timer0 wdsvr register 0xb6 timer0 t0cntrl register 0xb7 clock halt mode register 0xb8 - 0xbc reserved 0xbd lbd lbd register 0xbe core xhi register 0xbf core xlo register 0xc0 core power mode clear (pmc) register 0xce core sp register 0xcf core status register 0x800 - 0xff5 code eeprom/rom instruction data 0xff6 - 0xff7 core timer0 interrupt vector 0xff8 - 0xff9 core timer1 interrupt vector 0xffa - 0xffb core miwu interrupt vector 0xffc - 0xffd core software interrupt vector 0xffe - 0xfff reserved
19 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 4.5 memory the ace1202 device has 64 bytes of sram and 64 bytes of eeprom available for data storage. the microcontroller also has a 2k byte eeprom block for program storage. the user can read/ write to ram and data eeprom but cannot perform writes to the 2k byte eeprom array which is protected from writes during normal mode operations. the instruction data in the program eeprom array can only be rewritten when the device is in program mode and if the initialization register bit wdis (write disable) is not set. while in normal mode, the user can write to the data eeprom array by 1) polling the r bit of the status register, then 2) executing the appropriate write instruction. a "1" on the r bit indicates the data eeprom block is ready to perform the next write. a "0" indicates the data eeprom is busy. the data eeprom array will reset the r bit on the completion of a write cycle. attempts to read, write, or enter halt while the data eeprom is busy (r bit = "0") could affect the current data being written. 4.6 initialization registers the ace1202 has two 8-bit wide initialization registers. these registers are read from memory space on power-up and initializes certain on-chip peripherals. figure 13 provides a detailed descrip- tion of initialization register 1. the initialization register 2 is used to trim the internal oscillator. this register is pre-programmed in the factory to yield a 1mhz internal clock. both initialization registers 1 and 2 are read/writable in program- ming mode. however, retrimming the internal oscillator (writing to the initialization register 2) is discouraged . figure 13: initialization register 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmode0 cmode1 wden boren lbden ubd wdis rdis (0) rdis if set, disables attempts to read any eeprom contents in programming mode (1) wdis if set, disables attempts to write any eeprom contents in programming mode (2) ubd if set, the device will not allow writes to occur in the upper block of data eeprom (3) lbden 1 enables lbd, 0 disables lbd (4) boren if set, allows a brown-out reset to occur if vcc is so low that a reliable eeprom write cannot take place (5) wden if set, enables the on-chip processor watchdog circuit (6) cmode1 clock mode select bit one (7) cmode0 clock mode select bit zero note 1: if wdis and rdis bits are both set, the device will no longer be able to be placed into program mode. note 2: if the rdis or ubd bits are not set while the wdis bit is not set, then the rdis and ubd bits could be reset.
20 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 5.0 timer 1 timer1 is a versatile 16-bit timer which can operate in one of four modes: ? pulse width modulatio n (pwm) mode, which generates pulses of a specified width and duty cycle ? external event counter mode, which counts occurrences of an external event ? standard input capture mode, which measures the elapsed time between occurrences of external events ? difference input capture mode, which automatically measure the difference between edges. timer1 contains a 16-bit timer (counter) register, designated tmr1, and one 16-bit autoreload (capture) register, designated t1ra. these 16-bit registers are organized as a pair of 8-bit memory mapped register bytes, tmr1hi and tmr1lo, and t1rahi and t1ralo. the timer (counter) block uses one i/o pin, designated t1, which is the alternate function of g2. the timer can be started or stopped under program control. when running, the timer counts down (decrements). depending on the operating mode, the timer counts either instruction clock cycles or transitions on the t1 pin. occurrences of timer underflows (tran- sitions from 0x0000 to 0xffff) can either generate an interrupt and/or toggle the t1 pin, also depending on the operating mode. there is one interrupt associated with the timer, designated the timer1 interrupt. when timer interrupt is enabled, the source of the interrupt depends on the timer operating mode: either a timer underflow, or a transfer of data to or from the t1ra register. by default, the timer register is reset to ffff and the reload register is reset to 0000. 5.1 timer control bits timer1 is controlled by reading and writing to the t1cntrl register. by programming the control bits, the user can enable or disable the timer interrupts, set the operating mode, and start or stop the timer. the control bits operate as described in tables 10 and 11. table 10: timer1 control register bits t1cntrl register name function bit 7 t1c3 timer timer1 control bit 3 (see table 11) bit 6 t1c2 timer timer1 control bit 2 (see table 11) bit 5 t1c1 timer timer1 control bit 1 (see table 11) bit 4 t1c0 timer timer1 run: 1 = start timer, 0 = stop timer; or timer timer1 underflow interrupt pending flag in input capture or difference capture modes bit 3 t1pnda timer1 interrupt pending flag: 1 = timer1 interrupt pending, 0 = timer1 interrupt not pending bit 2 t1ena timer1 interrupt enable bit: 1 = timer1 interrupt enabled, 0 = timer1 interrupt disabled bit 1 m4s1 selects capture types 0 = pulse capture 1 = cycle capture bit 0 ----------- reserved table 11: timer operating modes t1 t1 t1 m4 timer mode interrupt a timer counts on c3 c2 c1 s1 source 0 0 0 x mode 2 timer underflow t1a pos. edge 0 0 1 x mode 2 timer underflow t1a neg. edge 1 0 1 x mode 1 t1a toggle autoreload t1ra instruction clock 1 0 0 x mode 1 no t1a toggle autoreload t1ra instruction clock 0 1 0 x mode 3 captures: t1a pos. edge pos. t1a edge instruction clock 0 1 1 x mode 3 captures: t1a neg. edge neg. t1a edge instruction clock 1 1 0 0 mode 4 difference capture pos. to neg. instruction clock 1 1 0 1 mode 4 difference capture pos. to pos. instruction clock 1 1 1 0 mode 4 difference capture neg. to pos. instruction clock 1 1 1 1 mode 4 difference capture neg. to neg. instruction clock
21 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 5.2 mode 1: pulse width modulation mode in the pulse width modulation (pwm) mode, the timer counts down at the instruction clock rate. when an underflow occurs, the timer register is reloaded from t1ra, and decrementing proceeds from the loaded value. at every underflow interrupt, software should load the t1ra register with the alternate pwm value. the timer can be configured to toggle the t1 output bit upon underflow. this results in the generation of a clock signal on t1 with the width and duty cycle controlled by the values stored in the t1ra. a block diagram of the timer operating in the pwm mode is shown in figure 14. there is one interrupt associated with the timer, designated the timer1 interrupt. the interrupt is maskable by the enable bit t1en. t1 will generate an interrupt with every timer underflow if the timer interrupt is enabled by t1en. the interrupt will be simultaneous with every rising and falling edge of the pwm output. generating interrupts only on rising-, or falling edges of t1 is achievable through appropriate handling of t1en by the user software. when an underflow occurs that causes a timer reload from t1ra, the interrupt pending flag bit t1pnda is set. a cpu interrupt occurs if t1en bit and the g (global interrupt enable) bit of the status register is set. the interrupt service routine must reset the pending bit and perform whatever processing is necessary at the interrupt point. timer underflow interrupts instruction clock t1 bus 16-bit autoreload register t1ra 16-bit timer data latch figure 14: pulse width modulation mode the following steps can be used to operate the timer in the pwm mode. in this example, the t1 output pin is toggled with every timer underflow, and the high and low times for the t1 output can be set to different values. the t1 output can start out either high or low; the instructions below are for starting with the t1 output high. (follow the instructions in parentheses to start the t1 output low.) 1. configure the t1 pin as an output by setting bit 2 of portgc. 2. initialize the t1 pin value to 1 (or 0) by setting (or clearing) bit 2 of portgd. 3. load the pwm high or low time into the timer register. 4. load the pwm low or high time into the t1ra register. 5. write the appropriate value to the timer control bits t1c3- t1c2- t1c1 to select the pwm mode, and to toggle the t1 output with every timer underflow (see table 11). 6. set the t1c0 bit to start the timer. 7. upon every underflow interrupt load t1ra with alternate values, on or off time. if the user wishes to generate an interrupt on timer output transitions, reset the pending flags and then enable the interrupt using t1en. the g bit must also be set. the interrupt service routine must reset the pending flag and perform whatever processing is desired.
22 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 5.3 mode 2: external event counter mode the external event counter mode is similar to the pwm mode, except that instead of counting instruction clock pulses, the timer counts transitions received on the t1 pin (configured as an input). the t1 pin should be connected to an external device that generates a pulse for each event to be counted. the input signal on t1 must have a pulse width equal to or greater than one instruction cycle. the timer can be configured to sense either positive-going or negative-going transitions on the t1 pin. the maximum frequency at which transitions can be sensed is one-half the frequency of the instruction clock. as with the pwm mode, when an underflow occurs, the timer register is reloaded from the t1ra registers, and counting pro- ceeds downward from the loaded value. a block diagram of the timer operating in the external event counter mode is shown in figure 15. the following steps can be used to operate the timer in the external event counter mode. 1. configure the t1 pin as an input by clearing bit 2 of portgc. 2. load the initial count into the timer register and the t1ra timer underflow interrupts edge selector logic t1 bus 16-bit autoreload register t1ra 16-bit timer (counter) figure 15: external event counter mode register. when this number of external events is detected, the counter will reach zero, however, it will not underflow until the next event is detected. to count n pulses, load the value n-1 into the registers. if it is only necessary to count the number of occurrences and no action needs to be taken at a particular count, load the value 0xffff into the registers. 3. in order to generate an interrupt each time the timer underflows, clear the t1pnd pending flag and then enable the interrupt by setting the t1en bit. the g bit must also be set. 4. write the appropriate value to the timer control bits t1c3- t1c2- t1c1 to select the external event counter mode, and to select the type of transition to be sensed on the t1 pin (positive-going or negative-going; see table 11). 5. set the t1c0 bit register to start the timer. if interrupts are being used, the timer1 interrupt service routine must clear the t1pnd flag and take whatever action is required when the timer underflows. if the user wishes to merely count the number of occurrences of an event, and anticipates that the number of events may exceed 65,536, the interrupt service routine should record the number of underflows by incrementing a counter in memory. on each underflow, the timer (counter) register is reloaded with the value from the t1ra register.
23 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 5.4 mode 3: input capture mode in the input capture mode, the t1 pin is configured as input. the timer counts down at the instruction clock rate. a transition received on the t1 pin causes a transfer of the timer contents to the t1ra register. the input signal on t1 must have a pulse width equal to or greater than one instruction cycle. (refer to the ac electrical specifications for this device.) the values captured in the t1ra register at different times reflect the elapsed time between transitions on the t1 pin. the input pin can be configured to sense either positive-going or negative-going transitions. a block diagram of the timer operating in the input capture mode is shown in figure 16. there are two interrupt events associated with the input capture mode: input capture in t1ra and timer underflow. if interrupts are enabled, a timer1 interrupt is triggered by either an input capture in t1ra or a timer underflow. in this operating mode, the t1c0 co ntrol bit serves as the timer underflow interrupt pending flag. the timer1 interrupt service routine can look at this flag and the t1pnd flag to determine what caused the interrupt. a set t1c0 flag means that a timer underflow occurred, whereas a set t1pnd flag means that an input capture occurred in t1ra. it is possible that both flags will be found set, meaning that both events occurred at the same time. the interrupt routine should take this possibility into consideration. because the t1c0 bit is used as the underflow interrupt pending flag, it is not available for use as a start/stop bit as in the other modes. the timer register counts down continuously at the instruction clock rate, starting from the time that the input capture mode is selected with bits t1c3-t1c2-t1c1. to stop the timer from running, you must change from the input capture mode to the pwm or external event counter mode and reset the t1c0 bit. the input pins can be independently configured to sense positive- going or negative-going transitions, resulting in two possible input capture mode configurations. the edge sensitivity of pin t1 is controlled by bit t1c1 as indicated in table 11. the edge sensitivity of a pin can be changed without leaving the input capture mode by setting or clearing the appropriate control bit (t1c1), even while the timer is running. this feature allows you to measure the width of a pulse received on an input pin. for example, the t1 pin can be programmed to be sensitive to a positive-going edge. when the positive edge is sensed, the timer contents are transferred to the t1ra register, and a t imer1 interrupt is generated. the t imer1 int a int a instruction clock edge selector logic t1 internal bus 16-bit timer 16-bit input capture t1ra figure 16: input capture mode interrupt service routine records the contents of the t1ra register and also reprograms the input capture mode, changing the t1 pin from positive to negative edge sensitivity. when the negative-going edge appears on the t1 pin, another t imer1 interrupt is generated. the interrupt service routine reads the t1ra register again. the difference between the previous reading and the current reading reflects the elapsed time between the positive edge and negative edge on the t1 input pin, i.e., the width of the positive pulse. remember that the timer1 interrupt service routine must test the t1c0 and t1pnd flags to determine what caused the interrupt. the software that measures elapsed time must take into account the possibility that an underflow occurred between the first and second readings. this can be managed by using the interrupt triggered by each underflow. the timer1 interrupt service routine, after determining that an underflow caused the interrupt, should record the occurrence of an underflow by incrementing a counter in memory, or by some other means. the software that calculates the elapsed time should check the status of the underflow counter and take it into account in making the calculation. the following steps can be used to operate the timer in the input capture mode. 1. configure the t1 pin as input by clearing bit 2 of portg2. 2. with the timer configured to operate in the pwm or external event counter mode (t1c2 equal to 0), reset the t1c0 bit. this stops the timer register from counting. 3. load the initial count into the timer register, typically the value 0xffff to allow the maximum possible number of counts before underflow. 4. clear the t1pnd interrupt pending flag, then set the t1en interrupt enable bit. the g bit should also be set. the interrupt is now enabled. 5. write the appropriate value to the timer control bits t1c3- t1c2- t1c1 to select the input capture mode, and to select the types of transitions to be sensed on the t1 pin (positive- going or negative-going; see table 11). as soon as the input capture mode is enabled, the timer starts counting. when the programmed type of edge is sensed on the t1 pin, the t1ra register is loaded and a timer1 interrupt is triggered. a timer1 interrupt is also triggered when an underflow occurs in the timer register. the interrupt service routine tests both the t1pnd and t1c0 flags to determine the cause of the interrupt, resets the pending bit, and performs the required task, such as recording the t1ra register contents or incrementing an underflow counter.
24 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 5.5 mode 4: difference input capture mode the difference capture mode is similar to the standard capture mode. the difference is the difference capture timer will automati- cally capture the difference between selectable edges. for example, a standard capture timer must be configured to capture a particular edge (rising or falling) at which time the timer value is copied into a capture register. if more information is required, software must move the captured data to ram and reconfigure the capture timer to capture on the next edge (rising or falling). software must then subtract the difference between the two edges to yield useful information. the difference capture timer eliminates the need for software intervention and allows for capturing very short pulse widths. the difference capture timer can be programmed to capture: 1. positive-edge to negative-edge 2. positive-edge to positive-edge 3. negative-edge to positive-edge 4. negative-edge to negative-edge once configured, the difference capture timer waits for the se- lected edge. when an edge transition has occurred, the 16-bit timer starts counting up based on the instruction clock. it will continue to count until the second edge transition occurs at which time the timer stops and stores the elapse time into the t1ra register. software can now read the difference between transitions directly without using any processor resources. this feature allows the ace1202 to capture very small pulses where standard microcontrollers might have missed due to limited bandwidth instruction clock edge selector logic t1 internal bus 16-bit timer difference logic figure 17: difference capture mode
25 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 6.0 timer 0 timer 0 is a 12-bit idle timer. upon power up or any reset, the timer is reset to 0 and then counts up continuously based on the instruction clock of 1mhz (1 s). software cannot read from or write to this timer. however, software can monitor the timer's pending (t0pnd) bit which is set every 4.096ms. the t0pnd is set each time the timer overflows (counts up to fffh). after an overflow, the timer will reset and restart its count up sequence. software can either poll the t0pnd bit or vector to interrupt routine. in order to interrupt on a t0pnd, software will need to make sure the interrupt enable (t0inten) bit is set in the t0cntrl register and also make sure the global interrupt bit (g) is set in the status register. once the timer interrupt is serviced, software should reset the t0pnd bit before exiting the routine. the timer 0 supports the following functions: 1. start up delay from halt mode. 2. watchdog prescaler. (see section 7 for details.) the timer 0 interrupt enable (t0inten) bit is a read/write bit. if set to 0, interrupt requests from the timer 0 are ignored. if set to 1, interrupt requests are accepted. the t0inten bit is set to zero at reset. the t0pnd (timer 0 pending) bit is a read/write bit. if set to "1," it indicates that a timer 0 interrupt is pending. this bit is set by a timer 0 overflow and is reset by software or reset. the wkinten bit is used in the multi-input wakeup block. (see section 8 for details.) 7.0 watchdog timer the 12-bit timer 0 is also used to clock the watchdog timer. if the wden bit in the initialization register is asserted, the watchdog timer must be updated at least every 65,536 cycles but no sooner than 4096 cycles since the last watchdog update. the watchdog is updated through software by writing the value 0x1bh to the wdsvr register (see figure 19). the part will be reset automati- cally if the watchdog is updated too frequently, or not frequently enough. the wden bit can only be set while the device is in programming mode. once set, the watchdog will always be powered up enabled. software cannot disable the watchdog. the watchdog timer can be disabled in programming mode by reset- ting the wden bit as long as the global write protect feature is not enabled (wdis). figure 18: timer 0 control register (t0cntrl) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wkinten x x x x x t0pnd t0inten figure 19: watchdog service register (wdsvr) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00011011
26 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 8.0 multi-input wakeup block there are three memory-mapped registers associated with this circuit: wkedg (wakeup edge), wken (wakeup enable), and wkpnd (wakeup pending). each register has eight bits, with the six least significant bits corresponding to one of the input pins shown in figure 20. all three registers are initialized to zero with a reset. the wkedg register establishes the edge sensitivity for each of the port input pins: either positive-going edges (0) or negative- going edges (1). the wken register enables (1) or disables (0) each of the port pins for the wakeup/interrupt function. any pin to be used for the wakeup/interrupt function must also be configured as an input pin in the portgc configuration register. the wkpnd register contains the pending flags corresponding to each of the port pins (1 for wakeup/interrupt pending, 0 for wakeup/interrupt not pending). the t0cntrl register is the timer0 control register; however, bit 7 (wkinten) is used as the wakeup interrupt enable bit (see figure 18). by setting this bit the device can interrupt in the event of a multi-input wakeup (if the global interrupt bit is set). to use the multi-input wakeup/interrupt circuit, perform the steps listed below. performing the steps in the order shown will prevent false triggering of a wakeup/interrupt condition. this same proce- dure should be used following a reset because the wakeup inputs will be set to high-impedence, resulting in unknown data on the port inputs. 1. clear the wken register. 2. set the wken bit. 3. if necessary, write to the port configuration register to change the desired port pins from outputs to inputs. 4. write the wkedg register to select the desired type of edge sensitivity for each of the pins used. 5. clear the wkpnd register to cancel any pending bits. 6. set the wken bits associated with the pins to be used, thus enabling those pins for the wakeup/interrupt function. once the multi-input wakeup/interrupt function has been set up, a transition sensed on any of the enabled pins will set the corresponding bit in the wkpnd register. this brings the device out of the halt mode (if in that mode), and also triggers a maskable interrupt if that interrupt is enabled. the interrupt service routine can read the wkpnd register to determine which pin triggered the interrupt. the interrupt service routine or other software should clear the pending bit. the device will not enter the halt mode as long as any wkpnd pending bit is pending and enabled. the user has the responsibility of clearing the pending flags before attempting to enter the halt mode. after reset, the wkedg register is configured to select positive- going edge sensitivity for all wakeup inputs. if the user wishes to change the edge sensitivity of a port pin, use the following procedure to avoid false triggering of a wakeup/interrupt condi- tion. 1. disable the pin by clearing the associated bit in the wken register. 2. write to the associated bit of the wkedg register selecting the new edge sensitivity of the pin. 3. clear the wkpnd bit associated with the pin. 4. re-enable the pin by setting the associated wken bit. portg provides the user with eight fully selectable, edge sensi- tive interrupts which are all vectored into the same service subroutine. the interrupt from portg shares logic with the wake up circuitry. the wken register allows interrupts from portg to be individu- ally enabled or disabled. the wkedg register specifies the trigger condition to be either a positive or a negative edge. the wkpnd register latches the pending trigger conditions. since portg is also used for exiting the device from the halt mode, the user can elect to exit the halt mode either with or without the interrupt enabled. if the user elects to disable the interrupt, then the device restarts execution from the point at which it was stopped (first instruction cycle of the instruction following the enter halt mode instruction). in the other case, the device finishes the instruction which was being executed when the part was stopped (the nop instruction following the enter halt mode instruction), and then branches to the interrupt service routine. the device then reverts to normal operation. wkoutint internal data bus 50 g0 wkedg wkpnd wken g5 0 5 figure 20: multi-input wakeup (miwu) block diagram
27 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 9.0 i/o port the eight i/o pins are bi-directional (see figure 21) with the exception of g3 which is always an input with weak pull-up. the bi-directional i/o pins can be individually configured by software to operate as high-impedance inputs, inputs with weak pull-up, or as push-pull outputs. the operating state is determined by the contents of the corresponding bits in the data and configuration registers. each bi-directional i/o pin can be used for general purpose i/o, or in some cases, for a specific alternate function determined by the on-chip hardware. 9.1 i/o registers the i/o pins (g0-g7) have three memory port registers associ- ated with them: a port configuration register (portgc), a port data register (portgd), and a port input register (portgp). portgc is used to configure the pins as inputs or outputs. a pin may be configured as an input by writing a 0 or as an output by writing a 1 to its corresponding portgc bit. if a pin is configured as an output, its portgd bit represents the state of the pin (1 = logic high, 0 = logic low). if the pin is configured as an input, its portgd bit selects whether the pin is a weak pull-up or a high- impedence input. table 12 provides details of the port configura- tion options. the port configuration and data registers are both read/writeable. reading portgp returns the value of the port pins regardless of how the pins are configured. since this device supports multi-input wakeup/interrupt, portg inputs have schmitt triggers. table 12: i/o configuration options configuration bit data bit port pin configuration 0 0 high-impedence input (tri-state output) 0 1 input with pull-up (weak one output) 1 0 push-pull zero output 1 1 push-pull one output figure 21: portg logic diagram weak pull-up control portgc portgd portgp pingx
28 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 10.0 in-circuit programming specification for ace1202 the ace1202 supports in-circuit programming of the internal data eeprom, program eeprom, and the initialization registers. an externally controlled four wire interface consisting of a load control pin (g3), a serial data shift_in input pin (g4), a serial data shift_out output pin (g2), and a clock pin (g1) is used to access the on-chip memory locations. communication be- tween the ace1202 and the external programmer is made through a 32-bit command and response word described in table 13. the serial data timing for the four wire interface is shown in figure 22. the programming protocol is shown in figure 23. the external programmer brings the ace1202 into programming mode by applying a supervoltage level (v supervoltage ) to the load pin. the external programmer then needs to set the load pin to 5v before shifting in the 32-bit serial command word using the shift_in and the clock signals. by definition, bit 31 of the command word is shifted in first. at the same time, the ace1202 shifts out the 32-bit serial response to the last command on the shift_out pin. it is recommended that the external programmer samples this signal t access (850ns) after the rising edge of the clock signal. the serial response word sent immediately after entering programming mode contains indeterminate data. after 32 bits have been shifted into the ace1202, the external programmer must set the load signal to 0v, and then apply two clock pulses as shown in figure 23. when reading the device, the external programmer must set the load signal to 5v before it sends a new command word. when writing to the ace1202, the shift_out signal acts as the ready signal. the ace1202 sets shift_out low by the time the programmer has sent the second rising edge during the load = 0v phase (if the timing specifica- tions in figure 23 are obeyed). the ace1202 will set the r bit of the status register when the write operation has completed. the external programmer must wait for the r bit to go high before bringing the load signal to 5v to initiate a new command cycle. powering down the device will cause the part to exit programming mode. writing a series of bytes to the ace1202 is achieved by sending a series of command words with bit 24 set to 0. reading a series of bytes from the ace1202 is achieved by sending a series of command words with the desired addresses in sequence and reading the following response words to verify the correct address and reading the data contents. the addresses for the data eeprom and code eeprom spaces are the same as those used in normal operation. table 13: 32-bit command and response word bit number input command word output response word bits 31 C 30 must be set to 0 x bit 29 set to 1 to read/write data eeprom, x 0 otherwise bit 28 set to 1 to read/write code eeprom, x initialization registers 0 otherwise bits 27 C 25 must be set to 0 x bit 24 set to 1 to read, 0 to write x bits 23 C 19 must be set to 0 x bits 18 C 8 address of the byte to be read or written same as input command word bits 7 C 0 data to be programmed or zero if data is to be read programmed data or data read at specified address note 1: during in-circuit programming, pin 3 (g5) must be either not connected or driven high. note 2: for further information, see application note an-8005.
29 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications clock (g1) shift_in (g4) shift_out (g2) t hi t lo t dos t doh t dih t dis valid valid 12v clock shift_in shift_out (in read mode) shift_out (in write mode) t sv1 t sv2 t load1 t load2 t load3 t load4 t ready t load3 + ch1 * enter programming mode 32 clock pulses a: denotes start of programming cycle a a *in read mode busy low by 2nd clock pulse busy ready bit 0 bit 30 bit 31 5v 0v load figure 22 - serial data timing figure 23 - programming protocol
30 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 11.0 low battery detect circuit the low battery detect (lbd) circuit sets the lbd bit in the lbd register (see figure 24) when v cc drops below the selected threshold voltage. the threshold voltage can be adjusted from 2.4v to 3.0v 10% using the three most significant bits of the lbd register. the lbden (low battery detect enable) bit in the initialization register is used to enable or disable the low battery detection. the lbd bit is read only. if 0, it indicates that the v cc level is higher than the desired threshold. if set to 1, it indicates that the v cc level is below the desired threshold. the lbd circuit is disabled during halt mode. on exiting halt mode, the software must wait 10 s before reading the lbd bit to ensure that the circuit has stabilized. voltage bat_trim2 bat_trim1 bat_trim0 range 0 0 0 2.9 - 3.0 0 0 1 2.8 - 2.9 0 1 0 2.7 - 2.8 0 1 1 2.6 - 2.7 1 0 0 2.5 - 2.6 1 0 1 2.4 - 2.5 12.0 brown-out detection circuit the brown-out detect circuit is used to reset the device when vcc falls below a 2.0v threshold. once v cc rises above the 2.0v threshold, a reset sequence will be generated. the brown-out reset enable (boren) bit in the initialization register is used to enable or disable the brown-out detection. this bit must be set after the device has been programmed. brown-out is not supported on 2.2/2.7v devices. 13.0 reset block when a reset sequence is initiated, all i/o registers will be reset, setting all i/os to high impedence inputs. the system clock is restarted after the required clock start-up delay. a reset is gener- ated by any one of the following three conditions: power-on reset (as described in section 14) brown-out reset (as described in section 12) watchdog reset (as described in section 7) 14.0 power-on reset the power-on reset circuit is guaranteed to work if the rate of rise of v dd is no slower than 10ms/1 volt. it is also necessary that v dd starts from 0v. 15.0 clock the ace1202 has an on-board oscillator trimmed to a frequency of 2mhz, yielding a 1mhz frequency and a tolerance over tem- perature, voltage, and device of 10%. upon power-up, the on- chip oscillator runs continuously unless entering halt mode. if required, an external oscillator circuit may be used depending on the states of the cmode bits. (see table 14.) when the device is driven using an external clock, the clock input to the device (g1/ cki) can range between dc to 4mhz. for crystal configuration, the output clock (cko) is on the g0 pin. if an external crystal or external rc is used, it will be internally divided by four (input frequency/4) to yield an instruction clock cycle time of the corre- sponding input frequency. if the device is configured for an external square clock, it will not be divided. see figure 26. table 14: cmodex bit definition cmode1 cmode0 clock type 0 0 internal 1 mhz clock 0 1 external square clock 1 0 external crystal/resonator 1 1 external rc clock figure 24: lbd register definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bat_trim2 bat_trim1 bat_trim0 undefined undefined undefined undefined lbd figure 25: halt register definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 undefined undefined undefined undefined undefined undefined undefined ehalt
31 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications 33pf 33pf 1m cki (g1) cko (g0) a) c v cc r cki (g1) cko (g0) b) figure 26: crystal (a) and rc (b) oscillator diagrams 16.0 halt mode the ace1202 is placed into halt by setting bit 0 of the halt mode register using the ld m, # instruction. the halt enable bit (bit 0) is a write only bit and is automatically cleared on exiting halt. upon entering halt, the internal oscillator, as well as all on-chip systems, including low battery detect and brown out circuits, are shut down. prior to entering halt, software should set the figure 27: recommended halt flow normal mode halt resume normal mode ld halt, #01h ld pmc, #00h multi-input wakeup appropriate wake-up i/o configuration. the device can only be brought out of halt by multi-input wake up. after wake up from halt, a 1ms startup delay is initiated to allow the internal oscillator to stabilize before normal execution resumes. immediately after exiting halt, software must clear the power mode clear register also using a ld m, # instruction. see figure 27 below.
32 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications ordering information ace 12 02 x e mt8 x letter description x tape and reel package m8 8-pin so m 14-pin so n 8-pin dip n14 14-pin dip temp. range none 0 to 70 c e -40 to +85 c v -40 to +125 c operating voltage range none 2.2v - 5.5v b 2.7v - 5.5v l 2.0v - 5.5v density 02 2k code eeprom 12 8-bit microcontroller core type ace arithmetic controller engine
33 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications molded small out-line package (m8) order number ace1202m8/ace1202em8/ace1202vm8 package number m08a physical dimensions inches (millimeters) unless otherwise noted 1234 8765 0.189 - 0.197 (4.800 - 5.004) 0.228 - 0.244 (5.791 - 6.198) lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) 0.014 (0.356) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.0075 - 0.0098 (0.190 - 0.249) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident molded dual-in-line package (n) order number ace1202n/ace1202en/ace1202vn package number n08e
34 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications physical dimensions inches (millimeters) unless otherwise noted molded small out-line package (m) order number ace1202m/ace1202em/ace1202vm package number m14a 123 4567 14 13 12 11 10 9 8 0.335 - 0.344 (8.509 - 8.788) 0.228 - 0.244 (5.791 - 6.198) 0.010 (0.254) max. lead #1 ident seating plane 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 (0.356 - 0.508) typ. 0.053 - 0.069 (1.346 - 1.753) 0.050 (1.270) typ typ 0.008 (0.203) 0.014 (0.356) 0.016 - 0.050 (0.406 - 1.270) typ. all leads 8 max, typ. all leads 0.150 - 0.157 (3.810 - 3.988) 0.008 - 0.010 (0.203 - 0.254) typ. all leads 0.04 (0.102) all lead tips 0.010 - 0.020 (0.254 - 0.508) x 45 30 typ. molded dual-in-line package (n14) order number ace1202n14/ace1202en14/ace1202vn14 package number n14a
35 www.fairchildsemi.com ace1202 rev. e.1 ace1202 arithmetic controller engine (acex?) for low power applications fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841

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