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fedl9475-01 issue date: mar. 1, 2010 ML9475 1/3 or 1/4 duty, 40-output lcd driver 1/20 general description the ML9475 is an lcd driver for dynamic display. it has a function to switch between 1/3 and 1/4 duty. when 1/4 duty is selected, an lcd of up to 160 segments can be driven directly; when 1/3 duty is selected, an lcd of up to 120 segments can be driven directly. features ? logic power supply voltage : 2.7 to 3.6 v, 4.5 to 5.5 v ? driver power supply voltage : 3.5 to 5.5 v ? operating temperature : ? 40 to +105c ? 40 segment outputs 1/4 duty : up to 160 segments can be displayed. 1/3 duty : up to 120 segments can be displayed. ? serially interfaces with the cpu using the th ree signal lines of load, data_in, and clock ? built-in rc oscillator circuit for lcd ac drive (the clksel pin allows selecting an external clock input) ? built-in voltage-dividing resistor for bias voltage generation ? package : 56-pin plastic qfp (qfp56-p-910-0.65-2k)
fedl9475-01 ML9475 2/20 block diagram 40-dot segment driver 40-bit latch4 latch selector load osc latch3 latch1 latch2 data_in clock 3/4sel dvdd vss timing generator 40-ch data selector common driver seg1 seg40 com1 40 46(40 + 6)-bit shift register 40-bit 40-bit 40-bit 40 40 40 com2 com3 com4 lvdd clksel bias res. 40 test osc rese t
fedl9475-01 ML9475 3/20 pin configuration (top view) 56-pin plastic qfp com1 com2 com3 com4 clksel vss osc lvdd 3/4sel test rese t nc data_in clock seg1 load seg2 seg40 seg3 seg39 seg4 seg38 seg5 seg37 seg6 seg36 seg7 seg35 seg8 seg34 seg9 seg33 seg10 seg32 seg11 seg31 seg12 seg30 seg13 seg29 seg14 seg28 seg15 seg16 seg17 seg18 seg19 seg20 dvdd seg21 seg22 seg23 seg24 seg25 seg26 seg27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
fedl9475-01 ML9475 4/20 pin description symbol i/o description osc i/o pin for oscillation. has a schmitt circuit built in. an oscillator circuit can be configured by connecting one external resistor and one external capacitor. since an oscillator circuit is susceptible to external noise, make the wiring between this pin and external components as short as possible. an external clock input can be selected by clksel. the relationship between oscillation frequency f osc and frame frequency f frm is: f frm = f osc /24 (*1) data_in i serial data input pin. has a schmitt circuit built in. the lcd display is turned on when the input data signal is at a ?h? level and turned off when the input data signal is at a ?l? level. clock i shift clock input pin. has a schmitt circuit built in. data to the data_in pin is shifted in sync with the rising edges of the shift clock pulses. load i load pulse input pin. has a schmitt circuit built in. used to transfer serially input data to the display latch or write commands. test i ic test pin. has a pull-down resistor built in. leave this pin open or connect it to vss when not used. clksel i osc pin input switching pin. when using the built-in oscillator circuit, set this pin to a ?l? level; when inputting an external clock, set this pin to a ?h? leve l. while this pin is at a ?h? level, the oscillator circuit connected is disabled. 3/4sel i 1/3- or 1/4-duty switching input pin. w hen ?h? level is input, 1/3 duty is selected and when ?l? level is input, 1/4 duty is selected. reset i reset signal input pin for initializing t he ic. has a schmitt circuit built in. this pin is enabled by setting it to ?l? level. this pin has a built-in pull-up resistor. normally, this pin, when connected with an external capacitor, performs power-on reset. (*2) com1 com2 com3 com4 o output pins for lcd display. connect to the common pins of the lcd panel. - when 1/3 duty is selected: common signals are outputted through the com1, com2, and com3 pins. leave the com4 pin open. - when 1/4 duty is selected: common signals are outputted throug h the com1, com2, com3, and com4 pins. seg1 to seg40 o output pins for lcd display. connect to the segment pins of the lcd panel. for the relationship between each output of these pins and data, see the section on ?data structure.? lvdd ? logic power supply pin. dvdd ? lcd driver power supply pin. vss ? ground pin.
fedl9475-01 ML9475 5/20 *1: oscillator circuit configuration *2: reset circuit configuration c o osc r o lvdd r ese t lvdd c rst
fedl9475-01 ML9475 6/20 absolute maximum ratings parameter symbol condition rating unit power supply voltage lvdd, dvdd ta = 25c ?0.3 to +6.5 v input voltage v i ta = 25c ?0.3 to lvdd+0.3 v power dissipation p d ta 105c 350 mw output current i o ta = 25c ?2.0 to +2.0 ma storage temperature t stg ? ?55 to +150 c recommended operating conditions parameter symbol condition range unit logic power supply voltage lvdd vss= 0 v 2.7 to 3.6, 4.5 to 5.5 v lcd drive voltage dvdd vss= 0 v 3.5 to 5.5 v clock frequency fcp ? 0.01 to 2 mhz operating temperature t a ? ?40 to +105 c recommended setting range for external parts (for oscillator circuit) (lvdd = 4.5 to 5.5 v) parameter symbol condit ion min. max. unit oscillator resistor r o ? 20 82 k oscillator capacitor c o ? 0.01 0.047 f frame frequency f frm ? 14.6 451.0 hz the relationship between external oscillator resistor va lue, external oscillator capacitor value, and frame frequency is as follows: ffrm = f osc / 24 f osc = 1 / (device coefficient external oscillator resistor value r o external oscillator capacitor value c o ) device coefficient = 0.6 23% (lvdd = 2.7 to 3.6 v) parameter symbol condit ion min. max. unit oscillator resistor r o ? 20 82 k oscillator capacitor c o ? 0.01 0.047 f frame frequency f frm ? 14.6 451.0 hz the relationship between external oscillator resistor va lue, external oscillator capacitor value, and frame frequency is as follows: ffrm = f osc / 24 f osc = 1 / (device coefficient external oscillator resistor value r o external oscillator capacitor value c o ) device coefficient = 0.6 23%
fedl9475-01 ML9475 7/20 electrical characteristics dc characteristics (lvdd = 2.7 to 3.6 v, 4.5 to 5.5 v, dvdd = 3.5 to 5.5, ta = ?40 to +105c) parameter symbol condit ion min. max. unit applicable pin lvdd = 4.5 to 5.5v 0.8lvdd v ih lvdd = 2.7 to 3.6v 0.85lvdd *1 lvdd = 4.5 to 5.5v clksel = ?h? 0.8lvdd ?h? input voltage v ihosc lvdd = 2.7 to 3.6v clksel = ?h? 0.85lvdd lvdd v osc lvdd = 4.5 to 5.5v 0.2lvdd v il lvdd = 2.7 to 3.6v 0.15lvdd *1 lvdd = 4.5 to 5.5v clksel = ?h? 0.2lvdd ?l? input voltage v ilosc lvdd = 2.7 to 3.6v clksel = ?h? 0 0.15lvdd v osc i ih1 v i = lvdd ? 1 a *2 ?h? input current i ihosc v i = lvdd clksel = ?h? ? 1 a osc i il1 v i = 0v ?1 ? a *2 lvdd = 5v v i = 0v ?0.009 ?0.045 ma i il2 lvdd = 3v v i = 0v ?0.004 ?0.030 ma reset ?l? input current i ilosc v i = 0v clksel = ?h? ?1 ? a osc v os0 dvdd = 4.5v i o = ?10 a dvdd ? 0.8 ? v v os1 dvdd = 4.5v i o = 10 a 2/3dvdd ? 0.8 2/3dvdd + 0.8 v v os2 dvdd = 4.5v i o = 10 a 1/3dvdd ? 0.8 1/3dvdd + 0.8 v segment output voltage v os3 dvdd = 4.5v i o = 10 a ? 0.8 v seg1 to seg40 v oc0 dvdd = 4.5v i o = ?10 a dvdd ? 0.77 ? v v oc1 dvdd = 4.5v i o = 10 a 2/3dvdd ? 0.77 2/3dvdd+0.77 v v oc2 dvdd = 4.5v i o = 10 a 1/3dvdd ? 0.77 1/3dvdd+0.77 v common output voltage v oc3 dvdd = 4.5v i o = 10 a ? 0.77 v com1 to com4 dynamic supply current i dvdd+ i l vdd *3 ? 0.5 ma lvdd, dvdd *1 clock, load, data_in, reset , 3/4sel, and clksel *2 clock, load, data_in, 3/4sel, and clksel *3 c o = 0.022 f, r o = 33 k , no load
fedl9475-01 ML9475 8/20 switching characteristic s (serial interface) (lvdd = 2.7 to 3.6 v, 4.5 to 5. 5 v, dvdd = 3.5 to 5.5 v, ta = ? 40 to +105c) parameter symbol condit ion min. max. unit clock frequency f cp ? 0.01 2.0 mhz clock pulse width t wcp ? 70 ? ns rise time, fall time *4 t r , t f ? ? 3 s data setup time t dsu ? 50 ? ns data hold time t dhd ? 50 ? ns load pulse width t wld ? 100 ? ns clock to load time t cl ? 100 ? ns load to clock time t lc ? 100 ? ns *4 applied to clock pin clock data_in load t r t wcp t wcp tf vih vil 1/f cp vih vil t lc t wld t cl vih vil vih vil t dsu t dhd
fedl9475-01 ML9475 9/20 switching characteristics (external clock input to osc) (lvdd = 2.7 to 3.6 v, 4.5 to 5. 5 v, dvdd = 3.5 to 5.5 v, ta = ? 40 to +105c) parameter symbol condit ion min. max. unit osc input frequency f osc clksel = ?h? 0.5 10 khz osc rise time, fall time *5 t rosc, t fosc clksel = ?h? ? 1 s osc ?h? period t whosc clksel = ?h? 4 ? s osc ?l? period t wlosc clksel = ?h? 4 ? s *5 applied to osc pin 1/f osc t rosc t whosc t fosc t wlosc osc v ihosc v ilosc v ilosc v ilosc v ihosc
fedl9475-01 ML9475 10/20 power-on/off timing if lvdd is in the range of 0 v to lvddmin, make sure that lvdd dvdd and t 0[ns] are satisfied. when performing power-on reset w ith a capacitor connected to the reset pin, be careful about the relationship between the capacitance value and the rise time of the power supply. initialization timing drive the reset pin low and hold it low under the condition ?t1 0[ns]? until lvdd reaches lvddmin. the value of the current of the pu ll-up resistor is specified for reset pin. the customer needs to select an external capacito r that meets the timing re quirements shown above. lvdd dvdd time voltage t t lvdd reset vil t1 lvddmin
fedl9475-01 ML9475 11/20 functional description description of operation ? display data input as described in the section on ?data structure,? display data consists of a data field, which corresponds to the lcd segments on and off, and a command field, which indicates the input of display data. set a value in each of bits c0 and c1 in the command field according to the common output that corresponds to the display data, and set a display data input command in the remaining four bits. data that has been input to the data_in pin is loaded in to the shift register on the rising edges of the clock pulses, transferred to the display data latch during the ?h? level period of the load pulse, and then output via the segment driver. d1 d2 d3 d4 d38 d39 d40 c0 c1 c2 c3 c4 clock data_in old data new data load display output c5
fedl9475-01 ML9475 12/20 ? display on, display off display goes off when power-on reset is executed; therefore, to turn display on, write the display on command (f5). the display off command (f4) is a command that make s all segments go off. by writing the display off command, the segments go off irrespective of display data. the display on command (f5) is a command that clears a display off state. by writing the display on command, display goes back to the previous state. d1 d2 c4 c2 c3 c4 c5 c2 c3 c4 c5 clock data_in load display on/off c5 r ese t input of display data write display on command write display off command
fedl9475-01 ML9475 13/20 list of commands command name c5 c4 c3 c2 c1 c0 description f0 0 0 0 0 disabled f0? 0 0 0 1 disabled 0 display data input (corresponds to com1) 0 1 display data input (corresponds to com2) 0 display data input (corresponds to com3) f1 0 0 1 0 1 1 display data input (corresponds to com4) f2 0 1 0 disabled 0 disabled 0 1 disabled 0 disabled f3 0 1 1 0 1 1 disabled f3? 0 1 1 1 disabled f4 1 0 1 0 display off f5 1 0 1 1 display on f6 1 1 0 disabled f7 1 0 0 disabled f8 1 1 1 disabled : don't care if a ?disabled? command is executed, no transfer is carried out fr om the shift register to the latch; however, data within the shift register will be rewritten. to transfer corr ect data to the latch, it is necessary to transfer data again using the f1 command.
fedl9475-01 ML9475 14/20 data structure [input data] d40 d39 d38 d3 d2 d1 c0 c1 c2 c3 c4 c5 command lcd display data corresponds to seg1 corresponds to seg40 first bit note 1: the setting of command f4 or f5 becomes enabled by inputting only the four bits of c2 to c5. (no need to input d1 to d40, c0, or c1.) note 2: if any dummy bits are required because of the transfer bit count, add th em before the first bit. note 3: command execution depends on the value of bits c5 to c0 stored immediately before load goes to a ?h? level.
fedl9475-01 ML9475 15/20 common and segment output waveforms x 1/3 duty dvdd v1 v2 vss com1 com2 com3 dvdd v1 v2 vss dvdd v1 v2 vss dvdd v1 v2 vss dvdd v1 v2 vss seg1 seg2 s e g 1 s e g 2 com1 com2 com3 display
fedl9475-01 ML9475 16/20 x 1/4 duty s e g 1 s e g 2 com1 com2 com3 display com4 dvdd v1 v2 vss com1 com2 com3 dvdd v1 v2 vss dvdd v1 v2 vss dvdd v1 v2 vss dvdd v1 v2 vss com4 seg1 dvdd v1 v2 vss seg2
fedl9475-01 ML9475 17/20 application circuit com3 com4 com4 com3 lvdd load data_in clock clksel seg1 seg40 ML9475 +5 v osc vss test r eset seg1 seg40 1/4 duty lcd cpu com1 com2 com2 com1 3/4sel +5 v dvdd
fedl9475-01 ML9475 18/20 package dimensions notes for mounting the su rface mount type package the surface mount type packages are ve ry susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact oki semiconductor?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ( unit: mm )
fedl9475-01 ML9475 19/20 revision history page document no. date previous edition current edition description fedl9475-01 mar. 1, 2010 ? ? final edition 1
fedl9475-01 ML9475 20/20 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circu it, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki semiconductor co., ltd. assumes no responsi bility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress includ ing, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third part y?s industrial and intellectual property right, etc. is granted by us in connection with the use of the produc t and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not, unless sp ecifically authorized by oki semiconductor co., ltd., authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where th e failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, tra ffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2010 oki semiconductor co., ltd.

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