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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9841a/ad9842a one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 complete 20 msps ccd signal processors functional block diagram dataclk shd shp bandgap reference 2:1 mux dout aux2in clpdm ccdin offset dac pblk aux1in vrt vrb internal timing internal bias 2db?6db avdd dvdd dvss avss drvdd drvss 10 8 cml digital interface sdata sck sl clpob 10/12 cds vga clp buf 2:1 mux clp ad9841a/ad9842a control registers clp adc 4db 6db color steering hd vd pxga 6 features 20 msps correlated double sampler (cds) 4 db 6 db 6-bit pixel gain ampli?er ( pxga ? ) 2 db to 36 db 10-bit variable gain ampli?er (vga) low noise clamp circuits analog preblanking function 10-bit (9841) or 12-bit (9842) 20 msps a/d converter auxiliary inputs with vga and input clamp 3-wire serial digital interface 3 v single supply operation low power: 65 mw @ 2.7 v supply 48-lead lqfp package applications digital still cameras digital video camcorders product description the ad9841a and ad9842a are complete analog signal proces- sors for ccd applications. both products feature a 20 mhz single-ch annel architecture designed to sample and condition the outputs of int erlaced and prog ressive scan area ccd arrays. the ad9841a/ad9842a? signal chain consists of an input clamp, correlated double sampler (cds), pixel gain ampli?r ( pxga ), digitally controlled variable gain ampli?r (vga), black level clamp, and a/d converter. the ad9841a offers 10-bit adc resolution, while the ad9842a contains a true 12-bit adc. additional input modes are provided for processing analog video signals. the internal registers are programmed through a 3-wire serial digital interface. programmable features include gain adjustment, black level adjustment, input con?uration, and power-down modes. the ad9841a and ad9842a operate from a single 3 v power supply, typically dissipate 78 mw, and are packaged in a 48- lead lqfp. pxga is a registered trademark of analog devices, inc.
rev. 0 C2C ad9841a/ad9842a?pecifications general specifications parameter min typ max unit temperature range operating ?0 +85 c storage ?5 +150 c power supply voltage analog, digital, digital driver 2.7 3.6 v power consumption normal operation (speci?d under each mode of operation) power-down modes fast recovery mode 30 mw standby 5 mw total power-down 1 mw maximum clock rate 20 mhz a/d converter (ad9841a) resolution 10 bits differential nonlinearity (dnl) 0.4 1.0 lsb no missing codes 10 bits guaranteed full-scale input voltage 2.0 v data output coding straight binary a/d converter (ad9842a) resolution 12 bits differential nonlinearity (dnl) 0.5 1.0 lsb no missing codes 12 bits guaranteed full-scale input voltage 2.0 v data output coding straight binary voltage reference reference top voltage (vrt) 2.0 v reference bottom voltage (vrb) 1.0 v speci?ations subject to change without notice. digital specifications parameter symbol min typ max unit logic inputs high level input voltage v ih 2.1 v low level input voltage v il 0.6 v high level input current i ih 10 a low level input current i il 10 a input capacitance c in 10 pf logic outputs high level output voltage, i oh = 2 ma v oh 2.2 v low level output voltage, i ol = 2 ma v ol 0.5 v speci?ations subject to change without notice. (drvdd = 2.7 v, c l = 20 pf unless otherwise noted.) (t min to t max , avdd = dvdd = 3.0 v, f dataclk = 20 mhz, unless otherwise noted.)
rev. 0 C3C ad9841a/ad9842a parameter min typ max unit notes p ower consumption 78 mw see tpc 1 for power curves maximum clock rate 20 mhz cds gain 0 db allowable ccd reset transient 1 500 mv see input waveform in footnote 1 max input range before saturation 1 1.0 v p-p pxga gain at 4 db max ccd black pixel amplitude 1 200 mv pixel gain amplifier ( pxga ) max input range 1.0 v p-p pxga gain at 4 db max output range 1.6 v p-p at any pxga gain gain control resolution 64 steps gain monotonicity guaranteed gain range (two? complement coding) see figure 28 for pxga gain curve min gain ( pxga gain code 32) ? db max gain ( pxga gain code 31) 10 db variable gain amplifier (vga) max input range 1.6 v p-p max output range 2.0 v p-p gain control resolution 1024 steps gain monotonicity . guaranteed gain range see figure 29 for vga gain curve low gain (vga gain code 91) 2 db max gain (vga gain code 1023) 36 db black level clamp clamp level resolution 256 steps clamp level measured at adc output min clamp level 0 lsb max clamp level 63.75 lsb system performance speci?ations include entire signal chain gain accuracy, vga code 91 to 1023 2 ?.5 +0.5 use equations on page 19 to calculate gain pxga gain accuracy min gain ( pxga register code 32) ? 0 +1 db vga gain fixed at 2 db (code 91) max gain ( pxga code 31) 11 12 13 db vga gain fixed at 2 db (code 91) peak nonlinearity, 500 mv input signal 0.1 % 12 db gain applied peak nonlinearity, 800 mv input signal 0.4 % 8 db gain applied total output noise 0.2 lsb rms ac grounded input, 6 db gain applied power supply rejection (psr) 40 db measured with step change on supply power-up recovery time normal clock signals applied fast recovery mode 0.1 ms reference standby mode 1 ms total shutdown mode 3 ms power-off condition 15 ms notes 1 input signal characteristics de?ed as follows: 200mv max optical black pixel 500mv typ reset transient 1v max input signal range 2 pxga gain fixed at 4 db. speci?ations subject to change without notice. ad9841a ccd-mode specifications (t min to t max , avdd = dvdd = 3.0 v, f dataclk = f shp = f shd = 20 mhz, unless other- wise noted.)
rev. 0 C4C ad9841a/ad9842a?pecifications parameter min typ max unit notes p ower consumption 78 mw see tpc 1 for power curves maximum clock rate 20 mhz cds gain 0 db allowable ccd reset transient 1 500 mv see input waveform in footnote 1 max input range before saturation 1 1.0 v p-p pxga gain at 4 db max ccd black pixel amplitude 1 200 mv pixel gain amplifier ( pxga ) max input range 1.0 v p-p max output range 1.6 v p-p gain control resolution 64 steps gain monotonicity guaranteed gain range (two? complement coding) see figure 28 for pxga gain curve min gain ( pxga gain code 32) ? db max gain ( pxga gain code 31) 10 db variable gain amplifier (vga) max input range 1.6 v p-p max output range 2.0 v p-p gain control resolution 1024 steps gain monotonicity guaranteed gain range see figure 29 for vga gain curve low gain (vga gain code 91) 2 db max gain (vga gain code 1023) 36 db black level clamp clamp level resolution 256 steps clamp level measured at adc output min clamp level 0 lsb max clamp level 255 lsb system performance speci?ations include entire signal chain gain accuracy, (vga code 91 to 1023) 2 ?.5 +0.5 use equations on page 19 to calculate gain pxga gain accuracy min gain ( pxga register code 32) ? 0 +1 db vga gain fixed at 2 db (code 91) max gain ( pxga code 31) 11 12 13 db vga gain fixed at 2 db (code 91) peak nonlinearity, 500 mv input signal 0.1 % 12 db gain applied total output noise 0.6 lsb rms ac grounded input, 6 db gain applied power supply rejection (psr) 40 db measured with step change on supply power-up recovery time normal clock signals applied fast recovery mode 0.1 ms reference standby mode 1 ms total shutdown mode 3 ms power-off condition 15 ms notes 1 input signal characteristics de?ed as follows: 200mv max optical black pixel 500mv typ reset transient 1v max input signal range 2 pxga gain fixed at 4 db. speci?ations subject to change without notice. ad9842a ccd-mode specifications (t min to t max , avdd = dvdd = 3.0 v, f dataclk = f shp = f shd = 20 mhz, unless otherwise noted)
rev. 0 C5C ad9841a/ad9842a aux1-mode specifications parameter min typ max unit power consumption 60 mw maximum clock rate 20 mhz input buffer gain 0db max input range 1.0 v p-p vga max output range 2.0 v p-p gain control resolution 1023 steps gain (selected using vga gain register) min gain 0 db max gain 36 db speci?ations subject to change without notice. aux2-mode specifications parameter min typ max unit power consumption 60 mw maximum clock rate 20 mhz input buffer (same as aux1-mode) vga max output range 2.0 v p-p gain control resolution 512 steps gain (selected using vga gain register) min gain 0 db max gain 18 db active clamp (ad9841a) clamp level resolution 256 steps clamp level (measured at adc output) min clamp level 0 lsb max clamp level 63.75 lsb active clamp (ad9842a) clamp level resolution 256 steps clamp level (measured at adc output) min clamp level 0 lsb max clamp level 255 lsb speci?ations subject to change without notice. (t min to t max , avdd = dvdd = 3.0 v, f dataclk = 20 mhz, unless otherwise noted.) (t min to t max , avdd = dvdd = 3.0 v, f dataclk = 20 mhz, unless otherwise noted.)
rev. 0 ad9841a/ad9842a C6C timing specifications parameter symbol min typ max unit sample clocks dataclk, shp, shd clock period t conv 48 50 ns dataclk hi/low pulsewidth t adc 20 25 ns shp pulsewidth t shp 712.5 ns shd pulsewidth t shd 712.5 ns clpdm pulsewidth t cdm 4 10 pixels clpob pulsewidth 1 t cob 2 20 pixels shp rising edge to shd falling edge t s1 012.5 ns shp rising edge to shd rising edge t s2 20 25 ns internal clock delay t id 3.0 ns inhibited clock period t inh 10 ns data outputs output delay t od 14.5 16 ns output hold time t h 7.0 7.6 ns pipeline delay 9 cycles serial interface maximum sck frequency f sclk 10 mhz sl to sck setup time t ls 10 ns sck to sl hold time t lh 10 ns sdata valid to sck rising edge setup t ds 10 ns sck falling edge to sdata valid hold t dh 10 ns sck falling edge to sdata valid read t dv 10 ns notes 1 minimum clpob pulsewidth is for functional operation only. wider typical pulses are recommended to achieve low noise clamp perf ormance. speci?ations subject to change without notice. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9841a/ad9842a features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device (c l = 20 pf, f samp = 20 mhz, ccd-mode timing in figures 5 and 6, aux-mode timing in figure 7. serial timing in figures 21 24.) absolute maximum ratings with respect parameter to min max unit avdd1, avdd2 avss ?.3 +3.9 v dvdd1, dvdd2 dvss ?.3 +3.9 v drvdd drvss ?.3 +3.9 v digital outputs drvss ?.3 drvdd + 0.3 v shp, shd, dataclk dvss ?.3 dvdd + 0.3 v clpob, clpdm, pblk dvss ?.3 dvdd + 0.3 v sck, sl, sdata dvss ?.3 dvdd + 0.3 v vrt, vrb, cmlevel avss ?.3 a vdd + 0.3 v byp1-4, ccdin avss ?.3 avdd + 0.3 v junction temperature 150 c lead temperature 300 c (10 sec) ordering guide temperature package package model range description option ad9841ajst ?0 c to +85 c thin plastic st-48 quad flatpack (lqfp) AD9842AJST ?0 c to +85 c thin plastic st-48 quad flatpack (lqfp) thermal characteristics thermal resistance 48-lead lqfp package ja = 92 c
rev. 0 ad9841a/ad9842a C7C pin function descriptions pin number name type description 1, 2 nc nc internally not connected (ad9841a only) 3?2 d0?9 do digital data outputs (ad9841a only) 1?2 d0?11 do digital data outputs (ad9842a only) 13 drvdd p digital output driver supply 14 drvss p digital output driver ground 15, 41 dvss p digital ground 16 dataclk di digital data output latch clock 17 dvdd1 p digital supply 18 hd di horizontal drive. used with vd for color steering control 19 pblk di preblanking clock input 20 clpob di black level clamp clock input 21 shp di cds sampling clock for ccd? reference level 22 shd di cds sampling clock for ccd? data level 23 clpdm di input clamp clock input 24 vd di vertical drive. used with hd for color steering control 25, 26, 35 avss p analog ground 27 avdd1 p analog supply 28 byp1 ao internal bias level decoupling 29 byp2 ao internal bias level decoupling 30 ccdin ai analog input for ccd signal 31 nc nc internally not connected 32 byp4 ao internal bias level decoupling 33 avdd2 p analog supply 34 aux2in ai analog input 36 aux1in ai analog input 37 cml ao internal bias level decoupling 38 vrt ao a/d converter top reference voltage decoupling 39 vrb ao a/d converter bottom reference voltage decoupling 40 dvdd2 p digital supply 42 three-state di digital output disable. active high 43 nc nc may be tied high or low. do not leave floating. 44 stby di standby mode, active high. same as serial interface 45 nc nc internally not connected. may be tied high or low 46 sl di serial digital interface load pulse 47 sdata di serial digital interface data 48 sck di serial digital interface clock type: ai = analog input, ao = analog output, di = digital input, do = digital output, p = power. 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) aux1in avss aux2in avdd2 byp4 nc ccdin nc nc (lsb) d0 d1 d2 d3 d4 nc = no connect d5 d6 d7 d8 byp2 byp1 avdd1 avss ad9841a (msb) d9 avss sck sdata sl nc stby nc three-state dvss dvdd2 vrb vrt cml drvdd drvss dvss dataclk dvdd1 hd pblk clpob shp shd clpdm vd 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) aux1in avss aux2in avdd2 byp4 nc ccdin (lsb) d0 d1 d2 d3 d4 d5 d6 nc = no connect d7 d8 d9 d10 byp2 byp1 avdd1 avss ad9842a (msb) d11 avss sck sdata sl nc stby nc three-state dvss dvdd2 vrb vrt cml drvdd drvss dvss dataclk dvdd1 hd pblk clpob shp shd clpdm vd pin configurations
rev. 0 ad9841a/ad9842a C8C definitions of specifications differential nonlinearity (dnl) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. thus every code must have a ?ite width. no missing codes guaranteed to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating conditions. peak nonlinearity peak nonlinearity, a full signal chain speci?ation, refers to the peak deviation of the output of the ad984x from a true straight line. the point used as ?ero scale?occurs 1/2 lsb before the rst code transition. p ositive full scale?is de?ed as a level 1, 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular output code to the true straight line. the error is then expressed as a percentage of the 2 v adc full-scale signal. the input signal is always appropriately gained up to ?l the adc? full-scale range. total output noise the rms output noise is measured using histogram techniques. the standard deviation of the adc output codes is calculated in lsb, and represents the rms noise level of the total signal chain at the speci?d gain setting. the output noise can be converted to an equivalent voltage, using the relationship 1 lsb = (adc full scale/2 n codes) when n is the bit resolution of the adc. for the ad9842a, 1 lsb is 500 v, and for the ad9841a, 1 lsb is 2 mv. power supply rejection (psr) the psr is measured with a step change applied to the supply pins. this represents a very high frequency disturbance on the ad984xa? power supply. the psr speci?ation is calcu lated from the change in the data outputs for a given step change in the supply voltage. internal delay for shp/shd the internal delay (also called aperture delay) is the time delay that occurs from when a sampling edge is applied to the ad984xa until the actual sample of the input signal is held. both shp and shd sample the input signal during the transition from low to high, so the internal delay is measured from each clock? rising edge to the instant the actual internal sample is taken. equivalent input circuits 330 dvdd dvss figure 1. digital inputsshp, shd, dataclk, clpob, clpdm, hd, vd, pblk, sck, sl dvdd dvss drvss drvdd three- state data dout figure 2. data outputsd0Cd9 (d11) 60 acvdd acvss acvss figure 3. ccdin (pin 30) 330 dvdd dvss dvdd dvss dvss data in rnw data out figure 4. sdata (pin 47)
rev. 0 ad9841a/ad9842a C9C typical performance characteristics sample rate mhz 100 70 40 520 10 power dissipation mw 50 60 80 90 15 v dd = 3.3v v dd = 3.0v v dd = 2.7v tpc 1. ad9841a/ad9842a power vs. sample rate 0 1000 400 200 600 800 0 0.5 0.5 0.25 0.25 tpc 2. ad9841a typical dnl performance vga gain code lsb 4 2 0 0 1000 400 output noise lsb 200 1 600 3 800 tpc 3. ad9841a output noise vs. vga gain 0 1000 500 1500 2000 2500 3000 3500 4000 0 0.5 0.5 0.25 0.25 /.0% 6)%#/ !1.

vga gain code lsb 15 0 0 1000 400 output noise lsb 200 5 600 10 800 /.0& 6)%#3 ! ::
rev. 0 ad9841a/ad9842a C10C ccd-mode and aux mode timing n n+1 n+2 n+9 n+10 t id t id t s1 t s2 t cp t inh t od t h n 10 n 9n 8n 1n notes: 1. recommended placement for dataclk rising edge is between the shd rising edge and next shp falling edge. 2. ccd signal is sampled at shp and shd rising edges. shp shd dataclk output data ccd signal figure 5. ccd-mode timing ccd signal effective pixels clpob clpdm optical black pixels horizontal blanking dummy pixels effective pixels pblk notes: 1. clpob and clpdm will overwrite pblk. pblk will not affect clamp operation if overlapping clpdm and/or clpob. 2. pblk signal is optional. 3. digital output data will be all zeros during pblk. output data latency is 9 dataclk cycles. output data effective pixel data ob pixel data dummy black effective data figure 6. typical ccd-mode line clamp timing dataclk output data video signal n n+1 n+2 n+8 n+9 n 10 n 9n 8n 1n t id t cp t od t h figure 7. aux-mode timing
rev. 0 ad9841a/ad9842a C11C pixel gain amplifier ( pxga ) timing frame n vd hd frame n+1 line 0 line 1 line 2 line m 0101... 2323... 0101... line m 1 line 0 line 1 line 2 line m 0101... 2323... 0101... line m 1 note: 0 = gain0, 1 = gain1, 2 = gain2, 3 = gain3 figure 8. pxga mode 1 (mosaic separate) frame/line gain register sequence shp hd pxga gain 3ns min gain0 vd 3ns min gain1 gain0 notes: 1. minimum pulsewidth for hd and vd is 5 pixel cycles. 2. both vd and hd are internally updated at shp rising edges. minimum set-up time is 3ns. 3. every hd rising edge with a previous vd rising edge will reset to 0101. 4. every hd rising edge without a previous vd rising edge will alternate between 0101... and 2323. gain3 gain2 gainx gainx 5 pixel min figure 9. pxga mode 1 (mosaic separate) detailed timing even field odd field 0101... 2323... 0101... note: 0 = gain0, 1 = gain1, 2 = gain2, 3 = gain3 0101... 2323... 0101... hd line 0 line 1 line 2 line m line m 1 line 0 line 1 line 2 line m line m 1 vd figure 10. pxga mode 2 (interlace) frame/line gain register sequence shp hd pxga gain 3ns min gain0 3ns min gain1 gain0 gain3 gain2 gainx gainx 5 pixel min vd notes: 1. both vd and hd are internally updated at shp rising edges. 2. every hd rising edge with a previous vd rising or falling edge will reset to 0101. 3. every hd rising edge without a previous vd rising edge will alternate between 0101... and 2323. figure 11. pxga mode 2 (interlace) detailed timing
rev. 0 ad9841a/ad9842a C12C vd hd note: 0 = gain0, 1 = gain1, 2 = gain2 line n line n+1 012012012... 012012012... ...01201 figure 12. pxga mode 3 (3-color) frame/line gain register sequence shp hd pxga gain gain1 vd gain2 gain0 gain1 gain0 gainx gain0 gainx 3ns min 5 pixel min 5 pixel min notes: 1. both vd and hd are internally updated at shp rising edges. 2. every hd rising edge with a previous vd rising edge will reset to 012012. figure 13. pxga mode 3 (3-color) detailed timing vd hd note: 0 = gain0, 1 = gain1, 2 = gain2, 3 = gain3 line n line n+1 012301230123... ...01230 01230123012... figure 14. pxga mode 4 (4-color) frame/line gain register sequence shp hd pxga gain gain1 vd gain2 gain0 gain1 gain0 gainx gain0 gainx 3ns min 5 pixel min 5 pixel min notes: 1. both vd and hd are internally updated at shp rising edges. 2. every hd rising edge with a previous vd rising edge will reset to 01230123. figure 15. pxga mode 4 (4-color) detailed timing
rev. 0 ad9841a/ad9842a C13C even field odd field 0101... 0101... 0101... note: 0 = gain0, 1 = gain1, 2 = gain2, 3 = gain3 2323... 2323... 2323... hd line 0 line 1 line 2 line m line m 1 line 0 line 1 line 2 line m line m 1 vd figure 16. pxga mode 5 (vd selected) frame/line gain register sequence shp hd pxga gain 3ns min gain0 vd gain1 gain0 notes: 1. both vd and hd are internally updated at shp rising edges. 2. every hd rising edge with a previous vd falling edge will reset to 0101. 3. every hd rising edge with a previous vd rising edge will reset to 2323. 4. every hd rising edge without a previous vd rising edge will repeat either 0101... (even) or 2323 ... (odd). gain3 gain2 gainx gainx 5 pixel min 3ns min *
+( .>:5 &7- 8 / frame n vd hd frame n+1 line 0 line 1 line 2 line m 0101... 1212... 0101... line m 1 line 0 line 1 line 2 line m 0101... 1212... 0101... line m 1 note: 0 = gain0, 1 = gain1, 2 = gain2 *
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91:
-? shp hd pxga gain 3ns min gain0 vd 3ns min gain1 gain0 notes: 1. minimum pulsewidth for hd and vd is 5 pixel cycles. 2. both vd and hd are internally updated at shp rising edges. minimum set-up time is 3ns. 3. every hd rising edge with a previous vd rising edge will reset to 0101. 4. every hd rising edge without a previous vd rising edge will alternate between 0101... and 1212. gain2 gainx gainx 5 pixel min gain1 *
+6 .>:5 '75 8 /
rev. 0 ad9841a/ad9842a C14C shp hd 3ns min gain1 vd gain0 gain2 gain3 3ns min 1. both vd and hd are internally updated at shp rising edges. 2. vd = 0 and hd = 0 selects gain0. 3. vd = 0 and hd = 1 selects gain1. 4. vd = 1 and hd = 0 selects gain2. 5. vd = 1 and hd = 1 selects gain3. gain0 pxga gain notes: figure 20. pxga mode 7 (user-speci?ed) detailed timing
rev. 0 ad9841a/ad9842a C15C sdata sck sl rnw test bit 0 a2 0 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 t ds t dh t ls t lh notes: 1. sdata bits are internally latched on the rising edges of sck. 2. rnw = read-not write. set low for write operation. 3. test bits = internal use only. must be set low. 4. system update of loaded registers occurs on sl rising edge. figure 21. serial write operation sdata sck sl rnw test bit 10 0 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 t ds t dh t ls t lh notes: 1. rnw = read-not write. set high for read operation. 2. test bits = internal use only. must be set low. 3. serial data from the selected register is valid starting after the 5th sck falling edge, and is updated on sck falling edges. t dv figure 22. serial readback operation serial interface timing and internal register description table i. ad9841a/ad9842a internal register map register address data bits name a0 a1 a2 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 operation 0 0 0 channel select power-down software ob clamp 0 * 1 ** 0 * 0 * 0 * ccd/aux1/2 modes reset on/off vga gain 1 0 0 lsb msb x clamp level 0 1 0 lsb msb x x x control 1 1 0 color steering mode pxga clock polarity select for 0 * 0 * three- x selection on/off shp/shd/clp/data state pxga gain0 0 0 1 lsb msb x x x x x pxga gain1 1 0 1 lsb msb x x x x x pxga gain2 0 1 1 lsb msb x x x x x pxga gain3 1 1 1 lsb msb x x x x x * internal use only. must be set to zero. ** must be set to one.
rev. 0 ad9841a/ad9842a C16C sdata sck sl a0 a1 a2 d0 d10 d0 d9 d0 d0 d7 rnw 0 0 d9 0 00 d0 1 21735 34 27 26 16 6 5 4 3 44 45 51 63 62 57 56 50 68 ... ... ... ... ... ... ... ... 10 bits acg gain d5 d0 d5 d0 d0 d5 d5 ... ... ... ... ... ... ... ... ... notes: 1. any number of adjacent registers may be loaded sequentially, beginning with the lowest address and incrementing one address at a time. 2. when sequentially loading multiple registers, the exact register length (shown above) must be used for each register. 3. all loaded registers will be simultaneously updated with the rising edge of sl. 8 bits clamp level 10 bits control 11 bits operation 6 bits pxga gain0 6 bits pxga gain1 6 bits pxga gain2 6 bits pxga gain3 figure 23. continuous serial write operation to all registers sdata a0 a1 a2 d1 d0 d1 d2 d3 d4 d5 d0 d3 d2 d4 0 0 23 24 12 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 29 18 ... ... d5 0 01 d5 d5 d0 d0 rnw sck sl pxga gain0 pxga gain1 pxga gain3 pxga gain2 ... ... ... figure 24. continuous serial write operation to all pxga gain registers table ii. operation register contents (default value x000) optical black clamp reset power-down modes channel selection d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 * 0 * 0 * 1 ** 0 * 0 enable clamping 0 normal 0 0 normal power 0 0 ccd mode 1 disable clamping 1 reset all registers 0 1 fast recovery 0 1 aux1 mode to default 1 0 standby 1 0 aux2 mode 1 1 total power-down 11 test only * must be set to zero. ** set to one. table iii. vga gain register contents (default value x096) msb lsb d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 gain (db) x00 010111112.0 ?? ?? ?? 11 11111110 35.965 11 11111111 36.0
rev. 0 ad9841a/ad9842a C17C table iv. ad9841a clamp level register contents (default value x080) msb lsb d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 clamp level (lsb) xxx0000 0000 0 0000 0001 0.25 0000 0010 0.5 ? ? ? ? ? ? 11111110 63.5 11111111 63.75 table v. ad9842a clamp level register contents (default value x080) msb lsb d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 clamp level (lsb) xxx0000 0000 0 0000 0001 1 0000 0010 2 ? ? ? ? ? ? 11111110 254 11111111 255 table vi. control register contents (default value x000) data out dataclk clp/pblk shp/shd pxga color steering modes d10 d9 d8 d7 d6 d5 d4 d3 ** d2 d1 d0 x 0 enable 0 * 0 * 0 rising edge trigger 0 active low 0 active low 0 disable 0 0 0 steering disabled 1 three-state 1 falling edge trigger 1 active high 1 active high 1 enable 0 0 1 mosaic separate 0 1 0 interlace 0 1 1 3-color 1 0 0 4-color 1 0 1 vd selected 1 1 0 mosaic repeat 1 1 1 user speci?d * must be set to zero. ** when d3 = 0 ( pxga disabled) the pxga gain is ?ed to 4 db. table vii. pxga gain registers for gain0, gain1, gain2, gain3 (default value x000) msb lsb d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 gain (db) * xxxxx0 11111 +10.0 ?? ?? ?? 000000+4.3 111111+4.0 ?? ?? ?? 100000 ?.0 * control register bit d3 must be set high ( pxga enable) to use the pxga gain registers.
rev. 0 ad9841a/ad9842a C18C circuit description and operation the ad9841a and ad9842a signal processing chain is shown in figure 25. each processing step is essential in achieving a high-quality image from the raw ccd pixel data. dc restore to reduce the large dc offset of the ccd output signal, a dc- restore circuit is used with an external 0.1 f series coupling capacitor. this restores the dc level of the ccd signal to approxi- mately 1.5 v, to be compatible with the 3 v single supply of the ad984xa. correlated double sampler the cds circuit samples each ccd pixel twice to extract the video information and reject low-frequency noise. the timing shown in figure 5 illustrates how the two cds clocks, shp and shd, are used to sample the reference level and data level of the ccd signal respectively. the ccd signal is sampled on the rising edges of shp and shd. placement of these two clock signals is critical in achieving the best performance from the ccd. an internal shp/shd delay (t id ) of 3 ns is caused by internal propagation delays. input clamp a line-rate input clamping circuit is used to remove the ccd? optical black offset. this offset exists in the ccd? shielded black reference pixels. unlike some afe architectures, the ad984xa rem oves this offset in the input stage to minimize the effect of a gain change on the system black level, usually called the ?ain step.?another advantage of removing this offset at the input stage is to maximize system headroom. some area ccds have large black level offset voltages, which, if not cor- rected at the input stage, can signi?antly reduce the available headroom in the internal circuitry when higher vga gain set- tings are used. horizontal timing is shown in figure 6. it is recommended that the clpdm pulse be used during valid ccd dark pixels. clpdm may be used during the optical black pixels, either together with clpob or separately. the clpdm pulse should be a minimum of 4 pixels wide. pxga the pxga provides separate gain adjustment for the individual color pixels. a programmable gain ampli?r with four separate values, the pxga has the capability to ?ultiplex?its gain value on a pixel-to-pixel basis. this allows lower output color pixels to be gained up to match higher output color pixels. also, the pxga may be used to adjust the colors for white balance, reducing the amount of digital processing that is needed. the four different gain values are switched according to the ?olor steering?circuitry. seven different color steering modes for different types of ccd color ?ter arrays are programmed in the ad984xa? control register. for example, mosaic separate steering mode accom- modates the popular ?ayer?arrangement of red, green, and blue ?ters (see figure 26). 2db to 36db clpdm ccdin digital filtering clpob dc restore optical black clamp 0.1 f dout 10-/12-bit adc vga 8-bit dac clamp level register 8 vga gain register 10 cds input offset clamp internal v ref 2v full scale color steering 4:1 mux 3 gain0 gain1 gain2 gain3 pxga 2db to +10db pxga mode selection 2 6 vd hd pxga gain registers 10/12 figure 25. ad9841a/ad9842a ccd-mode block diagram
rev. 0 ad9841a/ad9842a C19C rr gb gb gr gr bb ccd: progressive bayer line0 gain0, gain1, gain0, gain1 ... rr gr gr gb gb bb line1 line2 gain2, gain3, gain2, gain3 ... gain0, gain1, gain0, gain1 ... mosaic separate color steering mode figure 26. ccd color filter example: progressive scan line0 gain0, gain1, gain0, gain1 ... rr gr gr line1 line2 gain0, gain1, gain0, gain1 ... gain0, gain1, gain0, gain1 ... gb gb bb line0 gain2, gain3, gain2, gain3 ... line1 line2 gain2, gain3, gain2, gain3 ... gain2, gain3, gain2, gain3 ... ccd: interlaced bayer even field vd selected color steering mode odd field gb gb bb gb gb bb gb gb bb rr gr gr rr gr gr rr gr gr figure 27. ccd color filter example: interlaced the same bayer pattern can also be interlaced, and the vd selected mode should be used with this type of ccd (see fig- ure 27). the color steering performs the proper multiplexing of the r, g, and b gain values (loaded into the pxga gain regis- ters), and is synchronized by the user with vertical (vd) and horizontal (hd) sync pulses. for more detailed information, see the pxga timing section. the pxga gain for each of the four channels is variable from ? db to +10 db, controlled in 64 steps through the serial interface. the pxga gain curve is shown in figure 28. pxga gain register code 10 32 pxga gain db 40 48 56 0 8 16 24 31 8 6 4 2 0 -2 (100000) (011111) figure 28. pxga gain curve variable gain ampli?r the vga stage provides a gain range of 2 db to 36 db, program- mable with 10-bit resolution through the serial digital interface. combined with 4 db from the pxga stage, the total gain range for the ad984xa is 6 db to 40 db. the minimum gain of 6 db is needed to match a 1 v input signal with the adc full-scale range of 2 v. w hen compared to 1 v full-scale systems (such as adi? ad9803), the equivalent gain range is 0 db to 34 db. the vga gain curve is divided into two separate regions. when the vga gain register code is between 0 and 511, the curve follows a (1 + x)/(1 ?x) shape, which is similar to a ?inear-in- db?characteristic. from code 512 to code 1023, the curve follows a ?inear-in-db?shape. the exact vga gain can be calculated for any gain register value by using the following two equations: code range gain equation (db) 0?11 gain = 20 log 10 ([658 + code ]/[658 ? code ]) ?0.4 512 ?023 gain = (0.0354)( code ) ?0.4 as shown in the ccd mode speci?ations, only the vga gain range from 2 db to 36 db has tested and guaranteed accuracy. this corresponds to a vga gain code range of 91 to 1023. the gain accuracy speci?ations also include the pxga gain of 4 db, for a total gain range of 6 db to 40 db. vga gain register code 36 0 vga gain db 127 255 383 511 639 767 895 1023 30 24 18 12 6 0 figure 29. vga gain curve (gain from pxga not included) optical black clamp the optical black clamp loop is used to remove residual offsets in the signal chain, and to track low-frequency variations in the ccd? black level. during the optical black (shielded) pixel interval on each line, the adc output is compared with a ?ed black level reference, selected by the user in the clamp level register. any value between 0 lsb and 64 lsb (ad9841a) or 255 lsb (ad9842a) may be programmed, with 8-bit resolu- tion. the resulting error signal is ?tered to reduce noise, and the correction value is applied to the adc input through a d/a converter. normally, the opti cal black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. if external d igital clamping is used during the post processing, the ad984xa? optical black clamping may be disabled using bit d5 in the o peration register (see serial interface timing and internal register description section). when the loop is disabled, the clamp level register may still be used to provide programm able offset adjustment. horizontal timing is shown in figure 6. the clpob pulse should be placed during the ccd? optical black pixels. it is recommended that the clpob pulse duration be at least 20 pixels wide to minimize clamp noise. shorter pulsewidths may be used, but clamp noise may increase, and the ability to track low-fre quency variations in the black level will be reduced.
rev. 0 ad9841a/ad9842a C20C a/d converter the ad9841a and ad9842a use high-performance adc archi- tectures, optimized for high speed and low power. differential nonlinearity (dnl) performance is typically better than 0.5 lsb, as shown in tpcs 2 and 4. instead of the 1 v full-scale range used by the earlier ad9801 and ad9803 products from analog devices, the ad984xa adcs use a 2 v input range. better noise performance results from using a larger adc full-scale range (see tpcs 3 and 5). aux1 mode for applications that do not require cds, the ad9841a/ad9842a can be configured to sample ac-coupled waveforms. figure 30 shows the circuit configuration for using the aux1 channel input (pin 36). a single 0.1 f ac-coupling capacitor is needed between the input signal driver and the aux1in pin. an on-chip dc-bias circuit sets the average value of the input signal to approximately 0.4 v, which is referenced to the midscale code of the adc. the vga gain register provides a gain range of 0 db to 36 db in this mode of operation (see vga gain curve, figure 29). the vga gains up the signal level with respect to the 0.4 v bias level. signal levels above the bias level will be further increased to a higher adc code, while signal levels below the bias level will be further decreased to a lower adc code. aux2 mode for sampling video-type waveforms, such as ntsc and pal signals, the aux2 channel provides black level clamping, gain adjustment, and a/d conversion. figure 31 shows the circuit configuration for using the aux2 channel input (pin 34). a external 0.1 f blocking capacitor is used with the on-chip video clamp circuit, to level-shift the input signal to a d esired refer- ence level. the clamp circuit automatically senses the most negative portion of the input signal, and adjusts the voltage across the input capacitor. this forces the black level of the input signal to be eq ual to the value program med into the clamp level register (see serial interface register description). the vga provides gain adjustment from 0 db to 18 db. the same vga gain register is used, but only the 9 msbs of the gain register are used (see table viii.) aux1in 0.1 f vga gain register adc vga 10 5k 0.4v 0.4v input signal ??v 0.8v 0.4v midscale 0db to 36db figure 30. aux1 circuit con?guration 0db to 18db 8 aux2in buffer 0.1 f video signal 9 clamp level lpf vga gain register adc vga video clamp circuit clamp level register figure 31. aux2 circuit con?guration table viii. vga gain register used for aux2-mode msb lsb d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 gain (db) x0 xxxxxxxxx0.0 10000000000.0 111111111118.0
rev. 0 ad9841a/ad9842a C21C ccd ccdin buffer v out 0.1 f ad984xa adc out register data serial interface digital outputs digital image processing asic timing generator v-drive ccd timing cds/clamp timing figure 32. ad984xa system applications diagram 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 37 48 47 46 45 44 39 38 43 42 41 40 pin 1 identifier top view (not to scale) aux1in avss aux2in avdd2 byp4 nc ccdin byp2 byp1 avdd1 avss avss nc nc (lsb) d0 d1 d2 d3 d4 d5 d6 d7 d8 (msb) d9 ad9841a sck sdata sl nc stby nc three-state dvss dvdd2 vrb vrt cml drvdd drvss dvss dataclk dvdd1 hd pblk clpob shp shd clpdm vd 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 3v analog supply ccd signal 3v analog supply 10 data outputs 3 serial interface 0.1 f 1.0 f 1.0 f 0.1 f 3v analog supply 8 clock inputs 0.1 f 0.1 f 3v analog supply 3v driver supply nc = no connect figure 33. ad9841a recommended circuit configuration for ccd-mode applications information the ad9841a and ad9842a are complete analog front end (afe) products for digital still camera and camcorder appli- cations. as shown in figure 32, the ccd image (pixel) data is buffered and sent to the ad984xa analog input through a series input capacitor. the ad984xa performs the dc restoration, cds, gain adjustment, black level correction, and analog-to- digital conversion. the ad984xa? digital output data is then processed by the image processing asic. the internal regis- ters of the ad984xa?sed to control gain, offset level, and other functions?re programmed by the asic or microprocessor through a 3-wire serial digital interface. a system timing gen- erator provides the clock signals for both the ccd and the afe.
rev. 0 ad9841a/ad9842a C22C 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 37 48 47 46 45 44 39 38 43 42 41 40 pin 1 identifier top view (not to scale) aux1in avss aux2in avdd2 byp4 nc ccdin byp2 byp1 avdd1 avss avss d0 d1 d2 d3 d4 d5 d6 d7 d8 (msb) d11 ad9842a sck sdata sl nc stby nc three-state dvss dvdd2 vrb vrt cml drvdd drvss dvss dataclk dvdd1 hd pblk clpob shp shd clpdm vd 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 3v analog supply ccd signal 3v analog supply 12 data outputs 3 serial interface 0.1 f 1.0 f 1.0 f 0.1 f 3v analog supply 8 clock inputs 0.1 f 0.1 f 3v analog supply 3v driver supply nc = no connect d9 d10 figure 34. ad9842a recommended circuit configuration for ccd-mode internal power-on reset circuitry after pow er-on, the ad9842a will automatically reset all inter- nal registers and perform internal calibration procedures. this takes approximately 1 ms to complete. during this time, normal clock signals and serial write operations may occur. however, serial register writes will be ignored until the internal reset operation is completed. pin 43 (formerly rstb on the ad9842a non-a) is no longer used for the reset operation. toggling pin 43 in the ad9842a will have no effect. grounding and decoupling recommendations as shown in figures 33 and 34, a single ground plane is recom- mended for the ad9841a/ad9842a. this ground plane should be as continuous as possible, particularly around pins 25 through 39. this will ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. all decoupling capaci- tors should be located as close as possible to the package pins. a single clean power supply is r ecommended for the ad9841a/ad9842a, but a separate digital driver sup ply may be used for drvdd (pin 13). drvdd should always be decoupled to drvss (pin 14), which should be connected to the analog ground plane. advantages of using a separate digital driver supply include using a lower voltage (2.7 v) to match levels with a 2.7 v asic, reducing digital power dissipation, and reducing p otential noise coupling. if the digital outputs (pins 3?2) must drive a load larger than 20 pf, buffering is recommended to reduce digital code transi- tion noise. alternatively, placing series resistors close to the digital output pins may also help reduce noise.
rev. 0 ad9841a/ad9842a C23C outline dimensions dimensions shown in inches and (mm). 48-lead lqfp (st-48) top view (pins down) 1 12 13 25 24 36 37 48 0.019 (0.5) bsc 0.276 (7.00) bsc sq 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) bsc sq 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) 0.008 (0.2) 0.004 (0.09) 0 min coplanarity 0.003 (0.08) seating plane 0.006 (0.15) 0.002 (0.05) 7 0 0.057 (1.45) 0.053 (1.35) c02384C2.5C1/01 (rev. 0) printed in u.s.a.

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