vishay siliconix si3424cdv document number: 67443 s11-0863-rev. a, 02-may-11 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 n-channel 30 v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 definition ?trenchfet ? power mosfet ? 100 % r g te s t e d ? compliant to rohs directive 2002/95/ec applications ? load switch for portable devices ? dc/dc converters product summary v ds (v) r ds(on) ( ? )i d (a) a, b q g (typ.) 30 0.026 at v gs = 10 v 8 4.2 0.032 at v gs = 4.5 v 8 notes: a. package limited. b. based on t c = 25 c. c. surface mounted on 1" x 1" fr4 board. d. t = 5 s. e. maximum under steady state conditions is 110 c/w. absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 30 v gate-source voltage v gs 20 continuous drain current (t j = 150 c) t c = 25 c i d 8 a a t c = 70 c 7.7 t a = 25 c 7.2 c, d t a = 70 c 5.7 c, d pulsed drain current (t = 300 s) i dm 20 continuous source-drain diode current t c = 25 c i s 3 a t a = 25 c 1.7 c, d maximum power dissipation t c = 25 c p d 3.6 w t c = 70 c 2.3 t a = 25 c 2.0 c, d t a = 70 c 1.3 c, d operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient e t ?? 5 s r thja 50 62.5 c/w maximum junction-to-foot (drain) steady state r thjf 28 35 marking code bc xx lot tracea b ility and date code part # code y y tsop-6 top v ie w 6 4 1 2 3 5 3 mm 2. 8 5 mm d d d d s g n -channel mosfet g d s (1, 2, 5, 6) (3) (4) orderin g information: si3424cd v -t1-ge3 (lead (p b )-free and halogen-free)
www.vishay.com 2 document number: 67443 s11-0863-rev. a, 02-may-11 vishay siliconix si3424cdv this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 30 v v ds temperature coefficient ? v ds /t j i d = 250 a 28 mv/c v gs(th) temperature coefficient ? v gs(th) /t j - 3.7 gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 12.5v gate-source leakage i gss v ds = 0 v, v gs = 20 v 100 na zero gate voltage drain current i dss v ds = 30 v, v gs = 0 v 1 a v ds = 30 v, v gs = 0 v, t j = 85 c 10 on-state drain current a i d(on) v ds = ? 5 v, v gs = 10 v 20 a drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 7.2 a 0.021 0.026 ? v gs = 4.5 v, i d = 6.5 a 0.026 0.032 forward transconductance g fs v ds = 15 v, i d = 7.2 a 17 s dynamic b input capacitance c iss v ds = 15 v, v gs = 0 v, f = 1 mhz 405 pf output capacitance c oss 92 reverse transfer capacitance c rss 42 total gate charge q g v ds = 15 v, v gs = 10 v, i d = 7.2 a 8.3 12.5 nc v ds = 24 v, v gs = 4.5 v, i d = 7.2 a 4.2 6.3 gate-source charge q gs 1.2 gate-drain charge q gd 1.6 gate resistance r g f = 1 mhz 0.6 3 6 ? tu r n - o n d e l ay t i m e t d(on) v dd = 15 v, r l = 2.6 ? i d ? 5.7 a, v gen = 10 v, r g = 1 ? 36 ns rise time t r 12 20 turn-off delaytime t d(off) 16 24 fall time t f 816 tu r n - o n d e l ay t i m e t d(on) v dd = 15 v, r l = 2.6 ? i d ? 5.7 a, v gen = 4.5 v, r g = 1 ? 10 20 rise time t r 22 33 turn-off delaytime t d(off) 15 23 fall time t f 918 drain-source body diode characteristics continous source-drain diode current i s t c = 25 c 3 a pulse diode forward current a i sm 20 body diode voltage v sd i s = 5.7 a 0.8 1.2 v body diode reverse recovery time t rr i f = 5.7 a, di/dt = 100 a/s 13 20 nc body diode reverse recovery charge q rr 510 ns reverse recovery fall time t a 8 reverse recovery rise time t b 5
document number: 67443 s11-0863-rev. a, 02-may-11 www.vishay.com 3 vishay siliconix si3424cdv this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t a = 25 c, unless otherwise noted) output characteristics on-resistance vs. drain current gate charge 0 5 10 15 20 0 0.2 0.4 0.6 0.8 1 i d - drain current (a) v ds - drain-to-source voltage (v) v gs = 10 v thru 4 v v gs = 3 v 0.010 0.016 0.022 0.028 0.034 0 5 10 15 20 r ds(on) - on-resistance () i d -drain current (a) v gs = 4.5 v v gs = 10 v 0 2 4 6 8 10 0246810 v gs - gate-to-source voltage (v) q g - total gate charge (nc) i d = 7.2 a v ds = 15 v v ds = 8 v v ds = 24 v transer characteristics cures s. temp. capacitance on-resistance s. junction temperature 0 1 2 3 4 5 00.511.522.5 i d - drain current (a) v gs - gate-to-source voltage (v) t c = 125 c t c = 25 c t c = - 55 c 0 150 300 450 600 0 6 12 18 24 30 c - capacitance (pf) v ds - drain-to-source voltage (v) c iss c oss c rss 0.6 0.8 1.0 1.2 1.4 1.6 -50-250 255075100125150 r ds(on) -on-resistance (normalized) t j - junction temperature ( c) v gs = 10 v, i d = 7.2 a v gs = 4.5 v, i d = 6.5 a
www.vishay.com 4 document number: 67443 s11-0863-rev. a, 02-may-11 vishay siliconix si3424cdv this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t a = 25 c, unless otherwise noted) source-drain diode forward voltage threshold voltage 0.1 1 10 0.0 0.2 0.4 0.6 0.8 1.0 i s - source current (a) v sd - source-to-drain voltage (v) t j = 150 c t j = 25 c 1 1.2 1.4 1.6 1.8 -50-250 255075100125150 v gs(th) (v) t j -temperature ( c) i d = 250 a r ds(on) vs. v gs vs. temperature single pulse power 0.01 0.02 0.03 0.04 0.05 24 6 810 r ds(on) - on-resistance () v gs - gate-to-source voltage (v) t j = 125 c t j = 25 c i d = 7.2 a 0 9 1 8 27 36 45 0 1 1 1 0 0 . 00.01 time (s) po w er ( w ) 0.1 safe operating area, junction-to-ambient 0.01 0.1 1 10 100 0.1 1 10 100 i d - drain current (a) v ds - drain-to-source voltage (v) * v gs > minimum v gs at which r ds(on) is specified 100 ms limited by r ds(on) * 1 ms t c = 25 c single pulse bvdss limited 10 ms 100 s 1 s, 10 s dc
document number: 67443 s11-0863-rev. a, 02-may-11 www.vishay.com 5 vishay siliconix si3424cdv this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t a = 25 c, unless otherwise noted) * the power dissipation p d is based on t j(max) = 150 c, using junction-to-case thermal resi stance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. it is used to determ ine the current rating, when this rating falls below the package limit. current derating* 0 3 6 9 12 0 25 50 75 100 125 150 i d - drain current (a) t c - case temperature ( c) package limited power derating, junction-to-foot 0 0.9 1.8 2.7 3.6 4.5 0255075100125150 power (w) t c - case temperature ( c) power derating, junction-to-ambient 0.0 0.2 0.4 0.6 0.8 1.0 0 255075100125150 power (w) t a - ambient temperature ( c)
www.vishay.com 6 document number: 67443 s11-0863-rev. a, 02-may-11 vishay siliconix si3424cdv this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t a = 25 c, unless otherwise noted) vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?67443 . normalized thermal transient impedance, junction-to-ambient 10 -3 10 -2 1 10 1000 10 -1 10 -4 100 0.2 0.1 0.05 sq u are w a v ep u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1 0.1 0.01 single p u lse t 1 t 2 n otes: p dm 1. d u ty cycle, d = 2. per unit base = r thja =110c/ w 3. t jm -t a =p dm z thja (t) t 1 t 2 4. s u rface mo u nted d u ty cycle = 0.5 0.02 normalized thermal transient impedance, junction-to-foot 10 -3 10 -2 0 1 1 10 -1 10 -4 0.2 0.1 d u ty cycle = 0.5 sq u are w a v ep u lse d u ration (s) n ormalized effecti v e transient thermal impedance 1 0.1 0.01 single p u lse 0.02 0.05
vishay siliconix package information document number: 71200 18-dec-06 www.vishay.com 1 1 2 3 g au ge pl a ne l 5 4 r r c 0.15 m b a b c 0.0 8 0.17 ref s e a ting pl a ne -c- s e a ting pl a ne a 1 a 2 a -a- d -b- e 1 e l 2 (l 1 ) c 4x 1 4x 1 e e1 1 2 3 6 5 4 c 0.15 m b a b -b- e 1 e e e1 5-lead tsop 6-lead tsop tsop: 5/6?lead jedec part number: mo-193c millimeters inches dim min nom max min nom max a 0.91 - 1.10 0.036 - 0.043 a 1 0.01 - 0.10 0.0004 - 0.004 a 2 0.90 - 1.00 0.035 0.03 8 0.039 b 0.30 0.32 0.45 0.012 0.013 0.01 8 c 0.10 0.15 0.20 0.004 0.006 0.00 8 d 2.95 3.05 3.10 0.116 0.120 0.122 e 2.70 2. 8 5 2.9 8 0.106 0.112 0.117 e 1 1.55 1.65 1.70 0.061 0.065 0.067 e 0.95 b s c 0.0374 b s c e 1 1. 8 0 1.90 2.00 0.071 0.075 0.079 l 0.32 - 0.50 0.012 - 0.020 l 1 0.60 ref 0.024 ref l 2 0.25 b s c 0.010 b s c r 0.10 - - 0.004 - - 0 4 8 0 4 8 1 7 nom 7 nom ecn: c-06593-rev. i, 1 8 -dec-06 dwg: 5540
an823 vishay siliconix document number: 71743 27-feb-04 www.vishay.com 1 mounting little foot tsop-6 power mosfets surface mounted power mosfet packaging has been based on integrated circuit and small signal packages. those packages have been modified to provide the improvements in heat transfer required by power mosfets. le adframe materials and design, molding compounds, and die attach materials have been changed. what has remained the same is the footprint of the packages. the basis of the pad design for surface mounted power mosfet is the basic footprint for the package. for the tsop-6 package outline drawing see http://www.vishay.com/doc?71200 and see http://www.vishay.com/doc?72610 for the minimum pad footprint. in converting the footprint to th e pad set for a power mosfet, you must remember that not only do you want to make electrical connection to the package, but you must made thermal connection and provide a means to draw heat from the package, and move it away from the package. in the case of the tsop-6 package, the electrical connections are very simple. pins 1, 2, 5, and 6 are the drain of the mosfet and are connected together. for a small signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. the total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. also, heat spreads in a circular fashion from the heat source. in this case the drain pins are the heat sources when looking at heat spread on the pc board. figure 1 shows the copper spreading recommended footprint for the tsop-6 package. this pattern shows the starting point for utilizing the board area available for the heat spreading copper. to create this pattern, a plane of copp er overlays the basic pattern on pins 1,2,5, and 6. the copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and star t the process of spreading the heat so it can be dissipated into th e ambient air. notice that the planar copper is shaped like a ?t? to move heat away from the drain leads in all directions. this pattern uses all the available area underneath the body for this purpose. figure 1. recommended copper spreading footprint 0.049 1.25 0.010 0.25 0.014 0.35 0.074 1.875 0.122 3.1 0.026 0.65 0.167 4.25 0.049 1.25 since surface mounted packages are small, and reflow soldering is the most common form of soldering for surface mount components, ?thermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum power trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. reflow soldering vishay siliconix surface-mount packages meet solder reflow reliability requirements. devices are subjected to solder reflow as a test preconditioning and are then reliability-tested using temperature cycle, bias humidity, hast, or pressure pot. the solder reflow temperature profile used, and the temperatures and time duration, are shown in figures 2 and 3. ramp-up rate +6 c/second maximum temperature @ 155 15 c 120 seconds maximum temperature above 180 c 70 ? 180 seconds maximum t emperature 240 +5/ ? 0 c time at maximum t emperature 20 ? 40 seconds ramp-down rate +6 c/second maximum figure 2. solder reflow temperature profile
an823 vishay siliconix www.vishay.com 2 document number: 71743 27-feb-04 255 ? 260 c 1 4 c/s (max) 3-6 c/s (max) 10 s (max) reflow zone pre-heating zone 3 c/s (max) 140 ? 170 c maximum peak temperature at 240 c is allowed. figure 3. solder reflow temperature and time durations 60-120 s (min) 217 c 60 s (max) thermal performance a basic measure of a device?s thermal performance is the junction-to-case thermal resistance, r jc , or the junction-to-foot thermal resistance, r jf . this parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. table 1 shows the thermal performance of the tsop-6. table 1. equivalent steady state performance?tsop-6 thermal resistance r jf 30 c/w system and electrical impact of tsop-6 in any design, one must take into account the change in mosfet r ds(on) with temperature (figure 4). 0.6 0.8 1.0 1.2 1.4 1.6 ? 50 ? 25 0 25 50 75 100 125 150 v gs = 4.5 v i d = 6.1 a on-resistance vs. junction temperature t j ? junction temperature ( c) figure 4. si3434dv r ds(on) ? on-resiistance (normalized)
application note 826 vishay siliconix www.vishay.com document number: 72610 26 revision: 21-jan-08 application note recommended minimum pads for tsop-6 0.119 (3.023) recommended mi nimum pads dimensions in inches/(mm) 0.099 (2.510) 0.064 (1.626) 0.028 (0.699) 0.039 (1.001) 0.020 (0.508) 0.019 (0.493) return to index return to index
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.
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