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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. ad9874 * if digitizing subsystem * protected by u.s. patent no. 5,969,657; features 10 mhz to 300 mhz input frequency 7.2 khz to 270 khz output signal bandwidth 8.1 db ssb nf 0 dbm iip3 agc free range up to ?4 dbm 12 db continuous agc range 16 db front end attenuator baseband i/q 16-bit (or 24-bit) serial digital output lo and sampling clock synthesizers programmable decimation factor, output format, agc, and synthesizer settings 370 input impedance 2.7 v to 3.6 v supply voltage low current consumption: 20 ma 48-lead lqfp package (1.4 mm thick) applications multimode narrow-band radio products analog/digital uhf/vhf fdma receivers tetra, apco25, gsm/edge portable and mobile radio products base station applications satcom terminals - adc lna dac agc vo ltag e reference spi control logic formatting/ssi decimation filter lo syn clk syn lo vco and loop filter ifin fref douta doutb fs clkout syncb pepdpc vrefn vcm vrefp mxop mxon if2p if2n gcp gcn ?6db ad9874 clkn clkp ioutc lonlop ioutl loop filter general description the ad9874 is a general-purpose if subsystem that digitizes a low level 10 mhz to 300 mhz if input with a signal bandwidth ranging from 6.8 khz to 270 khz. the signal chain of the ad9874 consists of a low noise amplifier, a mixer, a band-pass sigma-delta analog-to-digital converter, and a decimation filter with program- mable decimation factor. an automatic gain control (agc) circuit gives the ad9874 12 db of continuous gain adjustment. auxil- iary blocks include both clock and lo synthesizers. t he ad9874? high dynamic range and inherent antialiasing provided by the band-pass sigma-delta converter allow the ad9874 to cope with blocking signals up to 95 db stronger than the desired signal. this attribute can often reduce the cost of a radio by reducing its if filtering requirements. also, it enables multimode radios of varying channel bandwidths, allowing the if filter to be specified for the largest channel bandwidth. the spi port programs numerous parameters of the ad9874, thus allowing the device to be optimized for any given application. programmable parameters include synthesizer divide ratios, agc attenuation and attack/decay time, received signal strength level, decimation factor, output data format, 16 db attenuator, and the selected bias currents. the bias currents of the lna and mixer can be further reduced at the expense of degraded performance for battery-powered applications. functional block diagram
rev. a ad9874 ? table of contents ad9874?pecifications . . . . . . . . . . . . . . . . . . . . . . . 3 absolute maximum ratings . . . . . . . . . . . . . . . . . 5 pin configuration/description . . . . . . . . . . . . . 6 definition of specifications/ test methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical performance characteristics . . . . . 8 serial peripheral interface (spi) . . . . . . . . . . . 13 synchronous serial interface (ssi) . . . . . . . . 16 synchronization using syncb . . . . . . . . . . . . . . . . . . . . 18 interfacing to dsps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 lo synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 fast acquire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 clock synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . 21 if lna/mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 band-pass sigma delta ( - ) adc . . . . . . . . . . . . 24 decimation filter . . . . . . . . . . . . . . . . . . . . . . . . . . 26 variable gain amplifier with agc . . . . . . . . . . 28 variable gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 automatic gain control . . . . . . . . . . . . . . . . . . . . . . . . . 29 system nf vs. vga control . . . . . . . . . . . . . . . . . . . . . . 31 application considerations . . . . . . . . . . . . . . . 32 frequency planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 spurious responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 external passive component requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 superheterodyne receiver . . . . . . . . . . . . . . . . . . . . . . . . 34 synchronization of multiple ad9874s . . . . . . . . . . . . . . . 36 split path rx architecture . . . . . . . . . . . . . . . . . . . . . . . . 37 hung mixer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 layout example evaluation board and software . . . . . . . . . 38 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 39 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
rev. a ad9874?pecifications ? parameter temp test level min typ max unit system dynamic performance 2 ssb noise figure @ min vga attenuation 3, 4 full iv 8.1 9.5 db @ max vga attenuation 3, 4 full iv 13 db dynamic range with agc enabled 3, 4 full iv 91 95 db if input clip point @ max vga attenuation 3 full iv ?0 ?9 dbm @ min vga attenuation 3 full iv ?2 ?1 dbm input third order intercept (iip3) full iv ? 0 dbm gain variation over temperature full iv 0.7 2 db lna + mixer maximum rf and lo frequency range full iv 300 500 mhz lna input impedance 25 o cv 370//1.4 //pf mixer lo input resistance 25 o cv 1 k lo synthesizer lo input frequency full iv 7.75 300 mhz lo input amplitude full iv 0.3 2.0 v p-p fref frequency (for sinusoidal input only) full iv 8 25 mhz fref input amplitude full iv 0.3 3 v p-p fref slew rate full iv 7.5 v/ s minimum charge pump current @ 5 v 5 full vi 0.48 0.67 0.78 ma maximum charge pump current @ 5 v 5 full vi 3.87 5.3 6.2 ma charge pump output compliance 6 full vi 0.4 vddp ?0.4 v synthesizer resolution full iv 6.25 khz clock synthesizer clk input frequency full iv 13 26 mhz clk input amplitude full iv 0.3 vddc v p-p minimum charge pump output current 5 full vi 0.48 0.67 0.78 ma maximum charge pump output current 5 full vi 3.87 5.3 6.2 ma charge pump output compliance 6 full vi 0.4 vddq ?0.4 v synthesizer resolution full iv 2.2 khz sigma-delta adc resolution full iv 16 24 bits clock frequency (f clk ) full iv 13 26 mhz center frequency full v f clk /8 mhz pass-band gain variation full iv 1.0 db alias attenuation full iv 80 db gain control programmable gain step full v 16 db agc gain range (continuous) full v 12 db gcp output resistance full iv 50 72.5 95 k overall analog supply voltage (vdda, vddf, vddi) full vi 2.7 3.0 3.6 v digital supply voltage (vddd, vddc, vddl) full vi 2.7 3.0 3.6 v interface supply voltage 7 (vddh) full vi 1.8 3.6 v charge pump supply voltage (vddp, vddq) full vi 2.7 5.0 5.5 v total current high performance setting 8 full vi 20 26.5 ma low power mode 8 full vi 17 22 ma standby full vi 0.01 0.1 ma operating temperatur e range ?0 +85 c notes 1 standard operating mode: lna/mixer @ high bias setting, vga @ min atten setting, synthesizers in normal (not fast acquire) mode , f clk = 18 mhz, decimation factor = 900, 16-bit digital output, and 10 pf load on ssi output pins. 2 this includes 0.9 db loss of matching network. 3 agc with dvga enabled. 4 measured in 10 khz bandwidth. 5 programmable in 0.67 ma steps. 6 voltage span in which lo (or clk) charge pump output current is maintained within 5% of nominal value of vddp/2 (or vddq/2). 7 vddh must be less than vddd + 0.5 v. 8 clock vco off, add additional 0.7 ma with vga @ max atten setting. specifications subject to change without notice. (vddi = vddf = vdda = vddc = vddl = vddd = vddh = 2.7 v to 3.6 v, vddq = vddp = 2.7 v to 5.5 v, f clk = 18 msps, f if = 109.65 mhz, f lo = 107.4 mhz, f ref = 16.8 mhz, unless otherwise noted.) 1
rev. a ad9874 ? digital specifications (vddi = vddf = vdda = vddc = vddl = vddd = vddh = 2.7 v to 3.6 v, vddq = vddp = 2.7 v to 5.5 v, f clk = 18 msps, f if = 109.65 mhz, f lo = 107.4 mhz, f ref = 16.8 mhz, unless otherwise noted.) 1 parameter temp test level min typ max unit decimator decimation factor 2 full iv 48 960 pass-band width full v 50% f clkout pass-band gain variation full iv 1.2 db alias attenuation full iv 88 db spi-read operation (see figure 1a) pc clock frequency full iv 10 mhz pc clock period (t clk ) full iv 100 ns pc clock hi (t hi ) full iv 45 ns pc clock low (t low ) full iv 45 ns pc to pd setup time (t ds ) full iv 2 ns pc to pd hold time (t dh ) full iv 2 ns pe to pc setup time (t s ) full iv 5 ns pc to pe hold time (t h ) full iv 5 ns spi-write operation 3 (s ee figure 1b) pc clock frequency full iv 10 mhz pc clock period (t clk ) full iv 100 ns pc clock hi (t hi ) full iv 45 ns pc clock low (t low ) full iv 45 ns pc to pd setup time (t ds ) full iv 2 ns pc to pd hold time (t dh ) full iv 2 ns pc to pd (or doubt) data valid time (t dv ) full iv 3 ns pe to pd output valid to hi-z (t ez ) full iv 8 ns ssi 3 (see figure 2b) clkout frequency full iv 0.867 26 mhz clkout period (t clk ) full iv 38.4 1153 ns clkout duty cycle (t hi, t low ) full iv 33 50 67 ns clkout to fs valid time (t v ) full iv ? +1 ns clkout to dout data valid time (t dv ) full iv ? +1 ns cmos logic inputs 4 logic ??voltage (v ih ) full iv vddh ?0.2 v logic ??voltage (v il ) full iv 0.5 v logic ??current (v ih ) full iv 10 a logic ??current (v il ) full iv 10 a input capacitance full iv 3 pf cmos logic outputs 3, 4, 5 logic ??voltage (v ih ) full iv vddh ?0.2 v logic ??voltage (v il ) full iv 0.2 v notes 1 standard operating mode: high iip3 setting, synthesizers in normal (not fast acquire) mode, f clk = 18 mhz, decimation factor = 300, 10 pf load on ssi output pins: vddx = 3.0 v. 2 programmable in steps of 48 or 60. 3 cmos output mode with c load = 10 pf and drive strength = 7. 4 absolute max and min input/output levels are vddh +0.3 v and ?.3 v. 5 i ol = 1 ma; specification is also dependent on drive strength setting. specifications subject to change without notice.
rev. a ad9874 ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9874 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * parameter with respect to min max unit vddf, vdda, vddc, vddd, vddh, gndf, gnda, gndc, gndd, gndh, ?.3 +4.0 v vddl, vddi gndl, gndi, gnds vddf, vdda, vddc, vddd, vddh, vddr, vdda, vddc, vddd, vddh, ?.0 +4.0 v vddl, vddi vddl, vddi vddp, vddq gndp, gndq ?.3 +6.0 v gndf, gnda, gndc, gndd, gndh, gndf, gnda, gndc, gndd, gndh, ?.3 +0.3 v gndl, gndi, gndq, gndp, gnds gndl, gndi, gndq, gndp, gnds mxop, mxon, lop, lon, ifin, gndi ?.3 vddi + 0.3 v cxif, cxvl, cxvm pc, pd, pe, clkout, douta, gndh ?.3 vddh + 0.3 v doutb, fs, syncb if2n, if2p, gcp, gcn gndf ?.3 vddf + 0.3 v vrefp, vrefn, rref gnda ?.3 vdda + 0.3 v ioutc gndq ?.3 vddq + 0.3 v ioutl gndp ?.3 vddp + 0.3 v clkp, clkn gndc ?.3 vddc + 0.3 v fref gndl ?.3 vddl + 0.3 v junction temperature 150 c storage temperature ?5 +150 c lead temperature (10 sec) 300 c * stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. ordering guide model temperature range package description package option ad9874abst 40 c to +85 c 48-lead thin plastic quad flatpack (lqfp) st-48 ad9874eb evaluation board explanation of test levels test level i. 100% production tested. ii. 100% production tested at 25 c and sample tested at specified temperatures. ac testing done on sample basis. iii. sample tested only. iv. parameter is guaranteed by design and/or characterization testing. v. parameter is a typical value only. vi. all devices are 100% production tested at 25 c; min and max guaranteed by design and characterization for industrial temperature range. thermal characteristics thermal resistance 48-lead lqfp ja = 76.2 c/w jc = 17 c/w
rev. a ad9874 ? pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 pin 1 identifier top view (not to scale) gndl fref gnds syncb gndh fs doutb mxop mxon gndf if2n if2p vddf gcp gcn vdda gnda vrefp douta clkout vddh vddd ad9874 vrefn pe vddi ifin cxif gndi cxvl lop lon cxvm vddl vddp ioutl gndp rref vddq ioutc gndq vddc gndc clkp clkn gnds gndd pc pd 40 41 42 13 19 18 17 16 15 14 20 21 22 23 24 pin function descriptions pin mnemonic description 1 mxop mixer output, positive. 2m xon mixer output, negative. 3 gndf ground for front end of adc. 4i f2n second if input (to adc), negative. 5 if2p second if input (to adc), positive. 6 vddf positive power supply for front end of adc. 7 gcp filter capacitor for adc full-scale control. 8 gcn full-scale control ground. 9 vdda positive power supply for adc back end. 10 gnda ground for adc back end. 11 vrefp voltage reference, positive. 12 vrefn voltage reference, negative. 13 rref reference resistor: requires 100 k ? to gnda. 14 vddq positive power supply for clock synthesizer. 15 ioutc clock synthesizer charge pump output current. 16 gndq ground for clock synthesizer charge pump. 17 vddc positive power supply for clock synthesizer. 18 gndc ground for clock synthesizer. 19 clkp sampling clock input/clock vco tank, positive. 20 clkn sampling clock input/clock vco tank, negative. 21 gnds substrate ground. 22 gndd ground for digital functions. 23 pc clock input for spi port. 24 pd data i/o for spi port. 25 pe enable input for spi port. 26 vddd positive power supply for internal digital function. 27 vddh positive power supply for digital interface. 28 clkout clock output for ssi port. 29 douta data output for ssi port. 30 doutb data output for ssi port (inverted) or spi port. 31 fs frame sync for ssi port. 32 gndh ground for digital interface. 33 syncb resets ssi and decimator counters; active low. 34 gnds substrate ground. 35 fref reference frequency input for both synthesizers. 36 gndl ground for lo synthesizer. 37 gndp ground for lo synthesizer charge pump. 38 ioutl lo synthesizer charge pump output current charge pump. 39 vddp positive power supply for lo synthesizer charge pump. 40 vddl positive power supply for lo synthesizer. 41 cxvm external filter capacitor; dc output of lna. 42 lon lo input to mixer and lo synthesizer, negative. 43 lop lo input to mixer and lo synthesizer, positive. 44 cxvl external bypass capacitor for lna power supply. 45 gndi ground for mixer and lna. 46 cxif external capacitor for mixer v-i con- verter bias. 47 ifin first if input (to lna). 48 vddi positive power supply for lna and mixer. pin mnemonic description
rev. a ad9874 ? definition of specifications/test methods single-sideband noise figure (ssb nf) noise figure (nf) is defined as the degradation in snr perfor- mance (in db) of an if input signal after it passes through a component or system. it can be expressed with the equation noise figure snr snr in out = 10 log( ) the term ssb is applicable for heterodyne systems containing a mixer. it indicates that the desired signal spectrum resides on only one side of the lo frequency (i.e., single sideband); thus a ?oiseless?mixer has a noise figure of 3 db. the ad9874? ssb noise figure is determined by the equation ssb nf p bw dbm hz snr in =? () {} ?? 10 174 log where p in is the input power of an unmodulated carrier, bw is the noise measurement bandwidth, ?74 d bm/hz is the thermal noise floor at 293 k, and snr is the measured signal-to-noise ratio in db of the ad9874. note that p in is set to ?5 dbm to minimize any degradation in measured snr due to phase noise from the rf and lo signal generators. the if frequency, clk frequency, and decimation factors are selected to minimize any spurious components falling within the measurement bandwidth. note also that a bandwidth of 10 khz is used for the data sheet specification. refer to figures 22a and 22b for an indication of how nf varies with bw. also, refer to the tpcs to see how nf is affected by different operating conditions. all references to noise figures within this data sheet imply single-sideband noise figure. input third order intercept (iip3) iip3 is a figure of merit used to determine a component? or system? susceptibility to intermodulation distortion (imd) from its third order nonlinearities. two unmodulated carriers at a specified frequency relationship ( f 1 and f 2 ) are injected into a nonlinear system exhibiting third order nonlinearities producing imd components at 2 f 1 ? f 2 and 2 f 2 ?f 1 . iip3 graphically repre- sents the extrapolated intersection of the carrier? input power with the third order imd component when plotted in db. the difference in power ( d in dbc) between the two carriers and the resulting third order imd components can be determined from the equation d iip p in = 23 () dynamic range (dr) dynamic range is the measure of a small target input signal (p target ) in the presence of a large unwanted interferer signal (p inter ). typically, the large signal will cause some unwanted characteristic of the component or system to degrade, thus making it unable to detect the smaller target signal correctly. in the case of the ad9874, it is often a degradation in noise figure at increased vga attenuation settings that limits its dynamic range (refer to tpcs 15a, 15b, and 15c). the test method for the ad9874 is as follows. the small target signal (an unmodulated carrier) is input at the center of the if frequency, and its power level ( p target ) is adjusted to achieve an snr target of 6 db. the power of the signal is then increased by 3 db prior to injecting the interferer signal. the offset fre quency of the interferer signal is selec ted so that aliases produced by the decimation filter? response as well as phase noise from the lo (due to reciprocal mixing) do not fall back within the measurement bandwidth. for this reason, an offset of 110 khz was selected. the interferer signal (also an unmodulated carrier) is then injected into the input and its power level is increased to the point ( p inter ) where the target signal snr is reduced to 6 db. the dynamic range is determined with the equation: dr p p snr inter target target =+ note that the ad9874? agc is enabled for this test. if input clip point the if input clip point is defined as 2 db below the input power level (p in ), resulting in the clipping of the ad9874? adc. unlike other linear components that typically exhibit a soft compression (characterized by its 1 db compression point), an adc exhibits a hard compression once its input signal exceeds its rated maximum input signal range. in the case of the ad9874, which contains a - adc, hard compression should be avoided because it causes severe snr degradation.
rev. a ad9874?ypical performance characteristics ? noise figure ?db percentage ?% 100 7.2 7.5 7.8 8.1 8.4 8.7 9.0 80 60 40 20 0 ?0 c +25 c +85 c tpc 1a. cdf of ssb noise figure (vddx = 3.0 v, high bias 2 ) iip3 ?dbm percentage ?% 100 ? 80 60 40 20 0 ? ? 0 1 2 ?0 c +25 c +85 c tpc 2a. cdf of iip3 (vddx = 3.0 v, high bias 2 ) dy namic range ?db percentage ?% 100 92 80 60 40 20 0 ?0 c +85 c +25 c 93 94 95 96 97 98 tpc 3a. cdf of dynamic range (vddx = 3.0 v, high bias 2 ) vddx ?v nf ?db 9.5 2.7 3.0 3.3 3.6 6.0 9.0 8.5 8.0 7.5 7.0 6.5 +85 c +25 c ?0 c tpc 1b. ssb noise figure vs. supply (high bias 2 ) vddx ?v iip3 ?dbm 1.5 2.7 3.0 3.3 3.6 ?.5 +85 c +25 c ?0 c 1.0 0.5 0 ?.5 ?.0 ?.5 ?.0 ?.5 ?.0 tpc 2b. iip3 vs. supply (high bias 2 ) vddx ?v dr ?db 98 2.7 3.0 3.3 3.6 92 97 96 95 94 93 ?0 c +85 c +25 c tpc 3b. dynamic range vs. supply (high bias 2 ) vddx ?v nf ?db 9.5 2.7 3.0 3.3 3.6 6.0 9.0 8.5 8.0 7.5 7.0 6.5 +85 c +25 c ?0 c tpc 1c. ssb noise figure vs. supply (low bias 3 ) vddx ?v iip3 ?dbm 0 2.7 3.0 3.3 3.6 ?2 +85 c +25 c ?0 c ?0 ? ? ? ? tpc 2c. iip3 vs. supply (low bias 3 ) vddx ?v dr ?db 98 2.7 3.0 3.3 3.6 92 97 96 95 94 93 ?0 c +85 c +25 c tpc 3c. dynamic range vs. supply (low bias 3 ) (vddi = vddf = vdda = vddc = vddl = vddd = vddh = vddx, vddq = vddp = 5.0 v, f clk = 18 msps, f if = 109.56 mhz, f lo = 107.4 mhz, t a = 25 c, lo = ? dbm, lo and clk synthesizer disabled, 16-bit data with agc and dvga enabled, unless otherwise noted.) 1 1 data taken with toko fslm series 10 h inductors. 2 high bias corresponds to lna_mixer setting of 33 in spi register 0x01. 3 low bias corresponds to lna_mixer setting of 12 in spi register 0x01.
rev. a ad9874 ? ifin clip point ?dbm percentage ?% 100 80 60 40 20 0 ?9.4 ?9.2 ?9.0 ?8.8 ?8.6 ?8.4 +25 c +85 c ?0 c tpc 4a. cdf of maximum vga attenuation clip point (vddx = 3.0 v, high bias 2 ) ifin clip point ?dbm percentage ?% 100 80 60 40 20 0 ?1.6 +25 c +85 c ?0 c ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 tpc 5a. cdf of minimum vga attenuation clip point (vddx = 3.0 v, high bias 2 ) supply current ?ma percentage ?% 100 80 60 40 20 0 18.5 19.0 19.5 20.0 20.5 21.0 21.5 22.0 +85 c +25 c ?0 c tpc 6a. cdf of supply current (vddx = 3.0 v, high bias 2 ) vddx ?v input clip point ?dbm 2.7 3.0 3.3 3.6 ?0.5 ?0.0 ?9.5 ?9.0 ?8.5 ?8.0 ?7.5 +25 c +85 c ?0 c tpc 4b. maximum vga attenuation clip point vs. supply (high bias 2 ) vddx ?v input clip point ?dbm ?9.5 2.7 3.0 3.3 3.6 +85 c +25 c ?0.0 ?0.5 ?1.0 ?1.5 ?2.0 ?0 c tpc 5b. minimium vga attenuation clip point vs. supply (high bias 2 ) f clk ?mhz supply current ?ma 16 13 14 10 6 2 0 12 8 4 15 17 19 21 23 25 digital ( iddd, iddc, and iddl) digital interface ( iddh) analog ( idda, iddf, and iddi) tpc 6b. supply current vs. f clk (vddx = 3.0 v, high bias 2 ) vddx ?v input clip point ?dbm ?7.5 2.7 3.0 3.3 3.6 ?0 c +85 c +25 c ?8.0 ?8.5 ?9.0 ?9.5 ?0.0 ?0.5 tpc 4c. maximum vga attenuation clip point vs. supply (low bias 3 ) vddx ?v input clip point ?dbm ?9.5 2.7 3.0 3.3 3.6 +85 c +25 c ?0.0 ?0.5 ?1.0 ?1.5 ?2.0 ?0 c tpc 5c. minimium vga attenuation clip point vs. supply (low bias 3 ) vddx ?v supply current ?ma 18 2.7 3.0 3.3 3.6 16 12 8 4 0 digital interface ( iddh) digital ( iddd, iddc, and iddl) analog ( idda, iddf, and iddi) 14 10 6 2 tpc 6c. supply current vs. supply (high bias 2 ) (vddi = vddf = vdda = vddc = vddl = vddd = vddh = vddx, vddq = vddp = 5.0 v, f clk = 18 msps, f if = 109.56 mhz, f lo = 107.4 mhz, t a = 25 c, lo = ? dbm, lo and clk synthesizer disabled, 16-bit data with agc and dvga enabled, unless otherwise noted.) 1 1 data taken with toko fslm series 10 h inductors. 2 high bias corresponds to lna_mixer setting of 33 in spi register 0x01. 3 low bias corresponds to lna_mixer setting of 12 in spi register 0x01.
rev. a ad9874 ?0 lo drive ?dbm gain variation ? db 0.1 ?0 ?4 ? ? 0 ?.2 ?.4 ?.6 ?.8 ?.1 ?.3 ?.5 ?.7 ?1 ?7 low bias high bias tpc 7a. normalized gain variation vs. lo drive (vddx = 3.0 v) frequency ?khz dbfs 0 ?40 ?0 ?0 ?0 ?0 ?00 ?20 ?0 ?0 ?0 ?0 0 20 40 60 80 ?.8dbfs output nbw = 3.66khz f clk = 18mhz max vga atten dec?y?20 tpc 8a. complex fft of baseband i/q for single-tone (high bias) frequency ?khz dbfs 0 ?40 ?0 ?0 ?0 ?0 ?00 ?20 ?0 ?0 ?0 ?0 0 20 40 60 80 nbw = 3.66khz f clk = 18mhz max vga atten dec?y?20 imd = 74dbc ?8.2dbfs output tpc 9a. complex fft of baseband i/q for dual tone imd (high bias with each ifin tone @ ?5 dbm) lo drive ?dbm noise figure ?dbc 9.0 ?0 ?0 0 5 8.6 8.2 7.8 7.4 7.0 8.4 8.0 7.6 7.2 ? ?5 nf-high bias imd-high bias nf-low bias imd-low bias 8.8 imd w/ ifin = ?6 dbm ?dbc 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 tpc 7b. noise figure and imd vs. lo drive (vddx = 3.0 v) ifin ?dbm dbfs 0 ?0 ?4 adc goes into hard compression ?8 ?6 ?4 ?2 ?0 ?8 ?6 ? ? ? ? ?0 ?2 2.7v 3.0v 3.3v 3.6v tpc 8b. gain compression vs. ifin (high bias 2 ) ifin ?dbm imd ?dbc ?0 ?24 ?6 ?2 ?8 ?00 ?06 ?18 ?1 ?8 ?5 ?2 ?9 ?6 ?3 ?0 pin 2.7v 3.6v 3.0v 3.3v ?30 ?12 ?4 pin ?dbfs ?5 ?2 ?8 ?1 ?4 ?0 ?3 ?9 ?5 ?6 ?7 tpc 9b. imd vs. ifin (high bias 2 ) ifin ?dbm dbm ?2 ?6 ?8 ?4 ?0 ?6 ?5 ?1 ?7 ?3 ?0 ?4 ?8 ?2 ? 0 high bias low bias tpc 7c. gain compression vs. ifin with 16 db lna attenuator enabled ifin ?dbm dbfs 0 ?0 ?4 adc does not go into hard compression ?8 ?6 ?4 ?2 ?0 ?8 ?4 ? ? ? ? ?0 ?2 2.7v 3.0v 3.3v 3.6v ?6 tpc 8c. gain compression vs. ifin (low bias 3 ) ifin ?dbm imd ?dbc ?5 ?09 ?1 ?7 ?3 ?5 ?1 ?03 ?1 ?8 ?5 ?2 ?9 ?6 ?3 ?0 pin 2.7v 3.6v 3.0v 3.3v ?15 ?7 ?9 pin ?dbfs ?5 ?2 ?8 ?1 ?4 ?0 ?3 ?9 ?5 ?6 ?7 tpc 9c. imd vs. ifin (low bias 3 ) (vddi = vddf = vdda = vddc = vddl = vddd = vddh = vddx, vddq = vddp = 5.0 v, f clk = 18 msps, f if = 109.56 mhz, f lo = 107.4 mhz, t a = 25 c, lo = ? dbm, lo and clk synthesizer disabled, 16-bit data with agc and dvga enabled, unless otherwise noted.) 1 1 data taken with toko fslm series 10 h inductors. 2 high bias corresponds to lna_mixer setting of 33 in spi register 0x01. 3 low bias corresponds to lna_mixer setting of 12 in spi register 0x01.
rev. a ad9874 ?1 channel bandwidth ?khz noise figure ?db 10.0 10 7.5 1000 100 9.5 9.0 8.5 8.0 24-bit i/q data 16-bit i/q data 16-bit i/q data w/ dvga enabled tpc 10a. noise figure vs. bw (mini- mum attenuation, f clk = 13 msps) vg a attenuation ?db noise figure ?db 11.5 0 7.0 12 6 9 3 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 bw = 6.78khz (k = 0, m = 15) bw = 12.04khz (k = 0, m = 8) bw = 27.08khz (k = 0, m = 3) tpc 11a. noise figure vs. vga attenuation (f clk = 13 msps) ifin ?dbm imd ?dbc ?5 ?30 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?2 ?9 ?6 ?3 ?0 ?7 ?4 low bias pin high bias pout ?dbfs ? ?0 ?0 ?5 ?0 ?5 ?0 ?5 ?5 tpc 12a. imd vs. ifin (f clk = 13 msps) channel bandwidth ?khz noise figure ?db 10.0 10 7.5 1000 100 9.5 9.0 8.5 8.0 24-bit data 16-bit data 16-bit data w/ dvga enabled tpc 10b. noise figure vs. bw (mini- mum attenuation, f clk = 18 msps) vg a attenuation ?db noise figure ?db 14 0 7 12 6 9 3 13 12 11 10 9 8 bw = 15khz (k = 0, m = 9) bw = 50khz (k = 0, m = 2) bw = 75khz (k = 0, m = 1) tpc 11b. noise figure vs. vga attenuation (f clk = 18 msps) ifin ?dbm imd ?dbc ?5 ?30 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?2 ?9 ?6 ?3 ?0 ?7 ?4 low bias pin high bias pin ?dbfs ? ?0 ?0 ?5 ?0 ?5 ?0 ?5 ?5 tpc 12b. imd vs. ifin (f clk = 18 msps) channel bandwidth ?khz noise figure ?db 10.0 10 7.5 1000 100 9.5 9.0 8.5 8.0 24-bit data 16-bit data 16-bit data w/ dvga enabled tpc 10c. noise figure vs. bw (mini- mum attenuation, f clk = 26 msps) vg a attenuation ?db noise figure ?db 14 0 7 12 6 9 3 13 12 11 10 9 8 bw = 27.08khz (k = 1, m = 9) bw = 90.28khz (k = 1, m = 2) bw = 135.42khz (k = 1, m = 1) tpc 11c. noise figure vs. vga attenuation (f clk = 26 msps) ifin ?dbm imd ?dbc ?5 ?30 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?2 ?9 ?6 ?3 ?0 ?7 ?4 low bias pin high bias pin ?dbfs ? ?0 ?0 ?5 ?0 ?5 ?0 ?5 ?5 tpc 12c. imd vs. ifin (f clk = 26 msps) (vddi = vddf = vdda = vddc = vddl = vddd = vddh = vddx, vddq = vddp = 5.0 v, f clk = 18 msps, f if = 109.56 mhz, f l o = 107.4 mhz, t a = 25 c, lo = ? dbm, lo and clk synthesizer disabled, 16-bit data with agc and dvga enabled, unless otherwise noted.) 1 1 data taken with toko fslm series 10 h inductors. 2 high bias corresponds to lna_mixer setting of 33 in spi register 0x01. 3 low bias corresponds to lna_mixer setting of 12 in spi register 0x01.
rev. a ad9874 ?2 frequency ?mhz noise figure ?db 13 0 6 12 11 10 9 8 7 50 500 100 150 200 250 300 350 400 450 24-bit 16-bit w/dvga tpc 13a. noise figure vs. frequency (minimum attenuation, f clk = 18 msps, bw = 10 khz, high bias) frequency ?mhz noise figure ?db 13 0 6 12 11 10 9 8 7 50 500 100 150 200 250 300 350 400 450 24-bit 16-bit w/dvga tpc 14a. noise figure vs. frequency (minimum attenuation, f clk = 26 msps, bw = 24 khz, high bias) interferer level ?dbm noise figure ?dbc 20.0 ?5 8.0 18.5 15.5 12.5 11.0 9.5 ? ?0 noise figure agc 17.0 14.0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 mean agc attn value 128 0 112 80 48 32 16 96 64 tpc 15a. noise figure vs. interferer level (16-bit data, bw = 12.5 khz, agcr = 1, f interferer = f if + 110 khz) frequency ?mhz noise figure ?db 13 0 6 12 11 10 9 8 7 50 500 100 150 200 250 300 350 400 450 24-bit 16-bit w/dvga tpc 13b. noise figure vs. frequency (m inimum attenuation, f clk = 18 msps, bw = 10 khz, low bias) frequency ?mhz noise figure ?db 13 0 6 12 11 10 9 8 7 50 500 100 150 200 250 300 350 400 450 24-bit 16-bit w/dvga tpc 14b. noise figure vs. frequency (m inimum attenuation, f clk = 26 msps, bw = 24 khz, low bias) interferer level ?dbm noise figure ?dbc 16 ?0 8 15 13 11 10 9 ?0 ?5 noise figure agc a ttn 14 12 ?0 ?5 ?0 ?5 ?0 ?5 mean agc attn value 256 0 224 160 96 64 32 192 128 tpc 15b. noise figure vs. interferer level (16-bit data with dvga, bw = 12.5 khz, agcr = 1, f interferer = f if + 110 khz) frequency ?mhz iip3 ?dbm 4 0 ?0 2 0 ? ? ? ? 50 500 100 150 200 250 300 350 400 450 low bias high bias tpc 13c. input ip3 vs. frequency (f clk = 18 msps) frequency ?mhz iip3 ?dbm 2 0 ?0 0 ? ? ? ? 50 500 100 150 200 250 300 350 400 450 low bias high bias tpc 14c. input ip3 vs. frequency (f clk = 26 msps) interferer level ?dbm noise figure ?dbc 16 ?5 8 15 13 11 10 9 ? ?5 noise figure agc a ttn 14 12 ?5 ?5 ?5 ?5 mean agc attn value 128 0 32 96 64 tpc 15c. noise figure vs. interferer level (24-bit data, bw = 12.5 khz, agcr = 1, f interferer = f if + 110 khz) (vddi = vddf = vdda = vddc = vddl = vddd = vddh = vddx, vddq = vddp = 5.0 v, f clk = 18 msps, f if = 109.56 mhz, f lo = 107.4 mhz, t a = 25 c, lo = ? dbm, lo and clk synthesizer disabled, 16-bit data with agc and dvga enabled, unless otherwise noted.) 1 1 data taken with toko fslm series 10 h inductors. 2 high bias corresponds to lna_mixer setting of 33 in spi register 0x01. 3 low bias corresponds to lna_mixer setting of 12 in spi register 0x01.
rev. a ad9874 ?3 serial peripheral interface (spi) the serial peripheral interface (spi) is a bidirectional serial port. it is used to load configuration information into the reg isters listed below as well as to read back their contents. table i provides a list of the registers that may be programmed through the spi po rt. addresses and default values are given in hexadecimal form. table i. spi address map address bit (hex) breakdown width default value name description power control registers 0x00 (7:0) 8 0xff stby standby control bits (ref, lo, cko, ck, gc, lnamx, unused, and adc). 0x01 (7:6) 2 0 lnab lna bias current (0 = 0.5 ma, 1 = 1 ma, 2 = 2 ma, 3 = 3 ma). (5:4) 2 0 mixb mixer bias current (0 = 0.5 ma, 1 = 1.5 ma, 2 = 2.7 ma, 3 = 4 ma). (3:2) 2 0 ckob ck oscillator bias (0 = 0.25 ma, 1 = 0.35 ma, 2 = 0.40 ma, 3 = 0.65 ma). (1:0) 2 0 adcb do not use. 0x02 (7:0) 8 0x00 test factory test mode. do not use. agc 0x03 (7) 1 0 atten apply 16 db attenuation in the front end. (6:0) 7 0x00 agcg (14:8) agc attenuation setting (7 msb of a 15-bit unsigned word). 0x04 (7:0) 8 0x00 agcg(7:0) agc attenuation setting (8 lsb of a 15-bit unsigned word). default corresponds to maximum gain. 0x05 (7:4) 4 0 agca agc attack bandwidth setting. default yields 50 hz raw loop bandwidth. (3:0) 4 0 agcd agc decay time setting. default is decay time = attack time. 0x06 (7) 1 0 agcv enable digital vga to increase agc range by 12 db. (6:4) 3 0 agco agc overload update setting. default is slowest update. (3) 1 0 agcf fast agc (minimizes resistance seen between gcp and gcn). (2:0) 3 0 agcr agc enable/reference level (disabled, 3 db, 6 db, 9 db, 12 db, 15 db below clip). decimation factor 0x07 (7:5) 3 unused (4) 1 0 k decimation factor = 60 (m + 1), if k = 0; 48 (m + 1), if k = 1. (3:0) 4 4 m default is decimate-by-300. lo synthesizer 0x08 (5:0) 6 0x00 lor(13:8) reference frequency divisor (6 msb of a 14-bit word). 0x09 (7:0) 8 0x38 lor(7:0) reference frequency divisor (8 lsb of a 14-bit word). default (56) yields 300 khz from f ref = 16.8 mhz. 0x0a (7:5) 3 0x5 loa ??counter (prescaler control counter). (4:0) 5 0x00 lob(12:8) ??counter msb (5 msb of a 13-bit word). default loa and lob values yield 300 khz from 73.35 mhz to 2.25 mhz. 0x0b (7:0) 8 0x1d lob(7:0) ??counter lsb (8 lsb of a 13-bit word). 0x0c (6) 1 0 lof enable fast acquire. (5) 1 0 loinv invert charge pump (0 = source current to increase vco frequency). (4:2) 3 0 loi charge pump current in normal operation. i pump = (loi + 1) 0.625 ma. (1:0) 2 3 lotm manual control of lo charge pump (0 = off, 1 = up, 2 = down, 3 = normal). 0x0d (5:0) 4 0x0 lofa(13:8) lo fast acquire time unit (6 msb of a 14-bit word). 0x0e (7:0) 8 0x04 lofa(7:0) lo fast acquire time unit (8 lsb of a 14-bit word).
rev. a ad9874 ?4 address bit (hex) breakdown width default value name description clock synthesizer 0x10 (5:0) 6 00 ckr(13:8) reference frequency divisor (6 msb of a 14-bit word). 0x11 (7:0) 8 0x38 ckr(7:0) reference frequency divisor (8 lsb of a 14-bit word). default yields 300 khz from f ref =16.8 mhz; min = 3, max = 16383. 0x12 (4:0) 5 0x00 ckn(12:8) synthesized frequency divisor (5 msb of a 13-bit word). 0x13 (7:0) 8 0x3c ckn(7:0) synthesized frequency divisor (8 lsb of a 13-bit word). default yields 300 khz from f clk = 18 mhz; min = 3, max = 8191. 0x14 (6) 1 0 ckf enable fast acquire. (5) 1 0 ckinv invert charge pump (0 = source current to increase vco frequency). (4:2) 3 0 cki charge pump current in normal operation. i pump = (cki + 1) 0.625 ma. (1:0) 2 3 cktm manual control of clk charge pump (0 = off, 1 = up, 2 = down, 3 = normal). 0x15 (5:0) 6 0x0 ckfa(13:8) ck fast acquire time unit (6 msb of a 14-bit word). 0x16 (7:0) 8 0x04 ckfa(7:0) ck fast acquire time unit (8 lsb of a 14-bit word). ssi control 0x18 (7:0) 8 0x12 ssicra ssi control register a. see table iii. (default is fs and clkout three-stated.) 0x19 (7:0) 8 0x07 ssicrb ssi control register b. see table iii. (16-bit data, maximum drive strength.) 0x1a (3:0) 4 1 ssiord output rate divisor. f clkout = f clk /ssiord. adc tuning 0x1c (1) 1 0 tune_lc perform tuning on the lc portion of the adc (cleared when done). (0) 1 0 tune_rc perform tuning on the rc portion of the adc (cleared when done). 0x1d (2:0) 3 0 capl1(2:0) coarse capacitance setting for lc tank (lsb is 25 pf, differential). 0x1e (5:0) 6 0x00 capl0(5:0) fine capacitance setting for lc tank (lsb is 0.4 pf, differential). 0x1f (7:0) 8 0x00 capr capacitance setting for rc resonator (64 lsb of fixed capacitance). test registers and spi port read enable 0x37 (7:0) 8 0x00 test factory test mode. do not use. 0x39 0x3a (7:4, 2:0) 7 0x0 test factory test mode. do not use. (3) 1 0 spiren enable read from spi port. 0x3b (7:4, 2:0) 7 0x0 test factory test mode. do not use. (3) 1 0 tri three-state doutb. 0x3c (7:0) 1 0x00 test factory test mode. do not use. 0x3e 0x3f (7:0) 8 subject to id revision id (read-only); a write of 0x99 to this register is equivalent to change a power-on reset. table i. spi address map (continued)
rev. a ad9874 ?5 serial port interface (spi) the serial port of the ad9874 has 3-wire or 4-wire spi capabil ity, allowing read/write access to all registers that configure the device? internal parameters. the default 3-wire serial commu- nication port consists of a clock (pc), peripheral enable (pe), and bidirectional data (pd) signal. the inputs to pc, pe, and pd contain a schmitt trigger with a nominal hysteresis of 0.4 v centered about the digital interface supply (i.e., vddh/2). a 4-wire spi interface can be enabled by setting the msb of the ssicrb register (reg. 0x19, bit 7), resulting in the output data also appearing on the doutb pin. note that since the default power-up state sets doutb low, bus contention is possible for systems sharing the spi output line. to avoid any bus conten tion, the doutb pin can be three-stated by setting the fourth con trol bit in the three-state bit (reg 0x3b, bit 3). this bit can then be toggled to gain access to the shared spi output line. an 8-bit instruction header must accompany each read and write spi operation. only the write operation supports an auto- increment mode, allowing the entire chip to be configured in a single write operation. the instruction header is shown in ta b le ii . it includes a read/not-write indicator bit, six address bits, and a don? care bit. the data bits immediately follow the instruction header for both read and write operations. note that the address and data are always given msb first. table ii. instruction header information msb lsb i7 i6 i5 i4 i3 i2 i1 i0 r/w a5 a4 a3 a2 a1 a0 x figure 1a illustrates the timing requirements for a write opera- tion to the spi port. after the peripheral enable (pe) signal goes low, data (pd) pertaining to the instruction header is read on the rising edges of the clock (pc). to initiate a write operation, the read/not-write bit is set low. after the instruction header is read, the eight data bits pertaining to the specified register are shifted into the data pin (pd) on the rising edge of the next eight clock cycles. pe stays low during the operation and goes high at the end of the transfer. if pe rises before the eight clock cycles have passed, the operation is aborted. if pe stays low for an additional eight clock cycles, the destina- tion address is incremented and another eight bits of data are shifted in. again, should pe rise early, the current byte is ignored. by using this implicit addressing mode, the entire chi p can be configured with a single write operation. regis- ters identified as being subject to frequent updates, namely those associated with power control and agc operation, have been assigned adjacent addresses to minimize the time required to update them. note that multibyte registers are big-endian (the most significant byte has the lower address) and are updated when a write to the least significant byte occurs. figure 1b illustrates the timing for a read operation to the spi port. although the ad9874 does not require read access for proper operation, it is often useful in the product development phase or for system authentication. note that the readback enable bit (register 0x3a, bit 3) must be set for a read opera- tion with a 3-wire spi interface. after the peripheral enable (pe) signal goes low, data (pd) pertaining to the instruction header is read on the rising edges of the clock (pc). a read operation occurs if the read/not-write indicator is set high. after the address bits of the instruction header are read, the eight data bits pertaining to the specified register are shifted out of the data pin (pd) on the falling edges of the next eight clock cycles. if the 4-wire spi interface is enabled, the eight data bits will also appear on the doutb pin with the same timing relation- ship as those appearing at pd. after the last data bit is shifted out, the user should return pe high, causing pd to become three-stated and return to its normal status as an input pin. since the auto increment mode is not supported for read opera- tions, an instruction header is required for each register read operation and pe must return high before initiating the next read operation. pc pe pd a5 d7 d6 d0 a0 don? care d1 r/w a1 t clk t hi t low t s t ez t ds t dh t dv doutb d7 d6 d0 don? care d1 don? care don? care don? care don? care don? care figure 1b. spi read operation timing pc pe pd a5 a4 d7 d6 d0 a0 don? care d1 r/w t ds t dh t clk t hi t low t s t h figure 1a. spi write operation timing
rev. a ad9874 ?6 synchronous serial interface (ssi) the ad9874 provides a high degree of programmability of its ssi output data format, control signals, and timing parameters to accommodate various digital interfaces. in a 3-wire digital interface, the ad9874 provides a frame sync signal (fs), a clock output (clkout), and a serial data stream (douta) signal to the host device. in a 2-wire interface, the frame sync information is embedded into the data stream, thus only clkout and douta output signals are provided to the ho st device. the ssi control registers are ssicra, ssicrb, and ssiord. table iii shows the different bit fields associated with these registers. the primary output of the ad9874 is the converted i and q demodulated signal available from the ssi port as a serial bit stream contained within a frame. the output frame rate is equal to the modulator clock frequency (f clk ) divided by the digital filter? decimation factor that is programmed in the decimator register (0x07). the bit stream consists of an i word followed by a q word, where each word is either 24 bits or 16 bits long and is given msb first in twos complement form. two optional bytes may also be included within the ssi frame following the qw ord. one byte contains the agc attenuation and the other byte contains both a count of modulator reset events and an estimate of the received signal amplitude (relative to full scale of the ad9874? adc). figure 2 illustrates the structure of the ssi data frames in a number of ssi modes. 16-bit i and q, eagc = 0, aagc = x:32 data bits 16-bit i and q, eagc = 1, aagc = 0:48 data bits 16-bit i and q, eagc = 1, aagc = 1:40 data bits i (15:0) q (15:0) i (15:0) q (15:0) a ttn (7:0) i (15:0) q (15:0) 0 i (15:0) q (15:0) 1 reset count i (24:0) q (24:0) 24-bit i and q, eagc = 0, aagc = x: 48 data bits a ttn (7:1) ssi(5:1) ssi(5:0) i (24:0) q (24:0) ssi(5:0) reset count a ttn (7:0) 24-bit i and q, eagc = 1, aagc = 0:64 data bits figure 2. ssi frame structure the two optional bytes are output if the eagc bit of ssicra is set. the first byte contains the 8-bit attenuation setting (0 = no attenuation, 255 = 24 db of attenuation), while the second byte contains a 2-bit reset field and 6-bit received signal strength field. the reset field contains the number of m odula- tor reset events since the last report, saturating at 3. the received signal strength (rssi) field is a linear estimate of the signal strength at the output of the first decimation stage; 60 corre- sponds to a full-scale signal. the two optional bytes follow the i and q data as a 16-bit word provided that the aagc bit of ssicra is not set. if the aagc bit is set, the two bytes follow the i and q data in an alternating fashion. in this alternate agc data mode, the lsb of the byte containing the agc attenuation is a 0, while the lsb of the byte containing reset and rssi information is always a 1. in a 2-wire interface, the embedded frame sync bit (efs) within the ssicra register is set to 1. in this mode, the framing infor- mation is embedded in the data stream, with each eight bits of data surrounded by a start bit (low) and a stop bit (high), and each frame ends with at least 10 high bits. fs remains either low or three-stated (default), depending on the state of the sfst bit. other control bits can be used to invert the frame sync (sfsi), to delay the frame sync pulse by one clock period (slfs), to invert the clock (scki), or to three-state the clock (sckt). note that if efs is set, slfs is a don? care. table iii. ssi control registers name width default description ssicra (addr = 0x18) aagc eagc efs sfst sfsi slfs sckt scki 1 a lternate agc data bytes. embed agc data. embed frame sync. t hree-state frame sync. invert frame sync. l ate fr ame sync (1 = late, 0 = early). t hree-state clkout. invert clkout. 1 1 1 1 1 1 1 ssicrb (addr = 0x19) ds 3 fs , clkout, and dout drive strength. 7 dw 1 output bit rate divisor f clkout = f clk / ssiord. 0 1 1 0 0 0 0 0 0 aagc eagc efs sfst sfsi slfs sckt scki dw ds_2 ds_1 ds_0 div_3 ssiord (addr = 0x1a) i/q data-word width (0 = 16 bit, 1 bit?4 bit). automatically 16-bit when the agcv = 1. 4 1 div_2 div_1 div_0 div 4_spi 4_spi 0 enable 4-wire spi interface for spi read operation via doutb. 1 the ssiord register controls the output bit rate (f clkout ) of the serial bit stream. f clkout can be set to equal the modulator clock frequency (f clk ) or an integer fraction of it. it is equal to f clk divided by the contents of the ssiord register. note that f clkout should be chosen such that it does not introduce harm- ful spurs within the pass band of the target signal. users must verify that the output bit rate is sufficient to accommodate the required number of bits per frame for a selected word size and decimation factor. idle (high) bits are used to fill out each frame.
rev. a ad9874 ?7 table iv. number of bits per frame for different ssicr settings number of bits dw eagc efs aagc per frame 0 (16-bit) 0 0 na 32 01na49 * 100 48 101 40 110 69 * 111 59 * 1 (24-bit) 0 0 na 48 01na69 * 100 64 101 56 110 89 * 111 79 * * the number of bits per frame with embedded frame sync (efs = 1) assume at least 10 idle bits are desired. the maximum ssiord setting can be determined by the equation ssiord trunc dec factor of bits per frame {( . ) / (# )} (1) where trunc is the truncated integer value. table iv lists the number of bits within a frame for 16-bit and 24-bit output data formats for all of the different ssicr set- tings. the decimation factor is determined by the contents of register 0x07. an example helps illustrate how the maximum ssiord setting is determined. suppose a user selects a decimation factor of 600 (register 0x07, k = 0, m = 9) and prefers a 3-wire interface with a dedicated frame sync (efs = 0) containing 24-bit data (dw = 1) with nonalternating embedded agc data included (eagc = 1, aagc = 0). referring to table iv, each frame will consist of 64 data bits. using equation 1, the maximum ssiord setting is 9 (= trunc (600/64)). thus, the user can select any ssiord setting between 1 and 9. figure 3a illustrates the output timing of the ssi port for several ssi control register settings with 16-bit i/q data, while figure 3b shows the associated timing parameters. note that the same timing relationship holds for 24-bit i/q data, with the exception that i and q word lengths now become 24 bits. in the default mode of the operation, data is shifted out on rising edges of clkout after a pulse equal to a clock period is output from the frame sync (fs) pin. as described above, the output data consists of a 16- or 24-bit i sample followed by a 16- or 24-bit q sample, plus two optional bytes containing agc and status information. fs dout i15 i14 clkout t v t clk t hi t low t dv figure 3b. timing parameters for ssi timing* * timing parameters also apply to inverted clkout or fs modes, with t dv relative to the falling edge of the clk and/or fs. fs dout clkout scki = 0, sckt = 0, slfs = 0, sfsi = 0, efs = 0, sfst = 0, eagc = 0 i15 i0 q15 q14 q0 clkout fs dout scki = 0, sckt = 0, slfs = 0, sfsi = 0, efs = 0, sfst = 0, eagc = 1, aagc = 0 i15 i0 q15 q14 q0 rssi0 a tten6 a ttn7 clkout fs dout scki = 0, sckt = 0, slfs = 1, sfsi = 0, efs = 0, sfst = 0, eagc = 0 i15 i0 q15 q14 q0 clkout fs dout scki = 0, sckt = 0, slfs = x, sfsi = x, efs = 1, sfst = 1, eagc = 0 scki = 0, sckt = 0, slfs = x, sfsi = x, efs = 1, sfst = 0, eagc = 0: as above, but fs is low idle (high) bits start bit start bit stop bit stop bit start bit hi-z i15 i8 i7 i0 q15 figure 3a. ssi timing for several ssicra settings with 16-bit i/q data
rev. a ad9874 ?8 the ad9874 also provides the means for controlling the switching characteristics of the digital output signals via the ds (drive strength) field of the ssicrb. this feature is useful in limiting switching transients and noise from the digital out- put that may ultimately couple back into the analog signal path, potentially degrading the ad9874? sensitivity performance. figures 3c and 3d show how the nf can vary as a function of the ssi setting for an if frequency of 109.65 mhz. the follow- ing two observations can be made from these figures: ? he nf becomes more sensitive to the ssi output drive strength level at higher signal bandwidth settings. ? he nf is dependent on the number of bits within an ssi frame, becoming more sensitive to the ssi output drive strength level as the number of bits is increased. as a result, one should select the lowest possible ssi drive strength set- ting that still meets the ssi timing requirements. ssi output drive strength setting 2 10.0 4 noise figure ?db 9.6 3 1 8.0 7 6 5 24-bit i/o data 9.8 9.4 9.2 9.0 8.6 8.8 8.4 8.2 16-bit i/o data w/dvga enabled 16-bit i/o data figure 3c. nf vs. ssi output drive strength (vddx = 3.0 v, f clk = 18 msps, bw = 10 khz) ssi output drive strength setting 2 14 4 noise figure ?db 12 3 1 7 7 6 5 24-bit i/o data 13 11 9 10 8 16-bit i/o data w/dvga enabled 16-bit i/o data figure 3d. nf vs. ssi output drive strength (vddx = 3.0 v, f clk = 18 msps, bw = 75 khz) table v lists the typical output rise/fall times as a function of ds for a 10 pf load. rise/fall times for other capacitor loads can be determined by multiplying the typical values presented in table v by a scaling factor equal to the desired capacitive load divided by 10 pf. table v. typical rise/fall times ( 25%) with a 10 pf capacitive load for each ds setting ds typ (ns) 013.5 1 7.2 2 5.0 3 3.7 4 3.2 5 2.8 6 2.3 7 2.0 synchronization using syncb many applications require the ability to synchronize one or more ad9874 in a way that causes the output data to be precisely aligned to an external asynchronous signal. for example, receiver applications employing diversity often require synchro nization of multiple ad9874 digital outputs. satellite communication appli- cations using tdma methods may require synchronization between payload bursts to compensate for reference frequency drift and doppler effects. syncb can be used for this purpose. it is an active-low signal that clears the clock counters in both the decimation filter and the ssi port. the counters in the clock synthesizers are not reset because it is presumed that the clk signals of multiple chips would be connected. syncb also resets the modulator, resulting in a large-scale impulse that must propagate through the ad9874? digital filter and ssi data formatting circuitry before recovering valid output data. at a result, data samples unaffected by this syncb induced impulse can be recovered 12 output data samples after syncb goes high (independent of the decimation factor). figure 4a shows the timing relationship between syncb and the ssi port? clkout and fs signals. syncb is an asyn- chronous active-low signal that must remain low for at least half an input clock period (i.e., 1/(2 f clk )). clkout remains high while fs remains low upon syncb going low. clkout will become active within one to two output clock periods upon syncb returning high. fs will reappear several output cycles later, depending on the digital filter? decimation factor and the ssiord setting. note that for any decimation factor and ssiord setting, this delay is fixed and repeatable. to verify proper synchronization, the fs signals of the multiple ad9874 devices should be monitored. fs syncb clkout figure 4a. syncb timing interfacing to dsps the ad9874 connects directly to an analog devices program mable digital signal processor (dsp). figure 4b illustrates an example with the blackfin series of adsp-2153x processors. the blackfin dsp series is a family of 16-bit products optimized for telecommu- nications applications with its dynamic power management feature, making it well suited for portable radio products. the code com patible family members share the fundamental core attributes of high performance, low power consumption, and the ease-of-use advantages of a microcontroller instruction set.
rev. a ad9874 e19e ad9874 clkout rsclk pc sck pe sel pd mosi doutb miso fs rfs douta dr spi ssi adsp-2153x serial port spi-port figure 4b. example of ad9874 and adsp-2153x interface as shown in figure 4b, ad9874?s synchronous serial interface (ssi) links the receive data stream to the dsp?s serial port (sport). for ad9874 setup and register programming, the device connects directly to adsp-2153x?s spi port. dedicated select lines (sel) allow the adsp-2153x to program and read back registers of multiple devices using only one spi port. the dsp driver code pertaining to this interface is available on the ad9874 web page (http://www.analog.com/analog_root/ static/techsupport/designtools/evaluationboards/ ad9874blackfininterfacing.html). power control to allow power consumption to be minimized, the ad9874 possesses numerous spi programmable power-down and bias control bits. the ad9874 powers up with all of its functional blocks placed into a standby state (i.e., stby register default is 0xff). each major block may then be powered up by writing a0 to the appropriate bit of the stby register. this scheme provides the greatest flexibility for configuring the ic to a spe- cific application as well as for tailoring the ic?s power-down and wake-up characteristics. table vi summarizes the function of each of the stby bits. note that when all the blocks are in standby, the master reference circuit is also put into standby, and thus the current is reduced by a further 0.4 ma. table vi. standby control bits current stby redu ction wake-up bit effect (ma) 1 time (ms) 7:ref voltage reference off; 0.6 <0.1 (c ref all biasing shut down. = 4.7 nf) 6:lo lo synthesizer off, 1.2 note 2 ioutl three-state. 5: cko clock oscillator off. 1.1 note 2 4:ck clock synthesizer off, 1.3 note 2 ioutc three-state. clock buffer off if adc is off. 3:gc gain control dac off. 0.2 depends gcp and gcn three-state. on c gc 2:lnamx lna and mixer off. cxvm, 8.2 <2.2 cxvl, and cxif three-state. 1:unused 0:adc adc off; clock buffer off 9.2 <0.1 if clk synthesizer off; vcm three-state; clock to the digital filter halted; digital outputs static. notes 1 when all blocks are in standby, the master reference circuit is also put into standby, and thus the current is further reduced by 0.4 ma. 2 wake-up time is dependent on programming and/or external components. the ad9874 also allows control over the bias current in the lna, mixer, and clock oscillator. the effects on current consumption and system performance are described in the section dealing with the affected block. lo synthesizer the lo synthesizer shown in figure 5 is a fully programmable pll capable of 6.25 khz resolution at input frequencies up to 300 mhz and reference clocks of up to 25 mhz. it consists of a low noise digital phase-frequency detector (pfd), a variable output current charge pump (cp), a 14-bit reference divider, programmable a and b counters, and a dual-modulus 8/9 pres- caler. the a (3-bit) and b (13-bit) counters, in conjunction with the dual 8/9 modulus prescaler, implement an n divider with n = 8 , at the pfd input. a complete pll (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and vco (voltage controlled oscillator). the a, b, and r counters can be programmed via the following registers: loa, lob, and lor. the charge pump output cur- rent is programmable via the loi register from 0.625 ma to 5.0 ma using the equation ipump loi ma =+ (). 10 625 (2) an on-chip fast acquire function (enabled by the lof bit) automatically increases the output current for faster settling during channel changes. the synthesizer may also be disabled using the lo standby bit located in the stby register. fa s t ac q uire 8/9 a, b counters lo bu ffer loa, lob f lo from vco ref bu ffer f ref lor r f ref phase/ frequency detector to external loop filter f lo charge pump figure 5. lo synthesizer the lo (and clk) synthesizer works in the following manner. the externally supplied reference frequency, f ref , is buffered and divided by the value held in the r counter. the internal f ref is then compared to a divided version of the vco fre- quency, f lo . the phase/frequency detector provides up and down pulses whose widths vary, depending upon the differ- ence in phase and frequency of the detector?s input signals. the up/down pulses control the charge pump, making current available to charge the external low-pass loop filter when there is a discrepancy between the inputs of the pfd. the output of the low-pass filter feeds an external vco whose output frequency, f lo , is driven such that its divided down version, f lo , matches that of f ref , thus closing the feedback loop. the synthesized frequency is related to the reference frequency and the lo register contents as follows: f lob loa lor f lo ref = + ()/ 8 (3) note that the minimum allowable value in the lob register is 3 and its value must always be greater than that loaded into loa .
rev. a ad9874 ?0 an example may help illustrate how the values of loa , lob , and lor can be selected. consider an application employing a 13 mhz crystal oscillator (i.e., f ref = 13 mhz) with the requirement that f ref = 100 khz and f lo = 143 mhz (i.e., high side injection with f if = 140.75 mhz and f clk = 18 msps). lor is selected to be 130 such that f ref = 100 khz. the n-divider factor is 1430, which can be realized by selecting lob = 178 and loa = 6. the stability, phase noise, spur performance, and transient response of the ad9874 s lo (and clk) synthesizers are determined by the external loop filter, the vco, the n-divide factor, and the reference frequency, fref. a good overview of the theory and practical implementation of pll synthesiz- ers (featured as a three-part series in analog dialogue) can be found at: ? www.analog.com/library/analogdialogue/archives/33-03/ phase/index.html ? www.analog.com/library/analogdialogue/archives/33-05/ phase_locked/index.html ? www.analog.com/library/analogdialogue/archives/33-07/ phase3/index.html also, a free software copy of the analog devices adisimpll, a pll synthesizer simulation tool, is available at www.analog.com. note that the adf4112 model can be used as a close approxima- tion to the ad9874 s lo synthesizer when using this software tool. fref 84k ~v ddl/2 lo bu ffer 500 500 to mixer lo port 1.75v bias lop lon notes 1. esd diode structures omitted for clarity. 2. fref stby switches shown with lo synthesizer on. figure 6. equivalent input of lo and ref buffers figure 6 shows the equivalent input structures of the synthesiz- ers lo and ref buffers (excluding the esd structures). the lo input is fed to the lo synthesizer s buffer as well as the ad9874 s mixer s lo port. both inputs are self-biasing and thus tolerate ac-coupled inputs. the lo input can be driven with a single-ended or differential signal. single-ended dc- coupled inputs should ensure sufficient signal swing above and below the common-mode bias of the lo and ref buffers (i.e., 1.75 v and vddl/2). note that the f ref input is slew rate dependent and must be driven with input signals exceeding 7.5 v/ s to ensure proper synthesizer operation. if this con- dition can not be m et, an external logic gate can be inserted prior to the f ref input to square-up the signal thus allowing a f ref input frequency approching dc. fast acquire mode the fast acquire circuit attempts to boost the output current when the phase difference between the divided-down lo (i.e., f lo ) and the divided-down reference frequency (i.e., f ref ) exceeds the threshold determined by the lofa register. the lofa register specifies a divisor for the f ref signal that deter- mines the period (t) of this divided-down clock. this period defines the time interval used in the fast acquire algorithm to control the charge pump current. assume for the moment that the nominal charge pump current is at its lowest setting (i.e., loi = 0) and denote this minimum current by i 0 . when the output pulse from the phase compara- tor exceeds t , the output current for the next pulse is 2 i 0 . when the pulse is wider than 2t, the output current for the next pulse is 3 i 0 , and so forth, up to eight times the minimum output current. if the nominal charge pump current is more than the minimum value (i.e., loi > 0), the preceding rule is only applied if it results in an increase in the instantaneous charge pump current. if the charge pump current is set to its lowest value (loi = 0) and the fast acquire circuit is enabled, the instantaneous charge pump current will never fall below 2 i 0 when the pulsewidth is less than t . thus, the charge pump current when fast acquire is enabled is given by: ii loi pulsewidth t pump fa ? =+ 0 11 { max( , , )} (4) the recommended setting for lofa is lor/16. choosing a larger value for lofa will increase t . thus, for a given phase difference between the lo input and the f ref input, the instan- taneous charge pump current will be less than that available for a lofa value of lor/16. similarly, a smaller value for lofa will decrease t , making more current available for the same phase difference. in other words, a smaller value of lofa will enable the synthesizer to settle faster in response to a frequency hop than will a large lofa value. care must be taken to choose a value for lofa that is large enough (values greater than 4 recommended) to prevent the loop from oscillating back and forth in response to a frequency hop. table vii. spi registers associated with lo synthesizer address bit default (hex) breakdown width value name 0x00 (7:0) 1 0xff stby 0x08 (5:0) 6 0x00 lor(13:8) 0x09 (7:0) 8 0x38 lor(7:0) 0x0a (7:5) 3 0x5 loa (4:0) 5 0x00 lob(12:8) 0x0b (7:0) 8 0x1d lob(7:0) 0x0c (6) 1 0 lof (5) 1 0 loinv (4:2) 3 0 loi (1:0) 2 0 lotm 0x0d (3:0) 4 0x0 lofa(13:8) 0x0e (7:0) 8 0x04 lofa(7:0)
rev. a ad9874 ?1 clock synthesizer the clock synthesizer is a fully programmable integer-n pll capable of 2.2 khz resolution at clock input frequencies up to 18 mhz and reference frequencies up to 25 mhz. it is similar to the lo synthesizer described in figure 5 with the following exceptions: it does not include an 8/9 prescaler nor an a counter. it includes a negative-resistance core that, when used in conjunc- tion with an external lc tank and varactor, serves as the vco. the 14-bit reference counter and 13-bit n-divider counter can be programmed via registers ckr and ckn . the clock frequency, f clk , is related to the reference frequency by the equation f ckn ckr f clk ref = () (5) the charge pump current is programmable via the cki register from 0.625 ma to 5.0 ma using the equation: i cki ma pump =+ () 10 625 . (6) the fast acquire subcircuit of the charge pump is controlled by the ckfa register in the same manner as the lo synthesizer is controlled by the lofa register. an on-chip lock detect func- tion (enabled by the ckf bit) automatically increases the output current for faster settling during channel changes. the synthesizer may also be disabled using the ck standby bit located in the stby register. 2 clk osc. bias i bias = 0.15 ma, 0.25 ma, 0.40 ma, or 0.65 ma vddc = 3.0 v ioutc l osc 0.1 f r bias c osc loop filter c va r r d ad9874 clkn clkp v cm = vddc ?r bias i bias > 1.6v f osc > 1/{2 (l osc (c v aractor //c osc )) 1/2 } c p c z r f figure 7a. external loop filter, varactor, and lc tank are required to realize a complete clock synthesizer the ad9874 clock synthesizer circuitry includes a negative- resistance core so that only an external lc tank circuit with a varactor is needed to realize a voltage controlled clock oscillator (vco). figure 7a shows the external components required to complete the clock synthesizer along with the equivalent input circuitry of the clk input. the resonant frequency of the vco is approximately determined by l osc and the series equivalent capacitance of c osc and c var . as a result, l osc , c osc , and c var should be selected to provide a sufficient tuning range to ensure proper locking of the clock synthesizer. the bias, i bias , of the negative-resistance core has four pro- grammable settings. lower equivalent q of the lc tank circuit may require a higher bias setting of the negative-resistance core to ensure proper oscillation. r bias should be selected so the common-mode voltage at clkp and clkn is approximately 1.6 v. the synthesizer may be disabled via the ck standby bit to allow the user to employ an external synthesizer and/or vco in place of those resident on the ic. note that if an external clk source or vco is used, the clock oscillator must be dis- abled via the cko standby bit. the phase noise performance of the clock synthesizer is depen- dent on several factors, including the clk oscillator i bias setting, charge pump setting, loop filter component values, and internal f ref setting. figures 7b and 7c show how the measured phase noise attributed to the clock synthesizer varies (relative to an external f clk ) as a function of the i bias setting and charge pump setting for a ?1 dbm ifin signal at 73.35 mhz with an external lo signal at 71.1 mhz. figure 7b shows that the opti- mum phase noise is achieved with the highest i bias (cko) setting, while figure 7c shows that the higher charge pump values provide the optimum performance for the given loop filter configuration. the ad9874 clock synthesizer and oscilla- tor were set up to provide an f clk of 18 mhz from an external f ref of 16.8 mhz. the following external component values were selected for the synthesizer: r f = 390 ? , r d = 2 k ? , c z = 0.68 f, c p = 0.1 f, c osc = 91 pf, l osc = 1.2 h, and c var = toshiba 1sv228 varactor. ?5 0 ?0 ?00 ?10 ?20 dbc/hz ?0 ?5 ?0 ? 0 5 10 15 20 25 frequency offset ?khz ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?30 ?40 cko = 1 cko = 0 cko = 2 cko = 3 ext clk figure 7b. clk phase noise vs. i bias setting (cko) (if = 73.35 mhz, if = 71.1 mhz, ifin = ?1 dbm, f clk = 18 mhz, f ref = 16.8 mhz) (clk syn settings: cki = 7, clr = 56, and cln = 60 with f ref = 300 khz)
rev. a ad9874 ?2 ?5 0 ?0 ?00 ?10 ?20 dbc/hz ?0 ?5 ?0 ? 0 5 10 15 20 25 frequency offset ?khz ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?30 ?40 cp = 0 cp = 2 cp = 4 cp = 6 ext clk figure 7c. clk phase noise vs. charge pump setting bias (if = 73.35 mhz, if = 71.1 mhz, ?1 dbm, f clk = 18 mhz, f ref = 16.8 mhz) (clk syn settings: cko bias = 3, ckr = 56, and ckn = 60 with f ref = 300 khz) table viii. spi registers associated with clk synthesizer address bit default (hex) breakdown width value name 0x00 (7:0) 8 0xff stby 0x01 (3:2) 2 0 ckob 0x10 (5:0) 6 00 ckr(13:8) 0x11 (7:0) 8 0x38 ckr(7:0) 0x12 (4:0) 5 0x00 ckn(12:8) 0x13 (7:0) 8 0x3c ckn(7:0) 0x14 (6) 1 0 ckf (5) 1 0 ckinv (4:2) 3 0 cki (1:0) 1 0 cktm 0x15 (3:0) 4 0x0 ckfa(13:8) 0x16 (7:0) 8 0x04 ckfa(7:0) if lna/mixer the ad9874 contains a single-ended lna followed by a gil- bert-type active mixer, shown in figure 8 with the required external components. the lna uses negative shunt feedback to set its input impedance at the ifin pin, thus making it depen- dent on the lna bias setting and input frequency. it can be modeled as approximately 370 ? //1.4 pf (620%) for the higher bias settings below 100 mhz. figures 9a and 9b show the equivalent input impedance versus frequency characteristics of the ad9874 with all the lna bias settings. the increase in shunt resistance versus frequency can be attributed to the reduction in bandwidth, thus the amount of negative feedback of the lna. note that the input signal into ifin should be ac-coupled via a 10 nf capacitor since the lna input is self-biasing. r f ifin r gain r bias vddi mxop lo input = 0.3v p-p to 1.0v p-p dc servo loop multi-tanh v? stage cxif mxon cxvm 50 c l l cxvl 2.7v to 3.6v figure 8. simplified schematic of ad9874? lna/mixer frequency ?mhz 500 100 400 600 200 resistance ? 0 550 450 150 50 350 300 350 300 250 lna bias = 0 lna bias = 1 lna bias = 2 lna bias = 3 figure 9a. the shunt input resistance vs. the frequency of the ad9874? if1 input frequency ?mhz 1.5 100 0.5 2.5 200 capacitance ?pf 0 2.0 1.0 150 50 0 350 300 250 lna bias = 3 lna bias = 2 lna bias = 1 lna bias = 0 figure 9b. the shunt capacitance vs. the frequency of the ad9874? if1 input
rev. a ad9874 ?3 the mixer? differential lo port is driven by the lo buffer stage shown in figure 6, which can be driven single-ended or differential. since it is self-biasing, the lo signal level can be ac-coupled and range from 0.3 v p-p to 1.0 v p-p with negli gible effect on performance. the mixer? open-collector outputs, mxop and mxon, drive an external resonant tank consisting of a differential lc network tuned to the if of the band-pass - adc (i.e., f if2_adc = f clk /8). the two inductors provide a dc bias path for the mixer core via a series resistor of 50 ? , which is included to dampen the common-mode response. the mixer? output must be ac-coupled to the input of the band-pass - adc, if2p, and if2n via two 100 pf capacitors to ensure proper tuning of the lc center frequency. the external differential lc tank forms the resonant element for the first resonator of the band-pass - modulator, and so must be tuned to the f clk /8 center frequency of the modulator. the inductors should be chosen such that their impedance at f clk /8 is about 140 ? (i.e., l = 180/ f clk ). an accuracy of 20% is considered to be adequate. for example, at f clk = 18 mhz, l = 10 h is a good choice. once the inductors have been selected, the required tank capacitance may be calculated using the relation f clk /8 = 1/{2 (2l c) 1/2 }. for example, at f clk = 18 mhz and l = 10 h, a capacitance of 250 pf is needed. however, in order to accommodate an induc- tor tolerance of 10%, the tank capacitance must be adjustable from 227 pf to 278 pf. selecting an external capacitor of 180 pf ensures that even with a 10% tolerance and stray capaci- tances as high as 30 pf, the total capacitance will be less than the minimum value needed by the tank. extra capacitance is supplied by the ad9874? on-chip programmable capacitor array. since the programming range of the capacitor array is at least 160 pf, the ad9874 has plenty of range to make up for the tolerances of low cost external components. note that if f clk is increased by a factor of 1.44 mhz to 26 mhz so that f clk /8 becomes 3.25 mhz, reducing l and c by approximately the same factor (i.e., l = 6.9 h and c = 120 pf) still satisfies the requirements stated above. the selection of the inductors is an important consideration in realizing the full linearity performance of the ad9874. this is true when operating the lna and mixer at maximum bias and low clock frequency. figure 10 shows how the two-tone input- referred imd versus the input level performance at an if of 109 mhz and f clk of 18 mhz varies between toko? fslm series and coilcraft? 1812cs series inductors. the graph also shows the extrapolated point of intersection used to determine the iip3 performance. note that the coilcraft inductor provides a 7 db to 8 db improvement in performance and closely approximates the 3:1 slope associated with a third order linearity compared to the 2.65:1 slope associated with the toko inductor. the coilcraft 1008cs series showed perfor- mance similar to that of the 1812cs series. it is worth noting that the difference in imd performance between these two inductor families with an f clk of 26 mhz is insignificant. ?0 ?4 ?8 ?6 ?8 ?2 ?4 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 input referred power ?dbm to ko inductor p imd = 2.64 p in + 4.6 p in f in = 109.65mhz coilcraft p imd = 2.92 p in + 6.9 figure 10. imd performance between different inductors with lna and mixer at full bias and f clk of 18 mhz both the lna and mixer have four programmable bias settings so that current consumption can be minimized for a given applica tion. figures 11a, 11b, and 11c show how the lna and mixer? noise figure (nf), linearity (iip3), if clip point, current consumption, and frequency response are affected for a given lna/mixer bias setting. the measurements were taken at an if = 73.35 mhz and lo = 71.1 mhz, with supplies set to 3 v. 1_0 13 12 11 10 9 8 noise figure ?db 1_1 1_2 1_3 2_0 2_1 2_2 2_3 3_0 3_1 3_2 3_3 ?0 ?8 ?6 ?4 ?2 ?0 clip point ?dbm clip point noise figure lna_mixer bias setting figure 11a. lna/mixer noise figure and conversion gain vs. bias setting 1_0 5 0 ? ?0 ?5 ?5 input iip3 ?dbm 1_1 1_2 1_3 2_0 2_1 2_2 2_3 3_0 3_1 3_2 3_3 7.00 8.25 5.75 4.50 3.25 2.00 iddi ?ma 9.50 ?0 lna_mixer current iip3 lna_mixer bias setting figure 11b. lna/mixer iip3 and current consumption vs. bias setting
rev. a ad9874 ?4 based on these characterization curves, a lna/mixer bias setting of 3_3 is suitable for most applications since it will provide the greatest dynamic range in the presence of multiple unfiltered interferers. however, portable radio applications demanding the lowest possible power may benefit by changing the lna/mixer bias setting based on the received signal strength power (i.e., rssi) available from the ssi output data. for instance, selecting an lna_mixer bias setting of 1_2 for nominal input strength conditions (i.e., ?8 dbm) from overdriving the - modulator. in such instances, the - modulator will become unstable, thus severely desensitizing the receiver. the 16 db step attenuator can be invoked by set- ting the atten bit (register 0x03, bit 7), causing the mixer gain to be reduced by 16 db. the 16 db step attenuator could be used in applications in which a potential target or blocker signal could exceed the if input clip point. although the lna will be driven into compression, it may still be possible to recover the desired signal if it is fm. refer to tpc 7c to see the gain compression characteristics of the lna and mixer with the 16 db attenuator enabled. table ix. spi registers associated with lna/mixer address bit default (hex) breakdown width value name 0x00 (7:0) 8 0xff stby 0x01 (7:6) 2 0 lnab 0x01 (5:4) 2 0 mixb 0x03 (7) 1 0 atten band-pass sigma-delta ( - ) adc the adc of the ad9874 is shown in figure 12. the adc contains a sixth order multibit band-pass - modulator that achieves very high instantaneous dynamic range over a narrow frequency band. the loop filter of the band-pass - modulator consists of two continuous-time resonators followed by a dis crete- time resonator, with each resonator stage contributing a pair of complex poles. the first resonator is an external lc tank, while the second is an on-chip active rc filter. the output of the lc resonator is ac-coupled to the second resonator input via 100 pf capacitors. the center frequencies of these two continuous-time resonators must be tuned to f clk /8 for the adc to function properly. the center frequency of the discrete-time resonator automatically scales with f clk , thus no tuning is required. to digital fi lter sc r eso- nator nine- l evel flas h esl g ain c ontrol mixer ou tput e xternal lc f clk = 13 msps to 26 msps mxop mxon if2p if2n rc r eso- nator dac1 figure 12. equivalent circuit of sixth order band-pass modulator figure 13a shows the measured power spectral density measured at the output of the undecimated band-pass - modulator. note that the wide dynamic range achieved at the center fre- quency, f clk /8, is achieved once the lc and rc resonators of the - modulator have been successfully tuned. the out-of- band noise is removed by the decimation filters following quadrature demodulation. 0 0 ?0 ?0 ?0 ?0 dbfs/nbw ?0 frequency ?mhz ?0 ?0 ?0 ?0 ?00 123456789 ?dbfs output f clk = 18mhz nbw = 3.3khz figure 13a. measured undecimated spectral out- put of modulator adc with f clk = 18 msps and noise bandwidth of 3.3 khz
rev. a ad9874 ?5 the signal transfer function of the ad9874 possesses inherent antialias filtering by virtue of the continuous-time portions of the loop filter in the band-pass - modulator. figure 13b illustrates this property by plotting the nominal signal transfer function of the adc for frequencies up to 2 f clk . the notches that naturally occur for all frequencies that alias to the f clk /8 pass band are clearly visible. even at the widest bandwidth setting, the notches are deep enough to provide greater than 80 db of alias protection. thus, the wideband if filtering requirements preceding the ad9874 will be determined mostly by the mixer? image band, which is offset from the desired if input frequency by f clk /4 (i.e., 2 3 f clk /8) rather than any aliasing associated with the adc. 0 0 ?0 ?0 ?0 ?0 db ?0 normalized frequency ?relative to f out ?0 ?0 ?0 0.5 1.0 1.5 2.0 notch at all alias frequencies figure 13b. signal transfer function of the band-pass - modulator from 0 f clk to 2 f clk figure 13c shows the nominal signal transfer function magni- tude for frequencies near the f clk /8 pass band. the width of the pass band determines the transfer function droop, but even at the lowest oversampling ratio (48) where the pass band edges are at f clk /192 ( 0.005 f clk ), the gain variation is less than 0.5 db. note that the amount of attenuation offered by the signal transfer function near f clk /8 should also be considered when determining the narrow-band if filtering requirements preceding the ad9874. ?.10 0 ? db ?0 normalized frequency ?relative to f clk ?5 ?0 ?.05 0 0.05 0.10 figure 13c. magnitude of the adc? signal transfer function near f clk /8 tuning of the - modulator? two continuous-time resonators is essential in realizing the adc? full dynamic range and must be performed upon system startup. to facilitate tuning of the lc tank, a capacitor array is internally connected to the mxop and mxon pins. the capacitance of this array is program- mable from 0 pf to 200 pf 20% and can be programmed either automatically or manually via the spi port. the capaci- tors of the active rc resonator are similarly programmable. note that the ad9874 can be placed in and out of its standby mode without retuning since the tuning codes are stored in the spi registers. when tuning the lc tank, the sampling clock frequency must be stable and the lna/mixer, lo synthesizer, and adc must all be placed in standby. tuning is triggered when the adc is taken out of standby if the tune_lc bit of register 0x1c has been set. this bit will clear when the tuning operation is com- plete (less than 6 ms). the tuning codes can be read from the 3-bit capl1 (0x1d) and the 6-bit capl0 (0x1e) registers. in a similar manner, tuning of the rc resonator is activated if the tune_rc bit of register 0x1c is set when the adc is taken out of standby. this bit will clear when tuning is com- plete. the tuning code can be read from the capr (0x1f) register. setting both the tune_lc and tune_rc bits tunes the lc tank and the active rc resonator in succession. during tuning, the adc is not operational and neither data nor a clock is available from the ssi port. table x lists the recommended sequence of the spi commands for tuning the adc, and table xi lists all of the spi registers associated with band-pass - adc. table x. tuning sequence address value comments 0x00 0x45 lo synthesizer, lna/mixer, and adc are placed in standby. * 0x1c 0x03 set tune_lc and tune_rc. wait for clk to stabilize if clk synthesizer used. 0x00 0x44 take the adc out of standby. wait for 0x1c to clear (<6 ms). lna/mixer can now be taken out of standby. * if external clk vco or source used, the clk oscillator must also be disabled. table xi. spi registers associated with band-pass - adc address bit default (hex) breakdown width value name 0x00 (7:0) 8 0xff stby 0x1c (1) 1 0 tune_lc (0) 1 0 tune_rc 0x1d (2:0) 3 0 capl1(2:0) 0x1e (5:0) 6 0x00 capl1(5:0) 0x1f (7:0) 8 0x00 capr
rev. a ad9874 ?6 once the ad9874 has been tuned, the noise figure degradation attributed solely to the temperature drift of the lc and rc resonators is minimal. since the drift of the rc resonator is actually negligible compared to that of the lc resonator, the external l and c components?temperature drift characteristics tend to dominate. figure 13d shows the degradation in noise figure as the product of the lc value is allowed to vary from ?2.5% to +12.5%. note that the noise figure remains relatively constant over a 3.5% range (i.e., 35,000 ppm), suggesting that most applications will not be required to retune over the operating temperature range. ?5 12 11 nf ?db 10 lc error ?% 9 8 0510 15 ? ?0 bw = 75khz bw = 10khz bw = 30khz figure 13d. typical noise figure degradation from l and c component drift (f clk = 18 msps, f if = 73.3501 mhz) decimation filter the decimation filter shown in figure 14 consists of an f clk /8 complex mixer and a cascade of three linear phase fir filters: dec1, dec2, and dec3. dec1 downsamples by a factor of 12 using a fourth order comb filter. dec2 also uses a fourth order comb filter, but its decimation factor is set by the m field of register 0x07. dec3 is either a decimate-by-5 fir filter or a decimate-by-4 fir filter, depending on the value of the k bit within register 0x07. thus, the composite decimation factor can be set to either 60 m or 48 m for k equal to 0 or 1, respectively. the output data rate (f out ) is equal to the modulator clock frequency (f clk ) divided by the digital filter? decimation factor. due to the transition region associated with the decimation filter? frequency response, the decimation factor must be selected such that f out is equal to or greater than twice the signal bandwidth. this ensures low amplitude ripple in the pass band along with the ability to provide further application-spe- cific digital filtering prior to demodulation. 4 or 5 cos sin data from - modulator dec1 sinc 4 filter 12 dec2 sinc 4 filter m + 1 m dec3 fir filter k i q complex data to ssi port figure 14. decimation filter architecture figure 15a shows the response of the decimation filter at a decimation factor of 900 (k = 0, m = 14) and a sampling clock frequency of 18 mhz. in this example, the output data rate (f out ) is 20 ksps, with a usable complex signal band- width of 10 khz centered around dc. as this figure shows, the first and second alias bands (occurring at even integer multiples of f out /2) have the least attenuation but provide at least 88 db of attenuation. note that signals falling around frequency offsets that are odd integer multiples of f out /2 (i.e., 10 khz, 30 khz, and 50 khz) will fall back into the transition band of the digital filter. frequency ?khz 0 ?0 ?00 030 10 20 ?0 ?0 ?0 40 100 db fold- ing point 5.0khz pass band ?20 70 80 60 50 90 ?8db ?8db ?01db ?03db figure 15a. decimation filter frequency response for f out = 20 ksps (f clk = 18 mhz, osr = 900) f igure 15b shows the response of the decimation filter with a decimation factor of 48 and a sampling clock rate of 26 mhz. the alias attenuation is at least 94 db and occurs for frequencies at the edges of the fourth alias band. the difference between the alias attenuation characteristics of figure 15b and those of figure 15a is due to the fact that the third decimation stage decimates by a factor of 5 for figure 15a compared with a factor of 4 for figure 15b. 0 ?0 ?00 ?0 ?0 ?0 db ?20 frequency mhz 0 1.5 0.5 1.0 2.0 2.5 135.466khz pass band ?8db ?15db ?4db figure 15b. decimation filter frequency response for f out = 541.666 ksps (f clk = 26 mhz, osr = 48)
rev. a ad9874 ?7 figures 16a and 16b show expanded views of the pass band for the two possible configurations of the third decimation filter. when decimating by 60 n (k = 0), the pass-band gain variation is 1.2 db; when decimating by 48 n (k = 1), the pass-band gain variation is 0.9 db. normalization of full scale at band center is accurate to within 0.14 db across all decimation modes. figures 17a and 17b show the folded frequency response of the decimator for k = 0 and k = 1, respectively. normalized frequency ?relative to f out 0 3 0.250 db 0.125 2 1 0 ? ? ? pa ss-band gain frequency = 1.2db figure 16a. pass-band frequency response of the decimator for k = 0 normalized frequency ?relative to f out 0 3 0.250 db 0.125 2 1 0 ? ? ? pa ss-band gain variation = 0.9db figure 16b. pass-band frequency response of the decimator for k = 1 normalized frequency ?relative to f out 0 0 0.50 db 0.25 ?0 ?0 ?0 ?0 ?00 ?20 min alias attn = 87.7db figure 17a. folded decimator frequency response for k = 0 normalized frequency ?relative to f out 0 0 0.50 db 0.25 ?0 ?0 ?0 ?0 ?00 ?20 min alias attn = 97.2db figure 17b. folded decimator frequency response for k = 1
rev. a ad9874 ?8 variable gain amplifier operation with automatic gain control the ad9874 contains both a variable gain amplifier (vga) and a digital vga (dvga) along with all of the necessary signal estimation and control circuitry required to implement auto- matic gain control (agc), as shown in figure 18. the agc control circuitry provides a high degree of programmability, allowing users to optimize the agc response as well as the ad9874? dynamic range for a given application. the vga is programmable over a 12 db range and implemented within the adc by adjusting its full-scale reference level. increasing the adc? full scale is equivalent to attenuating the signal. an additional 12 db of digital gain range is achieved by scaling the output of the decimation filter in the dvga. note that a slight increase in the supply current (i.e., 0.67 ma) is drawn from vddi and vddf as the vga changes from 0 db to 12 db attenuation. the purpose of the vga is to extend the usable dynamic range of the ad9874 by allowing the adc to digitize a desired signal over a large input power range as well as recover a low level signal in the presence of larger unfiltered interferers without saturating or clipping the adc. the dvga is most useful in extending the dynamic range in narrow-band applications requiring a 16-bit i and q data format. in these applications, quantization noise resulting from internal truncation to 16 bits as well as external 16-bit fixed point post-processing can degrade the ad9874? effective noise figure by 1 db or more. the dvga is enabled by writing a 1 to the agcv field. the vga (and the dvga) can operate in either a user controlled variable gain mode or automatic gain control (agc) mode. it is worth noting that the vga imparts negligible phase error upon the desired signal as its gain is varied over a 12 db range. this is due to the bandwidth of the vga being far greater than the downconverted desired signal (centered about f clk /8) and remaining relatively independent of gain setting. as a result, phase modulated signals should experience minimal phase error as the agc varies the vga gain while tracking an interferer or the desired signal under fading conditions. note that the enve- lope of the signal will still be affected by the agc settings. variable gain control the variable gain control is enabled by setting the agcr field of register 0x06 to 0. in this mode, the gain of the vga (and the dvga) can be adjusted by writing to the 16-bit agcg register. the maximum update rate of the agcg register via the spi port is f clk /240. the msb of this register is the bit that enables 16 db of attenuation in the mixer. this feature allows the ad9874 to cope with large level signals beyond the vga? range (i.e., > ?8 dbm at lna input) to prevent overloading of the adc. the lower 15 bits specify the attenuation in the remainder of the signal path. if the dvga is enabled, the attenuation range is from ?2 db to +12 db since the dvga provides 12 db of digital gain. in this case, all 15 bits are significant. however, with the dvga disabled, the attenuation range extends from 0 db to 12 db and only the lower 14 bits are useful. figure 19 shows the relationship between the amount of attenuation and the agc register setting for both cases. agcg setting ?hex ?2 0 12 0000 agc attenuation ?db 1fff 3fff 7fff 5fff 6 ? vga r ange dvga r ange only vga enabled dvga and vga enabled figure 19. agc gain range characteristics vs. agcg register setting with and without dvga enabled + vga dac - adc fs dec1 12 dec2 and dec3 i + q i + q select larger a gcr ref level k a gca/agcd scaling c dac gcp 1 (1 ?z ? ) a gcv setting dvga rssi data to ssi i/q data to ssi figure 18. functional block diagram of vga and agc
rev. a ad9874 ?9 referring to figure 18, the gain of the vga is set by an 8-bit con- trol dac that provides a control signal to the vga appearing at the gain control pin (gcp). for applications implementing auto- matic gain control, the dac? output resistance can be reduced by a factor of 9 to decrease the attack time of the agc response for faster signal acquisition. an external capacitor, c dac , from gcp to analog ground is required to smooth the dac? output each time it updates as well as to filter wideband noise. note that c dac , in combination with the dac? programmable out- put resistance, sets the ? db bandwidth and time constant associated with this rc network. a linear estimate of the received signal strength is performed at the output of the first decimation stage (dec1) and output of the dvga (if enabled) as discussed in the agc section. this data is available as a 6-bit rssi field within an ssi frame with 60 corresponding to a full-scale signal for a given agc attenua- tion setting. the rssi field is updated at f clk /60 and can be used with the 8-bit attenuation field (or agcg attenuation setting) to determine the absolute signal strength. the accuracy of the mean rssi reading (relative to the if input power) depends on the input signal? frequency offset relative to the if frequency since both dec1 filter? response as well as the adc? signal transfer function attenuate the mixer? downconverted signal level centered at f clk /8. as a result, the estimated signal strength of input signals falling within prox- imity to the if is reported accurately, while those signals at increasingly higher frequency offsets incur larger measure- ment errors. figure 20 shows the normalized error of the rssi reading as a function of the frequency offset from the if frequency. note that the significance of this error becomes apparent when determining the maximum input interferer (or blocker) levels with the agc enabled. 0 0 ? measured rssi error ?db ? normalized frequency offset ?( f in ? f if ) f clk ? ?8 0.03 0.04 0.05 0.02 0.01 ?2 ?5 figure 20. normalized rssi error vs. normalized if frequency offset automatic gain control (agc) the gain of the vga (and dvga) is automatically adjusted when the agc is enabled via the agcr field of register 0x06. in this mode, the gain of the vga is continuously updated at f clk /60 in an attempt to ensure that the maximum analog signal level into the adc does not exceed the adc clip level and that the rms output level of the adc is equal to a programmable reference level. with the dvga enabled, the agc control loop also attempts to minimize the effects of 16-bit truncation noise prior to the ssi output by continuously adjusting the dvga? gain to ensure maximum digital gain while not exceeding the programmable reference level. this programmable level can be set at 3 db, 6 db, 9 db, 12 db, and 15 db below the adc saturation (clip) level by writing values from 1 to 5 to the 3-bit agcr field. note that the adc clip level is defined to be 2 db below its full scale (i.e., ?8 dbm at the lna input for a matched input and maximum attenua- tion). if agcr is 0, automatic gain control is disabled. since clipping of the adc input will degrade the snr performance, the reference level should also take into consideration the peak- to-rms characteristics of the target (or interferer) signals. referring again to figure 18, the majority of the agc loop operates in the discrete time domain. the sample rate of the loop is f clk /60; therefore, registers associated with the agc algorithm are updated at this rate. the number of overload and adc reset occurrences within the final i/q update rate of the ad9874, as well as the agc value (8 msb), can be read from the ssi data upon proper configuration. the agc performs digital signal estimation at the output of the first decimation stage (dec1) as well as the dvga output that follows the last decimation stage (dec3). the rms power of the i and q signal is estimated by the equation xest n abs i n abs q n [] = [] () + [] () (7) signal estimation after the first decimation stage allows the agc to cope with out-of-band interferers and in-band signals that could otherwise overload the adc. signal estimation after the dvga allows the agc to minimize the effects of the 16-bit truncation noise. when the estimated signal level falls within the range of the agc, the agc loop adjusts the vga (or dvga) attenuation setting so that the estimated signal level is equal to the pro- grammed level specified in the agcr field. the absolute signal strength can be determined from the contents of the attn and rssi field that is available in the ssi data frame when properly configured. within this agc tracking range, the 6-bit value in the rssi field remains constant while the 8-bit attn field varies according to the vga/dvga setting. note that the attn value is based on the 8 msb contained in the agcg field of registers 0x03 and 0x04. a description of the agc control algorithm and the user adjust- able parameters follows. first, consider the case in which the in-band target signal is bigger than all out-of-band interferers and the dvga is disabled. with the dvga disabled, a control loop based only on the target signal power measured after dec1 is used to control the vga gain, and the target signal will be tracked to the programmed reference level. if the signal is too large, the attenuation is increased with a proportionality constant determined by the agca setting. large agca values result in large gain changes, thus rapid tracking of changes in signal strength. if the target signal is too small relative to the reference level, the attenuation is reduced; but now the propor- tionality constant is determined by both the agca and agcd settings. the agcd value is effectively subtracted from agca, so a large agcd results in smaller gain changes and thus slower tracking of fading signals. the 4-bit code in the agca field sets the raw bandwidth of the agc loop. with agca = 0, the agc loop bandwidth is at its minimum of 50 hz, assuming f clk = 18 mhz. each increment of agca increases the loop bandwidth by a factor of 2 1/2 , thus
rev. a ad9874 ?0 the maximum bandwidth is 9 khz. a general expression for the attack bandwidth is: bw f mhz hz a clk agca = () () 50 18 2 2 (8) and the corresponding attack time is: t attack bw agca a = ? ? ? ? = () 22 100 2 0 35 2 .. (9) assuming that the loop dynamics are essentially those of a single-pole system. the 4-bit code in the agcd field sets the ratio of the attack time to the decay time in the amplitude estimation circuitry. when agcd is zero, this ratio is one. incrementing agcd multiplies the decay time constant by 2 1/2 , allowing a 180:1 range in the decay time relative to the attack time. the decay time may be computed from: t decay t attack agcd = () 2 2 (10) figure 21a shows the agc response to a 30 hz pulse-modu- lated if burst for different agca and agcd settings. a gca = 0 80 64 0 48 32 16 96 time ?ms 10 20 0 50 40 30 80 64 0 48 32 16 96 vga attenuation setting a gca = 4 80 64 0 48 32 16 96 a gca = 8 a gcd = 8 a gcd = 0 a gcd = 8 a gcd = 0 a gcd = 8 a gcd = 0 figure 21a. agc response for different agca and agcd settings with f clk = 18 msps, f clkout = 20 ksps, decimate by 900, and agco = 0 the 3-bit value in the agco field determines the amount of attenuation added in response to a reset event in the adc. each increment in agco doubles the weighting factor. at the highest agco setting, the attenuation will change from 0 db to 12 db in approximately 10 s, while at the lowest setting the attenuation will change from 0 db to 12 db in approximately 1.2 ms. both times assume f clk = 18 mhz. figure 21b shows the agc attack time response for different agco settings. vga attenuation setting time ?ms 0.1 0.2 0 0.5 0.4 0.3 80 64 0 48 32 16 96 1.0 0.9 0.8 0.7 0.6 112 128 a gco = 7 a gco = 4 a gcd = 0 figure 21b. agc response for different agco settings with f clk = 18 msps, f clkout = 300 ksps, decimate by 60, and agca = agcd = 0 lastly, the agcf bit reduces the dac source resistance by at least a factor of 10. this facilitates fast acquisition by lowering the rc time constant that is formed with the external capacitors connected from the gcp pin-to-ground (gcn pin). for an overshoot-free step response in the agc loop, the capacitor connected from the gcp pin to the gcn ground pin should be chosen so that the rc time constant is less than one quarter of the raw loop. specifically: rc bw < 18 () (11) where r is the resistance between the gcp pin and ground (72.5 k 30% if agcf = 0, < 8 k if agcf = 1) and bw is the raw loop bandwidth. note that with c chosen at this upper limit, the loop bandwidth increases by approximately 30%. now consider the case described above but with the dvga enabled to minimize the effects of 16-bit truncation. with the dvga enabled, a control loop based on the larger of the two estimated signal levels (i.e., output of dec1 and dvga) is used to control the dvga gain. the dvga multiplies the output of the decimation filter by a factor of 1 to 4 (i.e., 0 db to 12 db). when signals are small, the dvga gain is 4 and the 16-bit output is extracted from the 24-bit data produced by the decimation filter by dropping 2 msb and taking the next 16 bits. as signals get larger, the dvga gain decreases to the point where the dvga gain is 1 and the 16-bit output data is simply the 16 msb of the internal 24-bit data. as signals get even larger, attenuation is accomplished by the normal method of increasing the adc? full scale. the extra 12 db of gain range provided by the dvga reduces the input-referred truncation noise by 12 db and makes the data more tolerant of lsb corruption within the dsp. the price paid for this extension to the gain range is that the start of agc action is 12 db lower and that the agc loop will be unstable if its bandwidth is set too wide. the latter difficulty results from the large delay of the decimation filters, dec2 and dec3, when one implements a large decimation factor. as a result, given an option, the use of 24-bit data is preferable to using the dvga.
rev. a ad9874 ?1 table xii indicates which agca values are reasonable for various decimation factors. the white cells indicate that the (decimation factor/agca) combination works well; the light gray cells indicate ringing and an increase in the agc settling time; and the dark gray cells indicate that the combination results in instability or near instability in the agc loop. setting agcf = 1 improves the time-domain behavior at the expense of increased spectral spreading. table xii. agca limits if the dvga is enabled agca m 0 1 4 8 e 60 120 300 540 900 decimation factor 45 6 78 9 10 11 12 13 14 15 lastly, consider the case of a strong out-of-band interferer (i.e., ?8 dbm to ?2 dbm for matched if input) that is larger than the target signal and large enough to be tracked by the control loop based on the output of the dec1. the ability of the con- trol loop to track this interferer and set the vga attenuation to prevent clipping of the adc is limited by the accuracy of the digital signal estimation occurring at the output of dec1. the accuracy of the digital signal estimation is a function of the frequency offset of the out-of-band interferer relative to the if frequency as shown in figure 20. interferers at increasingly higher frequency offsets incur larger measurement errors, poten- tially causing the control loop to inadvertently reduce the amount of vga attenuation that may result in clipping of the adc. figure 21c shows the maximum measured interferer signal level versus the normalized if offset frequency (relative to f clk ) tolerated by the ad9874 relative to its maximum target input signal level (0 dbfs = ?8 dbm). note that the increase in allowable interferer level occurring beyond 0.04 f clk results from the inherent signal attenuation provided by the adc? signal transfer function. normalized frequency offset = ( f in ? f if )/ f clk ? 0.02 ?2 0 0.04 0 ? ? 0.03 0.01 ?5 0.05 relative to clip point ?dbfs figure 21c. maximum interferer (or blocker) input level vs. normalized if frequency offset table xiii. spi registers associated with agc address bit default (hex) breakdown width value name 0x03 (7) 1 0 atten (6:0) 7 0x00 agcg(14:8) 0x04 (7:0) 8 0x00 agcg(7:0) 0x05 (7:4) 4 0 agca (3:0) 4 0x00 agcd 0x06 (7) 1 0 agcv (6:4) 3 0 agco (3) 1 0 agcf (2:0) 3 0 agcr system noise figure (nf) vs. vga (or agc) control the ad9874? system noise figure is a function of the acg attenuation and output signal bandwidth. figure 22a plots the nominal system nf as a function of the agc attenuation for both narrow-band (20 khz) and wideband (150 khz) modes with f clk = 18 mhz. also shown on the plot is the snr that would be observed at the output for a ? dbfs input. the high dynamic range of the adc within the ad9874 ensures that the system nf increases gradually as the agc attenuation is increased. in narrow-band (bw = 20 khz) mode, the system noise figure increases by less than 3 db over a 12 db agc range, while in wideband (bw = 150 khz) mode, the degra- dation is about 5 db. as a result, the highest instantaneous dynamic range for the ad9874 occurs with 12 db of agc attenuation, since the ad9874 can accommodate an addi- tional 12 db peak signal level with only a moderate increase in its noise floor. as figure 22a shows, the ad9874 can achieve an snr in excess of 100 db in narrow-band applications. to realize the full performance of the ad9874 in such applications, it is recom- mended that the i/q data be represented with 24 bits. if 16-bit data is used, the effective system nf will increase because of the quantization noise present in the 16-bit data after truncation. 36 0 15 14 12 13 11 10 9 8 noise figure ?db 912 vg a attenuation ?db snr = 90.1dbfs bw = 50khz bw = 150khz snr = 82.9dbfs bw = 10khz snr = 95.1dbfs snr = 103.2db figure 22a. nominal system noise figure and peak snr vs. agcg setting (f if = 73.35 mhz, f clk = 18 msps, and 24-bit i/q data)
rev. a ad9874 ?2 figure 22b plots the nominal system nf with 16-bit output data as a function of agc in both narrow-band and wideband mode. in wideband mode, the nf curve is virtually unchanged relative to the 24-bit output data because the output snr before truncation is always less than the 96 db snr that 16-bit data can support. however, in narrow-band mode, where the output snr approaches or exceeds the snr that can be supported with 16-bit data, the degradation in system nf is more severe. further- more, if the signal processing within the dsp adds noise at the level of an lsb, the system noise figure can be degraded even more than figure 22b shows. for example, this could occur in a fixed 16-bit dsp whose code is not optimized to process the ad9874? 16-bit data with minimal quantization effects. to limit the quantization effects within the ad9874, the 24-bit data undergoes noise shaping just prior to 16-bit truncation, thus reducing the in-band quantization noise by 5 db (with 23 oversampling). this explains why 98.8 dbfs snr performance is still achievable with 16-bit data in a 10 khz bw. noise figure ?db 15 8 14 13 12 11 10 9 snr = 98.8dbfs bw = 50khz bw = 150khz snr = 83dbfs snr = 94.1dbfs bw = 10khz snr = 89.9dbfs 16 17 3 6 0 9 12 vg a attenuation ?db figure 22b. nominal system noise figure and peak snr vs. agcg setting (f if = 73.35 mhz, f clk = 18 msps, and 16-bit i/q data) application considerations frequency planning the lo frequency (and/or adc clock frequency) must be chosen carefully to prevent known internally generated spurs from mixing down along with the desired signal, thus degrad- ing the snr performance. the major sources of spurs in the ad9874 are the adc clock and digital circuitry operating at 1/3 of f clk . thus, the clock frequency (f clk ) is the most important variable in determining which lo (and therefore if) frequencies are viable. many applications have frequency plans that take advantage of industry-standard if frequencies due to the large selection of low cost crystal or saw filters. if the selected if frequency and adc clock rate result in a problematic spurious component, an alternative adc clock rate should be selected by slightly modi- fying the decimation factor and clk synthesizer settings (if used) such that the output sample rate remains the same. also, applications requiring a certain degree of tuning range should take into consideration the location and magnitude of these spurs when determining the tuning range as well as optimum if and adc clock frequency. figure 23a plots the measured in-band noise power as a func- tion of the lo frequency for f clk = 18 mhz and an output signal bandwidth of 150 khz when no signal is present. any lo frequency resulting in large spurs should be avoided. as this figure shows, large spurs result when the lo is f clk /8 = 2.25 mhz away from a harmonic of 18 mhz (i.e., n f clk f clk /8). also problematic are lo frequencies whose odd order harmonics (i.e., m f lo ) mix with harmonics of f clk to f clk /8. this spur mechanism is a result of the mixer being internally driven by a squared-up version of the lo input consisting of the lo fre- quency and its odd order harmonics. these spur frequencies can be calculated from the relation mf n f lo clk = () 18 (12) where m = 1, 3, 5... and n = 1, 2, 3... a second source of spurs is a large block of digital circuitry that is clocked at f clk /3. problematic lo frequencies associated with this spur source are given by: ff nf f lo clk clk clk =+ /3 8 (13) where n = 1, 2, 3 ... in-band power ?dbfs ?0 ?0 ?0 ?0 ?0 0 250 300 200 150 100 50 lo frequency ?mhz figure 23a. total in-band noise + spur power with no signal applied as a function of the lo frequency (f clk = 18 mhz and output signal bandwidth of 150 khz)
rev. a ad9874 ?3 figure 23b shows that omitting the lo frequencies given by equation 12 for m = 1, 3, and 5 and by equation 13 accounts for most of the spurs. some of the remaining low level spurs can be attributed to coupling from the ssi digital output. as a result, users are also advised to optimize the output bit rate ( f clkout via the ssiord register) and the digital output driver strength to achieve the lowest spurious and noise figure perfor- mance for a particular lo frequency and f clk setting. this is especially the case for particularly narrow-band channels in which low level spurs can degrade the ad9874? sensitivity performance. despite the many spurs, sweet spots in the lo frequency are generally wide enough to accommodate the maximum signal bandwidth of the ad9874. as evidence of this property, fig- ure 24 shows that the in-band noise is quite constant for lo frequencies ranging from 70 mhz to 71 mhz. 70.5 70.0 ?0 ?0 ?0 ?0 ?0 71.0 lo frequency ?mhz in-band power ?dbfs figure 24. expanded view from 70 mhz to 71 mhz spurious responses the spectral purity of the lo (including its phase noise) is an important consideration since lo spurs can mix with undesired signals present at the ad9874? ifin input to produce an in-band response. to demonstrate the low lo spur level introduced within the ad9874, figure 25 plots the demodulated output power as a function of the input if frequency for an lo frequency of 71.1 mhz and a clock frequency of 18 mhz. 90 50 0 ?0 ?0 ?0 ?0 100 if frequency ?mhz dbfs ?20 ?00 60 70 80 d = f clk /4 = 4.5mhz desired responses figure 25. response of ad9874 to a ?0 dbm if input when f lo = 71.1 mhz the two large ?0 dbfs spikes near the center of the plot are the desired responses at f lo , f if2_adc , where f if2_adc = f clk /8, i.e., at 68.85 mhz and 73.35 mhz. lo spurs at f lo f spur would result in spurious responses at offsets of f spur around the desired responses. close-in spurs of this kind are not visible on t he plot, but small spurious responses at f lo f if2_adc f clk , i.e., at 50.85 mhz, 55.35 mhz, 86.85 mhz, and 91.35 mhz, are visible at the ?0 dbfs level. this data indicates that the ad 9874 does an excellent job of preserving the purity of the lo signal. figure 25 can also be used to gauge how well the ad9874 rejects undesired signals. for example, the half-if response (at 69.975 mhz and 72.225 mhz) is approximately ?00 dbfs, giving a selectivity of 90 db for this spurious response. the largest spurious response at approximately ?0 dbfs occurs with input frequencies of 70.35 mhz and 71.85 mhz. these spurs result from third order nonlinearity in the signal path (i.e., abs [3 f lo ?3 f if_input ] = f clk /8). in-band power ?dbfs ?0 ?0 ?0 ?0 ?0 0 250 300 lo frequency ?mhz 200 150 100 50 figure 23b. same as figure 23a excluding lo frequencies known to produce large in-band spurs
rev. a ad9874 ?4 external passive component requirements figure 26 shows an example circuit using the ad9874 and table xiv shows the nominal dc bias voltages seen at the differ- ent pins. the purpose is to show the various external passive components required by the ad9874, along with nominal dc voltages for troubleshooting purposes. mxop mxon gndf if2n if2p vddf gcp gcn vdda gnda vrefp vrefn gndl fref gnds syncb gndh fs doutb douta clkout vddh vddd pe vddi ifin cxif gndi cxvl lop lon cxvm vddl vddp ioutl gndp rref vddq ioutc gndq vddc gndc clkp clkn gnds gndd pc pd 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 25 26 27 28 29 30 31 32 33 34 35 36 ad9874 50 180pf 10 h 10 h lc tank 100pf 100 pf 2.2nf 100pf 10nf 100pf 100k 10nf 10nf 1nf 10nf 10nf 100nf 100nf 10nf figure 26. example circuit showing recommended component values table xiv. nominal dc bias voltages pin number mnemonic nominal dc bias (v) 1 mxop vddi ?0.2 2m xon vddi ?0.2 4i f2n 1.3 ?1.7 5 if2p 1.3 ?1.7 11 vrefp vdda/2 + 0.250 12 vrefn vdda/2 ?0.250 13 rref 1.2 19 clkp vddc ?1.3 20 clkn vddc ?1.3 35 fref vddc/2 41 cxvm 1.6 ?2.0 42 lon 1.65 ?1.9 43 lop 1.65 ?1.9 44 cxvl vddi ?0.05 46 cxif 1.6 ?2.0 47 ifin 0.9 ?1.1 the lo, clk, and ifin signals are coupled to their respective inputs using 10 nf capacitors. the output of the mixer is coupled to the input of the adc using 100 pf. an external 100 k ? resistor from the rref pin to gnd sets up the ad9874? internal bias currents. vrefp and vrefn provide a differential reference voltage to the ad9874? - adc and must be decoupled by a 0.01 f differential capacitor along with two 100 pf capacitors to gnd. the remaining capacitors are used to decouple other sensi- tive internal nodes to gnd. although power supply decoupling capacitors are not shown, it is recommended that a 0.1 f surface-mount capacitor be placed as close as possible to each power supply pin for maxi- mum effectiveness. also not shown is the input impedance matching network used to match the ad9874? if input to the external if filter. lastly, the loop filter components associated with the lo and clk synthesizers are not shown. lc component values for f clk = 18 mhz are given on the dia- gram. for other clock frequencies, the two inductors and the capacitor of the lc tank should be scaled in inverse proportion to the clock. for example, if f clk = 26 mhz, then the two inductors should be = 6.9 h and the capacitor should be about 120 pf. a tolerance of 10% is sufficient for these components since tuning of the lc tank is performed upon system startup. applications superheterodyne receiver example the ad9874 is well suited for analog and/or digital narrow- band radio systems based on a superheterodyne receiver architecture. the superheterodyne architecture is noted for achieving exceptional dynamic range and selectivity by using two or more downconversion stages to provide amplification of the target signal while filtering the undesired signals. the ad9874 greatly simplifies the design of these radio systems by integrating the complete if strip (excluding the lo vco) while providing an i/q digital output (along with other system parameters) for the demodulation of both analog and digital modulated signals. the ad9874? exceptional dynamic range often simplifies the if filtering requirements and eliminates the need for an external agc. figure 27 shows a typical dual conversion superheterodyne receiver using the ad9874. an rf tuner is used to select and downconvert the target signal to a suitable first if for the ad9874. a preselect filter may precede the tuner to limit the rf input to the band of interest. the output of the tuner drives an if filter that provides partial suppression of adja- cent channels and interferers that could otherwise limit the receiver? dynamic range. the conversion gain of the tuner should be set such that the peak if input signal level into the ad9874 is no greater than ?8 dbm to prevent clipping. the ad9874 downconverts the first if signal to a second if that is exactly 1/8 of the - adc? clock rate (i.e., f clk /8) to sim- plify the digital quadrature demodulation process.
rev. a ad9874 ?5 this second if signal is then digitized by the - adc, demodu- lated into its quadrature i and q components, filtered via matching decimation filters, and reformatted to enable a synchronous serial interface to a dsp. in this example, the ad9874? lo and clk synthesizers are both enabled, requiring some additional passive components (for the synthesizer? loop filters and clk oscillator) and a vco for the lo synthesizer. note that not all of the re quired decoupling capacitors are shown. refer to the previous section and figure 26 for more information on required external passive components. the selection of the first if frequency is often based on the availability of low cost standard crystal or saw filters as well as system frequency planning considerations. in general, crystal filters are often used for narrow-band radios having channel bandwidths below 50 khz with ifs below 120 mhz, while saw filters are more suited for channel bandwidths greater than 50 khz with ifs greater than 70 mhz. the ultimate stop-band rejection required by the if filter will depend on how much suppression is required at the ad9874? image band resulting from downconversion to the second if. this image band is offset from the first if by twice the second if frequency (i.e., f clk /4, depending on high or low side injection). the selectivity and bandwidth of the if filter will depend on both the magnitude and frequency offset(s) of the adjacent channel blocker(s) that could overdrive the ad9874? input or generate in-band intermodulation components. further suppression is performed within the ad9874 by its inherent band-pass response and digital decimation filters. note that some applications will require additional application-specific filtering performed in the dsp that follows the ad9874 to remove the adjacent channel and/or implement a matched filter for optimum signal detection. the output data rate of the ad 9874, f out , should be chosen to be at least twice the bandwidth or symbol rate of the desired signal to ensure that the decimation filters provide a flat pass- band response as well as to allow for postprocessing by a dsp. once f out is determined, the decimation factor of the digital filters should be set such that the input clock rate, f clk , falls between the ad9874? rated operating range of 13 mhz to 26 mhz and no significant spurious products related to f clk fall within the desired pass band, resulting in a reduction in sensitiv- ity performance. if a spurious component is found to limit the sensitivity performance, the decimation factor can often be modified slightly to find a spurious free pass band. selecting a higher f clk is typically more desirable given a choice, since the first if? filtering requirements often depend on the tran- sition region between the if frequency and the image band (i.e., f clk /4 ). lastly, the output ssi clock rate, f clkout , rf input preselect filter tuner if crystal or saw filter vdda - adc lna vco adf42xx pll syn refin to dsp ad9874 decimation filter sample clock synthesizer ioutc loop filter lop lon vco loop filter vddc ioutc clkp clkn from dsp lo synth. vo ltag e reference spi rref vrefp vrefn syncb pc pd pe crystal oscillator ifin ?6db lna vxop vxon ii-2p ii-2n dac agc formatting/ssi douta doutb fs clkout control logic gcp gcn if2 = f clk /8 figure 27. typical dual conversion superheterodyne application using the ad9874
rev. a ad9874 ?6 and digital driver strength should be set to their lowest pos- sible settings to minimize the potential harmful effects of digital induced noise while preserving a reliable data link to the dsp. note that the ssicra, ssicrb, and ssiord registers (i.e., 0x18, 0x19, and 0x1a) provide a large degree of flexibility for optimization of the ssi interface. synchronization of multiple ad9874s some applications such as receiver diversity and beam steering may require two or more ad9874s operating in parallel while maintaining synchronization. figure 28 shows an example of how multiple ad9874s can be cascaded, with one device serv- ing as the master and the other devices serving as the slaves. in this example, all of the devices have the same spi register con- figuration since they share the same spi interface to the dsp. since the state of each of the ad9874? internal counters is unknown upon initialization, synchronization of the devices is required via a syncb pulse (see figure 4) to synchronize their digital filters and ensure precise time alignment of the data streams. although all of the devices?synthesizers are enabled, the lo and clk signals for the slaves(s) are derived from the masters synthesizers and are referenced to an external crystal oscillator. all of the necessary external components (i.e., loop filters, varactor, lc, and vco) required to ensure proper closed-loop operation of these synthesizers are included. note that although the vco output of the lo synthesizer is ac- coupled to the slave? lo input(s), all of the clk inputs of the devices must be dc-coupled if the ad9874? clk oscilla tors are enabled. this is due to the dc current required by the clk oscillators in each device. in essence, these negative impedance cores are operating in parallel, increasing the effective q of the lc resonator circuit. note that rbias should be sized such that the sum of the oscillators?dc bias currents maintains a common-mode voltage of around 1.6 v. vco 25 23 24 pe pc pd 33 syncb 31 fs 29 28 douta clkout 35 f ref 19 20 clkp clkn lop lon 43 42 ifin 47 15 ad9874 master ioutc loop filter 38 15 ioutc 25 23 24 pe pc pd 35 lop lon 43 42 ifin 47 31 fs 29 28 douta clkout 33 syncb to dsp clkp clkn ioutl to dsp from dsp loop filter c va r r d r f c p c z 0.1 f l osc r bias c osc to ot her ad9874s from crystal oscillation vddc to ot her ad9874s ad9874 slave 19 20 f ref figure 28. example of synchronizing multiple ad9874s
rev. a ad9874 ?7 split path rx architecture a split path rx architecture may be attractive for those applica- tions whose instantaneous dynamic range requirements exceed the capability of a single ad9874 device. to cope with these higher dynamic range requirements, two ad9874s can be oper- ated in parallel with their respective clip points offset by a fixed amount. adding a fixed amount of attenuation in front of the ad9874 and/or programming the attenuation setting of its internal vga can adjust the input-referred clip point. to save power and simplify hardware, the lo and clk circuits of the device can also be shared. connecting the syncb pins of the two devices and pulsing this line low synchronizes the two devices. an example of this concept for possible use in a gsm base station is shown in figure 29. the signal chain consists of a high linearity rf front end and if stage followed by two ad9874s operating in parallel. the rf front end consists of a duplexer and preselect filter to pass the gsm rf band of interest. a high performance lna isolates the duplexer from the preselect filter while providing sufficient gain to minimize system nf. an rf mixer is used to downconvert the entire gsm band to a suitable if, where much of the channel selectivity is accomplished. the 170.6 mhz if is chosen to avoid any self-induced spurs from the ad9874. the if stage consists of two saw filters isolated by a 15 db gain stage. the cascaded saw filter response must provide sufficient blocker rejection in order for the receiver to meet its sensitivity requirements under worst-case blocker conditions. a composite response having 27 db, 60 db, and 100 db rejection at frequ ency offsets of 0.8 mhz, 1.6 mhz, and 6.5 mhz, respectively, provides enough blocker suppression to ensure that the ad9874 with the lower clip point will not be overdriven by any blocker. this configuration results in the best possible receiver sensitivity under all blocking conditions. the output of the last saw filters drives the two ad9874s via a direct signal path and an attenuated signal path. the direct path corresponds to the ad9874 having the lowest clip point and provides the highest receiver sensitivity with a system noise figure of 4.7 db. the vga of this device is set for maximum attenuation, so its clip point is approximately ?7 dbm. since conversion gain from the antenna to the ad9874 is 19 db, the digital output of this path will nominally be selected unless the target signal? power exceeds ?6 dbm at the antenna. the attenuated path corresponds to the ad9874 having the highest input-referred clip point, and its digital output point of this path is set to 7 dbm by inserting a 30 db attenuator and setting the ad9874? vga to the middle of its 12 db range. this setting vco lna x mixer if saw 1 if saw 2 duplexer preselect gain = ?db nf = 2db gain = 22db nf = 1db gain = ?db nf = 3db gain = 5db nf = 12db if amp gain = ?db nf = ?db gain = 15db nf = 2db 13mhz dsp or asic 36db pad 25 23 24 pe pc pd 33 syncb 31 fs 29 28 douta clkout 35 19 20 clkp clkn lop lon 43 42 47 15 ad9874 master loop filter 15 ioutc 25 23 24 pe pc pd 35 lop lon 43 42 ifin 47 ad9874 slave 31 fs 29 28 douta clkout 33 syncb 19 20 clkp clkn ioutl loop filter c var r d r f c p c z 0.1 f l osc r bias c osc vddc ifin 38 ioutc attenuated path with clip point = 7.0dbm direct path with clip point = ?7dbm f ref f ref figure 29. example of split path rx architecture to increase receiver dynamic range capabilities
rev. a ad9874 ?8 results in a 6d b adjustment of the clip point, allowing the clip point difference to be calibrated to exactly 24 db, so that a simple 5-bit shift would make up the gain difference. the attenuated path can handle signal levels up to ?2 db at the antenna before being overdriven. since the saw filters provide sufficient blocker suppression, the digital data from this path need only be selected when the target signal exceeds ?6 dbm. although the sensitivity of the receiver with the attenuated path is 20 db lower than the direct path, the strong target signal ensures a sufficiently high carrier-to-noise ratio. since gsm is based on a tdma scheme, digital data (or path) selection can occur on a slot-by-slot basis. the ad9874 would be configured to provide serial i and q data at a frame rate of 541.67 ksps, as well as additional information including a 2-bit reset field and a 6-bit rssi field. these two fields contain the information needed to decide whether the direct or attenuated path should be used for the current time slot. hung mixer mode the ad9874 can be operated in the hung mixer mode by tying one of the lo? self-biasing inputs to ground (i.e., gndi) or the positive supply (vddi). in this mode, the ad9874 acts as a narrow-band, band-pass - adc, since its mixer passes the ifin signal without any frequency translation. the ifin signal must be centered about the resonant frequency of the - adc (i.e., f clk /8) and the clock rate, f clk , and decimation factors must be selected to accommodate the bandwidth of the desired input signal. note that the lo synthesizer can be disabled because it is no longer required. since the mixer does not have any losses associated with the mixing operation, the conversion gain through the lna and mixer is higher resulting in a nominal input clip point of ?4 dbm. the linearity or iip3 performance of the lna and mixer remains roughly unchanged and similar to that shown in figure 11b. the snr performance is dependent of the vga attenuation setting, i/q data resolution, and output bandwidth as shown in figure 30. applications requiring the highest instantaneous dynamic range should set the vga for maximum attenuation. also, several extra decibels in snr performance can be gained at lower signal bandwidths by using 24-bit i/q data. 0 105 snr ?db 95 bw ?khz 85 80 80 120 140 160 40 20 60 100 100 90 min atten w/ 24-bit i/q data max atten w/ 16-bit i/q data min atten w/ 16-bit i/q data max atten w/ 24-bit i/q data f clk = 18msps figure 30. hung mixer snr vs. bw and vga layout example, evaluation board, and software the evaluation board and its accompanying software provide a simple way to evaluate the ad9874. the block diagram in figure 31 shows the major blocks of the evaluation board, which is designed to be flexible, allowing configuration for different applications. the power supply distribution block provides filtered, adjustable voltages to the various supply pins of the ad9874. in the if input signal path, component pads are available to implement different if impedance matching networks. the lo and clk signals can be externally applied or internally derived from a user-supplied vco module interface daughter board. the refer- ence for the on-chip lo and clk synthesizers can be applied via the external f ref input or an on-board crystal oscillator. the evaluation board is designed to interface to a pc via a national instruments ni 6533 digital io card. an xilinx fpga formats the data between the ad9874 and digital i/o card. mixer output dut if input lo input vco module interface crystal oscillator (optional) idt fifo (optional) power supply distribution eprom clk input fref input nidaq 68-pin connector xilinx sparton fpga ad9874 figure 31. evaluation board platform software developed using national instruments?labview (and provided as microsoft w indows executable programs) is supplied for the configuration of the spi port registers and evaluation of the ad9874 output data. these programs have a convenient graphical user interface that allows for easy access to the various spi port configuration registers and real-time frequency analysis of the output data. for more information on the ad9874 evaluation board, includ- ing an example layout, please refer to the eval-ad9874eb data sheet.
rev. a ad9874 ?9 outline dimensions 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc seating plane 1.60 max 0.75 0.60 0.45 view a 7 3.5 0 0.20 0.09 1.45 1.40 1.35 0.15 0.05 0.08 max coplanarity view a rotated 90 ccw pin 1 indicator 9.00 bsc compliant to jedec standards ms-026bbc seating plane
rev. a c02639??/03(a) ad9874 rev. a ?0 revision history location page 3/03?ata sheet changed from rev. 0 to rev. a change to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 replaced figure 1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 deleted synchronization section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 added synchronization using syncb section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 changes to lo synthesizer section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 changes to figure 7b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 changes to figure 7c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 changes to table x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 changes to automatic gain control section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 changes to figure 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 changes to layout example, evaluation board, and software section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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