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publication number s72ns-r_00 revision 07 issue date may 10, 2010 s72ns-r based mcps s72ns-r based mcps cover sheet mirrorbit ? flash memory and dram 128/256/512 mb (8/16/32 m x 16 bit) , 1.8 volt-only, multiplexed simultaneous read/write, burst mode flash memory 128/256 mb (8/16 m x 16 bit) ddr dram on split bus data sheet (advance information) notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 s72ns-r based mcps s72ns-r_00_07 may 10, 2010 data sheet (advance information) notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
this document contains information on one or more products under development at spansion inc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed pr oduct without notice. publication number s72ns-r_00 revision 07 issue date may 10, 2010 features ? power supply voltage of 1.7 v to 1.95 v ? burst speeds ? flash = 83mhz, 104 mhz ? ddr dram = 133 mhz, 166 mhz ? packages ? 8.0 x 8.0 mm, 133-ball mcp ? 11.0 x 10.0 mm, 133-ball mcp ? operating temperature of ?25c to +85c general description this document contains information on the s72ns-r mcp stacked products. refer to the s29ns-r data sheet (s29ns-r_00) for full electrical specific ations of the flash memory component. the s72ns series is a product line of st acked products (mcps), and consists of: ? s29ns family multiplexed flash memory die ? ddr dram the products covered by this document are listed in the tables below. ddr specification reference s72ns-r based mcps mirrorbit ? flash memory and dram 128/256/512 mb (8/16/32 m x 16 bit) , 1.8 volt-only, multiplexed simultaneous read/write, burst mode flash memory 128/256 mb (8/16 m x 16 bit) ddr dram on split bus data sheet (advance information) flash density dram density 128 mb 256 mb 128 mb s72ns128rd0 256 mb s72ns256rd0 512 mb s72ns512rd0 s72ns512re0 density manufacturer spansion documentation publication number 128 mb dram type 5 dram_15 dram type 1 dram_07 dram type 6 custcomspec_02 256 mb dram type 5 dram_14 dram type 1 dram_08
4 s72ns-r based mcps s72ns-r_00_07 may 10, 2010 data sheet (advance information) 1. product selector guide notes 1. for s72ns128rd0ahbl0 only: the factory secured silicon area cont ains a random, 128-bit electronic serial number (esn), stored in the address range 000000h-000007h. device opn flash density ddr dram density flash speed (mhz) ddr dram speed (mhz) dram supplier package s72ns128rd0ahbl0 (1) 128 mb 128 mb 83 166 ty p e 5 8.0 x 8.0 mm 133-ball mcp (rlb133) s72ns128rd0ahbg0 type 1 s72ns128rd0ahbm0 type 6 s72ns256rd0ahbl0 256 mb 128 mb 83 166 ty p e 5 8.0 x 8.0 mm 133-ball mcp (rlb133) s72ns256rd0ahbg0 type 1 s72ns256rd0ahbm0 type 6 s72ns512rd0ahgl0 512 mb 128 mb 83 166 ty p e 5 11.0 x 10.0mm 133-ball mcp (rld133) s72ns512rd0ahgg0 type 1 s72ns512rd0ahgm0 type 6 s72ns512rd0khfl0 ty p e 5 12.0 x 12.0 mm 128-ball pop (alf128) s72ns512rd0khfm0 type 6 s72ns512re0ahgg4 512 mb 256 mb 104 166 ty p e 1 11.0 x 10.0 mm 133-ball mcp (rld133) s72ns512re0ahgl0 83 ty p e 5 s72ns512re0ahgg0 type 1 s72ns512re0khfl0 ty p e 5 12.0 x 12.0 mm 128-ball pop (alf128) s72ns512re0khfg0 ty p e 1
may 10, 2010 s72ns-r_00_07 s72ns-r based mcps 5 data sheet (advance information) 2. product block diagram notes: 1. amax indicates highest address bit for memory component: a. amax = a25 for ns01gr, a24 for ns512r, a23 for ns256r, a22 for ns128r b. amax = a11 for 128 mb ddr dram c. amax = a12 for 256 mb ddr dram 2. for flash, a15 - a0 is tied to dq15 - dq0. mux flash memory s29ns-r ddr dram memory f-rst# f-acc f-ce# f-oe# f-we# avd# f-v ss rst# acc ce# oe# we# avd# v ss adq15-adq0 f-clk f-rdy amax - a16 f-v cc f-v ccq a15-a0 dq15-dq0 clk rdy v cc v ccq d-ras# d-cas# d-ba0 d-ba1 d-cke d-we# d-amax - d-a0 d-v cc ras# cas# ba0 ba1 cke we# v cc d-v ccq v ccq clk clk# dqs0 dqs1 ldqm udqm test dq15-dq0 v ss v ssq d-clk d-clk# d-ldqs d-udqs d-ldqm d-udqm d-test d-dq15 - d-dq0 d-v ss d-v ssq amax - a16 d-ce# ce#
6 s72ns-r based mcps s72ns-r_00_07 may 10, 2010 data sheet (advance information) 3. connection diagrams figure 3.1 133-ball fine-pitch ball grid array mcp note: additional nc locations are in reference to the superset connection diagram shown here device opn flash address amax ddr dram address amax additional nc locations s72ns128rd0 a22 a11 ball f1, ball e1, ball n11 s72ns256rd0 a23 a11 ball e1, ball n11 s72ns512rd0 a24 a11 ball n11 s72ns512re0 a24 a12 n/a 3 2910 5 47 68 1 13 12 14 11 d-vssq d-test d-vcc d-dq5 d-dq9 d-vccq d-vss d-dq8 d-vcc dnu dnu d-vssq dnu d-dq3 b d e f g h j k l m n p a c d-dq13 d-vss d-ldqm d-dq6 d-dq10 d-udqs d-vccq d-vssq d-vccq dnu d-vccq d-dq1 dnu d-dq4 d-dq14 d-dq15 d-vssq d-dq7 d-dq11 d-dq12 d-vss d-udqm d-vcc d-vcc d-dq0 d-dq2 d-vss d-ldqs nc nc index rfu adq8 f-oe# d-vcc a17 a22 a24 adq1 adq9 adq0 a18 a19 a23 adq3 f-vss adq2 f-we# nc f-ce# adq11 f-vccq adq10 f-clk f-vcc f-acc adq12 adq13 adq4 nc f-vss a16 f-vss f-vss adq5 nc f-avd# a21 adq7 nc adq6 d-ce# f-rst# a20 adq15 f-vccq adq14 d-a3 nc d-a10 d-a1 d-a9 d-a6 d-vss d-cke d-we# nc f-rdy nc f-vss nc d-vcc d-vss d-a11 d-a2 d-a8 d-a5 d-clk# d-cas# d-ba1 dnu f-vcc nc dnu d-a12 nc dnu d-ba0 d-a0 d-a7 d-a4 d-clk d-ras# d-vcc dnu dnu d-vss dnu d-vcc legend index location do not use no connect dram only code flash only reserved for future use
may 10, 2010 s72ns-r_00_07 s72ns-r based mcps 7 data sheet (advance information) 4. input/output descriptions amax ? a16 = flash address inputs adq15 ? adq0 = flash multiplexed address and data f-ce# = flash chip-enable input. f-oe# = flash output enable input. asynchronous relative to clk for burst mode. f-we# = flash write enable input f-vcc = flash device power supply (1.7 v to 1.95 v) f-vccq = flash input/output buffer power supply f-vss = flash ground f-rdy = flash ready output. indicates the status of the burst read. v ol = data invalid. v oh = data valid. f-clk = flash clock. the first rising edge of clk in conjunction with avd# low latches the address input and activates burst mode operation. after the initial word is output, subsequent rising edges of clk increment the internal address counter. clk should remain low during asynchronous access. f-avd# = flash address valid input. indicates to device that the valid address is present on the address inputs. v il = for asynchronous mode, indicates valid address; for burst mode, causes starting addr ess to be latched on rising edge of clk. v ih = device ignores address inputs f-rst# = flash hardware reset input. v il = device resets and returns to reading array data f-acc = flash accelerated input. at v hh , accelerates programming; automatically places device in unlock bypass mode. at v il , disables all program and erase functions. should be at v ih for all other conditions. d-a12 ? d-a0 = dram address inputs. d-dq15 ? d-dq0 = dram data input/output d-clk = dram system clock d-ce# = dram chip select d-cke = dram clock enable d-ba1 ? ba0 = dram bank select d-ras# = dram row address strobe d-cas# = dram column address strobe d-udqm ? d-ldqm = dram data input mask d-we# = dram write enable input d-vss = dram ground d-vssq = dram input/output buffer ground d-vccq = dram input/output buffer power supply d-vcc = dram device power supply d-udqs = dram upper data strobe, output with read data and input with write data d-ldqs = dram lower data strobe, output with read data and input with write data d-clk# = ddr clock for negative edge of clk rfu = reserved for future use nc = no connect. can be connected to ground or left floating. d-test = internal test mode pin for ddr dram only. do not apply any signal on this pin. can be connected to ground or left floating. dnu = do not use
8 s72ns-r based mcps s72ns-r_00_07 may 10, 2010 data sheet (advance information) 5. ordering information the order number (valid combination) is formed by the following: notes 1. packing type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. 3. valid combinations list configurations plann ed to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. s72ns 256 r d0 ah b l c 3 packing type 0 = tray 3 = 13-inch tape and reel flash and ddr speed 0 = 83 mhz flash, 166 mhz ddr dram 4 = 104 mhz flash, 166 mhz ddr dram ddr supplier g = dram type 1 x16 ddr dram l = dram type 5 x16 ddr dram m = dram type 6 x16 ddr dram package modifier b = 133-ball, 8x8mm, fbga mcp g = 133-ball, 11x10mm, fbga mcp package and material type ah = thin profile fine-pitch bga pb-free low-halogen mcp (0.5 mm pitch) ddr dram and data flash density d0 = 128 mb ddr, no data flash e0 = 256 mb ddr, no data flash process technology r = 65 nm, mirrorbit ? technology code flash density 512 = 512 mb 256 = 256 mb 128 = 128 mb product family s72ns multi-chip product (mcp) 1.8 v multiplexed, srw, burst mode flash and ddr dram on split bus valid combinations product family code flash density (mb) process technology ddr density (mb) package type/ material ddr vendor flash & ddr speed packing type s72ns 128 r d0 ahb, khf g, l, m 0, 4 0, 3 (note 1) 256 512 e0 ahg, khf g, l
may 10, 2010 s72ns-r_00_07 s72ns-r based mcps 9 data sheet (advance information) 6. physical dimensions 6.1 rlb133?133-ball fine-pitch ba ll grid array (fbga) 8.0 x 8.0 mm 3627 \ 16-039.63 \ 8.21.7 package rlb 133 jedec n/a d x e 8.0 mm x 8.00 mm package symbol min nom max note a 0.80 0.90 1.00 overall thickness a1 0.18 0.23 0.28 ball height a2 0.62 0.68 0.74 body thickness d 7.90 8.00 8.10 body size e 7.90 8.00 8.10 body size d1 6.50 bsc. ball footprint e1 6.50 bsc. ball footprint md 14 row matrix size d direction me 14 row matrix size e direction n 133 total ball count ?b 0.25 0.30 0.35 ball diameter e 0.50 bsc. ball pitch sd / se 0.25 bsc. solder ball placement d5-d11, e4-e11, f4-f11 depopulated solder balls g4-g11, h4-h11, j4-j11 k4-k11, l4-l11 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means.
10 s72ns-r based mcps s72ns-r_00_07 may 10, 2010 data sheet (advance information) 6.2 rld133?133-ball fine-pitch ball grid array (fbga) 11.0 x 10.0 mm 3674 \ 16-039.63 \ 2.11.8 package rld 133 jedec n/a d x e 11.0 mm x 10.00 mm package symbol min nom max note a 0.80 --- 1.00 overall thickness a1 0.18 --- --- ball height a2 0.62 --- 0.74 body thickness d 11.00 bsc. body size e 10.00 bsc. body size d1 6.50 bsc. ball footprint e1 6.50 bsc. ball footprint md 14 row matrix size d direction me 14 row matrix size e direction n 133 total ball count ?b 0.25 0.30 0.35 ball diameter e 0.50 bsc. ball pitch sd / se 0.25 bsc. solder ball placement d5-d11, e4-e11, f4-f11 depopulated solder balls g4-g11, h4-h11, j4-j11 k4-k11, l4-l11 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means.
may 10, 2010 s72ns-r_00_07 s72ns-r based mcps 11 data sheet (advance information) 6.3 alf128?128-ball fine-pitch ball grid array (fbga) 12.0 x 12.0 mm package alf 128 jedec n/a d x e 12.00 mm x 12.00 mm package symbol min nom max note a 0.85 0.95 1.05 profile a1 0.38 0.43 0.48 ball height a2 0.49 0.54 0.59 body thickness d 12.00 bsc. body size e 12.00 bsc. body size d1 11.05 bsc. matrix footprint e1 11.05 bsc. matrix footprint md 18 matrix size d direction me 18 matrix size e direction n 128 ball count n 128 maximum number of balls r 2 number of land perimeters ? b 0.43 0.48 0.53 ball diameter ee 0.65 bsc. ball pitch ed 0.65 bsc. ball pitch se / sd 0.325 bsc. solder ball placement c3-c16,d3-d16,e3-e16, depopulated solder balls f3-f16,g3-g16,h3-h16, j3-j16,k3-k16,l3-l16, m3-m16,n3-n16,p3-p16, r3-r16,t3-t16 3658 \ 16-038.24 \ 10.12.7 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 3.0, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. n is the maximum number of balls on the fbga package. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means.
12 s72ns-r based mcps s72ns-r_00_07 may 10, 2010 data sheet (advance information) 7. revision history section description revision 01 (august 7, 2007) initial release revision 02 (august 24, 2007) global updated package names and drawings for s72ns-r mcps revision 03 (january 15, 2008) global updated speed grades for all s72ns-r product offerings revision 04 (february 13, 2008) global changed rsa133 package to rld133 and updated outline drawing ordering information corrected typographica l character errors in example opn revision 05 (may 9, 2008) global added alf128 package and updated dram publication numbers ordering information updated opns revision 06 (december 4, 2008) general description removed 1gb flash density ddr specification reference changed publication number fo r 128 mb dram type 6 from dram_09 to custcomspec_02 product selector guide added esn note for s72ns128rd0ahbl0 revision 07 (may 10, 2010) product selector guide added opn s72ns512re0ahgg4
may 10, 2010 s72ns-r_00_07 s72ns-r based mcps 13 data sheet (advance information) colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2007-2010 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse ? , ornand ? , ecoram? and combinations thereof, are trademarks and registered trademarks of spansion llc in the united states and other countries. ot her names used are for informational purposes only and ma y be trademarks of their respective owners.

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