rai o RA8808 128x64 driver for dot matrix lcd specification version 1.0 march 26, 2009 ra i o technology inc. ?copyright raio technology inc. 2009 rai o technology inc. 1/7 www.raio.com.tw
preliminary version 1.0 128x64driver for dot matrix l cd RA8808 rai o technology inc. 2/7 www.raio.com.tw 1. general description the RA8808 is a lcd driver lsi with 128(segment) x 64(co mmon) driver output for dot matrix liquid crystal graphic display systems. this device consists of t he display ram,128-bit segment drivers, 64-bit common drivers and decoder logic. it has the internal display ram for storing the display data transferred from an 8- bit 8080/6800 micro controller or 3-wire-spi/iic controller and generates the dot matrix liquid crystal driving signals corresponding to stored data. 2. features ? dot matrix lcd segment driver with 128 channel output, and common driver with 64 channel output. ? internal timing generator circuit for dynamic display. ? selection of master/slave mode for combine two RA8808 controller to support 256x64 dot matrix. ? applicable lcd common duty: 1/48, 1/64. ? support 6800/8080 8-bit parallel mpu interface. ? support 3-wires spi and iic serial mpu interface. ? two 512 bytes (4096-bits) display ram ? lcd driving voltage: 8v ~17v ? built-in 2x~4x voltage booster and voltage follower ? power supply voltage: +2.7v ~ 5.5v ? high voltage cmos process ? bare gold bump chip available 3. block diagram mpuif block com drivers seg drivers 512x8 display ram a 512x8 display ram b register block power circuit & test db7~0 rs e rw scan block cs1 cs2b cs3 cs4b ps mode ms ds shl adc rstb rc oscillator test[2~0] ra rb seg127~0 com63~0 m cl frm clk_out v[4:0]a vout c[3:1]p c[2:1]n v[4:0]
preliminary version 1.0 128x64driver for dot matrix l cd RA8808 rai o technology inc. 3/7 www.raio.com.tw 4. pad diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 com47 com46 com45 com44 com43 com42 com41 com40 com39 com38 com37 com36 com35 com34 com33 com32 141 140 139 138 137 136 135 134 com15 com14 com13 com12 com11 com10 com9 com8 com7 com6 com5 com4 com3 com2 com1 com0 133 132 131 130 129 128 127 126 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 58 59 60 61 62 63 64 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 frm cl m vdd ms gnd vdd mode ps adc vdd gnd cs4b cs3 vdd rstb rs e rw gnd cs2b cs1 vdd gnd db0 db1 db2 db3 db4 db5 db6 db7 vdd vdd vddp vddp vddp avdd avdd agnd agnd gndp gndp gndp gnd gnd gnd vout vout vout vout c3p c3p c3p c3p c1n c1n c1n c1n c1p c1p c1p c1p c2n c2n c2n c2n c2p c2p c2p c2p v0a v1a v2a v3a v4a v4 v4 v3 v3 v2 v2 v1 v1 v0 v0 vdd vdd ra rb vdd shl gnd ds gnd test0 test1 test2 m cl frm clk_out avdd avdd agnd agnd 57 vdd 65 avdd agnd 19 20 17 18 301 300 299 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 seg65 seg63 seg62 seg61 seg60 seg59 seg58 seg57 seg56 seg55 seg54 seg53 seg52 seg51 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com31 com30 com29 com28 com27 com26 com25 com24 com23 com22 com21 com20 com19 com18 com17 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 com16 143 142 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 seg127 seg126 seg125 seg124 seg123 seg122 seg121 seg120 seg119 seg118 seg116 seg115 seg114 seg113 seg112 seg111 seg110 seg109 seg108 seg107 seg106 seg105 seg104 seg103 seg102 seg101 seg100 seg99 seg98 seg97 seg96 seg95 seg94 seg93 seg92 seg91 seg90 seg89 seg88 seg87 seg86 seg85 seg84 seg83 seg82 seg81 seg80 seg79 seg78 seg77 seg76 seg75 seg74 seg73 seg72 seg71 seg70 seg69 seg68 seg67 seg66 seg64 com50 com51 seg117 com48 com49 145 144 ( 0 , 0 ) x y pt1 pt2 pt3 pt4 pt5 pt6 pt7 RA8808 top view 9166 x 1171 p1 p2 raio RA8808 logo 5. pin description 5-1 mpu interface pin name i/o description db0~db7 i/o in parallel mode : data bus these are data bus for data trans fer between mpu(6800/8080) and RA8808. in serial mode : pin description db7 db6 these pins are not used and must be connected to low. db5 db4 db3 in iic interface : these pins are used as the iic device address input. (sa[2:0]) in spi interface : these pins are not used and must be connected to high or low. db2 in iic interface : this pin is not used and must be connected to low. in spi interface : this pin is used as chip selection, active low. (zcs) db1 in iic interface : this pin is used as bi-direction serial data.(sda) in spi interface : this pin is used as bi-direction serial data.(sda) db0 in iic interface : this pin is used as serial clock.(scl) in spi interface : this pin is used as serial clock.(sck) e i in parallel mode : enable or read control when use 6800 series interface, this pi n is used as enable, active high. when use 8080 series interface, this pi n is used as data read, active low. in serial mode : this pin is not used and must be connected to low.
preliminary version 1.0 128x64driver for dot matrix l cd RA8808 rw i in parallel mode : read-write control or write control when use 6800 series interface, this pi n is used as data read/write control. active high for read and active low for write. when use 8080 series interface, this pin is used as data write, active low. in serial mode : this pin is not used and must be connected to low. rs i in parallel mode : data or instruction rs = h ? db0~db7 : display ram data rs = l ? db0~db7 : instruction data in serial mode : this pin is not used and must be connected to low. cs1 cs2b i in parallel mode : chip selection for left side (note 1) in order to interface left side data for input or output, the terminals have to be cs1 = h, cs2b = l. in serial mode : these pins are not used and must be connected to high or low. cs3 cs4b i in parallel mode : chip selection for right side (note 1) in order to interface right side data fo r input or output, the terminals have to be cs3 = h, cs4b = l. in serial mode : these pins are not used and must be connected to to high or low. rstb i reset signal when rstb = l, _on/off register becomes set by 0. (display off) _display start line register becomes se t by 0.(z-address 0 set, display from line 0) after releasing reset, this condition can be changed only by instruction. ps i parallel/serial mpu interface selection ps parallel/serial h parallel l serial mode i mpu interface selection(combine with ps) ps mode mpu interface h h 6800 series h l 8080 series l h 3-wire spi l l iic rai o technology inc. 4/7 www.raio.com.tw
preliminary version 1.0 128x64driver for dot matrix l cd RA8808 5-2 lcd panel interface pin name i/o description seg0~ seg127 o lcd segment driver output display ram data 1 : on, display ram data 0 : off relation of display ram & m : m data output level l l v2 l h v0 h l v3 h h gnd com0~ com63 o common signal output for lcd driving relation of common signal & m : m common signal output level l l v1 l h gnd h l v4 h h v0 m i/o alternating signal input for lcd driving. the input/output selection is determined by ms. cl i/o display synchronous signal display data is latched at rising time of the cl signal and increments the z- address counter at cl falling time. t he input/output selection is determined by ms. frm i/o synchronous control signal presets the 6-bit z counter and sync hronizes the common signal with the frame signal when the frame signal becomes high. the input/output selection is determined by ms. ms i master/slave mode selection ms master/slave mode h master l slave when in master mode, m, cl, frm are output pins. when in slave mode, m, cl, frm are input pins. 5-3 clock pin name i/o description ra i in internal clock mode, this pin connects to external resistor for rc circuit. in external clock mode, this pin is an input of external clock. internal clock mode external clock mode RA8808 ra rb r 50pf 50pf RA8808 ra rb external clock open RA8808 ra rb external clock open rb o in internal clock mode, this pin connects to external resistor for rc circuit. in external clock mode, this pin must keep floating. clk_out o internal system clock output for ca scade application or others for user. rai o technology inc. 5/7 www.raio.com.tw
preliminary version 1.0 128x64driver for dot matrix l cd RA8808 5-4 power pin name i/o description vout o regulator voltage output vdd vddp p digital power gnd gndp p digital ground avdd p analog power agnd p analog ground c1n c1p i capacitor input these are used to connect a capac itor for internal booster. c2n c2p i capacitor input these are used to connect a capac itor for internal booster. c3p i capacitor input these are used to connect a capac itor for internal booster. v0a~v4a i voltage input v0~v4 o voltage source of lcd driver the relationship of the power is v0 > v1 > v2 > v3 > v4 > gnd. 5-5 misc pin name i/o description adc i selection of segment data direction adc common data shift direction h seg0 ? seg1 ? ?seg127 l seg127 ? seg126 ? ? seg0 shl i selection of common data shift direction shl common data shift direction h com0 ? com1 ? ?com63 l com63 ? com62 ? ? com0 ds i selection of display duty ds duty h 1/64 l 1/48 test0 test1 test2 i these pins must contact to gnd in normal mode. rai o technology inc. 6/7 www.raio.com.tw
preliminary version 1.0 128x64driver for dot matrix l cd ra o technology inc. 7/7 www.raio.com.tw RA8808 i 6. lcd panel interface application circuit RA8808 lcd panel (128x64 dots) seg127 seg0 6800 mpu com0 com31 com63 com32 db[7:0] cs3 cs1 rw e rs rstb cs4b mode ps vdd shl adc ds ms shl adc ds ms test0 test1 test2 ra rb 56k c2p c2n 1 f c1p c1n 1 f c3p 1 f vout vdd c1p c3p cs2b v0a v4a v4 v0 avdd gnd agnd vdd gnd cs3 cs1 rw e rstb rs vout v0a v1a v2a v3a v4a r0 r1 r2 r3 r4 r5 100k 100k 100k 500k 100k 100k vdd v0 v1 v2 v3 v4 1 f x 5 v0 v1 v2 v3 v4 1 f x 5 vout 1 f vdd 1 f c1p~c3p v0a~v4a v0~v4 v0a v1a v2a v3a v4a 0.1 f x 5 * * * * * v0a v1a v2a v3a v4a 0.1 f x 5 v0a v1a v2a v3a v4a 0.1 f x 5 * * * * * vdd cs1 cs3 10k 10k * * vdd cs1 cs3 10k 10k * * : reserved / option * vout 1 f vout 1 f 50pf 50pf mode vdd * 0 * 0 mode vdd * 0 * 0 ps vdd * 0 * 0 ps vdd * 0 mode ps * 0 rw rw e 50~ 300 pf 50~ 300 pf e 50~ 300 pf 50~ 300 pf 128x64 stn panel RA8808 pcb fpc fpc connector r-string booster-caps mcu i/f
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