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3 msps, 14-bit sar adc ad7484 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2009 analog devices, inc. all rights reserved. features fast throughput rate: 3 msps wide input bandwidth: 40 mhz no pipeline delays with sar adc excellent dc accuracy performance 2 parallel interface modes low power: 90 mw (full power) and 2.5 mw (nap mode) standby mode: 2 a maximum single 5 v supply operation internal 2.5 v reference full-scale overrange mode (using 15th bit) system offset removal via user access offset register nominal 0 v to 2.5 v input with shifted range capability pin compatible upgrade of 12-bit ad7482 functional block diagram 2.5v reference nap mode2 buf t/h av dd agnd c bias dv dd dgnd refsel refout refin vin 14-bit algorithmic sar cs rd mode1 clip d0 stby d1 reset d2 d3 convst d4 d14 d5 d13 d6 d12 d11 d10 d9 d8 control logic and i/o registers d7 ad7484 v drive write busy 02642-001 figure 1. general description the ad7484 is a 14-bit, high speed, low power, successive approximation adc. the part features a parallel interface with throughput rates up to 3 msps. the part contains a low noise, wide bandwidth track-and-hold that can handle input frequencies in excess of 40 mhz. the conversion process is a proprietary algorithmic successive approximation technique that results in no pipeline delays. the input signal is sampled, and a conversion is initiated on the falling edge of the convst signal. the conversion process is controlled by an internally trimmed oscillator. interfacing is via standard parallel signal lines, making the part directly compatible with microcontrollers and dsps. the ad7484 provides excellent ac and dc performance specifica- tions. factory trimming ensures high dc accuracy, resulting in very low inl, offset, and gain errors. the part uses advanced design techniques to achieve very low power dissipation at high throughput rates. power consumption in the normal mode of operation is 90 mw. there are two power saving modes: a nap mode, which keeps the reference circuitry alive for a quick power-up while consuming 2.5 mw, and a standby mode that reduces power consumption to a mere 10 w. the ad7484 features an on-board 2.5 v reference but can also accommodate an externally provided 2.5 v reference source. the nominal analog input range is 0 v to 2.5 v, but an offset shift capability allows this nominal range to be offset by 200 mv. this allows the user considerable flexibility in setting the bottom end reference point of the signal range, a useful feature when using single-supply op amps. the ad7484 also provides an 8% overrange capability via a 15th bit. therefore, if the analog input range strays outside the nominal range by up to 8%, the user can still accurately resolve the signal by using the 15th bit. the ad7484 is powered by a 4.75 v to 5.25 v supply. the part also provides a v drive pin that allows the user to set the voltage levels for the digital interface lines. the range for this v drive pin is 2.7 v to 5.25 v. the part is housed in a 48-lead lqfp package and is specified over a ?40c to +85c temperature range.
ad7484 rev. c | page 2 of 20 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 9 terminology .................................................................................... 11 circuit description ......................................................................... 12 converter operation .................................................................. 12 analog input ............................................................................... 12 adc transfer function ............................................................. 13 power saving ............................................................................... 13 offset/overrange ........................................................................ 14 parallel interface ......................................................................... 15 board layout and grounding ................................................... 17 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 r evision h istory 12/09 rev. b to rev. c changes to table 1 , power requirements section ....................... 4 changes to ordering guide .......................................................... 19 8/08 rev. a. to rev. b changes to table 1 ............................................................................ 3 changes to tabl e 3 ............................................................................ 6 changes to typical performance characteristics section ........... 9 changes to figure 9 ........................................................................ 10 changes to circuit description section ...................................... 11 changes to terminology section .................................................. 11 changes to analog input section ................................................. 12 changes to offset/overrange section ......................................... 14 changes to tabl e 5, table 6, table 7, and tabl e 8 ....................... 15 changes to paral lel interface section ........................................... 15 changes to tabl e 9 .......................................................................... 16 changes to board layout and gr ou nd ing section .................... 17 changes to ordering guide .......................................................... 19 2/04r ev . 0 to r ev . a updated format .................................................................. u niversal changes to timing characteristics section .................................. 5 changes to pin function descriptions s ection ............................. 8 changes to figure 9 ........................................................................ 11 changes to the converter operation s ection ............................. 13 changes to the offset/overrange s ection ................................... 15 8/02 revision 0: initial version
ad7484 rev. c | page 3 of 20 specifications av dd / dv dd = 5 v 5%, agnd = dgnd = 0 v, v ref = e xternal, f sample = 3 msps; all spec ifications t min to t max and valid for v drive = 2.7 v to 5.25 v, unless otherwise noted. operating temperature range is ?40c to +85c. table 1. parameter min typ max unit test conditions/comments dynamic performance 1 , 2 signal -to - noise + distortion (sinad ) 3 76.5 db f in = 1 mhz 78 db f in = 1 mhz 79 db f in = 1 mhz, extended i npu t 77 db f in = 1 mhz, internal r eference total harmonic distortion (thd) 3 ?90 db ?95 db ?92 db internal r eference peak harmonic or spurious noise (sfdr) 3 ?90 db intermodulation distortion (imd) 3 second order terms ?9 6 db f in1 = 95.053 khz, f in2 = 105.329 khz third order terms ?94 db aperture delay 10 ns full power bandwidth 40 mhz @ 3 db 3.5 mhz @ 0.1 db dc accuracy resolution 14 bits integral nonlinearity 3 0.5 1 lsb diffe rential nonlinearity 3 0.3 0.75 lsb guaranteed no missed c odes to 14 b its offset error 3 6 lsb 0.036 %fsr gain error 3 6 lsb 0.036 %fsr analog input input voltage ?200 mv +2.7 v dc leakage current 1 a v in from 0 v to 2.7 v 2 a v in = ?200 mv input capacitance 4 35 pf reference input/output input voltage , v refin +2.5 v 1% for specified p erformance input dc leakage current , v refin 1 a input capacitance , v refin 4 25 pf input current , v refin 220 a external r eference output voltage , v refout +2.5 v error @ 25c , v refout 50 mv error t min to t max , v refout 100 mv output impedance , v refout 1 ?
ad7484 rev. c | page 4 of 20 parameter min typ max unit test conditions/comments logic inputs input high voltage, v inh v drive ?1 v input low voltage, v inl 0.4 v input current, i in 1 a input capacitance, c in 4 10 pf logic outputs output high voltage, v oh 0.7 v drive v output low voltage, v ol 0.4 v floating state leakage current 10 a floating state output capacitance 4 10 pf output coding straight (natural) binary conversion rate conversion time 300 ns track - and - hold acquisition time (t acq ) 70 ns sine wave i nput 70 ns full - scale step i nput throughput rate 2.5 msps parallel mode 1 3 msps parallel mode 2 power requirements v dd 5 v 5% v drive 2.7 5.25 v i dd normal mode (static) 13 ma cs and rd = logic 1 normal mode (operational) 20 ma n ap mode 0.5 ma standby mode 0.5 2 a power dissipation normal mode (operational) 100 mw n ap mode 2.5 mw standby mode 5 10 w 1 sinad figures quoted include external analog input circuit noise contribution of approximately 1 db. 2 see the typical performance characteristics section for analog input circuits used . 3 see the terminology section. 4 sample tested @ 25 c to ensure compliance . 5 digital input levels at d gnd or v drive .
ad7484 rev. c | page 5 of 20 timing characteristi cs av dd / dv dd = 5 v 5%, agnd = dgnd = 0 v, v ref = e xternal; all specifications t min to t max a nd valid for v drive = 2.7 v to 5.25 v, unless otherwise noted. table 2. parameter 1 symbol min typ max unit data read conversion time t conv 300 ns quiet time b efore conversion start t quiet 100 ns convst t 1 pulse width 5 100 ns convst fal ling edge to t 2 busy falling edge 20 ns cs falling edge to t 3 rd falling edge 0 ns data access time t 4 25 ns convst t 5 falling edge to new data va lid 30 ns busy t 6 rising edge to new data valid 5 ns bus relinquish time t 7 10 ns rd rising edge to t 8 cs rising edge 0 ns cs t 14 pulse w idth 30 ns rd t 15 pulse width 30 ns data write write pulse width t 9 5 ns data setup time t 10 2 ns data hold time t 11 6 ns cs t 12 falling edge to write falling edge 5 ns write falling edge to cs t 13 rising edge 0 ns 1 all timing specifications given are with a 25 pf load capacitance. with a load capacitance greater than this value, a digital buffer or latch must be used .
ad7484 rev. c | page 6 of 20 absolute maximum ratings t a = 25 c, unless otherwise noted. table 3. parameter rating av dd to a gnd ?0.3 v to +7 v dv dd to d gnd ?0.3 v to +7 v v drive to d gnd ?0.3 v to +7 v analog input voltage to a gnd ?0.3 v to av dd + 0.3 v digital input voltage to d gnd ?0.3 v to v drive + 0.3 v refin to a gnd ? 0.3 v to av dd + 0.3 v input current to any pin except suppl y pins 10 ma operating temperature range ?40c to +85c commercial storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 50c/w jc thermal impedance 10c/w lead temperature, soldering vapor phase (60 se c) 215c infrared (15 sec) 220c esd 1 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7484 rev. c | page 7 of 20 pin configuration and function descripti ons 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier d10 d9 d8 d7 v drive dgnd dgnd av dd c bias agnd agnd av dd agnd vin refout refin refsel agnd dv dd d6 d5 d4 ad7484 top view (not to scale) agnd d3 agnd agnd av dd clip mode1 mode2 reset convst d14 d13 d12 d11 av dd agnd agnd stby nap cs rd write busy d0 d1 d2 02642-002 figure 2 . pin configuration table 4 . pin function descriptions pin no. mnemonic description 1, 5, 13, 46 av dd positive pow er supply for analog circuitry. 2 c bias decoupling pin for internal bias voltage. a 1 nf capacitor should be placed between this pin and agnd. 3, 4, 6, 11, 12, 14, 15, 47, 48 agnd power supply ground for analog circuitry. 7 vin analog input. single ended analog input channel. 8 refout reference output. refout connects to the output o f the internal 2.5 v reference buffer. a 470 nf capacitor must be placed between this pin and agnd. 9 refin reference input. a 470 nf capacitor must be placed between this pin and agnd. when using an external voltage reference source, the reference vol tage should be applied to this pin. 10 refsel reference decoupling pin. when using the internal reference, a 1 nf ca pacitor must be connected from t his pin to agnd. when using an external reference source, this pin should be connected directly to agnd. 16 stby standby logic input. when this pin is logic high, the device is placed in standby mode. see the power saving section for further details. 17 nap n ap logic input. when this pin is logic high, the device is pl aced in a very low power mode. see the power saving section for further details. 18 cs chip select logic input. this pin is used in conjunction with rd to ac c ess the conversion result. the data bus is brought out of three - state and the current contents of the output register driven onto the data lines following the falling edge of both cs and rd . cs is also use d in conjunction with write to perform a write to the offset register. cs can be hardwired permanently low. 19 rd read logic input. used in conjunction with cs to ac cess the conversion result. 20 write write logic input. used in conjunction with cs to write data to the offset reg ister. when the desired offset word has been placed on the data bus, the write line should be pulsed high. it is t he falling edge of this pulse that latches the word into the offset register. 21 busy busy logic output. this pin indicates the status of the conversion process. the busy signal goes low after the falling ed ge of convst and stays low for the duration of the conversion. in parallel mode 1, the busy signal returns high when the conversion result has been lat ched into the output register. in parallel mode 2, the busy signal returns high as soon as the conversion has been completed, but the conversion result does not get latched into the output register until the falling edge of the next convst pulse. 22 to 28, 33 to 39 d0 to d13 data i/o bits. d13 is msb . these are three - state pins that are controlled by cs , rd , and write. t he operating voltage level for these pins is determined by the v drive input. 29 dv dd positive power supply for digital circuitry. 30, 31 dgnd ground reference for digital circuitry. 32 v drive logic power supply input. the v oltage supplied at this pin determines at what voltage the int erface logic of the device operate s.
ad7484 rev. c | page 8 of 20 pin no. mnemonic description 40 d14 data output b it for overranging. if the overrange feature is not u sed, this pin should be pulled to dgnd via a 100 k ? resistor. 41 convst convert start logic input. a conversion is initiated on the falling edge of the convs t signal. the input track - and - hold amplifier goes from track mode to hold mode , and the conversion process commences. 42 reset reset logic input. an active low reset pulse must be applied to this pin after power - up to ensure cor rect operation. a falling edge on this pin resets the internal state machine an d terminates a conversion that may be in progress. the contents of the offset register will also be cleared on this edge. holding this pin low keeps the part in a reset state. 43 mode2 operating mode logic input. see table 8 for details. 44 mode1 operating mode logic input. see table 8 for details. 45 clip logic input. a logic high on this pin enables output clipping. in this mod e, any input voltage that is greater than positive full scale or less than negative full scale will be clipped to all 1s or all 0s, respectively. further details are given in the offset/overrange section.
ad7484 rev. c | page 9 of 20 typical performance characteristics frequency (khz) 0 0 200 400 600 800 1400 (db) ?20 ?40 ?80 ?100 ?140 ?60 1000 1200 f in = 10.7khz snr = 78.9db snr + d = 78.8db thd = ?93.9db ?120 02642-003 figure 3 . 64 k fft plot w ith 10 khz input tone frequency (khz) 0 0 200 400 600 800 1400 (db) ?20 ?40 ?80 ?100 ?140 ?60 1000 1200 f in = 1.013mhz snr = 77.7db snr + d = 77.6db thd = ?95.5db ?120 02642-004 figure 4 . 64 k fft plot w ith 1 mhz input tone adc (code) 1.0 0 4096 8192 16384 dnl (lsb) 0.8 0.2 ?0.6 ?0.8 ?1.0 ?0.4 12288 0.6 0 0.4 ?0.2 02642-005 figure 5 . typical dnl adc (code) 1.0 0 4096 8192 16384 inl (lsb) 0.8 0.2 ?0.6 ?0.8 ?1.0 ?0.4 12288 0.6 0 0.4 ?0.2 02642-006 figure 6 . typical inl input frequency (khz) 80 65 10 10000 100 sinad (db) 1000 70 75 02642-007 figure 7 . sinad vs. input tone ( ad8021 input circuit) input frequency (khz) ?40 100 1000 thd (db) ?70 ?90 ?100 ?60 10000 ?50 ?80 100? 10? 0 ? 51? 200? 02642-008 figure 8 . thd vs. input ton e for different input resistances
ad7484 rev. c | page 10 of 20 frequency (khz) 0 10 100 psrr (db) ?30 ?50 ?60 ?20 1000 ?10 ?40 ?70 ?80 100mv p-p sine wave on supply pins 02642-009 figure 9 . psrr without decoupling temperature (c) 0.0004 ?55 ?25 5 35 95 125 refout (v) ?0.0004 ?0.0008 ?0.0012 ?0.0016 ?0.0020 0 65 02642-010 figure 10 . reference error
ad7484 rev. c | page 11 of 20 terminology integral nonlinearity the integral nonlinearity is the maximum deviation from a straigh t line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1/2 lsb below the first code transition, and full scale, a point 1/2 lsb above the last code transition. differential nonlinea rity th e differential nonlinearity is the difference between the measured and ideal 1 lsb change between any two adjacent codes in the adc. offset error the offset error is the deviation of the first code transition (00000) to (00001) from the ideal, tha t is, agnd + 0.5 lsb. gain error th e gain error is the deviation of the last code transition (111 110) to (111 111) from the ide al, that is , v ref ? 1.5 lsb , after the offset error has been adjusted out. track - and- hold acquisition time the track - and - hold acquisition time is the time required for the output of the track - and - hold amplifier to reach its final value, within 1/2 lsb, after the end of con version (the point at which the track - and - hold returns to track mode). signal -to - noise + distortion (sinad) ratio the sinad ratio is the measured ratio of signal - to - noise + distortion at the output of the adc. the signal is the rms ampli - tude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical sinad ratio for an ideal n - bit converter with a sine wave input is given by signal - to - noise + distortion = (6.02 n + 1.76)db therefore, this is 86.04 db f or a 14 - bit converter. total harmonic distortion (thd) the thd is the ratio of the rms sum of the harmonics to the fundamental. i t is defined as ( ) 1 2 6 2 5 2 4 2 3 2 2 v vvvvv thd ++++ = log20 db where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise th e p eak harmonic or spurious noise is the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental . t he value of this specification is usually determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities create s dist ortion products at sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n is equal t o zero. for example, the second order terms include (fa + fb) and (fa ? fb ), whereas the third order terms include (2fa + fb), (2fa ? fb), (fa + 2fb) , and (fa ? 2fb). the ad7484 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in frequency from the origi nal sine waves, whereas the third order terms are usually at a frequency close to the input frequencies. as a result, the second order and third order terms are specified separately . the calculation of the intermodulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs.
ad7484 rev. c | page 12 of 20 circuit description converter operation the ad7484 i s a 14 - bi t algorithmic successive approximation adc based around a capacitive dac. it provides the user with track - and - hold, reference, an adc, and versatile interface logic functions on a single chip. the normal analog input signal range that the ad7484 c an convert is 0 v to 2.5 v. by using the offset and overrange features on the adc, the ad7484 can convert analog input signals from ? 200 mv to +2.7 v while operating from a single 5 v supply. the part requires a 2.5 v reference, which can be provided from the internal reference or an external reference source. figure 11 shows a simplified schematic of the adc. the control logic, sar, and capacitive dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back to a balanced condition. capacitive dac switches vin v ref sar control logic control inputs output data 14-bit parallel comparator 02642-013 figure 11 . simplified block diagram of the ad7484 c onversion is initiated on the ad7484 by pulsing the convst input. on the falling edge of figure 12 convst , the track - and - hold goes from track mode to hold mode and the conversion sequence is started. conversion time for the part is 300 ns. shows the adc during conversion. when conversion starts, sw2 open s and sw1 move s to p osition b, causing the comparator to become unbalanced. the adc t hen runs through its successive - approximation routi ne and brings the comparator back into a balanced condition. when the comparator is rebalanced, the conversion result is available in the sar r egister. capacitive dac comparator control logic + ? sw1 sw2 agnd vin a b 02642-014 figure 12 . adc conversion phase at the end of conversion, the track - and - hold returns to track mode and the acquisition time begins. the trac k- and - hold acquisition time is 7 0 ns. figure 13 shows the adc during its acquisition phas e. sw2 is closed and sw1 is in p osition a. the comparator is held in a balance d condition , and the sampling capacitor acquires the signal on v in . capacitive dac comparator control logic + ? sw1 sw2 agnd vin a b 02642-015 figure 13 . adc acquisition phase analog input 1 2 3 4 5 6 7 8 ad829 1k? 1k? 100? bias voltage ac signal 150? 220pf ?v s +v s ? + vin 02642-011 figure 14 . analog input circuit used for 10 khz input tone 220? bias voltage 1 2 3 4 5 6 7 8 ad8021 50? ac signal 220? 10pf ?v s +v s ? + vin 10pf 02642-012 figure 15 . analog input circuit used for 1 mhz input tone figure 14 shows the analog input circuit used to obtain the data for the fast fourier transfer ( fft ) plot shown in figure 3 . the circuit uses the ad829 op amp as the input buffer. a bipolar analog signal is applied and biased up with a stable, low noise dc voltage connected to the labeled terminal , as shown in figure 11 . a 220 pf comp ensation capacitor is connected between pin 5 of the ad829 and the analog ground plane. the ad829 is supplied with +12 v and ? 12 v supplies. the supply pins are decou pled as close to the device as possible with both a 0.1 f and a 10 f capacitor connected to each pin. in each case, the 0.1 f capacitor should be the closer of the two caps to the device. more informa - tion on the ad829 is available at www.analog.com .
ad7484 rev. c | page 13 of 20 for higher input bandwidth applications, the ad8021 op amp (also available as a dual ad8022 op amp ) is the recommended choice to drive the ad7484. figure 15 shows the analog input circuit used to obtain the data for the fft plot shown in figure 4 . a bipolar analog signa l is applied to the terminal and biased up with a stable, low noise dc voltage connected , as shown in figure 12 . a 10 pf compensation capacitor is connected between pin 5 of the ad8021 and the negative supply. t he ad8021 is supplied with +12 v and ? 12 v supplies. the supply pins are decoupled as close to the device as possible, with both a 0.1 f and a 10 f capacitor connected to each pin. in each case, the 0.1 f capacitor should be the closer of the two caps to the device. the ad8021 logic reference pin is tied to analog ground, and the disable adc transfer functio n pin is tied to the positive supply. detailed informa tion on the ad8021 is available at www.analog.com . the output coding of the ad7484 is straight binary. the designed code transitions occur midway be tween the successive integer lsb values , that is , 1/2 lsb, 3/2 lsb , and so on . the lsb size is v ref /16 , 384. the nominal transfer characteristic for the ad7484 is shown in figure 16 . this transfer characteristic may be shifted as detailed in the offset/overrange section. 000...000 0v adc code analog input 111...111 000...001 000...010 111...110 111...000 011...111 0.5lsb +v ref ? 1.5lsb 1lsb = v ref /16384 02642-016 figure 16 . ad7484 transfer characteristic power saving the ad7484 uses advanced design techniques to achieve very low power dissipation at high throughput rates. in addition, the ad7484 features two power saving modes, nap and s tandby. these modes are selected by bringing either the nap pin or the stby p in to a logic high, respectively. when operating the ad7484 in normal fully powered mode, the current consumption i s 18 ma during conversion and the quiescent current is 12 ma. operating at a throughput rate of 1 msps, the conversion time of 300 ns contributes 27 mw to the overall power dissipation. (300 ns/1 s) (5 v 18 ma) = 27 mw for the remaining 700 ns of the cycle, the ad7484 dissipates 42 mw of power. (700 ns/1 s) (5 v 12 ma) = 42 mw th erefore , the power dissipated during each cycle is 27 mw + 42 mw = 69 mw figure 17 shows the ad7484 conversion sequence operating in normal mode. convst busy 300ns 1s 700ns 02642-017 figure 17 . normal mode power dissipation in nap mode, almost all of the internal circuitry is powered down . in this mode, the power dissipation is reduced to 2.5 mw . when using an external reference, there must be a minimum of 300 ns from exiting nap mode to initiating a conversion . this is necessary to allow the internal circuitry to settle after power - up and for the track - and - hold to properly acquire the analog input signal. the internal reference cannot be used in conjunction with the nap m ode. if the ad7484 is put into nap m ode after each conversion, the average power dissipation is reduced, but the throughput rate is limited by the power - up time. using the ad7484 w ith a through - put rate of 500 ksps while placing the part in nap m ode after each conversion result s in average power dissipation as follows : the power - up phase contributes (300 ns/ 2 s) (5 v 12 ma) = 9 mw the conversion phase contributes (300 ns/ 2 s) (5 v 1 8 ma) = 13.5 mw while in nap mode for the rest of the cycle, the ad7484 dissipates only 1.75 mw of power. (1400 ns/ 2 s) (5 v 0.5 ma) = 1.75 mw th erefore , the power dis sipated during each cycle is 9 mw + 13.5 mw + 1.75 mw = 24.25 mw
ad7484 rev. c | page 14 of 20 figure 18 shows the ad7484 conversion sequence when the part is put into nap m ode after each conversion. 600ns nap 300ns 1400ns 2s convst busy 02642-018 figure 18 . n ap mode power dissipa tion figure 19 and figure 20 show a typical graphical representation of power vs . throughput for the ad7484 when in normal mode and nap m ode , respectively. throughput (ksps) 60 0 3000 power (mw) 500 1000 1500 2000 2500 65 70 75 80 85 90 02642-019 figure 19 . normal mode, power vs. throughput throughput (ksps) 0 0 2000 250 power (mw) 750 1250 1500 1750 10 500 1000 20 30 40 50 60 70 80 90 02642-020 figure 20 . n ap mode, power vs. throughput in s tandby m ode, all internal circuitry is powered down and the power consumption of the ad7484 is reduced to 10 w. the power - up tim e necessary before a conversion can be initiated is longer because more of the internal circuitry has been powered down. in using the internal reference of the ad7484, the adc must be brought out of standby mode 500 ms before a conversion is initiated. ini tiating a conversion before the required power - up time has elapsed result s in incorrect conversion data. if an external reference source is used and kept powered up while the ad7484 is in standby mode, the power - up time required is reduced to 80 s. offse t/overrange the ad7484 provides a 8% overrange capability as well as a programmable offset register. the overrange capability is achieved by the use of a 15th bit (d14) and the clip input. if the clip input is at logic high and the contents of the offset register are 0, then the ad7484 operates as a normal 14 - bit adc. if the input voltage is greater than the full - scale voltage, the data output from the adc is all 1s. similarly, if the input voltage is lower than the zero -scale voltage, the data o utput from the adc is all 0s. in this case, d14 acts as an ove rrange indicator. it is set to 1 if the analog input voltage is outside the nominal 0 v to 2.5 v range. the default contents of the offset register are 0. if the offset reg - ister contains any value o ther than 0, the contents of the register are added to the sar result at the end of conversion. this has the effect of shifting the transfer function of the adc as shown in figure 21 and figure 22. however, it s hould be noted that with the clip input set to logic high, the ma ximum and minimum codes that the ad7484 can output are 0x 3fff and 0 x 0000, r espectively. further details are given in table 5 and table 6 . figure 21 shows the effect of writing a positive value to the offset register. f or example, if the contents of the offset register contained the value 1024, then the value of the analog input voltage for which the adc transitions from reading all 0s to 000 001 (the bottom reference point) is 0.5 lsb ? (1024 lsb) = ?156.326 mv the analog input voltage for which the adc read s full - scale (0 x3f ff) in this example is 2.5 C 1.5 lsb C (1024 lsb) = 2.34352 v analog input 0v 1lsb = v ref /16384 0.5lsb ?offset 000...000 adc code 111...111 000...001 000...010 111...110 111...000 011...111 +v ref ? 1.5lsb ?offset 02642-021 figure 21 . transfer characteristic with positive offset the effect of writing a negative value to the offset register is shown in figure 22. if a value of ? 512 i s written to the offset register, the bottom end reference point occur s at 0.5 lsb C ( ?512 lsb) = 78.20 mw following this, the analog input volta ge needed to produce a full - scale ( 0x3fff) re sult from the adc is 2.5 v C 1.5 lsb C ( ?512 lsb) = 2.5779 v
ad7484 rev. c | page 15 of 20 000...000 0v adc code analog input 111...111 000...001 000...010 111...110 111...000 011...111 0.5lsb ?offset +v ref ? 1.5lsb ?offset 1lsb = v ref /16384 02642-022 figure 22 . transfer characteristic with negative offset table 5 shows the expected adc result for a given analog input voltage with different offset values and with clip tied to logic high. the combined advantages of the offset and overrange features of the ad7484 are shown in table 6 . table 6 shows the same range of analog input and offset values as table 5 but with the clipping feature disabled. table 5 . clipping enabled (clip = 1) adc data, d0:13 offset vin 512 0 +1024 d14 ?200 mv 0 0 0 1 1 1 ?156.3 mv 0 0 0 1 1 0 0 v 0 0 1024 1 0 0 +78.2 mv 0 512 1536 0 0 0 +2.3434 v 14,846 15,358 16,383 0 0 0 +2.5 v 15,871 16,383 16,383 0 0 1 +2.5782 v 16,383 16,383 16,383 0 1 1 + 2.7 v 16,383 16,383 16,383 1 1 1 table 6 . clipping disabled (clip = 0) adc data, d0:1 4 offset vin 512 0 +1024 ?200 mv ?1823 ?1311 ?287 ?156.3 mv ?1536 ?1024 0 0 v ?512 0 1024 +78.2 mv 0 512 1536 +2.3434 v 14,846 15,358 16,382 +2.5 v 15,872 16,384 17,408 +2.5782 v 16,384 16,896 17,920 +2.7 v 17,183 17,695 18,719 if the clip input is at logic low, the overrange indicator is disabled and the ad7484 can achieve outp ut codes outside the nominal 14 - bit range of 0 to 16 ,383 ( see table 6 ). d 14 acts as an indicator that the adc is outside this nominal range. if the adc is outside this nominal range on the negative side, the adc output s a twos complement code and if the adc is outside the range on th e positive side, the adc output s a strai ght binary code as normal. if d14 is logic 1, d 13 indicates if the adc is out of range on the positive or negative side. if db13 is l ogic 1, the adc is outside the nominal range on the negative s ide and the output co de is a 15 - bit twos complement n umber (a negative number). if d 13 is l ogic 0, the adc is outside the nominal range on the positive s ide and the output code is a 15 - bit straight binary code ( see table 7 ). table 7. db14, db13 d ecoding, clip = 0 db14 db13 output coding 0 0 straight b inary C inside nominal range 0 1 straight b inary C inside nominal range 1 0 straight b inary C outside nominal range 1 1 twos c omplement C outside nominal range values from ?1310 to +13 10 can be written to the offset register . these values correspond to an offset of 200 mv. a write to the offset register is performed by writing a 13 - bit word to the part , as detailed in the parallel interface section. the 12 lsbs of the 15- bit word contain the offset value, wh ereas the 3 msbs must be set to 0. failure to write 0 s to the 3 msbs may result in the incorrect operation of the device. parallel interface the ad7484 features two parallel interfacing modes. these modes are selected by the mode pins (see table 8 ). table 8 . operating modes operating mode m ode 2 m ode 1 do not use 0 0 parallel mode 1 0 1 parallel mode 2 1 0 do not use 1 1 in parallel mode 1, th e data in the output register is updated on the rising edge of busy at the end of a conversion and is available for reading almost immediately afterwards. using this mode, throughput rates of up to 2.5 msps can be achieved. this mode is to be used if the conversion data is required immediately after the conversion is completed. an example where this may be of use is if the ad7484 is operating at much lower throughput rates in conjunction with the nap m ode (for power saving reasons) , a nd the input signal i s being compared with set limits within the dsp or other controller. if the limits ar e exceeded, the adc is brought immediately into full power operation and commence s sampling at full speed. figure 31 shows a timing diagram for the ad7484 operating in parallel mode 1 with both cs and in parallel mode 2, the data in the output register is not updated until the next falling edge of rd tied low. con vst . this mode c an be used where a single sample delay is not vital to the system operation , and conversion speeds of greater than 2.5 msps are desired. f or example , this may occur in a system where a large amount of samples are taken at high speed befo re a n f ft is performed for frequency analysis of the input signal. figure 32 shows a timing diagram for the ad7484 operating in parallel mode 2 with both cs and rd tied low.
ad7484 rev. c | page 16 of 20 data must not be read from the ad7484 while a conversion is taking place. for this reason, if operating the ad7484 at throughput speeds greater than 2.5 msps, it is necessary to tie both the cs pin and rd p in on the ad74 84 low and use a buffer on the data lines. this situation may also arise in the case where a read operation cannot be completed in the time after the end of one conversion and the start of the quiet period before the next conversion. the maximum slew rate at the input of the adc must be limited to 500 v/s while busy is low to avoid corrupting the ongoing conversion. in any multiplexed application where the channel is switched during conversion, this is to happen as soon as possible a fter the reading data from the ad7484 busy falling edge. data is read from the part via a 15 - bit parallel data bus with the standard cs and rd signals. the cs and rd signals are internally gated to enable the conversion result onto the data bus. the data lines d0 to d14 leave their high impedance state when both cs and rd are logic low. therefore, cs can be permanently tied logic low if required, and the figure 29 rd signal used to access the conversion result. shows a timing specification called t quiet . this is the amount of time that must be left after any data bus activity before the next conversion is initiated. writing to the ad7484 the ad7484 features a user accessible offset register. this allows the bottom of the transfer function to be shifted by 200 mv. this feature is e xplained in more detail in the offset/overrange section. to write to the offset register, a 15 - bit word is written to the ad7484 with the 12 lsbs containing the offset value in twos complement format. the 3 msbs must be set to 0. the offset value must be within the range ? 1310 to +1310, corresponding to an offset from ?200 mv to +200 mv. the value written to the offset register is stored and used until power is removed from the device, or the device is reset. the value stored may be updated at any time between conversions by another write to the device. table 9 shows some examples of offset register values and their effective offset voltage. figure 30 shows a timing diagram for writing to the ad7484. table 9 . offset register examples code (decimal) d14 to d12 d11 to d0 (tos complement) offset (mv) ?1310 000 1010 1110 0010 ?200 ?512 000 1110 0000 0000 ?78.12 +256 000 0001 0000 0000 +39.06 +1310 000 0101 0001 1110 +200 driving the convst to achieve the specified performance from the ad7484, the pin convst p in must be driven from a low jitter source. because the falling edge on the ( ) ( ) 2 2 1 log10 db j in itter tf? snr = convst p in determines the sampling instant, any jitter that may exist on this edge appear s as noise when the analog input signal contai ns high frequency components . the relationship between the analog input frequency ( f in ), timing jitter ( t j ), and resulting snr is given by for example, if the desired snr due to jitter i s 100 db with a maximum full - scale analog inpu t frequency of 1.5 mhz, ignor - ing all other noise sources, the result is an allowable jitter on the convst falling edge of 1.06 ps. for a 14 - bit converter (ideal snr = 86.04 db), the allowable jitter is greater than 1.06 ps , but due consider - ation must be given to the design of the typical connection convst circuitry to achieve 14 - bit performance with large analog input frequencies. figure 23 shows a typical connection diagram for the ad 7484 operating in parallel mode 1. conversion is initiated by a falling edge on convst . when convst goes low, the busy signal goes low, and at the end of conversion, the rising edge of busy is used to activate an interrupt service routine. the cs and in rd lines are then activated to read the 14 data bits (15 bits if using the overrange feature). f igure 23 , the v drive pin is tied to d v dd , which results in logic output levels being either 0 v or dv dd . the voltage applied to v drive controls the voltage value of the output logic signals. for example, if dv dd is supplied by a 5 v supply and v drive is s upplied by a 3 v supply, the logic output levels are either 0 v or 3 v. this feature allows the ad7484 to inter face to 3 v devices while still enabling the adc to process signals at a 5 v supply. microcontroller/ microprocessor reset parallel interface mode1 mode2 write clip nap stby d0 to d13 cs convst rd busy c bias refsel refin refout vin ad7484 adm809 v drive dv dd av dd 0.1f digital supply 4.75v to 5.25v 10f 1nf + 0.1f 0.1f + 47f analog supply 4.75v to 5.25v 0v to 2.5v 1nf 0.47f 0.47f ad780 2.5v reference 02642-023 figure 23 . typical connection dia gram
ad7484 rev. c | page 17 of 20 board layout and grounding for optimum performance from the ad7484, it is recommended that a pcb with a minimum of three layers be used. one of these layers, preferably the middle layer, should be as complete a ground plane as possible to give the best shielding. the board should be designed in such a way that the analog and digital circuitry is separated and confined to certain areas of the board. this practice, along with not running digital and analog lines close together, helps to avoid coupling digital noise onto analog lines. the power supply lines to the ad7484 are to be approximately 3 mm wide to provide low impedance paths and reduce the effects of glitches on the power supply lines. it is vital that good decoupling also be present. a combination of ferrites and decoupling capa- citors should be used, as shown in figure 23.the decoupling capacitors are to be as close to the supply pins as possible. this is made easier by the use of multilayer boards. the signal traces from the ad7484 pins can be run on the top layer, while the decoupling capacitors and ferrites can be mounted on the bottom layer where the power traces exist. the ground plane between the top and bottom planes provides excellent shielding. figure 24 to figure 28 show a sample layout of the board area immediately surrounding the ad7484. pin 1 is the bottom left corner of the device. the black area in each figure indicates the ground plane present on the middle layer. figure 24 shows the top layer where the ad7484 is mounted with vias to the bottom routing layer highlighted. figure 25 shows the bottom layer silkscreen where the decoupling components are soldered directly beneath the device. figure 26 shows the top and bottom routing layers overlaid. figure 27 shows the bottom layer where the power routing is with the same vias highlighted. figure 28 shows the silkscreen overlaid on the solder pads for the decoupling components, which are c1 to c6: 100 nf, c7 to c8: 470 nf, c9: 1 nf, and l1 to l4: meggit-sigma chip ferrite beads (bmb2a0600rs2). 02642-024 figure 24. top layer routing 02642-026 figure 25. bottom layer silkscreen 02642-028 figure 26. top and bottom routing layers 02642-025 figure 27. bottom layer routing 0 2642-027 figure 28. silkscreen and bottom layer routing
ad7484 rev. c | page 18 of 20 busy cs rd convst d[14:0] t 1 t 2 t 4 data valid t 3 t 7 t quiet t conv t acq t 14 t 15 t 8 02642-029 figure 29 . parallel mode read cycle convst cs rd d[14:0] offset data t 12 t 13 t 9 t 10 t 11 write 02642-030 figure 30 . parallel mode write cycle d[14:0] t 1 t 6 data n ? 1 data n t conv n + 1 n t 2 busy convst 02642-031 figure 31 . parallel mode 1 read cycle busy convst d[14:0] t 1 t 5 data n ? 1 data n t conv n n + 1 t 2 02642-032 figure 32 . parallel mode 2 read cycle
ad7484 rev. c | page 19 of 20 outline dimensions compliant t o jedec s t andards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarit y view a ro ta ted 90 ccw se a ting plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706- a figure 33 . 48- lead plastic quad flatpack (lqfp) [st- 48] dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad 7484bstz ?40c to +85c 48- lead plastic quad flatpack package (lqfp) st-48 eval -ad7484cbz evaluation board 2 eval - controlbrd2 z controller board 3 1 z = rohs compliant part. 2 this can be used as a standalone evaluation board or in conjunction with the controller board for evaluation/demonstration purposes . 3 this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in th e cb designators .
ad7484 rev. c | page 20 of 20 ? 2002 C 2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02642 -0- 12/09( c) notes

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