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i datasheet ? I347-AT4 intel? ethernet network connection I347-AT4 datasheet may 2012 revision 2.2
I347-AT4 ? datasheet ii information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual proper ty rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever and intel disclaims any express or implied warranty, rela ting to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. unless otherwise agreed in writing by intel, the in tel products are not designed nor intended for any application in which the failure of the intel product co uld create a situation where personal injury or death may occur. intel may make changes to specifications and product description s at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the information here is subject to change without notice. do not finalize a design with this information. this document contains information on products in the design phase of development. the products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current ch aracterized errata are available on request. contact your local intel sales office or yo ur distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm . intel and intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2012, intel corporation. all rights reserved.
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I347-AT4 ? datasheet iv revision history rev date comments 2.2 may 2012 added thermal design recommendations. 2.1 march 2012 added power consumption table to section 5.2. 2.0 1 december 2011 changed 1.8v power rail to 1.9v. updated the pin interface section (added rclk1, rclk2, and sclk). initial public release. 0.75 april 2011 added clocking source descriptions (recovered clock and reference clock select). 0.7 february 2011 added I347-AT4 sgmii- to-copper dual-port mode details. 0.6 november 2010 major revision (all sections). 0.5 september 2010 initial rele ase (intel confidential). 1. no releases between revision 0.75 and 2.0.
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I347-AT4 ? contents vi contents 1.0 introduction ................................................................................................................ ........ 1 1.1 I347-AT4 features ................................................................................................ 2 2.0 pin interface ............................................................................................................... ........ 4 2.1 pin assignment ..................................................................................................... 4 2.1.1 signal type definitions ............................................................................ 4 2.1.2 media dependent interface ...................................................................... 5 2.1.3 sgmi ........................................................................................................ 6 2.1.4 reserved pins .......................................................................................... 7 2.1.5 management/control................................................................................ 7 2.1.6 led .......................................................................................................... 8 2.1.7 jtag ........................................................................................................ 8 2.1.8 master clock/reset .................................................................................. 9 2.1.9 test .......................................................................................................... 9 2.1.10 references ............................................................................................. 10 2.1.11 power and ground ................................................................................. 10 2.1.12 clocking ................................................................................................. 10 2.1.13 pins i/o state at various test or reset modes...................................... 11 2.2 pinouts (top view) .............................................................................................. 11 2.2.1 pin a1 location ...................................................................................... 11 2.2.2 pinouts (a1 through p7)........................................................................ 12 2.2.3 pinouts (a8 through p14)...................................................................... 13 3.0 device functionality ........................................................................................................ .14 3.1 I347-AT4 operation and major interfaces ........................................................... 16 3.2 copper media interface....................................................................................... 16 3.2.1 transmit side network interface ............................................................ 17 3.2.2 encoder .................................................................................................. 17 3.2.3 receive side network interface ............................................................. 18 3.2.4 decoder.................................................................................................. 19 3.2.5 electrical interface.................................................................................. 20 3.2.6 sgmii speed and link ........................................................................... 21 3.2.7 sgmii trr blocking .............................................................................. 21 3.3 loopback............................................................................................................. 21 3.3.1 system interface loopback.................................................................... 21 3.3.2 line loopback ........................................................................................ 22 3.3.3 external loopback ................................................................................. 23 3.4 synchronizing fifo ............................................................................................ 24 3.5 resets ................................................................................................................. 25 3.6 power management ............................................................................................ 26 3.6.1 manual power down .............................................................................. 26 3.6.2 mac interface power down ................................................................... 26 3.6.3 copper detect mode .............................................................................. 27 3.6.4 low power modes.................................................................................. 28 3.6.5 low power operating modes .......... ....................................................... 28 3.6.6 sgmii effect on low power modes ....................................................... 29 3.7 auto-negotiation ................................................................................................. 29
vii contents ? I347-AT4 3.7.1 10/100/1000base-t auto -negotiation...... ................................ ............. 30 3.8 downshift feature ............................................................................................... 31 3.9 fast 1000base-t link down indication ............................................................. 31 3.10 cable tester........................................................................................................ 32 3.10.1 maximum peak....................................................................................... 33 3.10.2 first peak ............................................................................................... 34 3.10.3 offset...................................................................................................... 35 3.10.4 sample point .......................................................................................... 35 3.10.5 pulse amplitude and pulse width .......................................................... 36 3.10.6 drop link ................................................................................................ 36 3.10.7 cable test with link up ......................................................................... 36 3.11 data terminal equipment (dte) detect .............................................................. 36 3.12 crc error counter and frame counter.............................................................. 37 3.12.1 enabling the crc er ror counter and frame counter .......................... 37 3.13 packet generator ................................................................................................ 38 3.14 rx_er byte capture .......................................................................................... 38 3.15 mdi/mdix crossover .......................................................................................... 39 3.16 unidirectional transmit........................................................................................ 40 3.17 polarity correction............................................................................................... 40 3.18 flp exchange complete with no link................................................................ 41 3.18.1 behavior in various low power states .................................................. 43 3.18.2 serial led ..............................................................................................44 3.19 ieee 1149.1 and 114 9.6 controller........... ................................................ .......... 45 3.19.1 bypass instruction ..... ................................................................ .......... 46 3.19.2 sample/preload instruction ...... ....................................................... 46 3.19.3 extest instruction................................................................................ 50 3.19.4 the clamp instruction ................... ....................................................... 50 3.19.5 the high-z instruction .......................................................................... 50 3.19.6 id code instruction............................................................................... 50 3.19.7 extest_pulse instruction .................................................................. 51 3.19.8 extest_train instruction ............ ....................................................... 51 3.19.9 ac-jtag fault detection....................................................................... 51 3.20 interrupt ............................................................................................................... 54 3.21 configuring the I347-AT4 ................................................................................... 54 3.21.1 hardware configuration ......................................................................... 55 3.21.2 configuration mapping ........................................................................... 56 3.21.3 software configuration - management interface.................................... 56 3.22 reference clock.................................................................................................. 58 3.23 temperature sensor ........................................................................................... 58 3.24 power supplies ................................................................................................... 59 3.24.1 avddh................................................................................................... 59 3.24.2 vddc ..................................................................................................... 59 3.24.3 dvdd ..................................................................................................... 59 3.24.4 vddol ................................................................................................... 59 3.24.5 vddor .................................................................................................. 60 3.24.6 vddom .................................................................................................. 60 3.24.7 power supply sequencing ..................................................................... 60 3.25 clocking support ................................................................................................. 60 3.25.1 recovered clock .................................................................................... 60 3.25.2 reference clock select.......................................................................... 61
I347-AT4 ? contents viii 4.0 programmer?s visible state.............................................................................................. 62 4.1 register map ....................................................................................................... 63 4.1.1 copper control register - page 0, register 0........................................ 65 4.1.2 copper status register - page 0, register 1 ......................................... 66 4.1.3 phy identifier 1 - page 0, register 2 ..................................................... 67 4.1.4 phy identifier 2 - page 0, register 3 ..................................................... 68 4.1.5 copper auto-negotiation advertisement register - page 0, register 4 ......................................... 68 4.1.6 copper link partner ability register - base page - page 0, register 5 ............................................ 70 4.1.7 copper auto-neg otiation expansion register - page 0, register 6....... 71 4.1.8 copper next pa ge transmit register - page 0, register 7 ................... 72 4.1.9 copper link part ner next page register - page 0, register 8 .............. 72 4.1.10 1000base-t control register - page 0, register 9 .... ................ .......... 73 4.1.11 1000base-t status regi ster - page 0, register 10.............. ................ 74 4.1.12 extended status register - page 0, register 15.................................... 74 4.1.13 copper specific cont rol register 1 - page 0, register 16 ..................... 75 4.1.14 copper specific status register 1 - page 0, register 17 ...................... 76 4.1.15 copper specific inte rrupt enable register - pa ge 0, register 18 .......... 77 4.1.16 copper interrupt status register - page 0, register 19......................... 78 4.1.17 copper specific cont rol register 2 - page 0, register 20 ..................... 79 4.1.18 copper specific receive error counter regist er - page 0, register 21 ........................................ 80 4.1.19 page address register - any page, register 22 ................................... 80 4.1.20 global interrupt status - page 0, register 23 ........................................ 80 4.1.21 copper specific cont rol register 3 - page 0, register 26 ..................... 80 4.1.22 phy identifier register - page 1, register............................................. 81 4.1.23 phy identifier register - page 1, register 3.......................................... 81 4.1.24 extended status register - page 1, register 15.................................... 81 4.1.25 prbs control - page 1, register 23 ...................................................... 82 4.1.26 prbs error counter lsb - page 1, register 24 .................................... 82 4.1.27 prbs error counter msb - page 1, register 25 ................................... 82 4.1.28 mac specific control register 1 - page 2, register 16......................... 83 4.1.29 mac specific interrupt enable regi ster - page 2, register 18.............. 83 4.1.30 mac specific status register - page 2, register 19 ............................. 84 4.1.31 copper rx_er byte capture - page 2, register 20.............................. 84 4.1.32 mac specific control register 2 - page 2, register 21......................... 85 4.1.33 led[3:0] function control register - page 3, register 16..................... 85 4.1.34 led[3:0] polarity co ntrol register - page 3, register 17 ...................... 87 4.1.35 led timer control register - page 3, register 18 ................................ 87 4.1.36 led[5:4] function control and pola rity - page 3, register 19 ............... 88 4.1.37 sgmii link partner ability register - sgmii (media mode) mode (registe r 16_4.0 = 1b) - page 4, register 5 ......... 89 4.1.38 cable tester tx to mdi[0] rx coupling - page 5, register 16 .............. 90 4.1.39 cable tester tx to mdi[1] rx coupling - page 5, register 17 .............. 91 4.1.40 cable tester tx to mdi[2] rx coupling - page 5, register 18 .............. 92 4.1.41 cable tester tx to mdi[3] rx coupling - page 5, register 19 .............. 92 4.1.42 1000base-t pair skew register - pa ge 5, register 20 .............. .......... 93 4.1.43 1000base-t pair swap and polarity - page 5, register 21 ........ .......... 93 4.1.44 cable tester control - page 5, re gister 23 ........................................... 94
ix contents ? I347-AT4 4.1.45 cable tester sample point distance - page 5, register 24 .................. 95 4.1.46 cable tester cross pair positive threshold - page 5, register 25 .......95 4.1.47 cable tester same pair impedance positive threshold 0 and 1 - page 5, register 26 ............... 95 4.1.48 cable tester same pair impedance positive threshold 2 and 3 - page 5, register 27 ............... 96 4.1.49 cable tester same pair impedance positive threshold 4 and transmit pulse cont rol - page 5, register 28 ............. 96 4.1.50 packet generation - page 6, register 16............................................... 97 4.1.51 crc counters - page 6, register 17 ..................................................... 97 4.1.52 checker control - page 6, register 18 .................................................. 97 4.1.53 general control register - page 6, register 20..................................... 98 4.1.54 late collision co unters 1 & 2 - page 6, register 23.............................. 98 4.1.55 late collision co unters 3 & 4 - page 6, register 24.............................. 99 4.1.56 late collision window adjust/link disconnect - page 6, register 25.... 99 4.1.57 misc test - page 6, register 26 ............................................................. 99 5.0 electrical and timing specifications...............................................................................102 5.1 recommended operating conditions ...............................................................102 5.2 current consumption ........................................................................................103 5.3 dc operating conditions ..................................................................................104 5.3.1 digital pins ...........................................................................................104 5.3.2 ieee dc transceiver pa rameters....................... ............. ............ ........105 5.3.3 sgmii interface ....................................................................................105 5.4 ac electrical specifications...............................................................................110 5.4.1 reset timing ........................................................................................110 5.4.2 xtal_in/xtal_out (c lk_sel[1:0] = 10b or 11b) timing ................111 5.4.3 led to config timing........................................................................111 5.4.4 serial led timing ................................................................................112 5.5 sgmii interface timing .....................................................................................113 5.5.1 sgmii output ac characteristics.........................................................113 5.5.2 sgmii input ac characteristics ...........................................................113 5.6 mdc/mdio timing ............................................................................................114 5.7 jtag timing .....................................................................................................115 5.8 ieee ac transceiver para meters............. ................................................ ........115 5.9 latency timing ..................................................................................................116 5.9.1 10/100/1000base-t to sgmii latency timing................ ............ ........116 5.9.2 sgmii to 10/100/10 00base-t latency timing... ............. ............ ........117 5.10 crystal specifications ........................................................................................120 6.0 package ..................................................................................................................... ....122 6.1 196-pin tfbga package ..................................................................................123 7.0 thermal design recommendations ...............................................................................125 7.1 introduction........................................................................................................125 7.2 intended audience ............................................................................................125 7.3 thermal considerations ....................................................................................125 7.4 thermal management importance ....................................................................126 7.5 terminology and definitions..............................................................................126 7.6 package thermal/mechanical specificatio ns and limits ..................................127 7.6.1 thermal limits - max junction/case ....................................................127
I347-AT4 ? contents x 7.6.2 thermal specifications ......................................................................... 128 7.6.3 mechanical limits - maximum static normal load .............................. 128 7.6.4 mechanical specifications .................................................................... 129 7.7 thermal solutions ............................................................................................. 129 7.7.1 extruded heat sinks ............................................................................ 130 7.7.2 thermal interface materials for heat sink solutions ............................ 131 7.7.3 attaching the extruded heat sink ........................................................ 133 7.8 reliability........................................................................................................... 134 7.9 jedec simulation results................................................................................ 134 7.9.1 designing for thermal performanc e .................................................... 134 7.9.2 simulation setup .................................................................................. 134 7.9.3 simulation results ............................................................................... 135 7.10 component measurement methodology ........................................................... 136 7.10.1 case temperat ure measurements....................................................... 136 7.11 conclusion ........................................................................................................ 138 7.12 heat sink and attach suppliers ........................................................................ 138 7.13 pcb layout guidelines ..................................................................................... 138
1 introduction?I347-AT4 1.0 introduction the intel ? ethernet network connection I347-AT4 (I347-AT4) quad, single-chip device contains four independent gigabit ethernet (gbe) transceivers on a single monolithic integrated circuit (ic) that supports sgmii on the mac interface in an sgmii-to-copper application. each transceiver performs a ll the physical layer (phy) functions for 100base-tx and 1000base-t full- or half-duplex ethernet on a cat 5 twisted pair cable, and 10base-t full- or half-duplex ethernet on a cat 3, 4, and 5 cable. note: the I347-AT4 can also operate in dual-por t mode. when set by the mac, the I347-AT4 uses two independent gbe transceivers (port 0 and port 1) in an sgmii-to-copper application. the I347-AT4 integrates mdi interface termin ation resistors and capacitors into the phy. this resistor integration simplifies board layout and lowers board cost by reducing the number of external components. the ne w calibrated resistor scheme achieves and exceeds the accuracy requirements of th e ieee 802.3 return loss specifications. the I347-AT4 consumes less than 500 mw per port; thereby, reducing overall system cost by eliminating heat-sink and reducing air-flow requirements. the I347-AT4 is fully compliant with the ieee 802.3 standard. it includes the pmd, pma, and pcs sublayers and performs: ? pam5, 8b/10b, 4b/5b, mlt-3, nrzi, and manchester encoding/decoding ? digital clock/data recovery ? stream cipher scrambling/descrambling ? digital adaptive equalization for the receiver data path as well as digital filtering for pulse-shaping for the line transmitter ? auto-negotiation and management functions. the I347-AT4 also supports auto-mdi/mdix at all three speeds to enable easier installation and reduce installation costs. the I347-AT4 uses advanced mixed-signal processing to perform equalization, echo and crosstalk cancellation, data recovery, and error correction at a gigabit-per-second data rate. the I347-AT4 dissipates very low power while achieving robust performance in noisy environments. in addition, the I347-AT4 supports a cable te ster feature that enables fault detection and advanced cable performance monitoring. the I347-AT4 is available in a 15 mm x 15 mm, 196-pin tfbga package.
I347-AT4?introduction 2 1.1 I347-AT4 features ? two or four ports sgmii-to-copper (see figure 1 and figure 2 ) ? integrated mdi interface termination resistors and capacitors ? low power consumption (< 500 mw per port) ? integrated cable diagnostic feature ? downshift mode for two-pair cable installations ? supports up to four leds per port progra mmable to indicate link, speed, duplex, and activity functions ? supports advance power management (apm) modes for significant power savings ? automatic mdi/mdix crossover for all three speeds of operation (10/100/ 1000base-t) ? automatic polarity correction ? 25 mhz clock input option ? loopback mode for diagnostics ? supports ieee 1149.1 jtag and 1149.6 ac jtag ? available in rohs 6 and halogen free packages ? manufactured in a 15 x 15 mm 196-pin tfbga package
3 introduction?I347-AT4 figure 1. sgmii (system) to copper ? dual port mode figure 2. sgmii (system) to copper ? quad port mode m a g n e t i c s 10/100/1000 mb/s ethernet mac sgmii (system interface) media types: - 10base-t - 100base-tx - 1000base-t rj45 I347-AT4 rj45 10/100/1000 mb/s ethernet mac port 1 port 0 m a g n e t i c s 10/100/1000 mb/s ethernet mac sgmii (system interface) media types: - 10base-t - 100base-tx - 1000base-t rj45 I347-AT4 rj45 rj45 rj45 10/100/1000 mb/s ethernet mac 10/100/1000 mb/s ethernet mac 10/100/1000 mb/s ethernet mac
I347-AT4?pin interface 4 2.0 pin interface 2.1 pin assignment the I347-AT4 is manufactured in a 15 x 15 mm 196-pin tfbga package. 2.1.1 signal type definitions signal type definition h input with hysteresis i/o input/output i input only o output only pu internal pull-up pd internal pull-down d open-drain output z tri-state output ma dc sink capability
5 pin interface?I347-AT4 2.1.2 media dependent interface table 1. media dependen t interface port 0 table 2. media dependen t interface port 1 pin # pin name pin type description n3 p3 p0_mdip[0] p0_mdin[0] i/o media dependent interface[0]. in 1000base-t mode in mdi configurat ion, mdip/n[0] correspond to bi_da. in mdix configuration, mdip /n[0] correspond to bi_db. in 100base-tx and 10base-t modes in md i configuration, mdip/n[0] are used for the transmit pair. in mdix configuration, mdip/n[0] are used for the receive pair. unused mdi pins must be left floating. the I347-AT4 contains an internal 100 resistor between the mdip/n[0] pins. n4 p4 p0_mdip[1] p0_mdin[1] i/o media dependent interface[1]. in 1000base-t mode in mdi configuration, mdip/n[1] correspond to bi_db. in mdix configuration, mdip/n[1] correspond to bi_da. in 100base-tx and 10base-t modes in md i configuration, mdip/n[1] are used for the receive pair. in mdix configuratio n, mdip/n[1] are used for the transmit pair. unused mdi pins must be left floating. the I347-AT4 contains an internal 100 resistor between the mdip/n[1] pins. p5 n5 p0_mdip[2] p0_mdin[2] i/o media dependent interface[2]. in 1000base-t mode in mdi configuration, mdip/n[2] correspond to bi_dc. in mdix configuration, mdip/n[2] correspond to bi_dd. in 100base-tx and 10base-t mode s, mdip/n[2] are not used. unused mdi pins must be left floating. the I347-AT4 contains an internal 100 resistor between the mdip/n[2] pins. m5 m6 p0_mdip[3] p0_mdin[3] i/o media dependent interface[3]. in 1000base-t mode in mdi configurat ion, mdip/n[3] correspond to bi_dd. in mdix configuration, mdip /n[3] correspond to bi_dc. in 100base-tx and 10base-t mode s, mdip/n[3] are not used. unused mdi pins must be left floating. the I347-AT4 contains an internal 100 resistor between the mdip/n[3] pins. pin # pin name pin type description m8 m7 p1_mdip[0] p1_mdin[0] i/o media dependent interface[0] for port 1. refer to p0_mdi[0]p/n . n8 p8 p1_mdip[1] p1_mdin[1] i/o media dependent interface[1] for port 1. refer to p0_mdi[1]p/n . n7 p7 p1_mdip[2] p1_mdin[2] i/o media dependent interface[2] for port 1. refer to p0_mdi[2]p/n . n6 p6 p1_mdip[3] p1_mdin[3] i/o m edia dependent interface[3] for port 1. refer to p0_mdi[3]p/n .
I347-AT4?pin interface 6 table 3. media dependent interface port 2 table 4. media dependent interface port 3 2.1.3 sgmi table 5. sgmii interface port 0 table 6. sgmii interface port 1 pin # pin name pin type description p9 n9 p2_mdip[0] p2_mdin[0] i/o media dependent interface[0] for port 2. refer to p0_mdi[0]p/n . p10 n10 p2_mdip[1] p2_mdin[1] i/o media dependent interface[1] for port 2. refer to p0_mdi[1]p/n . p11 n11 p2_mdip[2] p2_mdin[2] i/o media dependent interface[2] for port 2. refer to p0_mdi[2]p/n . m9 m10 p2_mdip[3] p2_mdin[3] i/o media dependent interface[3] for port 2. refer to p0_mdi[3]p/n . pin # pin name pin type description n14 p14 p3_mdip[0] p3_mdin[0] i/o media dependent interface[0] for port 3. refer to p0_mdi[0]p/n . m12 m11 p3_mdip[1] p3_mdin[1] i/o media dependent interface[1] for port 3. refer to p0_mdi[1]p/n . n13 p13 p3_mdip[2] p3_mdin[2] i/o media dependent interface[2] for port 3. refer to p0_mdi[2]p/n . n12 p12 p3_mdip[3] p3_mdin[3] i/o media dependent interface[3] for port 3. refer to p0_mdi[3]p/n . pin # pin name pin type description b1 a1 p0_s_inp p0_s_inn i sgmii transmit data. 1.25 gbaud input - positive and negative. b2 a2 p0_s_outp p0_s_outn o sgmii receive data. 1.25 gbaud output - positive and negative. output amplitude can be adjusted via register 26_1.2:0. pin # pin name pin type description a4 b4 p1_s_inp p1_s_inn i sgmii transmit data. 1.25 gbaud input - positive and negative. a3 b3 p1_s_outp p1_s_outn o sgmii r eceive data. 1.25 gbaud output - positive and negative. output amplitude can be adju sted via register 26_1.2:0.
7 pin interface?I347-AT4 table 7. sgmii interface port 2 table 8. sgmii interface port 3 2.1.4 reserved pins 2.1.5 management/control pin # pin name pin type description a11 b11 p2_s_inp p2_s_inn i sgmii transmit data. 1.25 gbaud input - positive and negative. a12 b12 p2_s_outp p2_s_outn o sgmii receive data. 1.25 gbaud output - positive and negative. output amplitude can be adjusted via register 26_1.2:0. pin # pin name pin type description b14 a14 p3_s_inp p3_s_inn i sgmii transmit data. 1.25 gbaud input - positive and negative. b13 a13 p3_s_outp p3_s_outn o sgmii receive data. 1.25 gbaud output - positive and negative. output amplitude can be adjusted via register 26_1.2:0. pin # pin name pin type description b9 a9 rsvd_nc rsvd_nc i reserved, do not connect. a8 b8 rsvd_nc rsvd_nc o reserved, do not connect. pin # pin name pin type description b6 mdc i management clock pin. mdc is the management data clock reference for the serial management interface. a continuous clock stream is not expected. the maximum frequency supported is 12 mhz. a6 mdio i/o management data pin. mdio is the management data. mdio tran sfers management data in and out of the device synchronously to mdc. this pin requires a pull-up resistor in a range from 1.5 k to 10 k . d2 intn od interrupt pin. the pull-up resistor used for the intn must be connected to the vddol level. the pull-up resistor should not be connected to voltage higher than vddol.
I347-AT4?pin interface 8 2.1.6 led 2.1.7 jtag pin # pin name pin type description f2 e1 e2 d1 p0_led[3] p0_led[2] p0_led[1] p0_led[0] o parallel led output port 0. h1 g1 g2 f1 p1_led[3] p1_led[2] p1_led[1] p1_led[0] o parallel led output port 1. k2 k1 j1 h2 p2_led[3] p2_led[2] p2_led[1] p2_led[0] o parallel led output port 2. m2 m1 l2 l1 p3_led[3] p3_led[2] p3_led[1] p3_led[0] o parallel led output port 3. l3 k3 p1 n1 config[3] config[2] config[1] config[0] i global hardware configuration. see section 3.21 for details. j2 v18_l i vddol voltage control. tie to vss = vddol operating at 3.3v floating = vddol operating at 1.9v e13 v18_r i vddor voltage control. tie to vss = vddor operating at 3.3v floating = vddor operating at 1.9v c7 v12_en i vddom voltage control. tie to vss = vddom operating at 3.3v floating = vddom operating at 1.9v pin # pin name pin type description g14 tdi i, pu boundary scan test data input. tdi contains an internal 150 k pull-up resistor. g13 tms i, pu boundary scan test mode select input. tms contains an internal 150 k pull-up resistor. g12 tck i, pu boundary scan test clock input. tck contains an internal 150 k pull-up resistor. e12 trstn i, pu boundary scan test reset input. active low. trstn contains an internal 150 k pull-up resistor. for normal operation, trstn should be pulled low with a 4.7 k pull-down resistor. d12 tdo o boundary scan test data output.
9 pin interface?I347-AT4 2.1.8 master clock/reset 2.1.9 test pin # pin name pin type description j13 xtal_in i 25 mhz clock input 25 mhz 50 ppm tolerance crystal reference or oscillator input. xtal_in should be left floating when it is not used. when xtal_in is driven directly from the oscillator or clock buffer, this pin should be ac-coupled with a 0.1 nf capacitor. no additional ac capacitor is needed if a capacitor divider is already used for level shifting. j14 xtal_out o 25 mhz crystal output. 25 mhz 50 ppm tolerance crystal reference. xtal_out should be left floating when it is not used. d13 d14 ref_clkp ref_clkn i 125 mhz/156.25 mhz reference clock inpu t positive and negative 50 ppm tolerance differential clock inputs. ref_clkp/n are lvds differential inputs with a 100 differential internal termination resistor. if not used, ref_clkp must be pulled high with a 1 k resistor to 1.9v. if not used, ref_clkn must be pulled to gnd with a 1 k resistor. h13 h14 clk_sel[1] clk_sel[0] i reference clock selection 00b = reserved. 01b = reserved. 10b = use 25 mhz xtal_in/xtal_out 1 . 11b = use 25 mhz xtal_in/xtal_out. clk_sel[1:0] must be connected to vddor for configuration high. 1. see section 3.21 for details. e3 resetn i hardware reset. xtal_in must be active for a minimum of 10 clock cycles before the rising edge of resetn. resetn mu st be in inactive state for normal operation. 1b = normal operation 0b = reset pin # pin name pin type description l14 l13 hsdacp hsdacn o ac test point. positive and negative. these pins are also used to bring out a differential tx_tclk. connect these pins with a 50 termination resistor to vss for ieee testing and debug purposes. if debug and ieee testing are not of importance, these pins can be left floating. k13 tstpt o dc test point. the tstpt pin should be left floating. c8 tstptf o dc test point. the tstptf pin should be left floating. a5 b5 test[1] test[0] i, pd test control. this pin should be left floating.
I347-AT4?pin interface 10 2.1.10 references 2.1.11 power and ground 2.1.12 clocking pin # pin name pin type description k12 rset i resistor reference external 5.0 k 1% resistor connected to ground. pin # pin name pin type description e6, e7, e8, e9, f4, f11, f12, g4, g11, h4, j4 dvdd power 1.0v digital supply d4, d5, d8, d9, d10, d11, e4, e5, e10, e11, k11, l4, l5, l6, l7, l8, l9, l10, l11 avddh power 1.9v analog supply. h12 vddc power 1.9v supply 1 . 1. vddc supplies xtal_in/out. d6, d7 vddom power 1.9v or 3.3v i/o supply 2 . 2. vddom supplies digital i/o pi ns for mdc, md io, and test. f13 vddor power 1.9v or 3.3v i/o supply 3 . 3. vddor supplies digital i/o pins for tdo, tdi, tms, tck, trstn, ref_clkp/n, and clk_sel[1:0]. f3, g3, h3, j3 vddol power 1. 9v or 3.3v i/o supply 4 . 4. vddol supplies digital i/o pins for resetn, led, config, and intn. a7, a10, b7, b10, c1, c2, c3, c4, c5, c6, c9, c10, c11, c12, c13, c14, d3, f5, f6, f7, f8, f9, f10, g5, g6, g7, g8, g9, g10, h5, h6, h7, h8, h9, h10, h11, j5, j6, j7, j8, j9, j10, j11, k4, k5, k6, k7, k8, k9, k10, l12, m3, m4, m13, m14, n2, p2 vss ground ground. j12 vssc ground ground. pin # pin name pin type description e14 rclk1 o 25/125 mhz gigabit recovered clock1. if not used pins must be left unconnected. f14 rclk2 o 25/125 mhz gigabit recovered clock2. if not used pins must be left unconnected. k14 sclk i 25 mhz input reference clock. do not electr ically short the sclk to xtal_in. if not used pins must be left unconnected.
11 pin interface?I347-AT4 2.1.13 pins i/o state at various test or reset modes 2.2 pinouts (top view) 2.2.1 pin a1 location pin(s) loopback software reset hardware reset power down mdi[3:0]p/n active tri-state tri-state tri-state s_outp/n active internally pulled up by terminations of 50 internally pulled up by terminations of 50 reg. 16.3 state 0b = internally pulled up by terminations of 50 1b = active mdio active active tri-state active intn active tri-state tri-state tri-state led active see section 2.27.5 tr i -s t a t e s ee section 2.27.5 tdo active active active active pin a1 location I347-AT4
I347-AT4?pin interface 12 2.2.2 pinouts (a1 through p7) 1234567 a p0_s_inn p0_s_outn p1_s_outp p1_s_inp test[1] mdio vss a b p0_s_inp p0_s_outp p1_s_outn p1_s_inn test[0] mdc vss b c vss vss vss vss vss vss v12_en c d p0_led[0] intn vss avddh avddh vddom vddom d e p0_led[2] p0_led[1] resetn avddh avddh dvdd dvdd e f p1_led[0] p0_led[3] vddol dvdd vss vss vss f g p1_led[2] p1_led[1] vddol dvdd vss vss vss g h p1_led[3] p2_led[0] vddol dvdd vss vss vss h j p2_led[1] v18_l vddol dvdd vss vss vss j k p2_led[2] p2_led[3] config[2] vss vss vss vss k l p3_led[0] p3_led[1] config[3] avddh avddh avddh avddh l m p3_led[2] p3_led[3] vss vss p0_mdip[3] p0_mdin[3] p1_mdin[0] m n config[0] vss p0_mdip[0] p0_mdip[1] p0_mdin[2] p1_mdip[3] p1_mdip[2] n p config[1] vss p0_mdin[0] p0_mdin[1] p0_mdip[2] p1_mdin[3] p1_mdin[2] p 1234567
13 pin interface?I347-AT4 2.2.3 pinouts (a8 through p14) 8 9 10 11 12 13 14 c tstptf vss vss vss vss vss vss c g vss vss vss dvdd tck tms tdi g h vss vss vss vss vddc clk_sel[1] clk_sel[0] h j vss vss vss vss vssc xtal_in xtal_out j l avddh avddh avddh avddh vss hsdacn hsdacp l m p1_mdip[0] p2_mdip[3] p2_mdin[3] p3_mdin[1] p3_mdip[1] vss vss m n p1_mdip[1] p2_mdin[0] p2_m din[1] p2_mdin[2] p3_mdip[3] p3_mdip[2] p3_mdip[0] n p p1_mdin[1] p2_mdip[0] p2_mdip[1] p2_mdip[2] p3_mdin[3] p3_mdin[2] p3_mdin[0] p 8 9 10 11 12 13 14 vss p2_s_inp p2_s_outp p3_s_outn p3_s_inn a a rsvd_nc rsvd_nc rsvd_nc rsvd_nc vss p2_s_inn p2_s_outn p3_s_outp p3_s_inp b b avddh avddh avddh avddh tdo rsvd_nc rsvd_nc d d e e dvdd dvdd avddh avddh trstn v18_r rclk1 f f vss vss vss dvdd dvdd vddor rclk2 k vss vss vss avddh rset tstpt sclk k
I347-AT4?device functionality 14 3.0 device functionality the I347-AT4 is a 2- or 4-port 10/100/1000base-t gigabit ethernet transceiver. each port of the I347-AT4 can operate completely independent of each other, but they are identical in performance and functionality. the functional description and electrical specifications for the I347-AT4 are applicable to each port. for simplicity, the functional description in this document describes the operation of a single transceiver. port numbers have been omitted from many diagrams and descriptive text indicating that the functionality applies to all ports. in this document, the pins for each port are specified by the port number, pin name, and signal number, respectively. for example, led 1 pin for port 0 shown in figure 3 (p0_led[1]): however, the mdio pin supported by the i3 47-at4 are global to the chip and do not have port numbers. figure 3 and figure 4 show the functional block diagram of the I347-AT4. figure 3. functional block diagram ? dual-port mode copper p0_mdip/n[3:0] sgmii p0_s_inp/n p0_s_outp/n copper p1_mdip/n[3:0] sgmii p1_s_inp/n p1_s_outp/n management interface mdc mdio intn jtag tck tms tdi tdo trstn led p0_led[3:0] p1_led[3:0] p2_led[3:0] p3_led[3:0] configuration v18_l v18_r v12_en config[3:0] clock/ reset xtal_in xtal_out resetn bias/ test tstpt tstptf hsdacp/n test[1:0] rset generator/ checker generator/ checker sclk rclk[2:1]
15 device functionality?I347-AT4 figure 4. functional block diagram ? quad-port mode copper p0_mdip/n[3:0] sgmii p0_s_inp/n p0_s_outp/n copper p1_mdip/n[3:0] sgmii p1_s_inp/n p1_s_outp/n copper p2_mdip/n[3:0] sgmii p2_s_inp/n p2_s_outp/n copper p3_mdip/n[3:0] sgmii p3_s_inp/n p3_s_outp/n management interface mdc mdio intn jtag tck tms tdi tdo trstn led p0_led[3:0] p1_led[3:0] p2_led[3:0] p3_led[3:0] configuration v18_l v18_r v12_en config[3:0] clock/ reset xtal_in xtal_out resetn bias/ test tstpt tstptf hsdacp/n test[1:0] rset generator/ checker generator/ checker generator/ checker generator/ checker
I347-AT4?device functionality 16 3.1 I347-AT4 operation and major interfaces the I347-AT4 supports an mdi interface-to-copper cable interface. the mdi interface is always a media interface. (the system interface is also known as mac interface. it is typically the conne ction between the phy and the mac or the system asic.) for example: figure 5. sgmii system interf ace example ? quad-port mode figure 6. sgmii system interface example ? dual-port mode as can be seen from this example, the sg mii interface acts as a system interface. the I347-AT4 supports one mode of operat ion: sgmii (system)-to-copper (register 20_6.2:0 (001b). 3.2 copper media interface the copper interface consists of the mdip/n[3:0] pins that connect to the physical media for 1000base-t, 100base-tx, and 10base-t modes of operation. the I347-AT4 integrates mdi interface termination resistors. the ieee 802.3 specification requires that both sides of a link have termination resistors to prevent reflections. traditionally, these resistors and additional capacitors are placed on the board between a phy device and the magnetics. the resistors have to be very accurate to meet the strict ieee return loss requirements. typically, 1% accuracy resistors are used on the board. these additional comp onents between the phy and the magnetics complicate board layout. integrating the resistors has many advantages including component cost savings, better ict yield, board reliability improvements, board area savings, improved layout, and signal integrity improvements. m a g n e t i c s 10/100/1000 mbps ethernet mac sgmii (system interface) media types: -10base-t - 100base-tx - 1000base-t rj45 I347-AT4 rj45 rj45 rj45 10/100/1000 mbps ethernet mac 10/100/1000 mbps ethernet mac 10/100/1000 mbps ethernet mac m a g n e t i c s 10/100/1000 mb/s ethernet mac sgmii (system interface) media types: - 10base-t - 100base-tx - 1000base-t rj45 I347-AT4 rj45 10/100/1000 mb/s ethernet mac port 1 port 0
17 device functionality?I347-AT4 3.2.1 transmit side network interface 3.2.1.1 multi-mode tx digi tal-to-analog converter the I347-AT4 incorporates a multi-mode transmit dac to generate filtered 4d pam 5, mlt3, or manchester coded symbols. the tr ansmit dac performs signal wave shaping to reduce emi. the transmit dac is designed for very low parasitic loading capacitances to improve the return loss requ irement, which allows the use of low cost transformers. 3.2.1.2 slew rate control and waveshaping in 1000base-t mode, partial response filtering and slew rate control is used to minimize high frequency emi. in 100base-tx mode, slew rate control is used to minimize high frequency emi. in 10base -t mode, the output waveform is pre- equalized via a digital filter. 3.2.2 encoder 3.2.2.1 1000base-t in 1000base-t mode, the transmit data bytes are scrambled to 9-bit symbols and encoded into 4d pam 5 symbols. upon init ialization, the initial scrambling seed is determined by the phy address. this preven ts multiple the i347-a t4 from outputting the same sequence during idle, which helps to reduce emi. 3.2.2.2 100base-tx in 100base-tx mode, the transmit data st ream is 4b/5b encoded, serialized, and scrambled. 3.2.2.3 10base-t in 10base-t mode, the transmit data is serialized and converted to manchester encoding.
I347-AT4?device functionality 18 3.2.3 receive side network interface 3.2.3.1 analog-to-digital converter the I347-AT4 incorporates an advanced high speed adc on each receive channel with greater resolution than the adc used in th e reference model of the 802.3ab standard committee. higher resolution adc results in better snr, and therefore, lower error rates. proprietary architectures and design techniques result in high differential and integral linearity, high power supply noise rejection, and low metastability error rate. the adc samples the input signal at 125 mhz. 3.2.3.2 active hybrid the I347-AT4 employs a sophisticated on-chip hybrid to substantia lly reduce the near- end echo, which is the super-imposed transmit signal on the receive signal. the hybrid minimizes the echo to reduce the precision requirement of the digital echo canceller. the on-chip hybrid allows both the transmitter and receiver to use the same transformer for coupling to the twisted pair ca ble, which reduces the cost of the overall system. 3.2.3.3 echo canceller residual echo not removed by the hybrid and echo due to patch cord impedance mismatch, patch panel discontinuity, and variations in cable impedance along the twisted pair cable result in drastic snr degradation on the receive signal. the I347-AT4 employs a fully developed digital echo canceller to adjust for echo impairments from more than 100 meters of cable. the echo ca nceller is fully adaptive to compensate for the time varying nature of channel conditions. 3.2.3.4 next canceller the 1000base-t physical layer uses all 4 pairs of wires to transmit data to reduce the baud rate requirement to only 125 mhz. th is results in significant high frequency crosstalk between adjacent pairs of cable in the same bundle. the I347-AT4 employs 3 parallel next cancellers on each receive channel to cancel any high frequency crosstalk induced by the adjacent 3 transmitters. a fu lly adaptive digital filter is used to compensate for the time varying nature of channel conditions. 3.2.3.5 baseline wander canceller baseline wander is more problematic in the 1000base-t environment than in the traditional 100base-tx environment due to th e dc baseline shift in both the transmit and receive signals. the I347-AT4 employs an advanced baseline wander cancellation circuit to automatically compensate for this dc shift. it minimizes the effect of dc baseline shift on the overall error rate.
19 device functionality?I347-AT4 3.2.3.6 digital adaptive equalizer the digital adaptive equalizer removes inter- symbol interference at the receiver. the digital adaptive equalizer takes unequalized signals from adc output and uses a combination of feed forward equalizer (ffe) and decision feedback equalizer (dfe) for the best-optimized signal-to-noise (snr) ratio. 3.2.3.7 digital phase lock loop in 1000base-t mode, the slave transmitter mu st use the exact receive clock frequency it sees on the receive signal. any slight long-term frequency phase jitter (frequency drift) on the receive signal must be tracked and duplicated by the slave transmitter; otherwise, the receivers of both the slave and master physical layer devices have difficulty canceling the echo and next comp onents. in the I347-AT4, an advanced dpll is used to recover and track the clock timing information from the receive signal. this dpll has very low long-term phase jitter of its own, thereby maximizing the achievable snr. 3.2.3.8 link monitor the link monitor is responsible for determining if link is established with a link partner. in 10base-t mode, link monitor function is performed by detecting the presence of valid link pulses (nlps) on the mdip/n pins. in 100base-tx and 1000base-t modes, link is established by scrambled idles. if force link good register 16_0.10 is set high, the link is forced to be good and the link monitor is bypassed for 100base-tx an d 10base-t modes. in the 1000base-t mode, register 16_0.10 has no effect. 3.2.3.9 signal detection in 1000base-t mode, signal detection is based on whether the local receiver has acquired lock to the incoming data stream. in 100base-tx mode, the signal detection function is based on the receive signal energy detected on the mdip/n pins that is continuously qualified by the squelch detect circuit, and the local receiver acquiring lock. 3.2.4 decoder 3.2.4.1 1000base-t in 1000base-t mode, the receive idle stream is analyzed so that the scrambler seed, the skew among the 4 pairs, the pair swap order, and the polarity of the pairs can be accounted for. once calibrated, the 4d pam 5 symbols are converted to 9-bit symbols that are then descrambled into 8-bit data values. if the descrambler loses lock for any reason, the link is brought down and calibrati on is restarted after the completion of auto-negotiation.
I347-AT4?device functionality 20 3.2.4.2 100base-tx in 100base-tx mode, the receive data stream is recovered and converted to nrz. the nrz stream is descrambled and aligned to th e symbol boundaries. the aligned data is put in parallel and then 5b/4b decoded. the receiver does not attempt to decode the data stream unless the scrambler is locked. the descrambler ?locks? to the scrambler state after detecting a sufficient number of consecutive idle code-groups. once locked, the descrambler continuously monitors the data stream to make sure that it has not lost synchronization. the descrambler is always forced into the unlocked state when a link failure condition is detected, or when insufficient idle symbols are detected. 3.2.4.3 10base-t in 10base-t mode, the recovered 10base-t signal is decoded from manchester to nrz, and then aligned. the alignment is necessary to insure that the start of frame delimiter (sfd) is aligned to the nibble boundary. 3.2.5 electrical interface the input and output buffers are internally terminated to 50 impedance. the output swing can be adjusted by programming register 26_1.2:0. figure 7. cml i/os 50 ohm internal bias 1 s_inp 50 ohm internal bias s_inn cml inputs cml outputs 50 ohm internal bias 1 50 ohm i sink s_outp s_outn 1. internal bias is generated from the avddh s upply and is typically 1.4v.
21 device functionality?I347-AT4 3.2.6 sgmii speed and link when the sgmii mac interface is used, the interface is copper . the operational speed of the sgmii mac interface is determined according to ta b l e 9 media interface status and/or loopback mode. table 9. sgmii (mac interf ace) operational speed 3.2.7 sgmii trr blocking when the sgmii receives a packet with odd num ber of bytes, a single symbol of carrier extension will be passed on and transmitted onto 1000base-t. this carrier extension may cause problems with full-duplex macs that incorrectly handle the carrier extension symbols. when register 16_1.13 is set to 1, all carrier extend and carrier extend with error symbols received by th e sgmii will be converted to idle symbols when operating in full-duplex. carrier extend and carrier ex tend with error symbols will not be blocked when operating in half-duplex, or if register 16_1.13 is set to 0b. note that symbol errors will continue to be propagated regardless of the setting of register 16_1.13. this function is on by default as the sgmii re v 1.8 standard requires this function to be implemented. 3.3 loopback the I347-AT4 implements various different loopback paths. 3.3.1 system inte rface loopback the functionality, timing, and signal integrit y of the system interface can be tested by placing the I347-AT4 in system interface l oopback mode. this can be accomplished by setting register 0_0.14 = 1b, 0_1.14 = 1b, or 0_4.14 = 1b. in loopback mode, the data received from the mac is not transmitted out on the media interface. instead, the data is looped back and sent to the mac. during loopback, link will be lost and packets will not be received. if loopback is enabled while auto-negotia ting, flp auto-negotiation codes will be transmitted. if loopback is enabled in forc ed 10base-t mode, 10base-t idle link pulses will be transmitted on the copper side. if loopback is enabled in forced 100base-t mode, 100base-t idles will be transmitted on the copper side. the speed of the sgmii interface is determin ed by register 21_2.2:0 during loopback. 21_2.2:0 is 100b = 10 mb/s, 101b = 100 mb/s, 110b = 1000 mb/s. link status or media interface status sgmii (mac interface) speed no link determined by speed setting of 21_2.2:0 mac loopback determined by speed setting of 21_2.2:0
I347-AT4?device functionality 22 figure 8. mac interface loopback diagram - copper media interface 3.3.2 line loopback line loopback allows a link partner to send frames into the I347-AT4 to test the transmit and receive data path. frames from a link partner into the phy, before reaching the mac interface pins, are looped back and sent out on the line. they are also sent to the mac. the packets receiv ed from the mac are ignored during line loopback. refer to figure 9 . this allows the link partner to receive its own frames. before enabling the line loopback feature, th e phy must first establish link to another phy link partner. if auto-negotiation is enab led, both link partners should advertise the same speed and full-duplex. if auto-negotiati on is disabled, both link partners need to be forced to the same speed and full-duplex. once link is established, the line loopback mode can be enabled. register 21_2.14 = 1b enables the line loopback on the copper interface. pcs pma pmd system interface copper interface mac (sgmii) 0_0.14 = 1b
23 device functionality?I347-AT4 figure 9. copper line loopback data path 3.3.3 external loopback for production testing, an external loopback stub allows testing of the complete data path. for 10base-t and 100base-tx modes, the loopba ck test requires no register writes. for 1000base-t mode, register 18_6.3 must be set to 1b to enable the external loopback. all copper modes require an external loopback stub. the loopback stub consists of a plastic rj-45 header, connecting rj-45 pair 1, 2 to pair 3, 6 and connecting pair 4, 5 to pair 7, 8, as seen in figure 10 . figure 10. loopback stub (top view with tab up) pcs pma pmd system interface mac copper interface (sgmii) 21_2.14 = 1b 1 2 3 4 5 6 7 8
I347-AT4?device functionality 24 the external loopback test setup requires the presence of a mac that will originate the frames to be sent out through the phy. instead of a normal rj-45 cable, the loopback stubs allows the phy to self-link at 1000 mb/s. it also allows the actual external loopback. see figure 11 . the mac should see the same packets it sent, looped back to it. figure 11. test setup for 10/100/1000 mb/s modes using an external loopback stub 3.4 synchronizing fifo the I347-AT4 has a transmit and receive synchronizing fifo to reconcile frequency differences between the clocks of the ma c interface and the media side. the fifo depths can be increased in length to support longer frames. the I347-AT4 can handle jumbo frame sizes up to 16 kb with up to 100 ppm clock jitter. the deeper the fifo depth, the higher the latency is. 1 2 3 4 5 6 7 8 mag/rj-45 loopback stub mac i347-ata 5.0 ghz serdes 8/10 8/10 mux de-mux k28.5 to k28.1 swapper k28.1 to k28.5 swapper 27_4.14 port 0 port 1 port 2 port 3 port 0port 1port 2port 3 27_4.0 27_4.1 mux
25 device functionality?I347-AT4 for the I347-AT4, the status of the fifo can be interrogated as in ta b l e 1 0 . registers 19_2.3:2 are set depending on whether the copper transmit fifo inserted or deleted idle symbols. idles inserted or deleted will be flagged only if the inter packet gap is 24 bytes or less at the input of the fifo. insert ed or deleted idles are ignored if the inter- packet gap is greater than 24 bytes. the fifo status bits can generate interrupts by setting the corresponding bits in register 18_1, 18_2, and 18_4. table 10. I347-AT4 fifo status bits figure 12. fifo locations 3.5 resets in addition to the hardware reset pin (reset n) there are several software reset bits as listed in ta b l e 1 1 . register 27_4.15 is a software bit that emulates the hardware reset. the entire chip is reset as if the resetn pin is asserted. once triggered, registers are not accessible through the mdio until the chip reset completes. the copper circuit is reset pe r port via register 0_0.15. register 20_6.15 resets the mode control, port power management, and generator and checkers. all the reset registers previously described are self cleared. however, register 20_6.9 is not self clearing. when register 20_6.9 is se t to 1b, registers in banks 8, 9, 10 and 11 are not accessible. register function setting 19_2.7 copper transmit fifo over/underflow 1b = over/underflow error 0b = no fifo error 19_2.3 copper transmit fifo idle inserted 1b = idle inserted 0b = no idle inserted 19_2.2 copper transmit fifo idle deleted 1b = idle deleted 0b = no idle deleted copper sgmii 16_1.15:14 fifo fifo 16_2.15:14
I347-AT4?device functionality 26 table 11. reset control bits 3.6 power management the I347-AT4 supports several advanced power management modes that conserve power. 3.6.1 manual power down there are multiple power down control bits on chip and they are listed in ta b l e 1 2 . each power down control independently powers down its respective circuits. in general, it is not necessary to power down an unused inte rface. the phy automatically powers down any unused circuit. the automatic phy power management can be overridden by setting the power down control bits. these bits have priority over the phy power management in that the circuit cannot be powered up by power management when it?s associated power down bit is set to 1b. when a circuit is powered ba ck up by setting the bit to 0b, a software reset is also automatically sent to the corresponding circuit. note that register 0_0.11 and 16_0.2 are logically ored to form a power down control. table 12. power down control bits 3.6.2 mac interface power down in some applications, the mac interface must run continuously regardless of the state of the network interface. additional powe r is required to keep the mac interface running during low power states. if absolute minimal power consumption is required during network interface power down mode or in cable detect mode, then regi ster 16_2.3 or 16_1.3 should be set to 0b to enable the mac interface to power down. ta b l e 1 3 lists which bit controls the automati c mac interface powe r down, and the mac interface that is powered down. in general 16_2.3 is used when the network interface is copper. reset register register effect block 27_4.15 chip hardware reset. entire chip. 0_0.15 software reset for bank 0, 2, 3, 5, 7. copper - per port. 0_1.15 software reset for ba nk 1. sgmii - per port. 20_6.15 software reset for bank 6. generator/checker/mode (per port). 20_6.9 reserved reserved reset register register effect 0_0.11 copper power down. 16_0.2 copper power down.
27 device functionality?I347-AT4 table 13. automatic mac interface power down 3.6.3 copper detect mode the I347-AT4 can be placed in cable detect mode power down modes by selecting either of the two cable detect modes. both modes enable the phy to wake up on its own by detecting activity on the cat 5 cable. the status of the cable detect is reported in register 17_0.4 and the cable detect changes are reported in register 19_0.4. 3.6.3.1 cable detect (mode 1) cable detect mode (mode 1) is entered by setting register 16_0.9:8 to 10. in mode 1, only the signal detection circuitry and serial management interface are active. if the phy detects energy on the line, it starts to auto-negotiate sending flps for five seconds. if at the end of five se conds the auto-negotiation is not completed, then the phy stops sending flps and goes back to monitoring receive energy. if auto- negotiation completes, then the phy goes in to normal 10/100/1000 mb/s operation. if during normal operation the link is lost, the phy re-starts auto-negotiation. if no energy is detected after five seconds, the phy goes back to monitoring receive energy. 3.6.3.2 cable detect mode (mode 2) cable detect mode (mode 2) is entered by setting register 16_0.9:8 to 11. in mode 2, the phy sends out a single 10 mb/s normal link pulse (nlp) every one second. except for this difference, mode 2 is identical to mode 1 operation. if the i347- at4 is in mode 1, it cannot wake up a connected device; therefore, the connected device must be transmitting nlps, or either device must be woken up through register access. if the I347-AT4 is in mode 2, then it can wake a connected device. 3.6.3.3 normal 10/100/1000 mb/s operation normal 10/100/1000 mb/s operation can be en tered by turning off cable detect mode by setting register 16_0.9:8 to 0x0. register 20_6.2:0 mode mac interface power down control bit mac interface powered down 001 sgmii (system) to copper 16_2.3 sgmii
I347-AT4?device functionality 28 3.6.3.4 power state up on exiting power down when the phy exits power down (register 0_0.11 or 16_0.2) the active state depends on whether the cable detect mode function is enabled (register 16_0.9:8 = 1x). if the cable detect mode function is enabled, th e phy transitions to the cable detect mode state first and wakes up only if there is a signal on the wire. table 14. power state after exiting power down 3.6.4 low power modes three low power modes are supported in the I347-AT4. ? ieee 22.2.4.1.5 compliant power down ? cable detect mode (mode 1) ? cable detect mode (mode 2) ieee 22.2.4.1.5 power down compliance enables the phy to be placed in a low-power consumption state by register control. cable detect mode (mode 1) enables the I347-AT4 to wake up when energy is detected on the wire. cable detect mode (mode 2) is identical to mode 1 with the additional capability to wake up a link partner. in mode 2, the 10base-t link pulses are sent once every second while listening for energy on the line. details of each mode follows. 3.6.5 low power operating modes 3.6.5.1 ieee power down mode the standard ieee power down mode is ente red by setting register 0_0.11. in this mode, the phy does not respond to any sgm ii signals except the mdc/mdio. it also does not respond to any activity on the copper media. in this power down mode, the phy cannot wake up on its own by detecting activity on the media. it can only wake up by setting registers 0_0.11 and 16_0.2 = 0b. register 0_0.11 register 16_0.2 register 16_0.9:8 behavior 1b x xx power down. x1 bx xp o w e r d o w n . 1b to 0b 0b 00b transition to power up. 0b 1b to 0b 00b transition to power up. 1b to 0b 0b 1x transition to cable detect mode state. 0b 1b to 0b 1x transition to cable detect mode state.
29 device functionality?I347-AT4 upon deassertion of hardware reset, register 0_0.11 and 16_0.2 are set to 1b to default the I347-AT4 to a power down state. register 0_0.11 and 16_0.2 are logically ored to form a power down control. 3.6.5.2 cable detect power down modes the I347-AT4 can be placed in cable detect power down modes by selecting either of the two cable detect modes. both modes en able the phy to wake up on its own by detecting activity on the cat 5 cable. the cable detect modes only apply to the copper media. the cable detect modes do not work while copper auto select ( section 3.4 ) is enabled. the status of the cable detect is reported in register 17_0.4 and the cable detect changes are reported in register 19_0.4. 3.6.6 sgmii effect on low power modes in some applications, sgmii must run conti nuously regardless of the state of the phy. additional power is required to keep this sgmii interface running during low power states. if absolute minimal power consumption is required during the ieee power down mode or the cable detect modes, then register 16_2. 3 should be set to 0b to enable sgmii to power down. note that for these settings to take effect a software reset must be issued. 3.7 auto-negotiation the I347-AT4 supports 10/100/1000base-t copper auto-negotiation (ieee 802.3 clauses 28 and 40). auto-negotiation provides a mechanism for transferring information from the local station to the link partner to establish sp eed, duplex, and master/slave preference during a link session. auto-negotiation is initiated upon any of the following conditions: ?power-up reset ? hardware reset ? software reset (register 0_0.15, 0_1.15, or 0_4.15) ? restart auto-negotiation (register 0_0.9, 0_1.9, 0_4.9) ? transition from power down to power up (register 0.0_0.11, 0_1.11, or 0_4.11) ? the link goes down the following sections describe each of the auto-negotiation modes in detail.
I347-AT4?device functionality 30 3.7.1 10/100/1000base-t auto-negotiation the 10/100/1000base-t auto-negotiation is based on clause 28 and 40 of the ieee802.3 specification. it is used to negotiate speed, duplex, and flow control over cat5 utp cable. once auto-negotiation is initiated, the I347-AT4 determines whether or not the remote device has auto-negotiation capability. if so, the I347-AT4 and the remote device negotiate the speed and duplex with which to operate. if the remote device does not have auto-negotiation capability, the I347-AT4 uses the parallel detect function to determine the speed of the remote device for 100base-tx and 10base-t modes. if link is established based on the parallel detect function, then it is required to establish link at half-duplex mode only. refer to ieee 802.3 clauses 28 and 40 for a full description of auto-negotiation. after hardware reset, 10/100/1000base-t auto-negotiation can be enabled and disabled via register 0_0.12. auto mdi/mdix and auto-negotiation can be disabled and enabled independently. when auto-negotiati on is disabled, the speed and duplex can be set via registers 0_0.13, 0_0.6, and 0_0.8, respectively. when auto-negotiation is enabled the abilities that are advertised can be changed via registers 4_0 and 9_0. changes to registers 0_0.12, 0_0.13, 0_0.6 and 0_0.8 do not take effect unless one of the following takes place: ? software reset (registers 0_0.15) ? restart auto-negotiation (register 0_0.9) ? transition from power down to power up (register 0_0.11) ? the copper link goes down to enable or disable auto-negotiation, register 0_0.12 should be changed simultaneously with either register 0_0.15 or 0_0.9. for example, to disable auto- negotiation and force 10base-t half-duplex mode, register 0_0 should be written with 0x8000. registers 4_0 and 9_0 are internally latche d once every time the auto-negotiation enters the ability detect state in the arbitration state machine. hence, a write into register 4_0 or 9_0 has no effect once the I347-AT4 begins to transmit fast link pulses (flps).this guarantees that sequences of flps transmitted are consistent with one another. register 7_0 is treated in a similar way as registers 4_0 and 9_0 during additional next page exchanges. if 1000base-t mode is advertised, then the I347-AT4 automatically sends the appropriate next pages to advertise the capa bility and negotiate master/slave mode of operation. if the user does not wish to tran smit additional next pages, then the next page bit (register 4_0.15) can be set to zero, and the user needs to take no further action. if next pages in addition to the ones re quired for 1000base-t are needed, then the user can set register 4_0.15 to one, and send and receive additional next pages via registers 7_0and 8_0, respectively. the I347-AT4 stores the previous results from register 8 in internal registers, so that new next pages can overwrite register 8_0. note that 1000base-t next page exchanges are automatically handled by the I347-AT4 without user intervention, regardless of whether or not additional next pages are sent.
31 device functionality?I347-AT4 once the I347-AT4 completes auto-negotia tion, it updates the various status in registers 1_0, 5_0, 6_0, and 10_0. speed, du plex, page received, and auto-negotiation completed status are also available in registers 17_0 and 19_0. see section 3 for more details. 3.8 downshift feature without the downshift feature enabled, co nnecting between two gigabit link partners requires a four-pair rj-45 cable to establish 10, 100, or 1000 mb/s link. however, there are existing cables that have only two-pair s, which are used to connect 10 mb/s and 100 mb/s ethernet phys. with the availability of only pairs 1, 2 and 3, 6, gigabit link partners can auto-negotiation to 1000 mb/s, but fail to link. the gigabit phy repeatedly goes through the auto-negotiation but fails 1000 mb/s link and never tries to link at 10 mb/s or 100 mb/s. with the downshift feature enabled, the i347 -at4 is able to auto-negotiation with another gigabit link partner using cable pairs 1, 2 and 3, 6 to downshift and link at 10 mb/s or 100 mb/s, whichever is the next highest advertised speed common between the two gigabit phys. in the case of a three pair cable (additional pair 4, 5 or 7, 8 - but not both) the same downshift function for two-pair cables applies. by default, the downshift feature is turned off. refer to register 16_0.14:11, which describes how to enable this feature and how to control the downshift algorithm parameters. to enable the downshift feature, the following registers must be set: ? register 16_0.11 = 1b ? enables downshift ? register 16_0.14:12 ? sets the number of link attempts before downshifting 3.9 fast 1000base-t li nk down indication per the ieee 802.3 clause 40 standard, a 1000base-t phy is required to wait 750 ms or more to report that link is down after detecting a problem with the link. for metro ethernet applications, a fast failover in 50 ms is specified, which cannot be met if the phy follows the 750 ms wait time. this dela y can be reduced by intentionally violating the ieee standard by setting register 26_0.9 to 1b. the delay at which link down is reported can be selected by setting register 26_0.11:10 as follows: ? 00b = 0 ms ? 01b = 10 2 ms ? 10b = 20 2ms ? 11b = 40 2ms
I347-AT4?device functionality 32 3.10 cable tester the I347-AT4 uses time domain reflectometry (tdr) to determine the quality of the cables, shorts, cable impedance mismatch, bad connectors, termination mismatch, and bad magnetics. the I347-AT4 transmits a si gnal of known amplitude (+1v) down each of the four pairs of an attached cable. it conducts the cable diagnostic test on each pair, testing the mdi_0_0p/n, mdi_0_1p/n, mdi_0_2p/n, and mdi_0_3p/n pairs sequentially. the transmitted signal continues down the cable until it reflects off of a cable imperfection. cable tester has four modes of operation that is programmable via register 23_5.7:6. the first mode returns the peak with the maximum amplitude that is above a certain threshold. the second mode returns the firs t peak detected that is above a certain threshold. the third mode measures the syst ematic offset at the receiver. the fourth mode measures the amplitude seen at a certain specified distance. the cable tester is initiated by setting register 23_5.15 to 1b. this bit self clears when the test completes. register 23_5.14 is set to a 1b indicating that the tdr results in the registers are valid. each point in the cable testerreflected waveform is sampled multiple times and averaged. the number of samples to take is programmable via register 23_5.10:8. each time the cable tester is enable, the re sults seen on the four receive channels are reported in registers 16_5, 17_5, 18_5, and 19_5. register 23_5.13:11 selects which channel transmits the test pulse. when register 23_5.13:11 is set to 000b the same channel reflection is recorded. in other words, channel 0 transmits a pulse and the reflection seen on channel 0 receiver is reported. channel 1 transmits a pulse and the reflection seen on channel 1 receiver is reported. the same for channel 2 and channel 3. when register 23_5.13:11 is set to 100b all four receive channels report the reflection seen by a pulse transmitted by channel 0. when register 23_5.13:11 is set to 101b all four receive channels report the reflection seen by a pulse transmitted by channel 1. when register 23_5.13:11 is set to 110b all four receive channels report the reflection seen by a pulse transmitted by channel 2. when register 23_5.13:11 is set to 111b all four receive channels report the reflection seen by a pulse transmitted by channel 3. as a result, if only the reflection seen on the same channel is desired the cable tester should be run with 23_5.13:11 = 000b. if all same channel and cross channel combinations are desired then the cable test er must be run four times with 23_5.13:11 set to 100b, 101b, 110b, and 111b for the four runs. registers 16_5, 17_5, 18_5, and 19_5 should be read and stored between each run.
33 device functionality?I347-AT4 3.10.1 maximum peak when register 23_5.7:6 is set to 00b, the maximum peak above a certain threshold is reported. pulses are sent out and recorded according to the setting of register 25_5.13:11. there are 10 threshold settings for same channel reflections and are specified by registers 26_5.6:0, 26_5.14:8, 27_5.6:0, 27_5.14:8, and 28_5.6:0 for positive reflections and 26_7.6:0, 26_7.14:8, 27_7.6:0, 27_7.14:8, and 28_7.6:0 for negative reflections. these settings correspond to the amplitude threshold the reflected signal has to exceed before it is counted. any reflected signal below this threshold level is ignored. the threshold settings are based on cable length with the breakpoints at 10 m, 50 m, 110 m, and 140 m. there are four threshold settings for cross- channel specified by registers 25_5.6:0 and 25_5.14:8 for positive reflections and 25_7.6:0 and 25_7.14:8 for negative reflections. the threshold settings are based on cable length with the breakpoints at 10 m. the default values are targeted to 85 to 115 . however these threshold settings should be calibrated for the desired impedance setting on the target system. the results are stored in registers 16_5, 17_5, 18_5, and 19_5. bits 7:0 report the distance of the peak. the distance can be converted to using the trend line in figure 13 . bits 14:8 report the reflected amplit ude. bit 15 reports whether the reflected amplitude was positive or negative. when bits 15:8 return a value of 0x80, it means there was no peak detected above the thresh old. if bits 15:8 return a value of 0x00 then the test failed. register 28_5.7 controls the exact distance that is reported. when set to 0b the distance where the amplitude falls to 50% of the peak amplitude is reported. when set to 1b the distance where the peak amplitude ac tually occurs is reported. in either case, the magnitude of the maximum amplit ude is reported in bits 14:8. in the maximum peak mode, register 24_5.7:0 is used to set the starting distance of the sweep. normally this value should be set to 0b. if this value is set to a non-zero value, any reflection below the starting distance is ignored. note that 24_5.8 is ignored. note that the maximum peak only measures up to about 200 meters of cable.
I347-AT4?device functionality 34 figure 13. cable fault distance trend line 3.10.2 first peak when register 23_5.7:6 is set to 01b, the first peak above a certain threshold is reported. the first peak operates in exactly the same way as the maximum peak except that there has to be some qualification as to what constitutes a peak since the first peak is not necessarily the maximum peak. the first peak is defined as the maximum amplitude seen before the reflected amplit ude drops by some value below this peak. this hysteresis value is defined by register 23_5.5:0. for example, in figure 14 , if pa is greater than the hysteresis value in 23_5.5:0 and va is above the threshold value, then va and da are reported since it is the first peak that is above the threshold. if pa is less than the hysteresis value in 23_5.5:0, then va and da are not reported as the first peak. vb and db will be reported as the first peak if pb is greater than the hysteresis value in 23_5.5:0 and vb is above the threshold value. if pa is greater than the hysteresis value in 23_5.5:0 but va is below the threshold value then va and da are not reported as the first peak. vb and db will be reported as the first peak if pb is greate r than the hysteresis value in 23_5.5:0 and vb is above the threshold value. register 28_5.7 controls the exact distance that is reported. when set to 0b the distance where the amplitude falls below the peak amplitude minus the hysteresis level as defined in register 23_5.5:0 is reported. when set to 1b the distance where the peak amplitude actually occurs is reported. in either case, the magnitude of the maximum amplitude of the first peak is reported in bits 14:8. in the first peak mode register 24_5.7:0 is used to set the starting distance of the sweep. normally, this value should be set to 0b. if this value is set to a non-zero value, any reflection below the starting distance is ignored. this may be useful to ignore reflections at the transformer that are report ed as the first peak. note that 24_5.8 is ignored. 0 50 100 150 200 0 50 100 150 200 250 register 16_5, 17_5, 18_5, and 19_5 (decimal) length (meter)
35 device functionality?I347-AT4 note that the maximum peak only measures up to about 200 meters of cable. figure 14. first peak example 3.10.3 offset the offset reports the offset seen at the receiver. this is a debug mode. bits 7:0 of registers 16_5, 17_5, 18_5, and 19_5 have no meaning. when bits 15:8 return a value of 0x80 it means there is zero offset. if bi t 15:8 returns a value of 0x00 then the test failed. note that in the maximum peak, first peak , and sample point modes, the systematic offset is automatically subtracted from the results. 3.10.4 sample point when register 20_8.7:6 is set to 11b, the amplitude of the reflected pulse at a particular distance on the cable is reported. unlike the maximum peak and first peak modes which only measures up to about 200 meters of cable, the sample point mode can measure up to 400 meters of cable. the sample point returns the amplitude of th e reflected pulse at a particular distance on the cable. the distance is set by register 24_5.8:0. the threshold registers 25_5, 26_5, 27_5, 28_5.6:0, 25_7, 26_7, 27_7, and 28_7.6:0 are ignored. bits 7:0 of registers 16_5, 17_5, 18_5, and 19_5 return the same value as 24_5.7:0. note that register 24_5.8 is not returned. bits 14:8 return the amplitude, and bit 15 the sign of the amplitude. if the test failed bits 15:8 returns 0x00000000 (zero amplitude will always return as 0x10000000). by programming register 24_5.8:0 from 0x00 0 to 0x1ff and running the sample point test at each distance it is possible to re construct the reflected amplitude. note that since the threshold is ignored, it is possible that some small reflections in the same channel measurements will be reported at short cable lengths when there are none. this is because the analog hybrid does not 100% cancel out the transmitted signal. pa pb da db va vb
I347-AT4?device functionality 36 3.10.5 pulse amplitude and pulse width the transmitted pulse amplitude and pulse width can be adjusted via registers 28_5.9:8 and 28_5.11:10, respectively. they sh ould normally be set to full amplitude and full pulse width. 3.10.6 drop link when register 28_5.12 is set to 0b the circuit waits 1.5 seconds to break the link before starting cable tester. when set to 1b this delay is bypassed. 3.10.7 cable test with link up the following status requires the phy to link up with a link partner. ? register 20_5 reports the pair skew of each pair of wires relative to each other. ? register 21_5.3:0 reports the polarity of each pair of wires. ? register 21_5.6:5 reports the crossover status. ? register 20_5 and 21_5 are not valid unless register 21_5.6 is set to 1b. 3.11 data terminal eq uipment (dte) detect the I347-AT4 supports the dte power function. the dte power function is used to detect if a link partner requires power supplied by the I347-AT4. the dte power function is enabled by writing to register 26_0.8. when dte is enabled, the I347-AT4 first monitors for any activity transmitted by the link partner. if the link partner is active, then the link partner has power and power from the poe pse device is not required. if there is no activity coming from the link partner, dte power engages, and special pulses are sent to detect if th e link partner requires dte power. if the link partner has a low pass filter (or similar fixture) installed, the link partner is detected as requiring dte power. the dte power status register (register 17_0.2) immediately comes up as soon as the link partner is detected as a device requiring dte power. register 19_0.2 is a stray bit that reports the dte power status has changed states. if a link partner that requires dte power is unplugged, the dte power status (register 17_0.2) drops after a user-controlled delay (default is 20 seconds - register 26_0.7:4) to avoid dte power status register drop during the link partner powering up (for most applications), since the low pass filter (or similar fixture) is removed during power up. if dte power status drop is desired to be reported immediately, write register 26_0.7:4 to 0x0000. a detailed description of the register bits used for dte power detection for the i347- at4 are listed in ta b l e 1 5 .
37 device functionality?I347-AT4 table 15. registers for dte power 3.12 crc error counter and frame counter the crc counter and frame counters, normally found in macs, are available in the I347-AT4. the error counter and frame counter features are enabled through register writes and each counter is stored in eight register bits. register 18_6.2:0 controls which path the crc checker and packet counter is counting. if register 18_6.2:0 is set to 010b then the copper receive path is checked. 3.12.1 enabling the crc error counter and frame counter to enable both counters to count, set 18_6.2:0 to a non-zero value. to disable and clear both counters, set 18_6.2:0 to 000b. to read the crc counter and frame counter, read register 17_6. 17_6.15:8 (frame count is stored in these bits). 17_6.7:0 (crc error count is stored in these bits). the crc counter and frame counter do not clear on a read command. to clear the counters, disable/reset the crc checker by writing reg 18_6.2:0 = 000b. register description 26_0.8 - enable power over ethernet detection 1b = enable dte detect. 0b = disable dte detect. a soft reset is required to enable this feature. hardware reset: 0b. software reset: update. 17_0.2 - power over ethernet detection status 1b = need power. 0b = do not need power. hardware reset: 0b. software reset: 0b. 19_0.2 - power over ethernet detection state changed 1b = changed. 0b = no change. hardware reset: 0b. software reset: 0b. 26_0.7:4 - dte detect status drop once the phy no longer detects that the link partner filter, the phy waits a period of time before clearing the power over ethernet detection status bit (17_0.2). the wait time is 5 seconds multiplied by the value of these bits. example: (5 * 0x4 = 20 seconds). default at hardware reset: 0x4. at software reset: retain.
I347-AT4?device functionality 38 3.13 packet generator the I347-AT4 contains a very simple packet generator. section 4.1.50 lists the i347- at4 packet generator register details. the packet generator is enabled when: register 16_6.7:6 controls which path the packet generator is connected to. if register 16_6.7:6 is set to 01b then the input into the sgmii is ignored and the packet is generated onto the copper transmit path. if register 16_6.7:6 is set to 10b then the copper receiver is ignored and the packet is generated onto the sgmii output path. if register 16_6.7:6 is set to 11b then the copper receiver or the sgmii is ignored. once enabled, a fixed length packet of 64 - or 1518- byte frame (including crc) is transmitted separated by 12 byte s of ipg. the preamble length is 8 bytes. the payload of the frame is either a fixed 5a, a5, 5a, a5 pattern or a pseudo random pattern. a correct ieee crc is appended to the end of the frame. an error packet can also be generated. the registers are as follows: ? 16_6.7:6 ? packet generation enable. 00b = normal operation, else = enable internal packet generator ? 16_6.2 ? payload type. ? 0b = pseudo random, 1b = fixed 5a, a5, 5a, a5,... ? 16_6.1 ? packet length. ? 0b = 64 bytes, 1b = 1518 bytes. ? 16_6.0 ? error packet ? 0b = good crc, 1b = symbol error and corrupt crc. ? 16_6.15:8 ? packet burst size. ? 0x00 = continuous, 0x01 to 0xff = burst 1 to 255 packets. if register 16_6.15:8 is set to a non-zero value, then register 16_6.7:6 self clears once the required number of packets are generated. note that if register 16_6.7:6 is manually set to 0b while packets are still bu rsting, the bursting ceases immediately once the current active packet finishes transmitting. the value in register 16_6.15:8 should not be changed while 16_6.7:6 is set to a non-zero value. 3.14 rx_er byte capture each time there is an rx_er in the internal gmii interface the phy captures four bytes before rx_er is asserted. once the bytes preceding the rx_er assertion are captured into the registers, they are not over written by new errors and they are only cleared after the registers are read. there is one set of rx_er capture registers. it captures the receive path of the copper path. these capture registers are always running. the copper path is accessed via register 20_2. the following description applies to the copper path.
39 device functionality?I347-AT4 once an error event is captured, register 20_2.15 is set to 1b indicating that the capture data is valid. no further errors are captured until all captured registers are read. register 20_2.13:12 is set to 00b. register 20_2.9:0 outputs the byte that is the earliest received. once register 20_2 is read register 20_2.13:12 increments and register 20_2.9.0 is updated with the next earliest byte. the register is incremented and byte updated until the fourth read occurs . after the fourth read to register 20_2 completes, register 20_2.15 is set to 0b and the error capturing resumes four rx_clk cycles after the final read completes. the 4 rx_clk cycle delay is required to insure that the register has four valid bytes loaded prior to being frozen. note that a side effect of doing this is the rx_er might be high in the captured bytes. table 16. error byte capture 3.15 mdi/mdix crossover the I347-AT4 automatically determines whethe r or not it needs to cross over between pairs as listed in ta b l e 1 7 so that an external crossover cable is not required. if the I347-AT4 interoperates with a device that cannot automatically correct for crossover, the I347-AT4 makes the necessary adjustment prior to commencing auto-negotiation. if the I347-AT4 interoperate s with a device that implements mdi/mdix crossover, a random algorithm as described in ieee 802.3 clause 40.4.4 determines which device performs the crossover. when the I347-AT4 interoperates with legacy 10base-t devices that do not implement auto-negotiation, the I347-AT4 follows the same algorithm as previously described since link pulses are present. however, wh en interoperating with legacy 100base-tx devices that do not implement auto-negotiation (such as, link pulses are not present), the I347-AT4 uses signal detect to determine whether or not to crossover. the auto mdi/mdix crossover function can be disabled via register 16_0.6:5. the pin mapping in mdi and mdix modes is listed in ta b l e 1 7 . register function setting 20_2.15 capture data valid 1b = bits 14:0 valid. 0b = bits 14:0 invalid. 20_2.13:12 byte number 00b = 4 bytes before rx_er asserted. 01b = 3 bytes before rx_er asserted. 10b = 2 bytes before rx_er asserted. 11b = 1 byte before rx_er asserted. the byte number increments after every read when register 20_2.15 is set to 1b. 20_2.9 rx_er rx error. normally this bit is low since th e capture is triggered by rx_er being high. however, it is possible to see an rx_er high when the capture is re-enabled after reading the fourth byte and there happens to be a long sequence of rx_er when the capture restarts. 20_2.8 rx_dv rx data valid. 20_2.7:0 rxd[7:0] rx data.
I347-AT4?device functionality 40 table 17. media dependent interface pin mapping note: ta b l e 1 7 assumes no crossover on pcb. the mdi/mdix status is indicated by register 17_0.6. this bit indicates whether the receive pairs (3, 6) and (1, 2) are crossed over. in 1000base-t operation, the I347-AT4 can correct for crossover between pairs (4, 5) and (7, 8) as listed in ta b l e 1 7 . however, this is not indicated by register 17_0.6. if 1000base-t link is established, pairs (1, 2) and (3, 6) crossover is reported in register 21_5.4, and pairs (4, 5) and (7, 8) crossover is reported in register 21_5.5. 3.16 unidirectional transmit ieee 802.3ah requires oam support with unidirectional transmit capability. unidirectional transmit enables a phy to transmit data when the phy does not have link due to potential issues on the receive path. 802.3ah formally requires two bits for this capability. register 0.5 enables this capability, and 1.7 advertises this ability. this ability only applies to 100base-tx or 1000base-x. it doesn?t apply to 1000base-t since 1000base-t requires master/slave relationship and training with both link partners participating, which requires that link exists for any data transmit. the I347-AT4 supports transmits of packets when there is no link by using register bit 16_0.10 = 1b ( force copper link good ). this is not the official bit specified by the 802.3ah but serves the same function. 3.17 polarity correction the I347-AT4 automatically corrects polarity errors on the receive pairs in 1000base-t and 10base-t modes. in 100base-tx mo de, the polarity does not matter. in 1000base-t mode, receive polarity errors are automatically corrected based on the sequence of idle symbols. once the descrambler is locked, the polarity is also locked on all pairs. the polarity becomes unlocked only when the receiver loses lock. in 10base-t mode, polarity errors are corre cted based on the detection of validly spaced link pulses. the detection begins during the mdi crossover detection phase and locks when the 10base-t link is up. the pola rity becomes unlocked when link is down. the polarity correction status is indicated by register 17_0.1. this bit indicates whether the receive pair (3, 6) is polarity reversed in mdi mode of operation. in mdix mode of operation, the receive pair is (1, 2) and register 17_0.1 indicates whether this pair is polarity reversed. although all pairs are corrected for receive polarity reversal, register 17_0.1 only indicates polarity reversal on the pairs described above. pin mdi mdix 1000base-t 100base-tx 10base-t 1000base-t 100base-tx 10base-t mdip/n[0] bi_da tx tx bi_db rx rx mdip/n[1] bi_db rx rx bi_da tx tx mdip/n[2] bi_dc unused unused bi_dd unused unused mdip/n[3] bi_dd unused unused bi_dc unused unused
41 device functionality?I347-AT4 if 1000base-t link is established register 21_5.3:0 reports the polarity on all four pairs. polarity correction can be disabled by register write 16_0.1 = 1b. polarity is then forced to normal 10base-t mode. 3.18 flp exchange comp lete with no link sometimes when link does not come up, it is difficult to determine whether the failure is due to the auto-negotiation fast link pulse (flp) not completing or from the 10/100/ 1000base-t link not being able to come up. register 19_0.3 is a sticky bit that gets set to 1b each time the flp exchange completes but the link cannot be established for some reason. once the bit is set, it is cleared only by reading the register. this bit is not set if the flp exchange does not complete, or if link is established. 3.18.0.1 compound led modes compound led modes are defined in ta b l e 1 8 . table 18. compound led status 3.18.0.2 speed blink when 16_3.3:0 is set to 0010b the led[0] pin takes on the following behavior. led[0] outputs the sequence listed in ta b l e 1 9 depending on the status of the link. the sequence consists of eight segments. if a 1000 mb/s link is established the led[0] outputs 3 pulses, 100 mb/s 2 pulses, 10 mb/s 1 pulse, and no link 0 pulses. the sequence repeats over and over again indefinitely. the odd numbered segment pulse duration is specified in 18_3.1:0. the even numbered pulse duration is specified in 18_3.3:2 ( ta b l e 2 0 ). table 19. speed blinking sequence compound mode description activity transmit activity or receive activity. copper link 10base-t link or 100base-tx link or 1000base-t link. link copper link.
I347-AT4?device functionality 42 table 20. speed blink 3.18.0.3 manual override when 19_3.7:6, 19_3.3:2,16_3.15:14, 16_3.11:10, 16_3.7:6, and 16_3.3:2 are set to 10b the led[5:0] are manually forced. registers 19_3.5:4, 19_3.1:0,16_3.13:12, 16_3.9:8, 16_3.5:4, and 16_3.1:0 then select whether the leds are to be on, off, hi-z, or blink. if bi-color leds are used, the manual overri de selects only one of the two colors. in order to get the third color by mixing, mode 1 and mode 2 should be used ( section 3.18.0.4 ). 3.18.0.4 mode 1, mode 2, mode 3, mode 4 mode 1 to 4 are dual led modes. these are used to mix a third color using bi-color leds. when 19_3.3:0,16_3.11:8 or 16_3.3:0 is set to 11xxb then one of the 4 modes are enabled. mode 1 ? solid mixed color. mode 2 ? blinking mixed color. segment 10 mb/s 100 mb/s 1000 mb/s no link duration 1 on on on off 18_3.1:0 2 off off off off 18_3.3:2 3 off on on off 18_3.1:0 4 off off off off 18_3.3:2 5 off off on off 18_3.1:0 6 off off off off 18_3.3:2 7 off off off off 18_3.1:0 8 off off off off 18_3.3:2 register pin definition 18_3.3:2 pulse period for even segments 00b = 84 ms. 01b = 170 ms. 10b = 340 ms. 11b = 670 ms. 18_3.1:0 pulse period for odd segments 00b = 84 ms. 01b = 170 ms. 10b = 340 ms. 11b = 670 ms.
43 device functionality?I347-AT4 mode 3 ? behavior according to ta b l e 2 1 . mode 4 ? behavior according to ta b l e 2 2 . note: mode 4 is the same as mode 3 except the 10 mb/s and 100 mb/s are reversed. table 21. mode 3 behavior table 22. mode 4 behavior 3.18.1 behavior in various low power states when the phy is in software reset, powered down, or the cable detect state, the leds are set to the inactive state in order to save power unless overridden by the designer. if the led[x] control (registers 16_3.11:8, 16_3.7:4, and 16_3.3:0 is set to 10xxb (forced mode) then the leds are forced regardless of the power state. this enables designers to have direct control over the leds. note that the led does not blink when the phy is in low power state. if the led[x] control is not set to 10xxb, th en the leds are forced off when the phy is in the software reset, power down state or in the cable detect state. the off value for led[x] is defined by the setting in registers 17_3.7:6, 17_3.5:4, 17_3.3:2, 17_3.1:0, 19_3.11:10, and 19_3.9:8. when the phy is in the powered up state and not in the cable detect state, the led[x] operates normally. status led[5] led[3] led[1] led[4] led[2] led[0] 1000 mb/s link - no activity off solid on 1000 mb/s link - activity off blink 100 mb/s link - no activity solid mix solid mix 100 mb/s link - activity blink mix blink mix 10 mb/s link - no activity solid on off 10 mb/s link - activity blink off no link off off status led[5] led[3] led[1] led[4] led[2] led[0] 1000 mb/s link - no activity off solid on 1000 mb/s link - activity off blink 100 mb/s link - no activity solid on off 100 mb/s link - activity blink off 10 mb/s link - no activity solid mix solid mix 10 mb/s link - activity blink mix blink mix no link off off
I347-AT4?device functionality 44 3.18.2 serial led when the clk_sel[1:0] is set to 10b at the de-assertion of hardware reset and the ptp_en configuration bit is set to 1b, the se rial led mode is enabled. all regular led functions are disabled and registers 16_3, 17_3, 18_3, and 19_3 are ignored. in the serial led mode the data is clocked through a shift register and the shifted values are output on the 16 led pins when strobed. config[1] is used as the data input. config[2] is used as the clock. clk_sel[0] is used as the strobe. note that this pin must be set to 0b at the de- assertion of hardware reset to enable the serial led mode. in addition to the above four pins register 27_4.9 is used to control whether all 16 leds are tri-stated or not. 0b = tristate 1b = output (hardware default) register 27_4.11:10 determines how many leds per port are in the shift chain. in all cases, p0_led[0] is the last bit to be shifte d in. (p3_led[3] is the fi rst bit to be shifted in if 27_4.11:10 = 11). 00b = shift through p0_led[0], p 1_led[0], p2_led [0], p3_led[0]. 01b = shift through p0_led[0], p0_led[1 ], p1_led[0], p1_led[1], p2_led[0], p2_led[1], p3_led [0], p3_led[1]. 10b = shift through p0_led[0], p0_led[1 ], p0_led[2], p1_led[0], p1_led[1], p1_led[2], p2_led[0], p2_l ed[1], p2_led[2], p3_led[0], p3_l ed[1], p3_led[2]. 11b = shift through p0_led[0], p0_led[1 ], p0_led[2], p0_led[3], p1_led[0], p1_led[1], p1_led[2], p1_l ed[3], p2_led[0], p2_led[1], p2_led [2], p2_led[3], p3_led[0], p3_led[1], p3_led[2], p3_l ed[3]. (hardware default). register 27_4.13:12 determines at what poin t in the shift register chain should be output to rclk. 00b = output after port 0. 01b = output after port 1. 10b = output after port 2. 1b1 = output after port 3. (hardware default) the initial value of the shift registers and the led outputs are that led[1] and led[3] output 0 and led[0] and led[2] output 1 for all ports.
45 device functionality?I347-AT4 figure 15. serial led 3.19 ieee 1149.1 and 1149.6 controller the ieee 1149.1 standard defines a test access port and boundary-scan architecture for digital integrated circuits and for the digital portions of mixed analog/digital integrated circuits. the ieee 1149.6 standard defines a test access port and boundary- scan architecture for ac coupled signals. this standard provides a solution for testin g assembled printed circuit boards and other products based on highly complex digital integrated circuits and high-density surface- mounting assembly techniques. the I347-AT4 implements the instructions listed in ta b l e 2 3 . upon reset, id_code instruction is selected. the prog_hyst is a proprietary command used to adjust the test receiver hysteresis threshold. the instruction opcodes are shown in ta b l e 2 3 . p0_led[0] p0_led[1] p0_led[2] p0_led[3] mux 01 23 p1_led[0] p1_led[1] p1_led[2] p1_led[3] mux 01 23 p2_led[0] p2_led[1] p2_led[2] p2_led[3] mux 01 23 p3_led[0] p3_led[1] p3_led[2] p3_led[3] mux 01 23 clk_sel[0] config[2] rclk p0_out p1_out p2_out p3_out mux 32 10 p3_out p1_out p2_out p0_out config[1] register 27_4.11:10 register 27_4.13:12
I347-AT4?device functionality 46 table 23. tap controller opcodes the I347-AT4 reserves five pins called the test access port (tap) to provide test access: test mode select input (tms), test clock input (tck), test data input (tdi), and test data output (tdo), and test re set input (trstn). to ensure race-free operation all input and output data is synchronous with the test clock (tck). tap input signals (tms and tdi) are clocked into the test logic on the rising edge of tck, while output signal (tdo) is clocked on the fallin g edge. for additional details refer to the ieee 1149.1 boundary scan architecture document. 3.19.1 bypass instruction the bypass instruction uses the bypass register. this register contains a single shift- register stage and is used to provide a minimum length serial path between the tdi and tdo pins of the I347-AT4 when test operation is not required. this arrangement allows rapid movement of test data to and from other testable devices in the system. 3.19.2 sample/preload instruction the sample/preload instruction enables scanning of the boundary-scan register without causing interference to the normal operation of the I347-AT4. two functions are performed when this instruction is selected: sample and preload. sample enables a snapshot to be taken of th e data flowing from the system pins to the on-chip test logic or vice versa, withou t interfering with normal operation. the snapshot is taken on the rising edge of tck in the capture-dr controller state, and the data can be viewed by shifting through the component's tdo output. while sampling and shifting data out throug h tdo for observation, preload enables an initial data pattern to be shifted in through tdi and to be placed at the latched parallel output of the boundary-scan register cells that are connected to system output pins. this step ensures that known data is driven through the system output pins upon entering the extest instruction. without pr eload, indeterminate data would be driven until the first scan sequence is complete. the shifting of data for the sample and preload phases can occur simultaneously. while data capture is being shifted out, the preload data can be shifted in. table 24. boundary scan chain order instruction opcode extest 0x00000000 sample/preload 0x00000001 clamp 0x00000010 high-z 0x00000011 id_code 0x00000100 extest_pulse 0x00000101 extest_train 0x00000110 prog_hyst 0x00001000 bypass 0x11111111
47 device functionality?I347-AT4 pin i/o p3_led[3] output p3_led[2] output p3_led[1] output p3_led[0] output p3_led[3] output enable p3_led[2] output enable p3_led[1] output enable p3_led[0] output enable p2_led[3] output p2_led[2] output p2_led[1] output p2_led[0] output p2_led[3] output enable p2_led[2] output enable p2_led[1] output enable p2_led[0] output enable p1_led[3] output p1_led[2] output p1_led[1] output p1_led[0] output p1_led[3] output enable p1_led[2] output enable p1_led[1] output enable p1_led[0] output enable p0_led[3] output p0_led[2] output p0_led[1] output p0_led[0] output p0_led[3] output enable p0_led[2] output enable p0_led[1] output enable p0_led[0] output enable config[3] input config[2] input config[1] input config[0] input mdc input mdio input mdio output mdio output enable reset input
I347-AT4?device functionality 48 table 25. boundary scan exclusion list clk_sel[1] input clk_sel[0] input rclk1 output rclk1 output enable rclk2 output rclk2 output enable intn output intn output enable p3_s_outp/p3_s_outn output enable p3_s_outp/p3_s_outn output port 3 ac/dc select ac/dc select p3_s_inn input p3_s_inp input p2_s_outp/p2_s_outn output enable p2_s_outp/p2_s_outn output port 2 ac/dc select ac/dc select p2_s_inn input p2_s_inp input q_outn/q_outp output enable q_outn/q_outp output q_inp input q_inn input p1_s_outp/p1_s_outn output enable p1_s_outp/p1_s_outn output port 1 ac/dc select ac/dc select p1_s_inn input p1_s_inp input p0_s_outp/p0_s_outn output enable p0_s_outp/p0_s_outn output port 0 ac/dc select ac/dc select p0_s_inn input p0_s_inp input pin i/o p0_mdip[0] analog p0_mdin[0] analog p0_mdip[1] analog p0_mdin[1] analog p0_mdip[2] analog p0_mdin[2] analog pin i/o
49 device functionality?I347-AT4 p0_mdip[3] analog p0_mdin[3] analog p1_mdip[0] analog p1_mdin[0] analog p1_mdip[1] analog p1_mdin[1] analog p1_mdip[2] analog p1_mdin[2] analog p1_mdip[3] analog p1_mdin[3] analog p2_mdip[0] analog p2_mdin[0] analog p2_mdip[1] analog p2_mdin[1] analog p2_mdip[2] analog p2_mdin[2] analog p2_mdip[3] analog p2_mdin[3] analog p3_mdip[0] analog p3_mdin[0] analog p3_mdip[1] analog p3_mdin[1] analog p3_mdip[2] analog p3_mdin[2] analog p3_mdip[3] analog p3_mdin[3] analog xtal_in analog xtal_out analog sclk analog rset analog tstpt analog tstptf analog hsdacp analog hsdacn analog test[1:0] analog v18_l analog v18_r analog v12_en analog vddol power vddor power vddom power pin i/o
I347-AT4?device functionality 50 3.19.3 extest instruction the extest instruction enables circuitry exte rnal to the I347-AT4 (typically the board interconnections) to be tested. prior to executing the extest instru ction, the first test stimulus to be applied is shifted into the boundary-scan registers using the sample/ preload instruction. thus, when the change to the extest instruction takes place, known data is driven immediately from the I347-AT4 to its external connections. note that the s_outp/n and q_outp/n pins are driven to static levels. the positive and negative legs of the s_outp/n and q_outp/n pins are controlled via a single boundary scan cell.the positive leg outputs the level sp ecified by the boundary scan cell while the negative leg outputs the opposite level. 3.19.4 the clamp instruction the clamp instruction enables the state of th e signals driven from component pins to be determined from the boundary-scan register while the bypass register is selected as the serial path between tdi and tdo. the signals driven from the component pins do not change while the clamp instruction is selected. 3.19.5 the high-z instruction the high-z instruction places all of the digital component system logic outputs in an inactive high-impedance drive state. in this state, an in-circuit test system might drive signals onto the connections normally driven by a component output without incurring the risk of damage to the component. 3.19.6 id code instruction the id code contains the manufacturer identity, part and version. table 26. id code instruction vddc power avddh power dvdd power vss power pin i/o version part number manufacturer identity bit 31 to 28 bit 27 to 12 bit 11 to 1 0 0000 0000000000001110 00111101110 1
51 device functionality?I347-AT4 3.19.7 extest_pulse instruction the ac or dc jtag test modes can be selected for each port individually by scanning in the desired bit value into ac/dc select scan registers shown in the scan chain ( ta b l e 2 4 ). when the ac/dc select is set to dc the extest_pulse instruction has the same behavior as the extest instruction. when the ac/dc select is set to ac, th e extest_pulse instruction has the same behavior as the extest instruction except for the behavior of the s_outp/n and q_outp/n pins. as in the extest instruction, the test stimulus must first be shifted into the boundary- scan registers. upon the execution of the extest_pulse instruction the s_outp and q_outp pins output the level specified by the test stimulus and s_outn and s_clkn pins output the opposite level. however, if the tap controller enters into the run-test/idle state the s_outn and q_outn pins output the level specified by the test stimulus and s_outp and q_outp pins output the opposite level. when the tap controller exits the run-test/idle state, the s_outp and q_outp pins again output the level specified by the te st stimulus and s_outn and q_outn pins output the opposite level. 3.19.8 extest_train instruction when the ac/dc select is set to dc, th e extest_train instruction has the same behavior as the extest instruction. when the ac/dc select is set to ac, th e extest_train instruction has the same behavior as the extest instruction except for the behavior of the s_outp/n and q_outp/n pins. as in the extest instruction, the test stimulus must first be shifted into the boundary- scan registers. upon the execution of the extest_pulse instruction the s_outp and q_outp pins output the level specified by the test stimulus and s_outn and q_outn pins output the opposite level. however, if the tap controller enters into the run-test/idle state the s_outp/n and q_outp/n will toggle between inverted and no n-inverted levels on the falling edge of tck. this toggling will continue for as long as the tap controller remains in the run- test/idle state. when the tap controller exits the run-test/idle state, the s_outp and q_outp pins again output the level specified by the te st stimulus and s_outn and q_outn pins output the opposite level. 3.19.9 ac-jtag fault detection the fault detection across ac coupled connect ions can be detected with a combination of (dc) extest and any one of the ac jt ag commands. the ac coupled connection is shown in figure 16 . the fault signature is listed in ta b l e 2 7 . column 1 lists the fault type.
I347-AT4?device functionality 52 columns 2 to 5 lists the behavior when both the transmitter and receiver are running the extest_train and extest_pulse co mmands. column 2 shows the expected value captured by the boundary scan cell that is connected to the test receiver, which is connected to the positive input when a nega tive differential pulse is transmitted. column 3 is the same as column 2 except for the negative input. columns 4 and 5 are similar to columns 2 and 3 except a positive differential pulse is transmitted. columns 6 to 9 is similar to columns 2 to 5 except both the transmitter and receiver are running the (dc) extest command. while it is not possible to identify precisely which fault is occurring based on the fault signature, the signature to the no fault condition is unique when the (dc) extest command is run with at least one of the extest_train, or extest_pulse commands. note that running only ac jtag commands is not sufficient since the no fault condition signature is not distinguishable from the tx to rx short (see shaded cells in ta b l e 2 7 ). table 27. ac coupled connection fault signature dc coupled fault ac testing sample 0 ac testing sample 1 (dc) extest sample 0 (dc) extest sample 1 positive leg negative leg positive leg negative leg positive leg negative leg positive leg negative leg tx+ open 0b x 0b x 1b x 1b x tx- open x 0b x 0b x 1b x 1b rx+ open 0b x 0b x 1b x 1b x rx- open x 0b x 0b x 1b x 1b tx+ short to power 0b 1 x0 b 1 x1 bx 1 bx tx- short to power x0 b 1 x0 b 1 x1 bx1 b rx+ short to power 0b 1 x0 b 1 x1 bx 1 bx rx- short to power x0 b 1 x0 b 1 x1 bx1 b tx+ short to ground 0b x 0b x 1b x 1b x tx- short to ground x 0b x 0b x 1b x 1b rx+ short to ground 0b x 0b x 0b x 0b x rx- short to ground x 0b x 0b x 0b x 0b tx+ short to tx- 22 22 1b 1b 1b 1b rx+ short to rx- 22 22 1b 1b 1b 1b tx+ short to rx- x 0b x 1b x 0b x 1b
53 device functionality?I347-AT4 figure 16. ac coupled connection the fault detection across dc coupled connections can be detected with any one of the ac jtag or (dc) extest commands. the dc coupled connection is shown in figure 17 . the fault signature is listed in ta b l e 2 8 . table 28. dc coupled connection fault signature tx- short to rx+ 1b x 0b x 1b x 0b x tx+ short to rx+ 0b x 1b x 0b x 1b x tx- short to rx- x 1b x 0b x 1b x 0b no fault0b 1b 1b0b1b1b1b1b 1. a solid short to power is assumed. if th e short has high inductance then a pulse ca n still be sent at the receiver and is mis taken as a good connection. 2. a short on a positive and negative leg can have several behavi ors on the test receiver. if both drivers cancel each other out then the output on both legs is zero. if one driver dominates the other, then both legs are either both one or both zero. in any cas e, the result is that both legs have same value. dc coupled fault ac testing sample 0 ac testing sample 1 (dc) extest sample 0 (dc) extest sample 1 positive leg negative leg positive leg negative leg positive leg negative leg positive leg negative leg rx+ rx tx tx+ rx- tx- dc coupled fault ac testing sample 0 ac testing sample 1 (dc) extest sample 0 (dc) extest sample 1 positive leg negative leg positive leg negative leg positive leg negative leg positive leg negative leg rx+ open 0b x 0b x 1b x 1b x rx- open x 0b x 0b x 1b x 1b rx+ short to power 0b 1 x0 b 1 x1 bx1 b x rx- short to power x0 b 1 x0 b 1 x1 bx 1 b rx+ short to ground 0b x 0b x 0b x 0b x rx- short to ground x 0b x 0b x 0b x 0b rx+ short to rx- 2222222 2
I347-AT4?device functionality 54 figure 17. dc coupled connection 3.20 interrupt the intn pin supports the interrupt function. intn is active low. registers 18_0, 18_1, 18_2, 18_4, and 26_6.7 are the interrupt enable registers. registers 19_0, 19_1, 19_2, 19_4, and 26_6.6 are the interrupt status registers. registers 23_0 is the interrupt status summary registers. register 23_0 lists the ports that have active interrupts. register 23_0 provides a quick way to isolate the interrupt so that the mac or switch does not have to poll register 19 for all ports. reading register 23_0 does not de-assert the intn pin. note that register 23_0 can be accessed by reading register 23_0 using the phy address of any of the four ports. the various pages of register 18 and 26_6.7 are used to select the interrupt events that can activate the interrupt pin. the interrupt pin will be activated if any of the selected events on any page of register 18 or 26_67 occurs. if a certain interrupt event is not enabled fo r the intn pin, it will still be indicated by the corresponding interrupt status bits if the interrupt event occurs. the unselected events do not cause the intn pin to be activated. 3.21 configuring the I347-AT4 the I347-AT4 can be configured two ways: ? hardware configuration strap options (unmanaged applications) ? mdc/mdio register writes (managed applications) all hardware configuration options can be ov erwritten by software except phyadr[4:2] and phy_order. n o f a u l t0 b1 b 1 b0 b0 b1 b1 b 0 b 1. a solid short to power is assumed. if the short has high induct ance then a pulse can still be sent at the receiver and is mis taken as a good connection. 2. a short on the positive and negative leg can have several behaviors on the test receiver. if both drivers cancel each other o ut then output on both legs is zero. if one driver dominates the othe r then both legs are either both one or both zero. in any cas e, the result is that both legs has the same value. dc coupled fault ac testing sample 0 ac testing sample 1 (dc) extest sample 0 (dc) extest sample 1 positive leg negative leg positive leg negative leg positive leg negative leg positive leg negative leg rx+ rx tx rx-
55 device functionality?I347-AT4 3.21.1 hardware configuration after the deassertion of resetn, the I347-AT4 is hardware configured. the I347-AT4 is configured through th e config[3:0] pins and clk_sel[1:0]. clk_sel[1:0] are used to select the reference clock input option as well as the serial led feature: table 29. clk_sel[1:0] configuration settings each config[3:0] pin is used to configure four bits. the 4-bit value is set depending on what is connected to the config pins soon after the deassertion of hardware reset. the 4-bit mapping is shown in ta b l e 3 0 . table 30. four bit mapping the four bits for each config pin is mapped as listed in ta b l e 3 0 . config[2:1] are reserved and should not be used as configuration pins. clk_sel[1:0] clock input ser_led ser_led feature 10b 25 mhz xtal_in/xtal_out 0b not supported 1b not supported 11b 25 mhz xtal_in/xtal_out 0b not supported 1b pin bit 3, 2,1,0 vss 0000 p0_led[1] 0001 p0_led[2] 0010 p0_led[3] 0011 p1_led[0] 0100 p1_led[1] 0101 p1_led[2] 0110 p1_led[3] 0111 p2_led[0] 1000 p2_led[1] 1001 p2_led[2] 1010 p2_led[3] 1011 p3_led[0] 1100 p3_led[1] 1101 p3_led[2] 1110 vddo 1111 p0_led[0] reserved p3_led[3] reserved
I347-AT4?device functionality 56 3.21.2 configuration mapping table 31. configuration mapping table 32. I347-AT4 pdown register setting as a function of mode[2:0] 3.21.3 software configuration - management interface the management interface provides access to the internal registers via the mdc and mdio pins and is compliant with ieee 802.3u clause 22. mdc is the management data clock input and, it can run from dc to a maximum rate of 12 mhz. at high mdio fanouts the maximum rate can be decreased de pending on the output loading. mdio is the management data input/output and is a bi-directional signal that runs synchronously to mdc. the mdio pin requires a pull-up resistor in a range from 1.5 k to 10 k that pulls the mdio high during the idle and turnaround. phy address is configured during th e hardware reset sequence. refer to section 3.21.1 for more information on how to configure phy addresses. typical read and write operations on the management interface are shown in figure 18 and figure 19 . all the required serial management registers are implemented as well as several optional registers. a description of the registers can be found in section 4.0 . pin ser_led bit3 bit 2 bit1 bit 0 config[0] x phy_order phyad[4] phyad[3] phyad[2] config[1] 0b sel_ms ena_pause c_aneg[1] c_aneg[0] 1b reserved config[2] 0b s_aneg ena_xc dis_sleep pdown 1b reserved config[3] x reserved, set to 0b mode[2] mode[1] mode[0] mode[2:0] pdown 0_0.11 0_1.11 0_4.11 xxx 0b 0b 0b 0b 000b 1b 1b 0b 0b 001b 1b 1b 0b 0b 010b 1b 0b 1b 0b 011b 1b 0b 1b 0b 100b 1b 0b 1b 0b 101b 1b 0b 0b 1b 110b 1b 1b 1b 0b 111b 1b 1b 1b 0b
57 device functionality?I347-AT4 figure 18. typical mdc/mdio read operation figure 19. typical mdc/ mdio write operation ta b l e 3 3 is an example of a read operation. table 33. serial management interface protocol 3.21.3.1 extended register access the ieee defines only 32 registers address space for the phy. in order to extend the number of registers address space available a paging mechanism is used. for register address 0 to 21, and 23 to 28 register 22 bits 7 to 0 are used to specify the page. for registers 30 and 31 register 29 bits 5:0 are used to specify the page. there is no paging for registers 22 and 29. in this document, the short hand used to specify the registers take the form register_page.bit:bit, register_page.bit, register.bit:bit, or register.bit. for example: register 16 page 2 bits 5 to 2 is specified as 16_2.5:2. register 16 page 2 bits 5 is specified as 16_2.5. currently there it takes four mdio write commands to write the same register to the same value on all four ports. register 22.15:14 can be used to selectively ignore phyad[4:2] and phyad[1:0] as listed in ta b l e 3 4 so that the same register address can be written to all four ports in one mdio write command. phyad[4:0] is still decoded for read commands. mdc mdio (sta) 0110 a4 a3 a2 a1 a0 r4 r3 r2 r1 r0 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 z mdio (phy) idle start opcode (read) phy address register address ta register data idle mdc mdio (sta) 0101 a4 a3 a2 a1 a0 r4 r3 r2 r1 r0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 idle start opcode (write) phy address register address ta register data 10 idle 32-bit preamble start of frame opcode read = 10b write = 01b 5-bit phy device address 5-bit phy register address (msb) 2-bit turn around read = z0b write = 10b 16-bit data field idle 11111111b 01b 10b 01100b 00000b z0b 0001001100000000b 11111111b
I347-AT4?device functionality 58 care must be taken to setup multiple port write. to enable the concurrent write access write register 22 four times in a row with bit 14 set to 1b ? once to each phyad[4:0]. the values written on all 16 bits must be the same otherwise unpredictable behavior can occur. once the four write commands to register 22 are issued, all subsequent writes are concurrent to all ports including writes to register 22. concurrent write access continues as long as every write to register 22 sets 22.14 to a 1b. to disable concurrent write access, write register 22:14 to 0b. table 34. page address 3.21.3.2 preamble suppression the I347-AT4 is permanently programmed for preamble suppression. a minimum of one idle bit is required between operations. 3.22 reference clock the I347-AT4 can use a 25 mhz crystal or 25 mhz oscillator as the reference clock.. the connection to the reference clock pins are shown in section 35 . the reference frequency used must be indicated by the clk_sel[1:0] pins. table 35. reference clock pin connections 3.23 temperature sensor the I347-AT4 contains an internal temperature sensor. register 26_6.4:0 reports the die temperature and is updated approximately once per second. the result can be read back on any port as long as the port is not disabled (such as register 0.11 = 1b). an interrupt can be generated when the temperature exceeds a certain threshold. register function setting mode hw rst sw rst 22.15 ignore phyad[4:2] 0b = use phyad[4:2] to decode write commands 1b = ignore phyad[4:2] to decode write commands r/w 0b retain 22.14 ignore phyad[1:0] 0b = use phyad[1:0] to decode write commands 1b = ignore phyad[1:0] to decode write commands r/w 0b retain 22.13:8 reserved 00000000b ro 0b 0b 22.7:0 page select for registers 0 to 28 page number r/w 00b retain reference source clk_sel[1:0] xtal_in xtal_out ref_clkp ref_clkn 25 mhz crystal 1xb connect to crystal connect to crystal pull-up to 1.9v with 1 k resistor pull-down to gnd with 1 k resistor 25 mhz oscillator 1xb connect to driver leave floating pull-up to 1.9v with 1 k resistor pull-down to gnd with 1 k resistor
59 device functionality?I347-AT4 register 26_6.6 is set high each time the te mperature is greater than or equal to the value programmed in register 26_6.12:8. register 26_6.6 remains high until read. register 26_6.7 controls whether the interrupt pin is asserted when register 26_6.6 is high. the interrupt should be enable d on only one port since there is only one temperature sensor for the entire chip. table 36. temperature sensor 3.24 power supplies the I347-AT4 requires two power supplies: 1. 9v and 1.0v. if a 3.3v i/o is required (such as, for jtag or mdc/mdio pins), then a third supply of 3.3v is required. for i/os to be 3.3v tolerant, vddo must be 3.3v. 3.24.1 avddh avddh is used as the 1.9v analog supply. 3.24.2 vddc vddc is used as the 1.9v xtal_in/out supply. these inputs are not 3.3v tolerant. 3.24.3 dvdd dvdd is used for the digital logic. dvdd is the 1.0v digital supply. 3.24.4 vddol vddol supplies the digital i/o pins for resetn, led, config, and intn. v18_l should be tied to vss if the vddol voltage is set to 3.3v. v18_l should be floating if the vddol voltage is set to 1.9v. register function setting mode hw rst sw rst 26_6.12:8 temperature threshold te m p e ra t u r e i n c = 5 x 26_6.4:0 - 25. for example, for 100 c the value is 11001b. r/w 11001b retain 26_6.7 temperature sensor interrupt enable 1b = interrupt enable. 0b = interrupt enable. r/w 0b retain 26_6.6 temperature sensor interrupt 1b = temperature reached threshold. 0b = temperature below threshold. ro, lh 0b 0b 26_6.4:0 temperature sensor te m p e ra t u r e i n c = 5 x 26_6.4:0 - 25. for example, for 100 c the value is 11001b. ro xxxxx xxxxx
I347-AT4?device functionality 60 3.24.5 vddor vddor supplies the digital i/o pins for tdo, tdi, tms, tck, trstn, ref_clkp/n, or clk_sel[1:0]. v18_r should be tied to vss if the vddor voltage is set to 3.3v. v18_r should be floating if the vddor voltage is set to 1.9v. 3.24.6 vddom vddom supplies the digital i/o pins for mdc, mdio, and test. v12_en should be tied to vss if the vddom voltage is set to 3.3v. v12_en should be floating if the vddom voltage is set to 1.9v. 3.24.7 power supply sequencing on power-up, no special power supply sequencing is required. 3.25 clocking support there two components to clocking suppo rt: recovered clock and reference clock select. the first is to output a recovered clock. the second is to select between the local reference clock and a cleaned-up recovered clock. 3.25.1 recovered clock the rclk1 and rclk2 pins of the chip output s either a 125 mhz or 25 mhz clock that is based on the 125 mhz recovered clock on the copper receive path when linked to 1000base-t or 100base-tx. if a 25 mhz clock is selected, the 125 mhz recovered clock is internally divided by 5 with 60% low and 40% high. register 16_2.11 selects whether rclk output s 25 mhz xtal clock or drives low when the link is down or when the copper receiver is linked to 10base-t. ? 0b = rclk outputs 25 mhz xtal clock during link down or 10base-t ? 1b = rclk drives low during link down or 10base-t rclk1 pin is enabled when register 16_2.8 is set to 1b, and rclk2 pin is enabled when register 16_2.9 is set to 1b. each of these bits should be set to 1b for only one port (16_2.8 set to 1b in port 0 and 16_2.9 set to 1b for port 1). if the bit is set high for multiple ports then the highest numbered physic al port that is enabled is selected. the highest numbered physical port is defined to be the port connected to mdip/n3 and not necessarily the port with the highest ph yad[4:0] value. (the phy_order setting affects the phyad[1:0] setting.) register 16_2.12 selects whether rclk 25 mhz outputs 25 mhz or 125 mhz. 0b = 25 mhz, 1 = 125 mhz.
61 device functionality?I347-AT4 3.25.2 reference clock select the 25 mhz reference clock source to the copper unit is independently selectable per port. on hardware reset xtal_in or ref_cl kp/n is selected as the reference clock source for all ports. sclk can be selected as the reference clock source on a per port basis. register 16_2.7 selects whether the reference clock for the copper interface is based on xtal_in/ref_clkp/n or sclk. 0b = xtal_in or ref_clkp/n, 1b = sclk. register 16_2.6 selects whether the reference clock for the 1.25 ghz serdes interface is based on xtal_in/ref_clkp/n or sclk. 0 = xtal_in or ref_clkp/n, 1 = sclk. the clk_sel[1:0] must be set to 11b in order to do the reference clock selection. since changing the reference clocks disturbs the phy, a software reset must be issued before any change to the clock select takes place.
I347-AT4?programmer?s visible state 62 4.0 programmer?s visible state the ieee defines only 32 registers address sp ace for the phy. in order to extend the number of registers address space available a paging mechanism is used. for register address 0 to 21, and 23 to 28 register 22 bits 7 to 0 are used to specify the page. for registers 30 and 31 register 29 bits 5:0 are used to specify the page. there is no paging for registers 22 and 29. in this document, the short hand used to specify the registers take the form register_page.bit:bit, register_page.bit, register.bit:bit, or register.bit. for example: register 16 page 2 bits 5 to 2 is specified as 16_2.5:2. register 16 page 2 bits 5 is specified as 16_2.5. register 2 bit 3 to 0 is specified as 2.3:0. note that in this context the setting of th e page register (register 22) has no effect. register 2 bit 3 is specified as 2.3. ta b l e 3 7 lists the register types used in the register map. table 37. register types type description c clear after read. lh register field with latching high function. if status is high, then the register is set to one and remains set until a read operation is performed through the management interface or a reset occurs. ll register field with latching low function. if status is low, then the register is cleared to zero and remains zero until a read operation is performed through the management interface or a reset occurs. retain the register value is retained after software reset is executed. res reserved for future use. all reserved bits are read as zero unless otherwise noted. ro read only. ros read only, set high after read. roc read only clear. after read, register field is cleared. rw read and write with initial value indicated. rwc read/write clear on read. all field bits are readable an d writable. after reset or after the register field is read, register field is cleared to zero. rwr read/write clear on read. all field bits are readable and writable. after reset, register field is cleared to 0.
63 programmer?s visible state?I347-AT4 for all binary equations appearing in the regist er map, the symbol | is equal to a binary or operation. 4.1 register map ta b l e 3 8 lists the registers used in the I347-AT4. table 38. I347-AT4 register names and addresses type description rws read/write set. all field bits are readable and writable. af ter reset, register field is set to a non-zero value specified in the text. sc self-clear. writing a one to this register causes the desired function to be immediately executed, then the register field is automatically cleare d to zero when the function is complete. update value written to the register field does n?t take effect until soft reset is executed. wo write only. reads to this type of register field return undefined data. register name register address page copper control register page 0, register 0 65 copper status register page 0, register 1 66 phy identifier 1 page 0, register 2 67 phy identifier 2 page 0, register 3 68 copper auto-negotiation advertisement register page 0, register 4 68 copper link partner ability register - base page page 0, register 5 70 copper auto-negotiation expansion register page 0, register 6 71 copper next page transmit register page 0, register 7 72 copper link partner next page register page 0, register 8 72 1000base-t control register page 0, register 9 73 1000base-t status register page 0, register 10 74 extended status register page 0, register 15 74 copper specific control register 1 page 0, register 16 75 copper specific status register 1 page 0, register 17 76 copper specific interrupt enable register page 0, register 18 77 copper interrupt status register page 0, register 19 78 copper specific control register 2 page 0, register 20 79 copper specific receive error coun ter register page 0, register 21 80 page address page any, register 22 80 global interrupt status page 0, register 23 80 copper specific control register 3 page 0, register 26 80
I347-AT4?programmer?s visible state 64 phy identifier page 1, register 2 81 phy identifier page 1, register 3 81 extended status register page 1, register 15 81 prbs control page 1, register 23 82 prbs error counter lsb page 1, register 24 82 prbs error counter msb page 1, register 25 82 mac specific control register 1 page 2, register 16 83 mac specific interrupt enable register page 2, register 18 83 mac specific status register page 2, register 19 84 copper rx_er byte capture page 2, register 20 84 mac specific control register 2 page 2, register 21 85 led[3:0] function control register page 3, register 16 85 led[3:0] polarity control register page 3, register 17 87 led timer control register page 3, register 18 87 led[5:4] function control and polarity register page 3, register 19 88 cable tester tx to mdi[0] rx coupling page 5, register 16 90 cable tester tx to mdi[1] rx coupling page 5, register 17 91 cable tester tx to mdi[2] rx coupling page 5, register 18 92 cable tester tx to mdi[3] rx coupling page 5, register 19 92 1000base-t pair skew register page 5, register 20 93 1000base-t pair swap and pola rity page 5, register 21 93 cable tester control page 5, register 23 94 cable tester sample point distance page 5, register 24 95 cable tester cross pair positive threshold page 5, register 25 95 cable tester same pair impedance positive threshold 0 and 1 page 5, register 26 95 cable tester same pair impedance positive threshold 2 and 3 page 5, register 27 96 cable tester same pair impedance positive threshold 4 and transmit pulse control page 5, register 28 96 packet generation page 6, register 16 97 crc counters page 6, register 17 97 register name register address page
65 programmer?s visible state?I347-AT4 4.1.1 copper control register - page 0, register 0 checker control page 6, register 18 97 general control register page 6, register 20 98 late collision counters 1 & 2 page 6, register 23 98 late collision counters 3 & 4 page 6, register 24 99 late collision window adjust/lin k disconnect page 6, register 25 99 misc test page 6, register 26 99 bits field mode hw rst sw rst description 15 copper reset r/w, sc 0x0 sc copper software reset. affect s pages 0, 2, 3, 5, and 7. writing a 1 to this bit causes the phy state machines to be reset. when the reset operation is done, this bit is cleared to 0 automatically. the reset occurs immediately. 1 = phy reset 0 = normal operation 14 loopback r/w 0x0 0x0 when loopback is activated, th e transmitter data presented on txd is looped back to rxd internally. link is broken when loopback is enabled. loopback speed is determined by registers 21_2.2:0. 1 = enable loopback 0 = disable loopback 13 speed select (lsb) r/w 0x0 update changes to this bit are disruptive to the normal operation; therefore, any changes to these registers must be followed by a software reset to take effect. a write to this register bit does not take effect until any one of the following also occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation bit 6, 13 11 = reserved 10 = 1000 mbps 01 = 100 mbps 00 = 10 mbps 12 auto-negotiation enable r/w 0x1 update changes to this bit are disruptive to the normal operation. a write to this register bit does not take effect until any one of the following occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation if register 0_0.12 is set to 0 an d speed is manually forced to 1000 mbps in registers 0.13 and 0.6, then auto-negotiation will still be enabled and onl y 1000base-t full-duplex is advertised if register 0_0.8 is set to 1, and 1000base-t half- duplex is advertised if 0.8 is set to 0. registers 4.8:5 and 9.9:8 are ignored. auto-negotiation is mandatory per ieee for proper operation in 1000base-t. 1 = enable auto-negotiation process 0 = disable auto-negotiation process register name register address page
I347-AT4?programmer?s visible state 66 4.1.2 copper status register - page 0, register 1 11 power down r/w see descr retain power down is controlled via register 0_0.11 and 16_0.2. both bits must be set to 0 before the phy will transition from power down to normal operation. when the port is switched from power down to normal operation, software reset and restart auto-negotiation are performed even when bits reset (0_0.15) and restart auto- negotiation (0_0.9) are not set by the user. upon hardware reset this bit takes on the value of pdown and (mode[2:0] = 00x or 11x) 1 = power down 0 = normal operation 10 isolate ro 0x0 0x0 this bit has no effect. 9 restart copper auto-negotiation r/w, sc 0x0 sc auto-negotiation automatically restarts after hardware or software reset regardless of whether or not the restart bit (0_0.9) is set. 1 = restart auto-negotiation process 0 = normal operation 8 copper duplex mode r/w 0x1 update changes to this bit are disruptive to the normal operation; therefore, any changes to these registers must be followed by a software reset to take effect. a write to this register bit does not take effect until any one of the following also occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation 1 = full-duplex 0 = half-duplex 7 collision test ro 0x0 0x0 th is bit has no effect. 6 speed selection (msb) r/w 0x1 update changes to this bit are disruptive to the normal operation; therefore, any changes to these registers must be followed by a software reset to take effect. a write to this register bit does not take effect until any one of the following occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation bit 6, 13 11 = reserved 10 = 1000 mbps 01 = 100 mbps 00 = 10 mbps 5:0 reserved ro 0x00 0x00 will always be 0. bits field mode hw rst sw rst description bits field mode hw rst sw rst description 15 100base-t4 ro 0x0 0x0 100base-t4. this protocol is not available. 0 = phy not able to perform 100base-t4 14 reserved ro 0x1 0x1 reserved
67 programmer?s visible state?I347-AT4 4.1.3 phy identifier 1 - page 0, register 2 13 reserved ro 0x1 0x1 reserved 12 10 mbps full- duplex ro 0x1 0x1 1 = phy able to perform full-duplex 10base-t 11 10 mbps half- duplex ro 0x1 0x1 1 = phy able to perform half-duplex 10base-t 10 100base-t2 full-duplex ro 0x0 0x0 this protocol is not available. 0 = phy not able to perform full-duplex 9 100base-t2 half-duplex ro 0x0 0x0 this protocol is not available. 0 = phy not able to perform half-duplex 8 extended status ro 0x1 0x1 1 = extended status information in register 15 7 reserved ro 0x0 0x0 must always be 0. 6 mf preamble suppression ro 0x1 0x1 1 = phy accepts management frames with preamble suppressed 5 copper auto- negotiation complete ro 0x0 0x0 1 = auto-negotiation process complete 0 = auto-negotiation process not complete 4 copper remote fault ro,lh 0x0 0x0 1 = remote fault condition detected 0 = remote fault condition not detected 3 auto-negotiation ability ro 0x1 0x1 1 = phy able to perform auto-negotiation 2 copper link status ro,ll 0x0 0x0 this register bit indicates when link was lost since the last read. for the current link status, either read this register back- to-back or read register 17_0.10 link real time. 1 = link is up 0 = link is down 1 jabber detect ro,lh 0x0 0x0 1 = jabber condition detected 0 = jabber condition not detected 0 extended capability ro 0x1 0x1 1 = extended register capabilities bits field mode hw rst sw rst description 15:0 organizationally unique identifier bit 3:18 ro 0x0141 0x0141 oui is 0x005043 0000 0000 0101 0000 0100 0011 ^ ^ bit 1....................................bit 24 register 2.[15:0] show bits 3 to 18 of the oui. 0000000101000001 ^ ^ bit 3...................bit18 bits field mode hw rst sw rst description
I347-AT4?programmer?s visible state 68 4.1.4 phy identifier 2 - page 0, register 3 4.1.5 copper auto-negotiation adve rtisement register - page 0, register 4 bits field mode hw rst sw rst description 15:10 oui lsb ro 0x03 0x03 organizationally unique identifier bits 19:24 00 0011 ^.........^ bit 19...bit24 9:4 model number ro 0x1c 0x1c model number 011100 3:0 revision number ro see descr see descr rev number contact faes for information on the device revision number. bits field mode hw rst sw rst description 15 next page r/w 0x0 update a write to this register bit does not take effect until any one of the following occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation copper link goes down. if 1000base-t is advertised then the required next pages are automatically transmitted. register 4.15 should be set to 0 if no additional next pages are needed. 1 = advertise 0 = not advertised 14 ack ro 0x0 0x0 must be 0. 13 remote fault r/w 0x0 update a write to this register bit does not take effect until any one of the following occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation copper link goes down. 1 = set remote fault bit 0 = do not set remote fault bit 12 reserved r/w 0x0 update a write to this register bit does not take effect until any one of the following occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation copper link goes down reserved bit is r/w to allow for forward comp atibility with future ieee standards.
69 programmer?s visible state?I347-AT4 11 asymmetric pause r/w see descr. update a write to this register bit does not take effect until any one of the following occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation copper link goes down. upon hardware reset this bit takes on the value of ena_pause. 1 = asymmetric pause 0 = no asymmetric pause 10 pause r/w see descr. update a write to this register bit does not take effect until any one of the following occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation copper link goes down. upon hardware reset this bit takes on the value of ena_pause. 1 = mac pause implemented 0 = mac pause not implemented 9 100base-t4 r/w 0x0 retain 0 = not capable of 100base-t4 8 100base-tx full-duplex r/w see descr. update a write to this register bit does not take effect until any one of the following occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation copper link goes down. if register 0_0.12 is set to 0 and speed is manually forced to 1000 mbps in registers 0_0.13 and 0_0.6, then auto- negotiation will still be enabled and only 1000base-t full- duplex is advertised if register 0_0.8 is set to 1, and 1000base-t half-duplex is advert ised if 0_0.8 set to 0. registers 4_0.8:5 and 9_0.9:8 are ignored. auto-negotiation is mandatory per ieee for proper operation in 1000base-t. upon hardware reset this bit takes on the value of c_aneg[1]. 1 = advertise 0 = not advertised 7 100base-tx half-duplex r/w see descr. update a write to this register bit does not take effect until any one of the following occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation copper link goes down. if register 0_0.12 is set to 0 and speed is manually forced to 1000 mbps in registers 0.13 and 0.6, then auto-negotiation will still be enabled and onl y 1000base-t full-duplex is advertised if register 0_0.8 is set to 1, and 1000base-t half- duplex is advertised if 0.8 set to 0. registers 4.8:5 and 9.9:8 are ignored. auto-negotiation is mandatory per ieee for proper operation in 1000base-t. upon hardware reset this bit takes on the value of c_aneg[1]. 1 = advertise 0 = not advertised bits field mode hw rst sw rst description
I347-AT4?programmer?s visible state 70 4.1.6 copper link partner ability re gister - base page - page 0, register 5 6 10base-tx full- duplex r/w see descr. update a write to this register bit does not take effect until any one of the following occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation copper link goes down. if register 0_0.12 is set to 0 an d speed is manually forced to 1000 mbps in registers 0_0.13 and 0_0.6, then auto- negotiation will still be enabled and only 1000base-t full- duplex is advertised if regi ster 0_0.8 is set to 1, and 1000base-t half-duplex is adve rtised if 0_0.8 set to 0. registers 4_0.8:5 and 9_0.9:8 are ignored. auto-negotiation is mandatory per ieee for proper operation in 1000base-t. upon hardware reset this bit ta kes on the value of c_aneg[1]. 1 = advertise 0 = not advertised 5 10base-tx half- duplex r/w see descr. update a write to this register bit does not take effect until any one of the following occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation copper link goes down. if register 0_0.12 is set to 0 an d speed is manually forced to 1000 mbps in registers 0_0.13 and 0_0.6, then auto- negotiation will still be enabled and only 1000base-t full- duplex is advertised if regi ster 0_0.8 is set to 1, and 1000base-t half-duplex is adve rtised if 0_0.8 set to 0. registers 4_0.8:5 and 9_0.9:8 are ignored. auto-negotiation is mandatory per ieee for proper operation in 1000base-t. upon hardware reset this bit ta kes on the value of c_aneg[1]. 1 = advertise 0 = not advertised 4:0 selector field r/w 0x01 retain selector field mode 00001 = 802.3 bits field mode hw rst sw rst description 15 next page ro 0x0 0x0 received code word bit 15 1 = link partner capable of next page 0 = link partner not capable of next page 14 acknowledge ro 0x0 0x0 acknowledge received code word bit 14 1 = link partner received link code word 0 = link partner does not have next page ability 13 remote fault ro 0x0 0x0 remote fault received code word bit 13 1 = link partner detected remote fault 0 = link partner has not detected remote fault 12 tec h no l o gy ability field ro 0x0 0x0 received code word bit 12 bits field mode hw rst sw rst description
71 programmer?s visible state?I347-AT4 4.1.7 copper auto-negotiation expans ion register - page 0, register 6 11 asymmetric pause ro 0x0 0x0 received code word bit 11 1 = link partner requests asymmetric pause 0 = link partner does not request asymmetric pause 10 pause capable ro 0x0 0x0 received code word bit 10 1 = link partner is capable of pause operation 0 = link partner is not capable of pause operation 9 100base-t4 capability ro 0x0 0x0 received code word bit 9 1 = link partner is 100base-t4 capable 0 = link partner is not 100base-t4 capable 8 100base-tx full-duplex capability ro 0x0 0x0 received code word bit 8 1 = link partner is 100base-tx full-duplex capable 0 = link partner is not 100base-tx full-duplex capable 7 100base-tx half-duplex capability ro 0x0 0x0 received code word bit 7 1 = link partner is 100base-tx half-duplex capable 0 = link partner is not 100base-tx half-duplex capable 6 10base-t full-duplex capability ro 0x0 0x0 received code word bit 6 1 = link partner is 10base-t full-duplex capable 0 = link partner is not 10base-t full-duplex capable 5 10base-t half-duplex capability ro 0x0 0x0 received code word bit 5 1 = link partner is 10base-t half-duplex capable 0 = link partner is not 10base-t half-duplex capable 4:0 selector field ro 0x00 0x00 selector field received code word bit 4:0 bits field mode hw rst sw rst description 15:5 reserved ro 0x000 0x000 reserved. must be 00000000000. 4 parallel detection fault ro,lh 0x0 0x0 register 6_0.4 is not valid until the auto-negotiation complete bit (reg 1_0.5) indicates completed. 1 = a fault has been detected via the parallel detection function 0 = a fault has not been detected via the parallel detection function 3 link partner next page able ro 0x0 0x0 register 6_0.3 is not valid until the auto-negotiation complete bit (reg 1_0.5) indicates completed. 1 = link partner is next page able 0 = link partner is not next page able 2 local next page able ro 0x1 0x1 register 6_0.2 is not valid until the auto-negotiation complete bit (reg 1_0.5) indicates completed. 1 = local device is next page able 0 = local device is not next page able 1 page received ro, lh 0x0 0x0 register 6_0.1 is not valid until the auto-negotiation complete bit (reg 1_0.5) indicates completed. 1 = a new page has been received 0 = a new page has not been received bits field mode hw rst sw rst description
I347-AT4?programmer?s visible state 72 4.1.8 copper next page transmit register - page 0, register 7 4.1.9 copper link partner next page register - page 0, register 8 0 link partner auto- negotiation able ro 0x0 0x0 register 6_0.0 is not valid until the auto-negotiation complete bit (reg 1_0.5) indicates completed. 1 = link partner is auto-negotiation able 0 = link partner is not auto-negotiation able bits field mode hw rst sw rst description 15 next page r/w 0x0 0x0 a write to register 7_0 implicitly sets a variable in the auto- negotiation state machine indicating that the next page has been loaded. link fail will clear reg 7_0. transmit code word bit 15 14 reserved ro 0x0 0x0 transmit code word bit 14 13 message page mode r/w 0x1 0x1 transmit code word bit 13 12 acknowledge2 r/w 0x0 0x0 transmit code word bit 12 11 toggle ro 0x0 0x0 transmit code word bit 11 10:0 message/ unformatted field r/w 0x001 0x001 transmit code word bit 10:0 bits field mode hw rst sw rst description 15 next page ro 0x0 0x0 received code word bit 15 14 acknowledge ro 0x0 0x0 received code word bit 14 13 message page ro 0x0 0x0 received code word bit 13 12 acknowledge2 ro 0x0 0x0 received code word bit 12 11 toggle ro 0x0 0x0 received code word bit 11 10:0 message/ unformatted field ro 0x000 0x000 received code word bit 10:0 bits field mode hw rst sw rst description
73 programmer?s visible state?I347-AT4 4.1.10 1000base-t control register - page 0, register 9 bits field mode hw rst sw rst description 15:13 test mode r/w 0x0 retain tx_clk comes from the rx_clk pin for jitter testing in test modes 2 and 3. after exiting the test mode, hardware reset or software reset (register 0_0.15) should be issued to ensure normal operation. a re start of auto-negotiation will clear these bits. 000 = normal mode 001 = test mode 1 - transmit waveform test 010 = test mode 2 - transmit jitter test (master mode) 011 = test mode 3 - transmit jitter test (slave mode) 100 = test mode 4 - transmit distortion test 101, 110, 111 = reserved 12 master/slave manual configuration enable r/w 0x0 update a write to this register bit does not take effect until any of the following also occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation copper link goes down. 1 = manual master/slave configuration 0 = automatic master/slave configuration 11 master/slave configuration value r/w see descr. update a write to this register bit does not take effect until any of the following also occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation copper link goes down. upon hardware reset this bit takes on the value of sel_ms. 1 = manual configure as master 0 = manual configure as slave 10 port type r/w see descr. update a write to this register bit does not take effect until any of the following also occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation copper link goes down. register 9_0.10 is ignored if register 9_0.12 is equal to 1. upon hardware reset this bit takes on the value of sel_ms. 1 = prefer multi-port device (master) 0 = prefer single port device (slave) 9 1000base-t full-duplex r/w 0x1 update a write to this register bit does not take effect until any of the following also occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation link goes down 1 = advertise 0 = not advertised 8 1000base-t half-duplex r/w see descr. update a write to this register bit does not take effect until any of the following also occurs: software reset is asserted (register 0_0.15) restart auto-negotiation is asserted (register 0_0.9) power down (register 0_0.11, 16_0.2) transitions from power down to normal operation copper link goes down. upon hardware reset this bit takes on the value of c_aneg[0]. 1 = advertise 0 = not advertised
I347-AT4?programmer?s visible state 74 4.1.11 1000base-t status regist er - page 0, register 10 4.1.12 extended status regist er - page 0, register 15 7:0 reserved r/w 0x00 retain 0 bits field mode hw rst sw rst description 15 master/slave configuration fault ro,lh 0x0 0x0 this register bit will clear on read. 1 = master/slave configuration fault detected 0 = no master/slave configuration fault detected 14 master/slave configuration resolution ro 0x0 0x0 1 = local phy configuration resolved to master 0 = local phy configuration resolved to slave 13 local receiver status ro 0x0 0x0 1 = local receiver ok 0 = local receiver is not ok 12 remote receiver status ro 0x0 0x0 1 = remote receiver ok 0 = remote receiver not ok 11 link partner 1000base-t full-duplex capability ro 0x0 0x0 1 = link partner is capable of 1000base-t full-duplex 0 = link partner is not capable of 1000base-t full-duplex 10 link partner 1000base-t half-duplex capability ro 0x0 0x0 1 = link partner is capable of 1000base-t half-duplex 0 = link partner is not capable of 1000base-t half-duplex 9:8 reserved ro 0x0 0x0 reserved 7:0 idle error count ro, sc 0x00 0x00 msb of idle error counter these register bits report the idle error count since the last time this register was read. the counter pegs at 11111111 and will not roll over. bits field mode hw rst sw rst description 15 reserved ro always 0 always 0 reserved 14 reserved ro always 0 always 0 reserved 13 1000base-t full-duplex ro always 1 always 1 1 =1000base-t full-duplex capable 12 1000base-t half-duplex ro always 1 always 1 1 =1000base-t half-duplex capable 11:0 reserved ro 0x000 0x000 000000000000 bits field mode hw rst sw rst description
75 programmer?s visible state?I347-AT4 4.1.13 copper specific control regi ster 1 - page 0, register 16 bits field mode hw rst sw rst description 15 disable link pulses r/w 0x0 0x0 1 = disable link pulse 0 = enable link pulse 14:12 downshift counter r/w 0x3 update changes to these bits are disruptive to the normal operation; therefore, any changes to these registers must be followed by software reset to take effect. 1x, 2x, ...8x is the number of times the phy attempts to establish gigabit link before th e phy downshifts to the next highest speed. 000 = 1x 100 = 5x 001 = 2x 101 = 6x 010 = 3x 110 = 7x 011 = 4x 111 = 8x 11 downshift enable r/w 0x0 update changes to these bits are disruptive to the normal operation; therefore, any changes to these registers must be followed by software reset to take effect. 1 = enable downshift. 0 = disable downshift. 10 force copper link good r/w 0x0 retain if link is forced to be good, the link state machine is bypassed and the link is always up. in 1000base-t mode this has no effect. 1 = force link good 0 = normal operation 9:8 cable detect r/w see descr. update upon hardware reset both bits takes on the inverted value of dis_sleep. 0x = off 10 = sense only on receive (cable detect) 11 = sense and periodically transmit nlp (cable detect) 7 enable extended distance r/w 0x0 retain when using cable exceedin g 100m, the 10base-t receive threshold must be lowered in order to detect incoming signals. 1 = lower 10base-t receive threshold 0 = normal 10base-t receive threshold 6:5 mdi crossover mode r/w see descr. update changes to these bits are disruptive to the normal operation; therefore, any changes to these registers must be followed by a software reset to take effect. upon hardware reset bits defaults as follows: ena_xc bits 6:5 0 01 1 11 00 = manual mdi configuration 01 = manual mdix configuration 10 = reserved 11 = enable automatic crossover for all modes 4 reserved r/w 0x0 retain set to 0 3 copper transmitter disable r/w 0x0 retain 1 = transmitter disable 0 = transmitter enable 2 power down r/w 0x0 retain power down is controlled via register 0_0.11 and 16_0.2. both bits must be set to 0 before the phy will transition from power down to normal operation. when the port is switched from power down to normal operation, software reset and restart auto-negotiation are performed even when bits reset (0_0.15) and restart auto- negotiation (0_0.9) are not set by the user. 1 = power down 0 = normal operation
I347-AT4?programmer?s visible state 76 4.1.14 copper specific status register 1 - page 0, register 17 1 polarity reversal disable r/w 0x0 retain if polarity is disabled, then the polarity is forced to be normal in 10base-t. 1 = polarity reversal disabled 0 = polarity reversal enabled the detected polarity status is shown in register 17_0.1, or in 1000base-t mode, 21_5.3:0. 0 disable jabber r/w 0x0 retain jabber has effect only in 10base-t half-duplex mode. 1 = disable jabber function 0 = enable jabber function bits field mode hw rst sw rst description 15:14 speed ro 0x2 retain these status bits are valid only after resolved bit 17_0.11 = 1. the resolved bit is set when au to-negotiation is completed or auto-negotiation is disabled. 11 = reserved 10 = 1000 mbps 01 = 100 mbps 00 = 10 mbps 13 duplex ro 0x0 retain this status bit is valid only after resolved bit 17_0.11 = 1. the resolved bit is set when auto -negotiation is completed or auto-negotiation is disabled. 1 = full-duplex 0 = half-duplex 12 page received ro, lh 0x0 0x0 1 = page received 0 = page not received 11 speed and duplex resolved ro 0x0 0x0 when auto-negotiation is not enabled 17_0.11 = 1. 1 = resolved 0 = not resolved 10 copper link (real time) ro 0x0 0x0 1 = link up 0 = link down 9 transmit pause enabled ro 0x0 0x0 this is a reflection of the mac pause resolution. this bit is for information purposes and is not used by the device. this status bit is valid only after resolved bit 17_0.11 = 1. the resolved bit is set when auto -negotiation is completed or auto-negotiation is disabled. 1 = transmit pause enabled 0 = transmit pause disable 8 receive pause enabled ro 0x0 0x0 this is a reflection of the mac pause resolution. this bit is for information purposes and is not used by the device. this status bit is valid only after resolved bit 17_0.11 = 1. the resolved bit is set when auto -negotiation is completed or auto-negotiation is disabled. 1 = receive pause enabled 0 = receive pause disabled 7 reserved ro 0x0 0x0 0 6 mdi crossover status ro 0x1 retain this status bit is valid only after resolved bit 17_0.11 = 1. the resolved bit is set when auto -negotiation is completed or auto-negotiation is disabled. th is bit is 0 or 1 depending on what is written to 16.6:5 in manual configuration mode. register 16.6:5 are updated with software reset. 1 = mdix 0 = mdi bits field mode hw rst sw rst description
77 programmer?s visible state?I347-AT4 4.1.15 copper specific interrupt enable register - page 0, register 18 5 downshift status ro 0x0 0x0 1 = downshift 0 = no downshift 4 copper cable detect status ro 0x0 0x0 1 = sleep 0 = active 3 global link status ro 0x0 0x0 1 = copper link is up 0 = copper link is down 2 dte power status ro 0x0 0x0 1 = link partner needs dte power 0 = link partner does not need dte power 1 polarity (real time) ro 0x0 0x0 1 = reversed 0 = normal polarity reversal can be disabled by writing to register 16_0.1. in 1000base-t mode, po larity of all pairs are shown in register 21_5.3:0. 0 jabber (real time) ro 0x0 0x0 1 = jabber 0 = no jabber bits field mode hw rst sw rst description 15 auto-negotiation error interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable 14 speed changed interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable 13 duplex changed interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable 12 page received interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable 11 auto-negotiation completed interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable 10 link status changed interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable 9 symbol error interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable 8 false carrier interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable 7 reserved r/w 0x0 retain 0 6 mdi crossover changed interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable 5 downshift int errupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable bits field mode hw rst sw rst description
I347-AT4?programmer?s visible state 78 4.1.16 copper interrupt status re gister - page 0, register 19 4 copper cable detect interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable 3 flp exchange complete but no link interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable 2 dte power detection status changed interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable 1 polarity changed interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable 0 jabber interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable bits field mode hw rst sw rst description 15 copper auto- negotiation error ro,lh 0x0 0x0 an error is said to occur if master/slave does not resolve, parallel detect fault, no common hcd, or link does not come up after negotiation is completed. 1 = auto-negotiation error 0 = no auto-negotiation error 14 copper speed changed ro,lh 0x0 0x0 1 = speed changed 0 = speed not changed 13 copper duplex changed ro,lh 0x0 0x0 1 = duplex changed 0 = duplex not changed 12 copper page received ro,lh 0x0 0x0 1 = page received 0 = page not received 11 copper auto- negotiation completed ro,lh 0x0 0x0 1 = auto-negotiation completed 0 = auto-negotiation not completed 10 copper link status changed ro,lh 0x0 0x0 1 = link status changed 0 = link status not changed 9 copper symbol error ro,lh 0x0 0x0 1 = symbol error 0 = no symbol error 8 copper false carrier ro,lh 0x0 0x0 1 = false carrier 0 = no false carrier 7 reserved ro always 0 always 0 0 6 mdi crossover changed ro,lh 0x0 0x0 1 = crossover changed 0 = crossover not changed 5 downsh ift interrupt ro,lh 0x0 0x0 1 = downshift detected 0 = no down shift bits field mode hw rst sw rst description
79 programmer?s visible state?I347-AT4 4.1.17 copper specific control regi ster 2 - page 0, register 20 4 copper cable detect changed ro,lh 0x0 0x0 1 = cable detect state changed 0 = no cable detect state change detected 3 flp exchange complete but no link ro,lh 0x0 0x0 1 = flp exchange completed but link not established 0 = no event detected 2 dte power detection status changed interrupt ro,lh 0x0 0x0 1 = dte power detection status changed 0 = no dte power detection status change detected 1 polarity changed ro,lh 0x0 0x0 1 = polarity changed 0 = polarity not changed 0jabber ro,lh0x00x0 1 = jabber 0 = no jabber bits field mode hw rst sw rst description 15:7 reserved r/w 0x000 retain write all 0s 6 break link on insufficient ipg r/w 0x0 retain 0 = break link on insufficient ipgs in 10base-t and 100base- tx. 1 = do not break link on insuffi cient ipgs in 10base-t and 100base-tx. 5 100 base-t transmitter clock source r/w 0x1 update 1 = local clock 0 = recovered clock 4 accelerate 100base-t link up r/w 0x0 retain 0 = no acceleration 1 = accelerate 3 reverse mdip/ n[3] transmit polarity r/w 0x0 retain 0 = normal transmit polarity 1 = reverse transmit polarity 2 reverse mdip/ n[2] transmit polarity r/w 0x0 retain 0 = normal transmit polarity 1 = reverse transmit polarity 1 reverse mdip/ n[1] transmit polarity r/w 0x0 retain 0 = normal transmit polarity 1 = reverse transmit polarity 0 reverse mdip/ n[0] transmit polarity r/w 0x0 retain 0 = normal transmit polarity 1 = reverse transmit polarity bits field mode hw rst sw rst description
I347-AT4?programmer?s visible state 80 4.1.18 copper specific receive erro r counter register - page 0, register 21 4.1.19 page address register - any page, register 22 4.1.20 global interrupt stat us - page 0, register 23 4.1.21 copper specific control regi ster 3 - page 0, register 26 bits field mode hw rst sw rst description 15:0 receive error count ro, lh 0x0000 retain counter will peg at 0xffff and will not roll over. both false carrier and symbol errors are reported. bits field mode hw rst sw rst description 15 ignore phyad[4:2] r/w 0x0 retain 0 = use phyad[4:2] to decode write commands 1 = ignore phyad[4:2] to decode write commands 14 ignore phyad[1:0] r/w 0x0 retain 0 = use phyad[1:0] to decode write commands 1 = ignore phyad[1:0] to decode write commands 13:8 reserved ro 0x00 0x00 00000000 7:0 page select for registers 0 to 28 r/w 0x00 retain page number bits field mode hw rst sw rst description 15:4 reserved ro 0x000 0x000 0 3:0 port x interrupt ro 0x0 0x0 1 = interrupt active on port x 0 = no interrupt active on port x bits field mode hw rst sw rst description 15 1000 base-t transmitter type r/w 0x0 retain 0 = class b 1 = class a 14 reserved r/w 0x0 retain write 0 13 reserved r/w 0x0 retain write 0 12 100 base-t transmitter type r/w 0x0 retain 0 = class b 1 = class a 11:10 gigabit link down delay r/w 0x0 retain this register only have effect if register 26_0.9 is set to 1. 00 = 0ms 01 = 10 2ms 10 = 20 2ms 11 = 40 2ms 9 speed up gigabit link down time r/w 0x0 retain 1 = enable faster gigabit link down 0 = use ieee gigabit link down
81 programmer?s visible state?I347-AT4 4.1.22 phy identifier register - page 1, register 4.1.23 phy identifier register - page 1, register 3 4.1.24 extended status register - page 1, register 15 8 dte detect enable r/w 0x0 update 1 = enable dte detection 0 = disable dte detection 7:4 dte detect status drop hysteresis r/w 0x4 retain 0000: report immediately 0001: report 5s after dte power status drop ... 1111: report 75s after dte power status drop 3:2 100 mb test select r/w 0x0 retain 0x = normal operation 10 = select 112 ns sequence 11 = select 16 ns sequence 1 10 bt polarity force r/w 0x0 retain 1 = force negative polarity for receive only 0 = normal operation 0 reserved r/w 0x0 retain set to 0 bits field mode hw rst sw rst description 15:0 organizationally unique identifier bit 3:18 ro 0x0141 0x0141 oui is 0x005043 0000 0000 0101 0000 0100 0011 ^ ^ bit 1....................................bit 24 register 2.[15:0] show bits 3 to 18 of the oui. 0000000101000001 ^ ^ bit 3...................bit18 bits field mode hw rst sw rst description 15:10 oui lsb ro always 000011 0x00 organizationally unique identifier bits 19:24 000011 ^.........^ bit 19...bit24 9:4 model number ro always 011100 0x00 model number 011100 3:0 revision number ro always 0000 0x0 rev number = 0000 bits field mode hw rst sw rst description 15 1000base-x full-duplex ro see descr see descr if register 16_1.1:0 (mode[1:0]) = 00 then this bit is 0, else this bit is 1. 1 = 1000base-x full-duplex capable 0 = not 1000base-x full-duplex capable bits field mode hw rst sw rst description
I347-AT4?programmer?s visible state 82 4.1.25 prbs control - page 1, register 23 4.1.26 prbs error counter lsb - page 1, register 24 4.1.27 prbs error counter msb - page 1, register 25 14 1000base-x half-duplex ro see descr see descr if register 16_1.1:0 (mode[1:0]) = 00 then this bit is 0, else this bit is 1. 1 = 1000base-x half-duplex capable 0 = not 1000base-x half-duplex capable 13 1000base-t full- duplex ro 0x0 0x0 0 = not 1000base-t full-duplex capable 12 1000base-t half-duplex ro 0x0 0x0 0 = not 1000base-t half-duplex capable 11:0 reserved ro 0x000 0x000 000000000000 bits field mode hw rst sw rst description 15:8 reserved r/w 0x00 retain set to 0s 7 invert checker polarity r/w 0x0 retain 0 = invert 1 = normal 6 invert generator polarity r/w 0x0 retain 0 = invert 1 = normal 5 prbs lock r/w 0x0 retain 0 = counter free runs 1 = do not start counting until prbs locks first 4clear counterr/w, sc0x00x0 0 = normal 1 = clear counter 3:2 reserved r/w 0x0 retain set to 0s 1 prbs checker enable r/w 0x0 0x0 0 = disable 1 = enable 0 prbs generator enable r/w 0x0 0x0 0 = disable 1 = enable bits field mode hw rst sw rst description 15:0 prbs error count lsb ro 0x0000 retain a read to this register freezes register 25_1. cleared only when register 23_1.4 is set to 1. bits field mode hw rst sw rst description 15:0 prbs error count msb ro 0x0000 retain this register does not update unless register 24_1 is read first. cleared only when register 23_1.4 is set to 1. bits field mode hw rst sw rst description
83 programmer?s visible state?I347-AT4 4.1.28 mac specific control register 1 - page 2, register 16 4.1.29 mac specific interrupt enable register - page 2, register 18 bits field mode hw rst sw rst description 15:14 copper transmit fifo depth r/w 0x1 retain 00 = 16 bits 01 = 24 bits 10 = 32 bits 11 = 40 bits 13 reserved r/w 0x0 update set to 0 12 rclk frequency select r/w 0x0 retain 0 = 25 mhz 1 = 125 mhz 11 rclk link down disable r/w 0x0 retain 0 = rclk outputs 25 mhz clock during link down and 10base-t. 1 = rclk low during link down and 10base-t. 10 reserved r/w 0x0 retain set to 0 9 rclk2 select r/w 0x0 retain the highest numbered port with this bit set will output the clock. the 125 mhz recovered clock is output as is or divided by 5 and output on rclk2 depending on the setting of 16_2.12. 1 = output recovered clock on rclk2 0 = do not output recovered clock on rclk2 8 rclk1 select r/w 0x0 retain the highest numbered port with this bit set will output the clock. the 125 mhz recovered clock is output as is or divided by 5 and output on rclk1 depending on the setting of 16_2.12. 1 = output recovered clock on rclk1 0 = do not output recovered clock on rclk1 7 copper reference clock source select r/w 0x0 update changes to this bit are disruptive to the normal operation; therefore, any changes to these registers must be followed by a software reset to take effect. 1 = use sclk as 25mhz source 0 = use xtal_in/ref_clkp/n as source 6 reserved r/w 0x0 update reserved 5:4 reserved r/w 0x0 retain set to 0s 3 mac interface power down r/w 0x1 update changes to this bit are disruptive to the normal operation; therefore, any changes to these registers must be followed by a software reset to take effect. this bit determines whether the mac interface powers down when register 0_0.11, 16_0.2 ar e used to power down the device or when the phy enters the cable detect state. 1 = always power up 0 = can power down 2:0 reserved r/w 0x0 retain set to 0s bits field mode hw rst sw rst description 15:8 reserved r/w 0x00 retain 000000000 7 fifo over/ underflow interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable
I347-AT4?programmer?s visible state 84 4.1.30 mac specific status register - page 2, register 19 4.1.31 copper rx_er byte capture - page 2, register 20 6:4 reserved r/w 0x0 retain 000 3 fifo idle inserted interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable 2 fifo idle deleted interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable 1:0 reserved r/w 0x0 retain 00 bits field mode hw rst sw rst description 15:8 reserved ro always 00 always 00 00000000 7 copper fifo over/underflow ro,lh 0x0 0x0 1 = over/underflow error 0 = no fifo error 6:4 reserved ro always 0 always 0 000 3 copper fifo idle inserted ro,lh 0x0 0x0 1 = idle inserted 0 = no idle inserted 2 copper fifo idle deleted ro,lh 0x0 0x0 1 = idle deleted 0 = idle not deleted 1:0 reserved ro always 0 always 0 00 bits field mode hw rst sw rst description 15 capture data valid ro 0x0 0x0 1 = bits 14:0 valid 0 = bits 14:0 invalid 14 reserved ro 0x0 0x0 0 13:12 byte number ro 0x0 0x0 00 = 4 bytes before rx_er asserted 01 = 3 bytes before rx_er asserted 10 = 2 bytes before rx_er asserted 11 = 1 byte before rx_er asserted the byte number increments after every read when register 20_2.15 is set to 1. 11:10 reserved ro 0x0 0x0 000 9 rx_er ro 0x0 0x0 rx error. normally this bit will be low si nce the capture is triggered by rx_er being high. however it is possible to see an rx_er high when the capture is re-enabled after reading the fourth byte and there happens to be a long sequence of rx_er when the capture restarts. 8 rx_dv ro 0x0 0x0 rx data valid bits field mode hw rst sw rst description
85 programmer?s visible state?I347-AT4 4.1.32 mac specific control register 2 - page 2, register 21 4.1.33 led[3:0] function control register - page 3, register 16 7:0 rxd[7:0] ro 0x00 0x00 rx data bits field mode hw rst sw rst description 15 reserved r/w 0x0 0x0 0 14 copper line loopback r/w 0x0 0x0 1 = enable loopback of mdi to mdi 0 = normal operation 13:12 reserved r/w 0x1 update 1 11:7 reserved r/w 0x00 0x00 00000 6 reserved r/w 0x1 update 1 5:4 reserved r/w 0x0 retain 0 3 block carrier extension bit r/w 0x0 retain 1 = enable block carrier extension 0 = disable block carrier extension 2:0 default mac interface speed r/w 0x6 update changes to these bits are disrup tive to the normal operation; therefore, any changes to these registers must be followed by software reset to take effect. mac interface speed during link down while auto- negotiation is enabled. bit speed 0xx = reserved 100 = 10 mbps 101 = 100 mbps 110 = 1000 mbps 111 = reserved bits field mode hw rst sw rst description 15:12 led[3] control r/w 0x1 retain if 16_3.11:10 is set to 11 then 16_3.15:12 has no effect 0000 = on - reserved, off - else 0001 = on - link, blink - activity, off - no link 0010 = on - link, blink - receive, off - no link 0011 = on - activity, off - no activity 0100 = blink - activity, off - no activity 0101 = reserved 0110 = on - 10 mb/s or 1000 mb/s master, off - else 0111 = on - full-duplex, off - half-duplex 1000 = force off 1001 = force on 1010 = force hi-z 1011 = force blink 11xx = reserved bits field mode hw rst sw rst description
I347-AT4?programmer?s visible state 86 11:8 led[2] control r/w 0x7 retain 0000 = on - link, off - no link 0001 = on - link, blink - activity, off - no link 0010 = ptp output 0011 = on - activity, off - no activity 0100 = blink - activity, off - no activity 0101 = on - transmit, off - no transmit 0110 = on - 10/1000 mbps link, off - else 0111 = on - 10 mbps link, off - else 1000 = force off 1001 = force on 1010 = force hi-z 1011 = force blink 1100 = mode 1 (dual led mode) 1101 = mode 2 (dual led mode) 1110 = mode 3 (dual led mode) 1111 = mode 4 (dual led mode) 7:4 led[1] control r/w 0x7 retain if 16_3.3:2 is set to 11 then 16_3.7:4 has no effect 0000 = on - copper link, off - else 0001 = on - link, blink - activity, off - no link 0010 = on - link, blink - receive, off - no link 0011 = on - activity, off - no activity 0100 = blink - activity, off - no activity 0101 = on - 100 mb/s link, off - else 0110 = on - 100/1000 mb/s link, off - else 0111 = on - 100 mb/s link, off - else 1000 = force off 1001 = force on 1010 = force hi-z 1011 = force blink 11xx = reserved 3:0 led[0] control r/w 0x7 retain 0000 = on - link, off - no link 0001 = on - link, blink - activity, off - no link 0010 = 3 blinks - 1000 mb/s 2 blinks - 100 mb/s 1 blink - 10 mb/s 0 blink - no link 0011 = on - activity, off - no activity 0100 = blink - activity, off - no activity 0101 = on - transmit, off - no transmit 0110 = on - copper link, off - else 0111 = on - 1000 mb/s link, off - else 1000 = force off 1001 = force on 1010 = force hi-z 1011 = force blink 1100 = mode 1 (dual led mode) 1101 = mode 2 (dual led mode) 1110 = mode 3 (dual led mode) 1111 = mode 4 (dual led mode) bits field mode hw rst sw rst description
87 programmer?s visible state?I347-AT4 4.1.34 led[3:0] polarity control register - page 3, register 17 4.1.35 led timer control regist er - page 3, register 18 bits field mode hw rst sw rst description 15:12 led[5], led[3], led[1] mix percentage r/w 0x8 retain when using 2 terminal bi-color leds the mixing percentage should not be set greater than 50%. 0000 = 0% 0001 = 12.5% ... 0111 = 87.5% 1000 = 100% 1001 to 1111 = reserved 11:8 led[4], led[2], led[0] mix percentage r/w 0x8 retain when using 2 terminal bi-color leds the mixing percentage should not be set greater than 50%. 0000 = 0% 0001 = 12.5% ... 0111 = 87.5% 1000 = 100% 1001 to 1111 = reserved 7:6 led[3] polarity r/w 0x0 retain 00 = on - drive led[3] low, off - drive led[3] high 01 = on - drive led[3] high, off - drive led[3] low 10 = on - drive led[3] low, off - tristate led[3] 11 = on - drive led[3] high, off - tristate led[3] 5:4 led[2] polarity r/w 0x0 retain 00 = on - drive led[2] low, off - drive led[2] high 01 = on - drive led[2] high, off - drive led[2] low 10 = on - drive led[2] low, off - tristate led[2] 11 = on - drive led[2] high, off - tristate led[2] 3:2 led[1] polarity r/w 0x0 retain 00 = on - drive led[1] low, off - drive led[1] high 01 = on - drive led[1] high, off - drive led[1] low 10 = on - drive led[1] low, off - tristate led[1] 11 = on - drive led[1] high, off - tristate led[1] 1:0 led[0] polarity r/w 0x0 retain 00 = on - drive led[0] low, off - drive led[0] high 01 = on - drive led[0] high, off - drive led[0] low 10 = on - drive led[0] low, off - tristate led[0] 11 = on - drive led[0] high, off - tristate led[0] bits field mode hw rst sw rst description 15 force intn r/w 0x0 retain 1 = interrupt pin forced to be asserted 0 = normal operation 14:12 pulse stretch duration r/w 0x4 retain 000 = no pulse stretching 001 = 21 ms to 42 ms 010 = 42 ms to 84 ms 011 = 84 ms to 170 ms 100 = 170 ms to 340 ms 101 = 340 ms to 670 ms 110 = 670 ms to 1.3 s 111 = 1.3 s to 2.7 s 11 reserved r/w 0x1 retain must be set to 1.
I347-AT4?programmer?s visible state 88 4.1.36 led[5:4] function control and polarity - page 3, register 19 10:8 blank rate r/w 0x1 retain 000 = 42 ms 001 = 84 ms 010 = 170 ms 011 = 340 ms 100 = 670 ms 101 to 111 = reserved 7:4 reserved r/w 0x0 retain 0000 3:2 speed off pulse period r/w 0x1 retain 00 = 84 ms 01 = 170 ms 10 = 340 ms 11 = 670 ms 1:0 speed on pulse period r/w 0x1 retain 00 = 84 ms 01 = 170 ms 10 = 340 ms 11 = 670 ms bits field mode hw rst sw rst description 15 led[3] function pin mapping r/w 0x0 retain 0 = map led[3] function to led[3] pin 1 = map led[5] function to led[3] pin 14 led[2] function pin mapping r/w 0x0 retain 0 = map led[2] function to led[2] pin 1 = map led[4] function to led[2] pin 13 filter ptp activity r/w 0x0 retain 1 = filter ptp packets from led activity 0 = do not filter ptp packets from led activity 12 reserved r/w 0x0 retain 0 11:10 led[5] polarity r/w 0x0 retain 00 = on - drive led[5] low, off - drive led[5] high 01 = on - drive led[5] high, off - drive led[5] low 10 = on - drive led[5] low, off - tristate led[5] 11 = on - drive led[5] high, off - tristate led[5] 9:8 led[4] polarity r/w 0x0 retain 00 = on - drive led[4] low, off - drive led[4] high 01 = on - drive led[4] high, off - drive led[4] low 10 = on - drive led[4] low, off - tristate led[4] 11 = on - drive led[4] high, off - tristate led[4] bits field mode hw rst sw rst description
89 programmer?s visible state?I347-AT4 4.1.37 sgmii link partner ability re gister - sgmii (media mode) mode (register 16_4.0 = 1b) - page 4, register 5 7:4 led[5] control r/w 0x7 retain if 19_3.3:2 is set to 11 then 19_3.7:4 has no effect 0000 = on - receive, off - no receive 0001 = on - link, blink - activity, off - no link 0010 = on - link, blink - receive, off - no link 0011 = on - activity, off - no activity 0100 = blink - activity, off - no activity 0101 = on - transmit, off - no transmit 0110 = on - full-duplex, off - half-duplex 0111 = on - full-duplex, blink - collision off - half-duplex 1000 = force off 1001 = force on 1010 = force hi-z 1011 = force blink 11xx = reserved 3:0 led[4] control r/w 0x3 retain 0000 = on - receive, off - no receive 0001 = on - link, blink - activity, off - no link 0010 = on - link, blink - receive, off - no link 0011 = on - activity, off - no activity 0100 = blink - activity, off - no activity 0101 = on - transmit, off - no transmit 0110 = on - full-duplex, off - half-duplex 0111 = on - full-duplex, blink - collision off - half-duplex 1000 = force off 1001 = force on 1010 = force hi-z 1011 = force blink 1100 = mode 1 (dual led mode) 1101 = mode 2 (dual led mode) 1110 = mode 3 (dual led mode) 1111 = mode 4 (dual led mode) bits field mode hw rst sw rst description 15 link ro 0x0 0x0 register bit is cleared when link goes down and loaded when a base page is received received code word bit 15 1 = copper link is up on the link partner 0 = copper link is not up on the link partner 14 acknowledge ro 0x0 0x0 register bit is cleared when link goes down and loaded when a base page is received acknowledge received code word bit 14 1 = link partner received link code word 0 = link partner has not received link code word 13 reserved ro 0x0 0x0 register bit is cleared when link goes down and loaded when a base page is received received code word bit 13 must be 0 bits field mode hw rst sw rst description
I347-AT4?programmer?s visible state 90 4.1.38 cable tester tx to mdi[0] rx coupling - page 5, register 16 12 duplex status ro 0x0 0x0 register bit is cleared when link goes down and loaded when a base page is received received code word bit 12 1 = copper interface on the link partner is capable of full- duplex 0 = copper interface on the link partner is capable of half- duplex 11:10 speed status ro 0x0 0x0 register bits are cleared when link goes down and loaded when a base page is received received code word bit 11:10 00 = 10 mbps 01 = 100 mbps 10 = 1000 mbps 11 = reserved 9 tra ns m i t pa us e status ro 0x0 0x0 this bit is non-zero only if the link partner supports enhanced sgmii auto negotiation. received code word bit 9 1 = enabled 0 = disabled 8 receive pause status ro 0x0 0x0 this bit is non-zero only if the link partner supports enhanced sgmii auto negotiation. received code word bit 8 1 = enabled 0 = disabled 7 copper status ro 0x0 0x0 this bit is non-zero only if the link partner supports enhanced sgmii auto negotiation. received code word bit 7 1 = reserved 0 = copper media 6:0 reserved ro 0x00 0x00 register bits are cleared when link goes down and loaded when a base page is received received code word bits 6:0 must be 0000001 bits field mode hw rst sw rst description 15 reflected polarity ro xx retain 1 = positive reflection 0 = negative reflection bits field mode hw rst sw rst description
91 programmer?s visible state?I347-AT4 note: this register reports the reflection seen based on the setting of register 23_5.13:11 000 = mdi[0] tx to mdi[0] rx 100 = mdi[0] tx to mdi[0] rx 101 = mdi[1] tx to mdi[0] rx 110 = mdi[2] tx to mdi[0] rx 111 = mdi[3] tx to mdi[0] rx 4.1.39 cable tester tx to mdi[1] rx coupling - page 5, register 17 14:8 reflected amplitude ro xx retain 0000000 = no reflection (0 mv) each bit above increases 7.8125mv. when 23_5.7 = 0 and 23_5.13:11 = 000 or 100 the reflected amplitude between the thresholds specified in registers 26_5, 27_5, 28_5.6:0, 26_7, 27 _7, and 28_7.6:0 are reported as 0 mv. when 23_5.7 = 0 and 23_5.13:11 is not 000 or 100 the reflected amplitude between the thresholds specified in register 25_5 and 25_7 are reported as 0 mv. when 23_5.7 = 1 the actu al offset or reflected amplitude is reported and the threshold specified in registers 25_5, 26_5, 27_5, 28_5, 25_7, 26_7, 27_7, and 28_7 are ignored. the amplitude value is va lid only when 23_5.14 = 1. if bit 15:8 = 0x00 indicates that the test failed. 7:0 distance ro xx retain distance of reflection. the distance value is valid only when 23_5.7 = 0 and 23_5.14 = 1. bits field mode hw rst sw rst description 15 reflected polarity ro xx retain 1 = positive reflection 0 = negative reflection 14:8 reflected amplitude ro xx retain 0000000 = no reflection (0 mv) each bit above increases 7.8125mv. when 23_5.7 = 0 and 23_5.13:11 = 000 or 101 the reflected amplitude between the thresholds specified in registers 26_5, 27_5, 28_5.6:0, 26_7, 27_7, and 28_7.6:0 are reported as 0 mv. when 23_5.7 = 0 and 23_5.13:11 is not 000 or 101 the reflected amplitude between the thresholds specified in register 25_5 and 25_7 are reported as 0 mv. when 23_5.7 = 1 the actual offset or reflected amplitude is reported and the threshold specified in registers 25_5, 26_5, 27_5, 28_5, 25_7, 26_7, 27_7, and 28_7 are ignored. the amplitude value is valid only when 23_5.14 = 1. if bit 15:8 = 0x00 indicates that the test failed. 7:0 distance ro xx retain distance of reflection. the distance value is valid only when 23_5.7 = 0 and 23_5.14 = 1. bits field mode hw rst sw rst description
I347-AT4?programmer?s visible state 92 note: this register reports the reflection seen based on the setting of register 23_5.13:11 000 = mdi[1] tx to mdi[1] rx 100 = mdi[0] tx to mdi[1] rx 101 = mdi[1] tx to mdi[1] rx 110 = mdi[2] tx to mdi[1] rx 111 = mdi[3] tx to mdi[1] rx 4.1.40 cable tester tx to mdi[2] rx coupling - page 5, register 18 note: this register reports the reflection seen based on the setting of register 23_5.13:11 000 = mdi[2] tx to mdi[2] rx 100 = mdi[0] tx to mdi[2] rx 101 = mdi[1] tx to mdi[2] rx 110 = mdi[2] tx to mdi[2] rx 111 = mdi[3] tx to mdi[2] rx 4.1.41 cable tester tx to mdi[3] rx coupling - page 5, register 19 bits field mode hw rst sw rst description 15 reflected polarity ro xx retain 1 = positive reflection 0 = negative reflection 14:8 reflected amplitude ro xx retain 0000000 = no reflection (0 mv) each bit above increases 7.8125mv. when 23_5.7 = 0 and 23_5.13:11 = 000 or 110 the reflected amplitude between the thresholds specified in registers 26_5, 27_5, 28_5.6:0, 26_7, 27_7, and 28_7.6:0 are reported as 0 mv. when 23_5.7 = 0 and 23_5.13: 11 is not 000 or 110 the reflected amplitude between th e thresholds specified in register 25_5 and 25_7 are reported as 0 mv. when 23_5.7 = 1 the actu al offset or reflected amplitude is reported and the threshold specified in registers 25_5, 26_5, 27_5, 28_5, 25_7, 26_7, 27_7, and 28_7 are ignored. the amplitude value is valid only when 23_5.14 = 1. if bit 15:8 = 0x00 indicates that the test failed. 7:0 distance ro xx retain distance of reflection. the distance value is valid only when 23_5.7 = 0 and 23_5.14 = 1. bits field mode hw rst sw rst description 15 reflected polarity ro xx retain 1 = positive reflection 0 = negative reflection
93 programmer?s visible state?I347-AT4 note: this register reports the reflection seen based on the setting of register 23_5.13:11 000 = mdi[3] tx to mdi[3] rx 100 = mdi[0] tx to mdi[3] rx 101 = mdi[1] tx to mdi[3] rx 110 = mdi[2] tx to mdi[3] rx 111 = mdi[3] tx to mdi[3] rx 4.1.42 1000base-t pair skew register - page 5, register 20 4.1.43 1000base-t pair swap and polarity - page 5, register 21 14:8 reflected amplitude ro xx retain 0000000 = no reflection (0 mv) each bit above increases 7.8125mv. when 23_5.7 = 0 and 23_5.13:11 = 000 or 111 the reflected amplitude between the thresholds specified in registers 26_5, 27_5, 28_5.6:0, 26_7, 27 _7, and 28_7.6:0 are reported as 0 mv. when 23_5.7 = 0 and 23_5.13:11 is not 000 or 111 the reflected amplitude between the thresholds specified in register 25_5 and 25_7 are reported as 0 mv. when 23_5.7 = 1 the actu al offset or reflected amplitude is reported and the threshold specified in registers 25_5, 26_5, 27_5, 28_5, 25_7, 26_7, 27_7, and 28_7 are ignored. the amplitude value is va lid only when 23_5.14 = 1. if bit 15:8 = 0x00 indicates that the test failed. 7:0 distance ro xx retain distance of reflection. the distance value is valid only when 23_5.7 = 0 and 23_5.14 = 1. bits field mode hw rst sw rst description 15:12 pair 7,8 (mdi[3]) ro 0x0 0x0 skew = bit value x 8ns. value is correct to within 8ns. the contents of 20_5.15:0 are valid only if register 21_5.6 = 1 11:8 pair 4,5 (mdi[2]) ro 0x0 0x0 skew = bit value x 8ns. value is correct to within 8ns. 7:4 pair 3,6 (mdi[1]) ro 0x0 0x0 skew = bit value x 8ns. value is correct to within 8ns. 3:0 pair 1,2 (mdi[0]) ro 0x0 0x0 skew = bit value x 8ns. value is correct to within 8ns. bits field mode hw rst sw rst description 15:7 reserved ro 0x000 0x000 reserved for future use. 6 register 20_5 and 21_5 valid ro 0x0 0x0 the contents of 21_5.5:0 and 20_5.15:0 are valid only if register 21_5.6 = 1 1= valid . 0 = invalid bits field mode hw rst sw rst description
I347-AT4?programmer?s visible state 94 4.1.44 cable tester contro l - page 5, register 23 5 c, d crossover ro 0x0 0x0 1 = channel c received on mdi[2] channel d received on mdi[3] 0 = channel d received on mdi[2] channel c received on mdi[3] 4 a, b crossover ro 0x0 0x0 1 = channel a received on mdi[0] channel b received on mdi[1] 0 = channel b received on mdi[0] channel a received on mdi[1] 3 pair 7,8 (mdi[3]) polarity ro 0x0 0x0 1 = negative 0 = positive 2 pair 4,5 (mdi[2]) polarity 0x0 0x0 1 = negative 0 = positive 1 pair 3,6 (mdi[1]) polarity ro 0x0 0x0 1 = negative 0 = positive 0 pair 1,2 (mdi[0]) polarity ro 0x0 0x0 1 = negative 0 = positive bits field mode hw rst sw rst description 15 enable test r/w, sc 0x0 0x0 0 = disable test 1 = enable test this bit will self clear when the test is completed 14 test status ro 0x0 0x0 0 = test not started/in progress 1 = test completed 13:11 transmitter channel select r/w 0x0 0x0 000 - tx 0 => rx 0, tx 1 => rx 1, tx 2 => rx 2, tx 3 => rx 3. 100 - tx 0 => rx 0, tx 0 => rx 1, tx 0 => rx 2, tx 0 => rx 3. 101 - tx 1 => rx 0, tx 1 => rx 1, tx 1 => rx 2, tx 1 => rx 3. 110 - tx 2 => rx 0, tx 2 => rx 1, tx 2 => rx 2, tx 2 => rx 3. 111 - tx 3 => rx 0, tx 3 => rx 1, tx 3 => rx 2, tx 3 => rx 3. 01x - reserved 0x1 - reserved 10:8 number of sample averaged r/w 6 retain 0 = 2 samples 1 = 4 samples 2 = 8 samples 3 = 16 samples 4 = 32 samples 5 = 64 samples 6 = 128 samples 7 = 256 samples bits field mode hw rst sw rst description
95 programmer?s visible state?I347-AT4 4.1.45 cable tester sample point distance - page 5, register 24 4.1.46 cable tester cross pair positi ve threshold - page 5, register 25 4.1.47 cable tester same pair impe dance positive threshold 0 and 1 - page 5, register 26 7:6 mode r/w 0x0 retain 00 = maximum peak above threshold 01 = first or last peak above threshold. see register 28_5.13. 10 = offset 11 = sample point at distance set by 24_5.7:0 5:0 peak detection hysteresis r/w 0x03 retain 0x00 = 0 mv, 0x01 = 7.81 mv,..., 0x3f = 492 mv bits field mode hw rst sw rst description 15:10 reserved ro 0x00 0x00 0 9:0 distance to measure/ distance to start r/w 0x000 retain when 23_5.7:6 = 11 the measur ement is taken at this distance. (00 to 3ff) when 23_5.7:6 = 0x any distance below this distance is not considered (00 to ff). bit 9:8 is ignored. bits field mode hw rst sw rst description 15 reserved ro 0x0 0x0 0 14:8 cross pair positive threshold > 30m r/w 0x01 retain 0x00 = 0 mv, 0x01 = 7.81 mv,..., 0x7f = 992 mv 7 reserved ro 0x0 0x0 0 6:0 cross pair positive threshold < 30m r/w 0x04 retain 0x00 = 0 mv, 0x01 = 7.81 mv,..., 0x7f = 992 mv bits field mode hw rst sw rst description 15 reserved ro 0x0 0x0 0 14:8 same-pair positive threshold 10m - 50m r/w 0x0f retain 0x00 = 0 mv, 0x01 = 7.81 mv,..., 0x7f = 992 mv 7 reserved ro 0x0 0x0 0 6:0 same-pair positive threshold < 10m r/w 0x12 retain 0x00 = 0 mv, 0x01 = 7.81 mv,..., 0x7f = 992 mv bits field mode hw rst sw rst description
I347-AT4?programmer?s visible state 96 4.1.48 cable tester same pair impe dance positive threshold 2 and 3 - page 5, register 27 4.1.49 cable tester same pair im pedance positive threshold 4 and transmit pulse control - page 5, register 28 bits field mode hw rst sw rst description 15 reserved ro 0x0 0x0 0 14:8 same-pair positive threshold 110m - 140m r/w 0x0a retain 0x00 = 0 mv, 0x01 = 7.81 mv,..., 0x7f = 992 mv 7 reserved ro 0x0 0x0 0 6:0 same-pair positive threshold 50m - 110m r/w 0x0c retain 0x00 = 0 mv, 0x01 = 7.81 mv,..., 0x7f = 992 mv bits field mode hw rst sw rst description 15:14 reserved ro 0x0 0x0 0 13 first peak/last peak select r/w 0x0 retain this register takes effect only if register 23_5.7:6 = 01. 0 = first peak 1 = last peak 12 break link prior to measurement r/w 0x0 retain 1 = do not wait 1.5s to break link before starting cable tester 0 = wait 1.5s to break link before starting cable tester 11:10 transmit pulse width r/w 0x0 retain 00 = full pulse (128ns) 01 = 3/4 pulse 10 = 1/2 pulse 11 = 1/4 pulse 9:8 tra ns m i t amplitude r/w 0x0 retain 00 = full amplitude 01 = 3/4 amplitude 10 = 1/2 amplitude 11 = 1/4 amplitude 7 distance measurement point r/w 0x0 retain if 23_5.7:6 = 00 then 0 = measure distance when amplitude drops to 50% of peak amplitude 1 = measure distance at actual maximum amplitude if 23_5.7:6 = 01 then 0 = measure distance when amplitude drops below hysteresis 1 = measure distance at actual maximum amplitude if 23_5.7:6 = 1x then this bit is ignored. 6:0 same-pair positive threshold > 140m r/w 0x06 retain 0x00 = 0 mv, 0x01 = 7.81 mv,..., 0x7f = 992 mv
97 programmer?s visible state?I347-AT4 4.1.50 packet generation - page 6, register 16 4.1.51 crc counters - page 6, register 17 4.1.52 checker control - page 6, register 18 bits field mode hw rst sw rst description 15:8 packet burst r/w 0x00 retain 0x00 = continuous 0x01 to 0xff = burst 1 to 255 packets 7:5 enable packet generator r/w, sc 0x0 retain 000 = normal operation 010 = generate packets on copper interface 100 = generate packets on sgmii interface 110 = reserved else = reserved 4:3 reserved r/w 0x0 retain set to 0 2 payload of packet to transmit r/w 0x0 retain 0 = pseudo-random 1 = 5a,a5,5a,a5,... 1 length of packet to transmit r/w 0x0 retain 1 = 1518 bytes 0 = 64 bytes 0 transmit an errored packet r/w 0x0 retain 1 = tx packets with crc errors & symbol error 0 = no error bits field mode hw rst sw rst description 15:8 packet count ro 0x00 retain 0x00 = no packets received 0xff = 256 packets received (max count). the crc error counter and frame counter must be enabled (reg 18_6.2:0) in order for this register to be valid. 7:0 crc error count ro 0x00 retain 0 x 0 0 = n o c r c e r r o r s d e t e c t e d i n t h e p a c k e t s r e c e i v e d . 0xff = 256 crc errors detected in the packets received (max count). the crc error counter and frame counter must be enabled (reg 18_6.2:0) in order for this register to be valid. bits field mode hw rst sw rst description 15:4 reserved r/w 0x000 retain set to 0s 3 enable stub test r/w 0x0 retain 1 = enable stub test 0 = normal operation 2:0 enable crc checker r/w 0x0 retain 000 = disable/reset crc checker 010 = check data from copper interface 100 = check data from sgmii interface 110 = reserved else = reserved
I347-AT4?programmer?s visible state 98 4.1.53 general control regist er - page 6, register 20 4.1.54 late collision counters 1 & 2 - page 6, register 23 bits field mode hw rst sw rst description 15 reset r/w, sc 0x0 sc mode software reset. affects page 6. writing a 1 to this bit causes the main phy state machines to be reset. when the reset operation is done, this bit is cleared to 0 automatically. the reset occurs immediately. 1 = phy reset 0 = normal operation 14:12 reserved r/w 0x0 retain set to 0s 11:10 snooping r/w 0x0 retain 00 = turn off snooping 01 = reserved 10 = snoop data from network 11 = snoop data from mac 9 reserved r/w 0x1 retain reservedp 8reserved r/w see descr. retain reserved 7reserved r/w see descr. retain reserved 6 reserved r/w 0x0 retain set to 0 5:4 preferred media r/w 0x0 retain 00 = link on first media 01 = copper preferred 10 = reserved 11 = reserved 3reserved r/w0x0update 0 = normal operation 1 = reserved. 2:0 mode[2:0] r/w see descr. update changes to this bit are disruptive to the normal operation; therefore, any changes to these registers must be followed by a software reset to take effect. on hardware reset these bits take on the value of mode[2:0]. 0x0 0x0 000 = reserved 001 = sgmii (system mode) to copper 010 = reserved 011 = reserved 100 = reserved 101 = reserved 110 = reserved 111 = reserved bits field mode hw rst sw rst description 15:8 late collision 97- 128 bytes ro, sc 0x00 retain this counter increments by 1 when the phy is in half-duplex and a start of packet is received while the 97th to 128th bytes of the packet are transmitted. the measurement is done at th e internal gmii interface. the counter will not roll over and will clear on read.
99 programmer?s visible state?I347-AT4 4.1.55 late collision counters 3 & 4 - page 6, register 24 4.1.56 late collision window adjust/link disconnect - page 6, register 25 4.1.57 misc test - page 6, register 26 7:0 late collision 65- 96 bytes ro, sc 0x00 retain this counter increments by 1 wh en the phy is in half-duplex and a start of packet is received while the 65th to 96th bytes of the packet are transmitted. the measurement is done at the internal gmii interface. the counter will not roll over and will clear on read. bits field mode hw rst sw rst description 15:8 late collision >192 bytes ro, sc 0x00 retain this counter increments by 1 when the phy is in half-duplex and a start of packet is received after 192 bytes of the packet are transmitted. the measurement is done at the internal gmii interface. the counter will not roll over and will clear on read. 7:0 late collision 129-192 bytes ro, sc 0x00 retain this counter increments by 1 when the phy is in half-duplex and a start of packet is received while the 129th to 192nd bytes of the packet are transmitted. the measurement is done at the internal gmii interface. the counter will not roll over and will clear on read. bits field mode hw rst sw rst description 15:13 reserved r/w 0x0 retain set to 0s 12:8 late collision window adjust r/w 0x00 retain number of bytes to advanc e in late collision window. 0 = start at 64th byte, 1 = start at 63rd byte, etc. 7:0 link disconnect ro, sc 0x00 retain this counter counts the number of times link status changed from up to down. the counter will not roll over and will clear on read. bits field mode hw rst sw rst description 15 tx_tclk enable r/w 0x0 0x0 the highest numbered enabled port will drive the transmit clock to the hsdacp/n pin. 1 = enable 0 = disable 14:13 reserved r/w 0x0 retain set to 0 12:8 te m p e ra t u r e threshold r/w 0x19 retain temperature in c = 5 x 26_6.4:0 - 25 i.e. for 100c the value is 11001 7 te m p e ra t u r e sensor interrupt enable r/w 0x0 retain 1 = interrupt enable 0 = interrupt disable 6 te m p e ra t u r e sensor interrupt ro, lh 0x0 0x0 1 = temperature reached threshold 0 = temperature below threshold bits field mode hw rst sw rst description
I347-AT4?programmer?s visible state 100 5 reserved r/w 0x0 retain set to 0 4:0 tem p era t u re sensor ro xxxxx xxxxx temperature in c = 5 x 26_6.4:0 - 25 i.e. for 100c the value is 11001 bits field mode hw rst sw rst description
101 programmer?s visible state?I347-AT4 note: this page intentionally left blank.
I347-AT4?electrical and timing specifications 102 5.0 electrical and timing specifications this section describes the electrical and timing specifications for the I347-AT4. table 39. absolute maximum ratings 1 stresses above those listed in ta b l e 3 9 might cause permanent device failure. functionality at or above these limits is no t implied. exposure to absolute maximum ratings for extended periods might affect device reliability. 5.1 recommended operating conditions 1. on power-up, no special power supply sequencing is required. symbol parameter min typ max units v ddah power supply voltage on avddh with respect to vss -0.5 2.5 v v dd power supply voltage on dvdd with respect to vss -0.5 1.5 v v ddol power supply voltage on vddol with respect to vss -0.5 3.6 v v ddor power supply voltage on vddor with respect to vss -0.5 3.6 v v ddom power supply voltage on vddom with respect to vss -0.5 3.6 v v ddc power supply voltage on vddc with respect to vss -0.5 2.5 v v pin voltage applied to any digital input pin -0.5 5.0 or vddo + 0.7, whichever is less v t storage storage temperature -55 +125 1 1. 125 c is only used as bake temperature for not more than 24 hours. long term storage (such as weeks or longer) should be kept at 85 c or lower. c symbol parameter condition min typ max units v ddah 1 avddh supply for avddh 1.8 1.9 2.0 v v ddc 1 vddc supply for vddc 1.8 1.9 2.0 v v dd 1 dvdd supply for dvdd at 1.0v 0.95 1.0 1.05 v v ddol 1 vddol supply for vddol at 1.9v 1.8 1.9 2.0 v v ddol 1 vddol supply for vddol at 3.3v 3.13 3.3 3.47 v
103 electrical and timing specifications?I347-AT4 5.2 current consumption symbol parameter condition min typ max units v ddor 1 vddor supply for vddor at 1.9v 1.8 1.9 2.0 v v ddor 1 vddor supply for vddor at 3.3v 3.13 3.3 3.47 v v ddom 1 vddom supply for vddom at 1.9v 1.8 1.9 2.0 v v ddom 1 vddom supply for vddom at 3.3v 3.13 3.3 3.47 v rset internal bias reference resistor connected to v ss 5000 1% to l e ra n c e w t a ambient operating temperature commercial parts 0 70 c t j maximum junction temperature 125 c 1. maximum noise allowed on su pplies is 50 mv peak-peak. # of ports conditions link state 3.3v current rail (ma) 1.9v current rail (ma) 1.0v current rail (ma) external power (mw) mode speed 4 max active 1000 mb/s 5.2 1051 876 3034 typ active 1000 mb/s 4.5 946 366 2179 100 mb/s 4.5 376 67 797 10 mb/s 4.5 571 42 1142 idle 1000 mb/s 4.5 948 334 2151 100 mb/s 4.5 377 69 800 10 mb/s 4.5 380 41 777 cable disconnect 4.5 126 37 292 2 max active 1000 mb/s 5.2 605 935 2195 typ active 1000 mb/s 4.5 539 200 1239 100 mb/s 4.5 245 50 530 10 mb/s 4.5 336 37 690 idle 1000 mb/s 4.5 533 186 1214 100 mb/s 4.5 250 51 541 10 mb/s 4.5 250 37 527 cable disconnect 4.5 134 36 305
I347-AT4?electrical and timing specifications 104 note: typical conditions: room temperature (ta) = 25 c, nominal voltages and continuous network traffic at full duplex. maximum conditions: maximum operating temp erature values, nominal voltage values and continuous network traffic at full duplex. 5.3 dc operating conditions 5.3.1 digital pins note: over full range of values listed in section 5.1 unless otherwise specified. # of ports conditions link state 3.3v current rail (ma) 1.9v current rail (ma) 1.0v current rail (ma) external power (mw) mode speed 1typ active 1000 mb/s 4.5 327 117 754 100 mb/s 4.5 187 42 412 10 mb/s 4.5 235 35 496 idle 1000 mb/s 4.5 328 113 752 100 mb/s 4.5 187 42 412 10 mb/s 4.5 187 36 406 cable disconnect 4.5 129 35 295 symbol parameter pins condition min typ max units vih input high voltage all digital inputs vddo = 3.3v 2.0 vddo + 0.6v v vih input high voltage all digital inputs vddo = 1.9v 1.26 vddo + 0.6v v vil input low voltage all digital inputs vddo = 3.3v -0.3 0.8 v vil input low voltage all digital inputs vddo = 1.9v -0.3 0.54 v voh high level output voltage all digital outputs ioh = -4 ma vddo - 0.4v v vol low level output voltage all digital outputs iol = 4 ma 0.4 v iilk input leakage current with internal pull-up resistor 10 -50 ua all others without resistor 10 ua
105 electrical and timing specifications?I347-AT4 5.3.2 ieee dc transceiver parameters ieee tests are typically based on template an d cannot simply be specified by a number. for an exact description of the template an d the test conditions, refer to the ieee specifications. ? 10base-t ieee 802.3 clause 14 ? 100base-tx ansi x3.263-1995 note: over full range of values listed in section 5.1 unless otherwise specified. 5.3.3 sgmii interface the I347-AT4 adds flexibility by enabling th e programmable output voltage swing and supply voltage option as described in section 2.3 . cin input capacitance all pins 5p f symbol parameter pins condition min typ max units v odiff absolute peak differential output voltage mdip/n[1:0] 10base-t no cable 2.2 2.5 2.8 v mdip/n[1:0] 10base-t cable model 585 1 1. ieee 802.3 clause 14, figure 14.9 shows th e template for the ?far end? wave form. th is template allows as little as 495 mv peak differential voltage at the far end receiver. mv mdip/n[1:0 100base-tx mode 0.950 1.0 1.050 v mdip/n[3:0] 1000base-t 2 2. ieee 802.3ab figure 40 -19 points a&b. 0.67 0.75 0.82 v overshoot 2 mdip/n[1:0] 100base-tx mode 0 5% v amplitude symmetry (positive/ negative) mdip/n[1:0] 100base-tx mode 0.98x 1.02x v+/v- v idiff peak differential input voltage mdip/n[1:0] 10base-t mode 585 3 3. the input test is actually a template test ; ieee 802.3 clause 14, figure 14.17 show s the template for the receive wave form. mv signal detect assertion mdip/n[1:0] 100base-tx mode 1000 460 4 4. the ansi tp-pmd specification requires th at any received signal with peak-to-peak differential amplitude greater than 1000 mv should turn on signal detect (internal signal in 100base -tx mode). the I347-AT4 accepts signals typically with 460 mv peak-to-peak differential amplitude. mv peak- peak signal detect de-assertion mdip/n[1:0] 100base-tx mode 200 360 5 5. the ansi-pmd specification requires that any received sign al with peak-to-peak differential amplitude less than 200 mv should de-assert signal detect (internal signal in 100base-tx mode). the I347-AT4 rejects signals typically with peak-to- peak differential amplitude less than 360 mv. mv peak- peak
I347-AT4?electrical and timing specifications 106 5.3.3.1 transmitter dc characteristics symbol parameter 1 1. parameters are measured with outputs ac connected with 100 differential load. min typ max units v oh output voltage high 1600 mv v ol output voltage low 700 mv v ring output ringing 10 mv |v od | 2 2. output amplitude is programmable by writing to register 26.2:0. output voltage swing (differential, peak) programmable - see section 4.1 . mv peak v os output offset voltag e (also called common mode voltage) variable - see section 5.3.3.3 for details. mv r o output impedance (single-ended) (50 termination) 40 60 s delta r o mismatch in a pair 10 % delta v od change in v od between 0 and 1 25 mv delta v os change in v os between 0 and 1 25 mv i s+ , i s- output current on short to vss 40 ma i s+- output current when s_out+ and s_out- are shorted 12 ma i x+ , i x- power off leakage current 10 ma
107 electrical and timing specifications?I347-AT4 5.3.3.2 transmitter dc characteristics table 40. programming sgmii output amplitude figure 20. cml i/os 5.3.3.3 common mode voltage (voffset) calculations there are four different main configurations for the sgmii interface connections. these are: ? dc connection to an lvds receiver ? ac connection to an lvds receiver ? dc connection to an cml receiver ? ac connection to an cml receiver if ac coupling or dc coupling to an lvds re ceiver is used, the dc output levels are determined by the following: ? internal bias. see section 3.2.5 and figure 20 for details. (if avddh is used to generate the internal bias, the internal bias value is typically 1.4v.) ? the output voltage swing is programmed by register 26_2.2:0 (see section 4.1 ). register 26_2 bits field description 2:0 sgmii output amplitude differential voltage peak measured. note that internal bias minus the diffe rential peak voltage must be greater than 700 mv. 000b = 14 mv 001b = 112 mv 010b = 210 mv 011b = 308 mv 100b = 406 mv 101b = 504 mv 110b = 602 mv 111b = 700 mv 50 ohm internal bias 1 s_in+ 50 ohm internal bias s_in- cml inputs cml outputs 50 ohm internal bias 1 50 ohm i sink s_out+ s_out- 1. internal bias is generated from the avddh supply and is typically 1.4v.
I347-AT4?electrical and timing specifications 108 voffset (such as, common mode voltage) = internal bias - single-ended peak-peak voltage swing. see figure 21 for details. if dc coupling is used with a cml receiver , then the dc levels are determined by a combination of the macs output structure an d the device input structure shown in the cml inputs diagram in figure 22 . assuming the same mac cml voltage levels and structure, the common mode output levels are determined by: ? voffset (such as, common mode voltage) = internal bias - single-ended peak-peak voltage swing/2. see figure 22 for details. ? if dc coupling is used, the output voltag e dc levels are determined by the ac coupling considerations previously described , plus the i/o buffer structure of the mac. figure 21. ac connections (cml or lvds re ceiver) or dc connec tion lvds receiver cml outputs 50 ohm internal bias 1 50 ohm i sink s_out+ s_out- (opposite of s_out+) 1. internal bias is generated from the avddh supply and is typically 1.4v. ac coupling cap. v = internal bias - vpeak v = voffset v = voffset (i.e., common mode voltage) = internal bias - vpeak-peak vmin = internal bias - 3 * vpeak vmin must be greater than 700 mv single-ended voltage details s_outp s_outn internal bias - vpeak vpeak
109 electrical and timing specifications?I347-AT4 figure 22. dc connection to a cml receiver 5.3.3.4 receiver dc characteristics symbol parameter min typ max units v i input voltage range a or b 675 1725 mv v idth 1 1. receiver is at high level when v s_inp - v s_inn is greater than v idth (min) and is at low level when v s_inp - v s_inn is less than -v idth (min) . a minimum hysterisis of v hyst is present between -v idth and +v idth as shown in figure 23 . input differential threshold 200 2100 mv (peak- peak differential) v hyst 1 input differential hysteresis 25 mv r in receiver 100 differential input impedance 80 120 cml outputs 50 ohm internal bias 1 50 ohm i sink s_out+ s_out- (opposite of s_out+) 1. internal bias is generated from the avddh supply and is typically 1.4v. v = internal bias v = voffset v = internal bias - vpeak-peak v = voffset (i.e., common mode voltage) = internal bias - vpeak vmin = internal bias - vpeak-peak (single ended) (v min must be greater than 700 mv) single-ended voltage details s_outp s_outn internal bias internal bias 50 ohm internal bias 1 s_in+ 50 ohm internal bias s_in- cml inputs vpeak
I347-AT4?electrical and timing specifications 110 figure 23. input differential hysteresis 5.4 ac electrical specifications 5.4.1 reset timing over a full range of values listed in section 5.1 unless otherwise specified. figure 24. reset timing -v idth v idth v s_in+ - v s_in- v hyst receiver high receiver low -50 mv +50 mv symbol parameter condition min typ max units t pu_reset valid power to reset de- asserted 10 ms t su_xtal_in number of valid xtal_in cycles prior to reset de- asserted 10 clks t reset minimum reset pulse width during normal operation 10 ms power xtal reset t pu_reset t su_xtal_in t reset
111 electrical and timing specifications?I347-AT4 5.4.2 xtal_in/xtal_out (clk_sel[1:0] = 10b or 11b 1 ) timing 2 over a full range of values listed in section 5.1 unless otherwise specified. figure 25. xtal_in/xtal_out timing 5.4.3 led to config timing 1. see section 3.21 for details. 2. if the crystal option is used, ensure that the fr equency is 25 mhz 50 pp m. capacitors must be chosen carefully. refer to the application note supplied by crystal vendor. symbol parameter condition min typ max units t p_xtal_in xtal_in period 40 -50 ppm 40 40 +50 ppm ns t h_xtal_in xtal_in high time 13 20 27 ns t l_xtal_in xtal_in low time 13 20 27 ns t r_xtal_in xtal_in rise 10% to 90% - 3.0 - ns t f_xtal_in xtal_in fall 90% to 10% - 3.0 - ns t j_xtal_in xtal_in total jitter 1 1. pll generated clocks are not recommended as input to xtal_in since they can have excessive jitter. zero delay buffers are als o not recommended for the same reason. - - 200 ps 2 2. in sgmii to copper mode, broadband peak-peak = 200 ps, 12 khz to 20 mhz rms = 3 ps. symbol parameter condition min typ max units t dly_config led to config delay 0 25 ns t p_xtal_in t h_xtal_in t l_xtal_in t r_xtal_in t f_xtal_in xtal_in
I347-AT4?electrical and timing specifications 112 figure 26. led-to-config timing 5.4.4 serial led timing figure 27. serial led timing diagram symbol parameter min typ max units t per clock, strobe period 20 ns t pw clock, strobe high/low time 5.0 ns t su shift in to clock setup 4.0 ns t hd shift in clock hold 1.5 ns t cs clock rising edge to strobe rising edge 4.0 ns t dly clock to shift out delay, strobe to led out delay 2.0 12 ns t dly_config config led clk_sel[0] config[1] config[2] rclk p*_led[*] tsu thd tdly tcs tdly tpw tpw tper tpw tpw tper
113 electrical and timing specifications?I347-AT4 5.5 sgmii interface timing 5.5.1 sgmii output ac characteristics figure 28. serial interfac e rise and fall times 5.5.2 sgmii input ac characteristics symbol parameter min typ max units t fall v od fall time (20% - 80%) 100 200 ps t rise v od rise time (20% - 80%) 100 200 ps clock clock signal duty cycle @ 625 mhz 48 52 % t skew1 1 1. skew measured at 50% of the transition. skew between two members of a differential pair 20 ps t outputjitter total output jitter tolerance (deterministic + 14*rms random) 127 ps symbol parameter min typ max units t inputjitter total input jitter tolerance (deterministic + 14*rms random) 599 ps s_outp/n t rise t fall s_clkp/n t fall t soutput t rise
I347-AT4?electrical and timing specifications 114 5.6 mdc/mdio timing over a full range of values listed in section 5.1 unless otherwise specified. figure 29. mdc/mdio timing figure 30. mdc/mdio input hysteresis symbol parameter condition min typ max units t dly_mdio mdc to mdio (output) delay time 020ns t su_ mdio mdio (input) to mdc setup time 10 ns t hd_ mdio mdio (input) to mdc hold time 10 ns t p_ mdc mdc period 83.333 ns 1 1. maximum frequency = 12 mhz. t h_ mdc mdc high 30 ns t l_ mdc mdc low 30 ns v hyst vddo input hysteresis 360 mv valid data mdc t hd_mdio t su_mdio mdc t p_mdc t dly_mdio mdio (output) mdio (input) t h_mdc t l_mdc v hyst high low v in
115 electrical and timing specifications?I347-AT4 5.7 jtag timing over a full range of values listed in section 5.1 unless otherwise specified. figure 31. jtag timing 5.8 ieee ac transceiver parameters ieee tests are typically based on templates and cannot simply be specified by number. for an exact description of the templates an d the test conditions, refer to the ieee specifications: ? 10base-t ieee 802.3 clause 14-2000 ? 100base-tx ansi x3.263-1995 ? 1000base-t ieee 802.3ab clause 40 section 40.6.1.2. figure 40-26 shows the template waveforms for transmitter electrical specifications. symbol parameter condition min typ max units t p_tck tck period 60 ns t h_tck tck high 12 ns t l_tck tck low 12 ns t su_tdi tdi, tms to tck setup time 10 ns t hd_tdi tdi, tms to tck hold time 10 ns t dly_tdo tck to tdo delay 0 15 ns tck tdo t dly_tdo t su_tdi t hd_tdi t h_tck t l_tck tms tdi t p_tck
I347-AT4?electrical and timing specifications 116 over a full range of values listed in section 5.1 unless otherwise specified. 5.9 latency timing 5.9.1 10/100/1000base-t to sgmii latency timing over a full range of values listed in section 5.1 unless otherwise specified. symbol parameter pins condition min typ max units t rise rise time mdip/n[1:0] 100base-tx 3.0 4.0 5.0 ns t fall fall time mdip/n[1:0] 100base-tx 3.0 4.0 5.0 ns t rise/ tfall symmetry mdip/n[1:0] 100base-tx 0 0.5 ns dcd duty cycle distortion mdip/n[1:0] 100base-tx 0 0.5 1 1. ansi x3.263-1995 figure 9-3. ns, peak-peak tra n sm it jitter mdip/n[1:0] 100base-tx 0 1.4 ns, peak-peak symbol parameter condition min typ max units t as_mdi_sert x_1000 mdi ssd1 to s_outp/n start of packet 292 1,2 1. in 1000base-t, the signals on the four md i pairs arrive at different times because of the skew introduced by the cable. all t iming on mdip/n[3:0] is referenced from the latest arriving signal. 336 ns t da_mdi_sertx_ 1000 mdi csreset, csextend, csextend_err to s_outp/ n/t/ 292 1,2,3 2. assumes register 16.13:12 is set to 00b, which is the minimum latency. each increase in setting adds 8 ns of latency 1000 mb/s, 40 ns in 100 mb/s, and 400 ns in 10 mb/s. 3. minimum and maximum values on end of pa cket assume zero frequency drift between the received signal on mdi and s_outp/ n. the worst case variation is outside these limits if th ere is a frequency difference. 336 ns t as_mdi_sert x_100 mdi /j/ to s_outp/n start of packet 620 2 732 ns t da_mdi_sertx_ 100 mdi /t/ to s_outp/n/t/ 620 2,3 732 ns t as_mdi_sert x_10 mdi preamble to s_outp/ n start of packet 4817 2,4 4. actual values depend on number of bits in preamble and number of dr ibble bits, since nibbles on m ii are aligned to start of f rame delimiter and dribble bits are truncated. 5603 ns t da_mdi_sertx_ 10 mdi etd to s_outp/n/t/ 4817 2,3,4 5603 ns
117 electrical and timing specifications?I347-AT4 figure 32. 10/100/1000base-t-to-sgmii latency timing 5.9.2 sgmii to 10/100/1000base-t latency timing over a full range of values listed in section 5.1 unless otherwise specified. mdi preamble /k/ /j/ ssd2 ssd1 /t/ /r/ csreset etd 1000 100 10 (csextend, csextend_err) t da_mdi_sertx t as_mdi_sertx /t/ /s/ s_outp/n 1st /s/ 1st /t/ symbol parameter condition min typ max units t as_serrx_mdi_ 1000 s_inp/n start of packet /s/ to mdi ssd1 192 1 1. assumes register 16.15:14 is set to 00b, which is the minimum latency. each increase in sett ing adds 8 ns of latency in 1000 mb/s, 40 ns in 100 mb/s, and 400 ns in 10 mb/s. 216 ns t da_serrx_mdi_ 1000 s_inp/n /t/ to mdi csreset, csextend, csextend_err 192 1,2 2. minimum and maximum values on end of packet assume zero frequency drift between the tran smitted signal on mdi and the received signal on s_inp/n. the worst case variation is outside these limits, if there is a frequency difference. 216 ns t as_serrx_mdi_ 100 s_inp/n start of packet /s/ to mdi /j/ 528 1 612 ns t da_serrx_mdi_ 100 s_inp/n /t/ to mdi /t/ 528 1,2 612 ns t as_serrx_mdi_ 10 s_inp/n start of packet /s/ to mdi preamble 3822 1 4634 ns t da_serrx_mdi_ 10 s_inp/n /t/ to mdi etd 3822 1,2 4634 ns
I347-AT4?electrical and timing specifications 118 figure 33. sgmii-to-10/100/1000base-t latency timing 5.9.2.1 10/100/1000base-t to sgmii latency timing (register 27_4.14 = 1b) over a full range of values listed in section 5.1 unless otherwise specified. /s/ s_inp/n /t/ 1st /s/ 1st /t/ preamble /k/ /j/ ssd2 ssd1 /t/ /r/ csreset etd (csextend, csextend_err) t da_serrx_mdi t as_serrx_mdi mdi 1000 100 10 symbol parameter condition min typ max units t as_mdi_sert x_1000 mdi ssd1 to s_outp/n start of packet 404 1,2 1. in 1000base-t the signals on the four mdi pairs arrive at differe nt times because of the skew introduced by the cable. all ti ming on mdip/n[3:0] is referenced from the latest arriving signal. 484 ns t da_mdi_sertx_ 1000 mdi csreset, csextend, csextend_err to s_outp/ n /t/ 404 1,2,3 2. assumes register 16.13:12 is set to 00b, which is the minimum latency. each increase in setting adds 8 ns of latency 1000 mb/s, 40 ns in 100 mb/s, and 400 ns in 10 mb/s. 3. minimum and maximum values on end of packet assume zero fr equency drift between the received signal on mdi and s_outp/ n. the worst case variation is outside these limits if th ere is a frequency difference. 484 ns t as_mdi_sert x_100 mdi /j/ to s_outp/n start of packet 1048 2 1300 ns t da_mdi_sertx_ 100 mdi /t/ to s_outp/n /t/ 1048 2,3 1300 ns t as_mdi_sert x_10 mdi preamble to s_outp/ n start of packet 8577 2,4 4. actual values depend on number of bits in preamble and numbe r of dribble bits, since nibbles on mii are aligned to start of f rame delimiter and dribble bits are truncated. 10583 ns t da_mdi_sertx_ 10 mdi etd to s_outp/n /t/ 8577 2,3,4 10583 ns
119 electrical and timing specifications?I347-AT4 figure 34. 10/100/1000base-t to sgmii latency timing (register 27_4.14 = 1b) 5.9.2.2 sgmii to 10/100/1000base-t latency timing (register 27_4.14 = 1b) over a full range of values listed in section 5.1 unless otherwise specified. mdi preamble /k/ /j/ ssd2 ssd1 /t/ /r/ csreset etd 1000 100 10 (csextend, csextend_err) t da_mdi_sertx t as_mdi_sertx /t/ /s/ s_outp/n 1st /s/ 1st /t/ symbol parameter condition min typ max units t as_serrx_ mdi_1000 s_inp/n start of packet /s/ to mdi ssd1 304 1 1. assumes register 16.15:14 is set to 00b, which is the minimum latency. each increase in sett ing adds 8 ns of latency in 1000 mb/s, 40 ns in 100 mb/s, and 400 ns in 10 mb/s. 364 ns t da_serrx_ mdi_1000 s_inp/n/t/ to mdi csreset, csextend, csextend_err 304 1,2 2. minimum and maximum values on end of packet assume zero frequency drift between the transmitted signal on mdi and the received signal on s_inp/n. the worst case variation is outside these limits, if there is a frequency difference. 364 ns t as_serrx_ mdi_100 s_inp/n start of packet /s/ to mdi /j/ 952 1 1180 ns t da_serrx_ mdi_100 s_inp/n /t/ to mdi /t/ 952 1,2 1180 ns t as_serrx_ mdi_10 s_inp/n start of packet /s/ to mdi preamble 7582 1 9615 ns t da_serrx_ mdi_10 s_inp/n/t/ to mdi etd 7582 1,2 9615 ns
I347-AT4?electrical and timing specifications 120 figure 35. sgmii to 10/100/1000base-t latency timing (register 27_4.14 = 1b) 5.10 crystal specifications parameter name symbol recommended value max/min range conditions frequency fo 25.000 [mhz] @25 [c] vibration mode fundamental frequency tolerance ? f/fo @25c 30 [ppm] @25 [c] temperature tolerance ? f/fo 30 [ppm] 0 to +70 [c] series resistance rs 50 [ ? ] max @25 [mhz] crystal load capacitance cload 18 [pf] shunt capacitance co 6 [pf] max drive level d l 500 [ w] max aging ? f/fo 5 ppm per year max calibration mode parallel insulation resistance ir 500 [m ? ] min @ 100 v dc external capacitors c1, c2 27 [pf] /s/ s_inp/n /t/ 1st /s/ 1st /t/ preamble /k/ /j/ ssd2 ssd1 /t/ /r/ csreset etd (csextend, csextend_err) t da_serrx_mdi t as_serrx_mdi mdi 1000 100 10
121 electrical and timing specifications?I347-AT4 figure 36. crystal layout i347 25 mhz c1 c2 xtal_in xtal_out
I347-AT4?package 122 6.0 package the I347-AT4 is a 15 x 15 mm 196-pin tfbga halogen free package . table 41. 196-pin tfbga package dimensions (mm) 1. controlling dimension : millimeter. 2. primary datum c and seating plane are defined by the spherical crowns of the solder balls. 3. dimension b is measured at the maximum solder ball diameter, parallel to primary datum c. 4. there shall be a minimum clearance of 0.25mm between the edge of the solder ball and the body edge. dimension in mm max 1.50 15.10 --- --- 0.60 --- 0.50 --- 15.10 --- d 15.00 14.90 note : md/me ddd eee fff 14/14 0.12 0.25 0.10 --- --- 0.40 --- 14.90 e aaa bbb ccc b d1 e1 e 1.00 0.20 0.25 0.35 0.50 13.00 15.00 13.00 min 0.30 --- --- --- a a2 c a1 symbol 0.89 0.36 0.40 --- nom
123 package?I347-AT4 6.1 196-pin tfbga package figure 37. 196-pin tfbga pa ckage mechanical drawing 2 detail : b cavity (note 2) seating plane detail : a 8 "b" a b 21 5 34 67 l g d c e f h j k m p n "a" e d1 14 11 910 12 13 e1 a 1 b pin #1 d e c (note 3) ?b solder ball a1 a2 a
I347-AT4?package 124 note: this page intentionally left blank.
125 thermal design recommendations ? I347-AT4 7.0 thermal design recommendations 7.1 introduction this section can be used as an aid to designing a thermal solution for systems implementing the i347- at4 product line. it details the maximum allowabl e operating junction and case temperatures and provides the methodology necessary to measure these values. it also outlines the results of thermal simulations of the I347-AT4 in a standard jedec test environment with a 2s2p board using various thermal solutions. 7.2 intended audience the intended audience for this section is system design engineers using the I347-AT4. system designers are required to address component and system-level thermal challenges as the market continues to adopt products with higher speeds and port densities. new designs might be required to provide more effective cooling solutions for silicon de vices depending on the type of system and target operating environment. 7.3 thermal considerations in a system environment, the temperature of a co mponent is a function of both the system and component thermal characteristics. system-level thermal constraints consist of the local ambient temperature at the component, the airflow over the component and surrounding board, and the physical constraints at, above, and surrounding the component that might limit the size of a thermal solution. the component's case and die temperature are the result of: ? component power dissipation ?component size ? component packaging materials ? type of interconnection to the substrate and motherboard ? presence of a thermal cooling solution ? power density of the substrate, nearby components, and motherboard all of these parameters are pushed by the continued trend of technology to increase performance levels (higher operating speeds, mhz) and power densit y (more transistors). as operating frequencies increase and package size decreases, the power de nsity increases and the thermal cooling solution space and airflow become more constrained. the result is an increased emphasis on optimizing system design to ensure that thermal design requirements are met for each component in the system.
126 I347-AT4 ? thermal design recommendations 7.4 thermal management importance the objective of thermal management is to ensu re that all system component temperatures are maintained within their functional limits. the functional temperatur e limit is the range in which the electrical circuits are expected to meet specif ied performance requirements. operation outside the functional limit can degrade system performance, ca use logic errors, or cause device and/or system damage. temperatures exceeding the maximum operating limits can result in irreversible changes in the device operating characteristics. also note that sustained operation at a component maximum temperature limit might affect long-term device reliability. see section 7.6.2 for more details. 7.5 terminology and definitions the following is a list of the terminology that is used in this section and their definitions: tfbga ? thin profile fine pitch ball grid array: a surface-mount package using a bga structure whose pcb-interconnect method consists of a pb-free solder ball array on the interconnect side of the package and is attached to a near chip-scale size substrate. 2s2p ? a 4-layer board with two signal layers on the outside and two internal plane layers. thermal resistance ? the resulting change in temperature per watt of heat that passes from one reference point to another. junction ? refers to a p-n (diode) junction on the s ilicon. in this section, it is used as a temperature reference point (for example, ja refers to the junction-to-ambient thermal resistance). ambient ? refers to the local ambient temperature of the bulk air approaching the component. it can be measured by placing a thermocouple approxim ately 1 inch upstream from the component edge. lands ? the pads on the pcb to which bga balls are soldered. pcb ? printed circuit board. printed circuit assembly (pca) ? a pcb that has components assembled on it. thermal design power (tdp) ? the estimated ma ximum possible/expected power generated in a component by a realistic application. tdp is a sy stem design target associated with the maximum component operating temperature specifications. maximum power values are determined based on typical dc electrical specification and maximum ambient temperature for a worst-case realistic application running at maximum use. lfm ? a measure of airflow velocity in linear feet per minute. ja (theta ja) ? thermal resistance from component junction to ambient, c/w. jt (psi jt) ? junction-to-top (of package) thermal characterization parameter, c/w. jt does not represent thermal resistance, but instead is a characteristic parameter that can be used to convert between t j and t case when knowing the total tdp. jt is easy to characterize in simulations or measurements and is defined as follows: this parameter can vary with environmental conditions, such as airflow, thermal solution presence, and design.
127 thermal design recommendations ? I347-AT4 7.6 package thermal/mechanical specifications and limits 7.6.1 thermal limits - max junction/case to ensure proper operation of the I347-AT4, the ther mal solution must dissipate the heat generated by the component and maintain a case temperature at or below the values listed in ta b l e 7 . 1 . ta b l e 7 . 2 lists the thermal performance paramete rs per jedec jesd51-2 standard. the I347-AT4 is designed to operate properly as long as the t case rating is not exceeded. section 7.10.1 describes the proper guidelines for measuring the case temperature. table 7.1. absolute maximum junction/case temperature the thermal limits previously defined are based on simulated results of the package assembled on a standard multi-layer, 2s2p board with 1 oz internal planes and 2 oz external trace layers in a forced convection environment. the maximum case te mperature is based on the maximum junction temperature and defined by the relationship, t case-max = t j-max ? ( jt * p tdp ) where jt is the junction-to-top (of package) thermal characterization parameter. if the case temperature exceeds the specified t case-max , thermal enhancements such as heat sinks or forced air are required. analysis indicates that real applications are unlikely to cause the I347-AT4 to be at t case-max for sustained periods of time, given a properly desi gned thermal solution. sustained operation at t case-max might affect long-term reliability of the I347-AT4 and the system and thus should be avoided. application measured tdp (w) t case-max (c) 1 1. max t case is based on 27 x 27 x 10 mm thermalloy heat sink as shown in figure 7.3 . I347-AT4 3.0 w @ 125 c t j-max 108.11
128 I347-AT4 ? thermal design recommendations 7.6.2 thermal specifications ta b l e 7 . 2 lists the package-specific parameters under different conditions and environments. the values ja and jt should be used as references only as they can vary by system environments and thermal solutions. unless otherwise noted, the simu lations were run in a jedec environment with a four layer (2s2p), 76.2 mm x 114.3 mm board with no heat sink. table 7.2. package thermal characteristics in standard jedec environment for reference 7.6.3 mechanical limits - ma ximum static normal load the I347-AT4 package is capable of sustaining a ma ximum static normal load of 8 lbf (35.6 n). this load is an evenly distributed, uniform, compressive load in a direction perpendicular to the top surface of the package. this limit must not be exceeded duri ng heat sink installation, mechanical stress testing, standard shipping conditions, and/or any other use co ndition. the load put on the package by the heat sink attachment method should also not exceed th is value. the pcb under the package must be fully supported during heat sink installation to prevent an y deformation of the pcb. this load specification is based on limited testing for design characterization, and is for the package only. parameter equation conditions no heat sink (c/w) heat sink 1 (c/w) 1 1. 101.5 mm x 114.5 mm, 2s2p jedec board using 19 x 19 x 6.3 mm alpha novatech* heat sink as shown in figure 7.2 . heat sink 2 (c/w) 2 2. 101.5 mm x 114. 5mm, 2s2p jedec board using 27 x 27 x 10 mm thermalloy* heat sink as shown in figure 7.3 . ja p = tdp no airflow 31 22 19.2 1 m/s 28.3 16.4 14 2 m/s 27 14 12.1 3 m/s 25.9 - - jt p = tdp no airflow 0.75 5.3 5.4 1 m/s 0.87 5.4 5.6 2 m/s 0.96 5.5 5.63 3 m/s 1.03 - - jc p top = power through top of package no airflow 7.9 - - jb p bot = power through bottom of package no airflow 23.5 - -
129 thermal design recommendations ? I347-AT4 7.6.4 mechanical specifications the I347-AT4 is packaged in a 15 x 15 mm tfbga as shown in figure 7.1 . figure 7.1. I347-AT4 tf bga mechanical drawing 7.7 thermal solutions one method frequently used to improve thermal perfor mance is to attach a metallic heat sink to the top of the device. the heat sink increases the surface area exposed to the ambient air promoting higher rates of heat transfer. this in turn reduces the ther mal resistance from the device junction to the air ( ja ). in order to be effective, heat sinks should have a pocket of air around them that is free of obstructions. this enables air to more easily flow thro ugh the fins of the heat sink, further increasing its effectiveness. good system airflow is critical to dissipate the hi ghest possible thermal power. the size and number of fans, vents, and ducts, as well as their placement in relation to components and airflow channels within the system determine the airflow path and volumetr ic flow rates throughout the system. note that acoustic noise constraints might limit the size and type s of fans, vents, and ducts that can be used in a particular design.
130 I347-AT4 ? thermal design recommendations to develop a robust, reliable, cost-effective thermal solution, all system variables must be considered. use system-level thermal characteristics and simulations to account for individual component thermal requirements. 7.7.1 extruded heat sinks if required, the following extruded heat sinks are suggested for I347-AT4 thermal solutions. they can be seen as shown in figure 7.2 and figure 7.3 with their respective mechanical drawings. figure 7.2. 6.3 mm tall passive heat sink (alpha novatech, inc. pn: z19-6.3b)
131 thermal design recommendations ? I347-AT4 figure 7.3. 10 mm tall passive heat si nk (aavid thermalloy pn: 374324b60023g) 7.7.2 thermal interface materi als for heat sink solutions to maximize the effectiveness of any thermal solution, it is important to understand the interface between the package surface and th e heat sink base. the purpose of the thermal interface material (tim) is to enhance the heat transfer between two objects in contact (see figure 7.4 ). at a microscopic level, surfaces are often rough and contain many pe aks and valleys. they only contact each other at random points across the interfacing surfaces, thus heat only conducts effectively through those small points of contact. heat also conducts through the air in the areas that are not touching; however, air is a very poor thermal conductor. this results in a high thermal resistance between the two objects. when a thermal interface material is applied, it f ills the remaining gaps between the two surfaces and provides a much more effective heat path. this enab les more heat to conduct through to the heat sink, reducing the temperature drop across the interface.
132 I347-AT4 ? thermal design recommendations figure 7.4. tim function 7.7.2.1 tim types and performance there are several different types of tims, such as: ? greases ? a tacky, liquid like substance. ? phase change materials (pcm) ? a material that starts out as a dry film and changes to a liquid above a specific temperature. ? gap pads ? compressible (typically) non-liquid ma terial designed to fill a large gap between the heat sink and package. ? pressure sensitive adhesives (psa's) ? a permanent adhesive applied to the bottom of a heat sink. pcms and greases tend to be the most effective as they offer the thinnest bond lines with great wetting/spreading characteristics. the effectiveness of each of these different material types is governed primarily by the following: ? material wetting/filling characteristics ? determines how well the material flows to fill in the small gaps between interfacing surfaces. the more complete ly the material fills the voids at the interface, the lower the resulting thermal resistance. ? bond line thickness ? the resulting thickness of material between the heat sink and package surface once the heat sink has been installed and the material has heated to its equilibrium temperature. greases and phase change materials te nd to flow after they have been heated above a temperature specific to that tim. ? material thermal conductivity ? the thermal conductivity of the interface material. while the wetting and thermal conductivity are ma terial dependent characteristics, the bond line thickness is primarily controlled by the interfacial pressure between the heat sink and package (as well as the tim malleability). typically, higher interfacial pressure leads to lower thermal conductivity as demonstrated (for example only) in the plot the follows.
133 thermal design recommendations ? I347-AT4 figure 7.5. thermal impedance vs. interfacial pressure note: caution should be taken so that the maximum normal force as explained in section 7.6.3 is never exceeded. 7.7.2.2 pcm45 series tim the recommended thermal interface material is the pcm45 series from honeywell*. the pcm45 series thermal interface pads are phase change materials formulated for use in high performance devices requiring minimum thermal resistance for maximum heat sink performance and component reliability. these pads consist of an electrically non-conductive, dry film that softens at device operating temperatures resulting in a greasy-like performance. however, intel has not fully validated the pcm45 series tim. if adequate thermal margin exists, cheaper tim with less performance can be used, especially for low power applications. the selected material should be fully evaluated for long term reliability issues such as dry-out and pump-out (if applicable). double-sid ed psas should also be carefully evaluated to ensure they provide robust, long term re liability and will not lose their adhesion. other tim vendors to consider are laird*, chromerics*, and 3m*. 7.7.3 attaching the extruded heat sink there are several different ways of attaching the heat sink to the component such as sheet metal clips, wire gates, psas, or spring loaded push pins. each of these solutions has their own pros and cons. for detailed attaching methods, please contact the heat sink manufacturer. a well designed clip, wire gate, or spring loaded push pin can offer a high level of reliability and rework-ability.
134 I347-AT4 ? thermal design recommendations 7.8 reliability each pca, system, heat sink, and tim combination varies in attach strength, long-term adhesive performance, and tim reliability. carefully evaluate the reliability of the completed assembly prior to high-volume use. some reliability recommendations are listed in ta b l e 7 . 3 . table 7.3. reliability validation 7.9 jedec simulation results 7.9.1 designing for thermal performance section 7.12 and section 7.13 describe the pcb and system design recommendations that can aid in achieving the I347-AT4 thermal performance documented in this section. 7.9.2 simulation setup a simulation environment conforming to the jedec jesd51-2 standard was developed using a 101.5 mm x 114.5 mm, 2s2p board according to jedec jesd 51-9. simulations were run with different combinations of ambient temperature and airflow sp eed for three different thermal solution scenarios as follows: ?no heat sink ? 19 mm x 19mm x 6.3 mm heat sink ( figure 7.2 ) ? 27 mm x 27 mm x 10 m heat sink ( figure 7.3 ) note: keep the following in mind when reviewing th e data that is included in this section: ? all data is preliminary and is not validated against physical samples. ? your system design might be significantly different. ? a larger board with more than four copper layers might improve I347-AT4 thermal performance. test requirement pass/fail criteria mechanical shock 50 g trapezoidal, board level 11 ms, 3 shocks/axis visual and electrical check. random vibration 7.3 g, board level 45 minutes/axis, 50 to 2000 hz visual and electrical check. high temperature life 85 c 2000 hours total checkpoints occur at 168, 500, 1000, and 2000 hours visual and mechanical/electrical check. thermal cycling per-target environment (for example: -40 c to +85 c) 500 cycles visual and mechanical/electrical check. humidity 85% relative humidity 85 c, 1000 hours visual and mechanical/electrical check.
135 thermal design recommendations ? I347-AT4 7.9.3 simulation results table 4 shows the t case as a function of airflow and ambient temperature with the component operating at the tdp in the environment previously listed. th is table can be used as an aid in determining a starting point for the optimum airflow and heat sink combination for the I347-AT4. again, your system design might vary considerab ly from the environment used to generate these values. note: thermal models are available upon request (f lotherm*: detailed model). contact your local intel sales representative for I347-AT4 thermal models. table 7.4. thermal simulation results for va rious environmental conditions @ 3 w tdp airflow (lfm) note: no heat sink. airflow (lfm) note: 19 x 19 x 6.3 mm alpha novatech hs in figure 7.2 . t c 0 50 100 150 200 250 300 350 400 tem p era t u re ( c) 45 143.9 139.1 136.4 134.8 133.5 132.4 131.7 130.9 130.1 50 148.6 143.9 141.3 139.6 138.3 137.3 136.6 135.8 135.1 55 153.1 148.6 146.1 144.5 143.2 142.3 141.5 140.7 140 60 157.7 153.4 150.9 149.4 148.1 147.2 146.4 145.6 145 65 162.3 158.3 155.8 154.2 153 152.1 151.3 150.5 149.9 70 166.9 163.1 160.6 159.1 157.9 157 156.3 155.5 154.8 75 171.5 167.9 165.5 164 162.8 161.9 161.2 160.4 159.8 80 176.1 172.7 170.3 168.8 167.7 166.8 166.1 165.4 164.7 85 180.7 177.5 175.2 173.7 172.6 171.7 171.1 170.3 169.6 t c 0 50 100 150 200 250 300 350 400 tem p era t u re ( c) 45 94.96 88.46 84.77 81.01 78.06 75.55 73.62 72.06 70.88 50 99.25 93.19 88.63 85.23 82.54 80.47 78.57 77.01 75.83 55 103.8 97.95 92.96 89.82 87.41 85.4 83.51 81.96 80.54 60 108.4 102.7 97.76 94.54 92.23 90.32 88.45 86.91 85.67 65 112.9 107.5 102.6 99.33 97.16 95.24 93.39 91.86 90.62 70 117.5 112.3 107.4 104.1 102 100.2 98.32 96.81 95.58 75 122.1 117.1 112.3 108.9 106.8 105.1 103.3 101.8 100.5 80 126.7 122.1 117.1 113.8 111.8 110 108.2 106.7 105.5 85 131.3 126.7 122 118.6 116.7 114.9 113.1 111.7 110.4
136 I347-AT4 ? thermal design recommendations airflow (lfm) note: 27 x 27 10 mmmm thermalloy hs in figure 7.3 . the red value(s) indicate airflow/ambient combinations that exceed the allowable case temperature for the I347-AT4 at 3.0 w. 7.10 component measur ement methodology measurement methodologies for determining the case and junction temperature are outlined in the sections that follow. 7.10.1 case temperature measurements special care is required when measuring the t case temperature to ensure an accurate temperature measurement is produced. use the following guidelines when measuring t case : ? use 36-gauge (maximum) k-type thermocouples. ? calibrate the thermocouple before making temperature measurements. ? measure the surface temperature of the case in the geometric center of the case top. note: it is critical that the thermocouple bead be completely in contact with the package surface. ? use thermally conductive epoxies, as necessary (again, ensuring the thermocouple bead is in contact with the package surface). ? care must be taken in order to avoid introducing error into the measurements when measuring a surface temperature. measurement error may be induced by: ? poor thermal contact between the thermocouple junction and the surface of the package. ? contact between the thermocouple ceme nt and the heat-sink base (if used). ? heat loss through thermocouple leads. t c 0 50 100 150 200 250 300 350 400 te m p e ra t u r e ( c ) 45 86.5 79.8 76.45 73.18 70.55 68.5 67.08 65.77 64.68 50 91.09 84.52 79.94 77.02 74.95 73.24 71.75 70.44 69.44 55 95.71 89.26 84.65 81.44 79.22 77.56 76.16 75.01 74.1 60 100.3 94.01 89.45 86.29 84.03 82.39 80.94 79.84 78.97 65 104.9 98.78 94.28 91.16 88.88 87.18 85.79 84.76 83.93 70 109.5 103.6 99.1 96.04 93.77 92.07 90.74 89.7 88.86 75 114.1 108.4 103.9 100.9 98.68 97.06 95.7 94.66 93.8 80 118.7 113.1 108.7 105.8 103.6 101.9 100.7 99.62 98.75 85 123.3 117.9 113.6 110.7 108.5 106.9 105.7 104.6 103.7
137 thermal design recommendations ? I347-AT4 7.10.1.1 attaching the thermocouple (no heat sink) following the guidelines listed in section 7.10.1 , attach the thermocouple at a 0 angle if there is no interference with the thermocouple attach location or leads (see figure 7.6 ). figure 7.6. technique for measuring t case with 0 angle attachment, no heat sink 7.10.1.2 attaching the thermocouple (with a heat sink) in addition to the guidelines listed in section 7.10.1 , the following is also recommended when measuring the t case with a heat sink. ? for testing purposes, a hole (no larger than 0.150 inches in diameter) must be drilled vertically through the center of the heat sink to route the thermocouple wires out. ? attach the thermocouple at a 90 angle if there is no interference with the thermocouple attach location or leads (see figure 7.7 ). ? ensure there is no contact between the thermocouple cement and heat sink base as that provides a heat transfer path from the thermocouple to the heat sink that can affect the thermocouple reading. figure 7.7. technique for measuring t case with 90 angle attachment
138 I347-AT4 ? thermal design recommendations 7.11 conclusion increasingly complex systems require more robust and well thought out thermal solutions. the use of system air, ducting, passive or active heat sinks, or any combination thereof can help lead to a low cost solution that meets your environmental constraints. the simplest and most cost-effective method is to improve the inherent system cooling characteristics through careful design and placement of fans, vents, and ducts. when additional cooling is required, thermal enhancements can be implemented in conjunct ion with enhanced system cooling. the size of the fan or heat sink can be varied to balance size and space constraints with acoustic noise. use the data and methodologies in this section as a starting point to designing and validating a thermal solution for the I347-AT4. by maintaining the i347 -at4 case temperature below those recommended in this section, the I347-AT4 functions properly and reliably. 7.12 heat sink and attach suppliers table 7.5. heat sink and attach suppliers 7.13 pcb layout guidelines the following general pcb design guidelines are re commended to maximize the thermal performance of tfbga packages: ? when connecting ground (thermal) vias to the ground planes, do not use thermal-relief patterns. ? thermal-relief patterns are designed to limit heat transfer between the vias and the copper planes, thus constricting the heat flow path from th e component to the ground planes in the pcb. ? as board temperature also has an effect on the thermal performance of the package, avoid placing the I347-AT4 adjacent to high-power dissipation devices. ? if airflow exists, locate the components in the ma instream of the airflow path for maximum thermal performance. avoid placing the components downstream, behind larger devices or devices with heat sinks that obstruct or significantly preheat the air flow. note: this information is provided as a general guid eline to help maximize the thermal performance of the components. part part number supplier contact alpha heat sinks lpd40-10b lpd25-7b z19-6.3b alpha novatech, inc sales aplha novatech, inc. 408-567-8082 sales@alphanovtech.com aavid-thermalloy heat sink 374324b60023g aavid thermalloy harish rutti 67 primrose dr. suite 200 laconia, nh 03246 business: 972-633-9371 x27 pcm45 series pcm45f honeywell north america technical contact: paula knoll 1349 moffett park dr. sunnyvale, ca 94089 cell: 1-858-705-1274 business: 858-279-2956 paula.knoll@h oneywell.com

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