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preliminary rev. 0.1 9/09 copyright ? 2009 by silicon laboratories SI5356 this information applies to a product under development. its characteristics and specifications are subject to change without n otice. SI5356 i 2 c p rogrammable , a ny -r ate 1?200 mh z , q uad f requency 8-o utput c lock g enerator features applications description the SI5356 is a highly flexible, i 2 c programmable clock generator capable of synthesizing four completely non-integer related frequencies up to 200 mhz. the device has four banks of outputs with each bank supporting two cmos outputs at the same frequency. using silicon laboratories' patented multisynth fractional divider technology, all outputs are guaranteed to have 0 ppm frequency synthesis error regardless of configuration, enablin g the replacement of multiple clock ics and crystal oscillators with a single device. each output bank is independently configurable to support 1.8, 2.5, or 3.3 v. the device is programmable via an i 2 c/ smbus-compatible serial interface and su pports operation from a 1.8, 2.5, or 3.3 v core supply. functional block diagram ? generates any frequency from 1 to 200 mhz on each of the 4 output banks ? programmable frequency configuration ? guaranteed 0 ppm frequency synthesis error for any combination of frequencies ? 25 or 27 mhz xtal or 5?200 mhz input clk ? eight cmos clock outputs ? easy to use programming software ? configurable ?triple a? spread spectrum: any clock, any frequency, and with any spread amount ? programmable output phase adjustment with resolution of 20 ps per step ? interrupt pin indicates los or lol ? oe pin disables all outputs or per bank oe control via i 2 c ? low jitter: 50 ps pk-pk (typ), 100 ps pk-pk period jitter (max) ? excellent psrr performance eliminates need for external power supply filtering ? low power: 45 ma ? core vdd: 1.8, 2.5, or 3.3 v ? separate vddo for each bank of outputs: 1.8, 2.5, or 3.3 v ? small size: 4x4 mm 24-qfn ? industrial temperature range: ?40 to +85 c ? printers ? audio/video ? residential gateways ? dslam ? femtocells ? storage area networks ? switches/routers ? servers ordering information: see page 20. pin assignments xa clk5 clk4 vddoc vddob clk3 clk2 vdd vdd p2 clk6 clk7 los p3 vddoa clk1 clk0 gnd vddod gnd gnd xb p1 clkin p4 p5 top view 1 6 5 4 3 2 712 1110 98 18 13 14 15 16 17 24 1920212223 xa clk5 clk4 vddoc vddob clk3 clk2 vdd vdd scl clk6 clk7 intr sda vddoa clk1 clk0 gnd vddod gnd gnd xb i2c_lsb clkin ssc_dis oeb top view 1 6 5 4 3 2 712 1110 98 18 13 14 15 16 17 24 1920212223 free datasheet http://www.datasheet-pdf.com/
SI5356 2 preliminary rev. 0.1 free datasheet http://www.datasheet-pdf.com/
SI5356 preliminary rev. 0.1 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application ci rcuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1. input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2. breakthrough multisynth technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3. input and output frequen cy configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4. output phase adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5. cmos output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6. jitter performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.7. i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.8. custom device configurat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.9. spread spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.10. power supply considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4. pin descriptions?SI5356 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. package outline: 24-lead qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6. recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 free datasheet http://www.datasheet-pdf.com/
SI5356 4 preliminary rev. 0.1 1. electrical specifications table 1. recommended operating conditions (v dd = 1.8 v ?5% to +10%, 2.5 or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units ambient temperature t a ?40 ? 85 o c core supply voltage v dd 2.97 3.3 3.63 v 2.25 2.5 2.75 1.71 1.8 1.98 output buffer supply voltage v ddo 1.71 ? 3.63 v note: all minimum and maximum specifications are guar anteed and apply across the recommended operating conditions. typical values apply at nominal supply vo ltages and an operating temperature of 25 c unless otherwise noted. table 2. absolute maximum ratings 1 parameter symbol rating units supply voltage range v dd ?0.5 to +3.8 v input voltage range (all pi ns except pins 1,2,5,6) v i ?0.5 to 3.8 v input voltage range (pins 1,2,5,6) v i2 ?0.5 to 1.2 v output voltage range v o ?0.5 to v dd + 0.3 v storage temperature range t s ?55 to +150 o c esd tolerance hbm 2.5 kv cdm 550 v mm 175 v latch-up tolerance lu jesd78 compliant soldering temperature (pb-free profile) 2 t peak 260 o c notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specif ied in the operational sections of this data sheet. exposure to maximum rating cond itions for extended periods may affect device reliability. 2. the device is compliant with jedec j-std-020c. free datasheet http://www.datasheet-pdf.com/
SI5356 preliminary rev. 0.1 5 table 3. dc characteristics (v dd = 1.8 v ?5% to +10%, 2.5 or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units current consumption i dd 100 mhz on all outputs, 25 mhz refclk ?4560ma high level input voltage v ih clkin (cmos), i2c_lsb 0.8 x v dd ?? v low level input voltage v il clkin (cmos), i2c_lsb ??0.2xv dd v clock output high level output voltage v oh pins: clk0-7 i oh = -4 ma v ddo ? 0.3 ? ? v clock output low level out- put voltage v ol pins: clk0-7 i oh = +4 ma ??0.3v los low level output voltage v ollos pin: los i oh = +3 ma 0?0.4v i2c_lsb input resistance r in 20 ? ? k ? free datasheet http://www.datasheet-pdf.com/
SI5356 6 preliminary rev. 0.1 table 4. ac characteristics (v dd = 1.8 v ?5% to +10%, 2.5 or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units input clock clock input frequency f in 5?200mhz clock input rise/fall time t r /t f 20 to 80% v dd ?? 4 ns clock input duty cycle dc < 2 ns tr/tf 40 ? 60 % clock input capacitance c in ?2? pf output clocks clock output frequency f o 1?200mhz clock output frequency synthesis resolution f res see "3.3. input and output frequency configuration" on page 10 ? ? 0 ppm output load capacitance c l ?15? pf clock output rise/fall time t r /t f 20 to 80% v dd , c l = 15 pf ??1.7 ns clock output rise/fall time t r /t f 20 to 80% v dd , c l = 2 pf ? 0.45 0.85 ns clock output duty cycle dc measured at v dd /2 45 50 55 % powerup time t pu por to output clock valid ? ? 2 ms output enable time t oe ??10 s output-output skew t skew outputs at same frequency, f out > 5 mhz ?150 ? +150 ps period jitter j ppkpk 10000 cycles ? 50 100 ps pk-pk pll loop bandwidth f bw ?1.6? mhz free datasheet http://www.datasheet-pdf.com/
SI5356 preliminary rev. 0.1 7 table 5. crystal specifications parameter symbol test condition min typ max units crystal frequency f xtal option 1 ? 25 ? mhz option 2 ? 27 ? mhz load capacitance (on-chip differential) c l 11 12 13 pf crystal output capacitance c o ??4pf equivalent series resistance esr 25 mhz ? ? 100 ? 27 mhz ? ? 75 ? max drive level d l 100 ? ? w table 6. thermal characteristics parameter symbol test condition value units thermal resistance junction to ambient theta ja still air 37 o c/w table 7. i 2 c specifications (scl,sda) 2 parameter symbol test condition standard mode fast mode 3 unit min max min max low level input voltage: v ili2c ?0.5 0.3*v ddi2c ?0.5 0.3*v ddi2c 1 v high level input voltage: v ihi2c 0.7*v ddi2c 3.63 0.7* v ddi2c 1 3.63 v hysteresis of schmitt trigger inputs v hys n/a n/a 0.1 ? v low level output voltage (open drain or open collector) at 3 ma sink current v oli2c 1 v ddi2c 1 = 2.5 / 3.3 v 0 0.4 0 0.4 v v ddi2c 1 = 1.8 v n/a n/a 0 0.2 x v ddi2c v input current i ii2c ?10 10 ?10 10 a capacitance for each i/o pin c ii2c v in = ?0.1 to v ddi2c ?4 ? 4p f i 2 c bus timeout ? 25 35 25 35 msec notes: 1. only i 2 c pull up voltages (vddi2c) of 1.71 to 3.63 v are supported. must write r egister 27[7] = 1 if the i 2 c bus voltage is less than 2.25 v. 2. refer to nxp?s um10204 i 2 c-bus specification and user manual, revision 03, for further details: www.nxp.com/acrobat_download /usermanuals/um10204_3.pdf. 3. compliant with fast mode+ pending characterization. free datasheet http://www.datasheet-pdf.com/
SI5356 8 preliminary rev. 0.1 2. typical application circuits i 2 c bus i 2 c address = 0x70 +3.3v 1k 1k 1k ethernet phy SI5356 4-port ethernet switch/router 33/66 mhz 125 mhz x x ethernet phy ethernet phy ethernet phy 22 18 14 10 9 25 mhz clk0 clk2 clk4 clk6 clk7 21 clk1 17 clk3 13 clk5 ethernet switch mcu/ processor 16 15 11 20 24 7 vddoa vddob vddoc vddod vdd vdd 1 2 4 25 mhz xtal xa xb clkin 25 mhz 25 mhz 25 mhz 23 gnd gnd pad 23 pad 5 6 ssc_dis oeb 2.2k 1k 8 intr 19 12 3 sda scl i2c_lsb +3.3v +3.3 v 0.1 uf power supply decoupling capacitors (1 per vdd or vddox pin) i 2 c bus i 2 c address = 0x70 +3.3v 1k 1k 1k SI5356 laser printer x x 22 18 14 10 9 clk0 clk2 clk4 clk6 clk7 21 clk1 17 clk3 13 clk5 16 15 11 20 24 7 vddoa vddob vddoc vddod vdd vdd 1 2 4 25 mhz xtal xa xb clkin 23 gnd gnd pad 23 pad 5 6 ssc_dis oeb 8 intr 19 12 3 sda scl i2c_lsb processor 125 mhz ddr memory touchscreen controller usb controller print head paper tray lcd screen key pad 48 mhz 66/100 mhz ethernet phy 35.788 mhz x x +3.3 v 0.1 uf power supply decoupling capacitors (1 per vdd or vddox pin) free datasheet http://www.datasheet-pdf.com/
SI5356 preliminary rev. 0.1 9 3. functional description 3.1. input configuration the SI5356 input can be driven from either an external cryst al or a reference clock. if the crystal input option is used, the SI5356 operates as a free-running clock generator. in this mode of operation the device requires a low cost 25 or 27 mhz fundamental mode crystal connected across xa and xb as shown in figure 1. given the SI5356?s frequency flexibility, the same crystal can be reused to generate any combination of output frequencies. custom frequency crystals are not required. the SI5356 in tegrates the crystal load capacitors on-chip to reduce external component count. the crystal should be placed ve ry close to the device to minimize stray capacitance. to ensure a stable and accurate output frequency, the recommended crystal specifications provided in table 5 on page 7 must be followed. see an360 for additional details regarding crystal recommendations. figure 1. connecting an xtal to the SI5356 for synchronous timing applications, the SI5356 can lock to a 5 to 200 mhz cmos reference clock. a typical interface circuit is shown in figure 2. a series terminatio n resistor matching the driver?s output impedance to the impedance of the transmission line is recommended to reduce reflections. figure 2. interfacing cmos reference clocks to the SI5356 3.2. breakthrough multisynth technology modern timing architectures require a wide range of freq uencies which are often non-integer related. traditional clock architectures address this by using a combination of single pll ics, 4-pll ics and discrete xos, often at the expense of bom complexity and power. the SI5356 use pa tented multisynth technology to dramatically simplify timing architectures by inte grating the frequency synthesis capability of 4 phase-locked loops (plls) in a single device, greatly minimizing size and power requirements ve rsus traditional solutions. based on a fractional-n pll, the heart of the architecture is a low phase noise, hi gh-frequency vco. the vco supplies a high frequency output clock to the multisynth block on each of the four indepe ndent output paths. each mu ltisynth operates as a high- speed fractional divider with silicon labor atories' proprietary phase error corr ection to divide down the vco clock to the required output frequency with very low jitter. the first stage of the multisynth architecture is a fracti onal-n divider which switches seamlessly between the two closest integer divider values to pr oduce the exact output clock frequency with 0 ppm error. to eliminate phase error generated by this process, multisynth calculates the relative phase difference between the clock produced by the fractional-n divider and the desired output clock an d dynamically adjusts the phase to match the ideal clock waveform. this novel approach makes it possible to generat e any output clock frequency without sacrificing jitter performance. based on this architecture, the output of each multisynth can produce any frequency from 1 to 200 mhz. xb xa xtal SI5356 clkin 50 rs SI5356 free datasheet http://www.datasheet-pdf.com/
SI5356 10 preliminary rev. 0.1 figure 3. silicon labs' multisynth technology 3.3. input and output frequency configuration the SI5356 utilizes a single pll-based ar chitecture, four independent multisyn th fractional output dividers, and a multisynth fractional feedback divider such that a single device provides the cl ock generation capability of 4 independent plls. unlike competitive multi-pll solution s, the SI5356 can generate four unique non-integer related output frequencies with 0 ppm frequency error for an y combination of output frequencies. in addition, any combination of output frequencies can be generated from a single reference frequency without having to change the crystal or reference clock frequency between frequency configurations. frequency configurations are fully programmable by writing to device registers using the i 2 c interface. any combination of output frequencies ranging from 1 to 20 0 mhz can be configured on eac h of the device outputs. the following equation governs how the output frequency is calculated. where f in is the reference frequency, n is th e multisynth feedback divider value, p is the reference divider value, m i is the multisynth output divider value and f out is the resulting output frequency. the multisynth output and feedback dividers are fractional dividers expressed in term s of an integer and a fraction. the integer portion has 10-bit resolution and the fractional portion has 30-bit re solution in both the numerator and denominator, meaning that any output frequency can be de fined exactly from the input frequen cy with exact (0 ppm) frequency synthesis error. 3.4. output phase adjustment the SI5356 has a digitally-controlled phase adjustment feat ure that allows the user to adjust the phase of each output clock in relation to the other output clocks. the phase of each output clock can be adjusted with an accuracy of 20 ps per step over a range of 45 ns. this feature is available on any clock output that does not have spread spectrum enabled. fractional-n divider phase adjust phase error calculator divider select (div1, div2) f vco f out multisynth f out f in n ? pm i ? ----------------- = free datasheet http://www.datasheet-pdf.com/
SI5356 preliminary rev. 0.1 11 3.5. cmos output drivers the SI5356 has 4 banks of outputs with each bank compri sed of 2 clocks for a total of 8 cmos outputs per device. each of the output banks can operate from a differen t vddo supply (1.8 v, 2.5 v, 3.3 v), simplifying usage in mixed supply applications. all clock outputs betw een 5 and 200 mhz are in-phase to within 150 ps. the cmos output driver has a controlled impedance in the range of 42 to 50 ? . an external series resistor can be added to provide optimum impedance matching with higher impedance traces. a typical configuration is shown in figure 4. figure 4. cmos output driver configuration 3.6. jitter performance the SI5356 provides consistently low jitter for any combi nation of output frequencies. the device leverages a low phase noise single pll architecture and silicon labora tories? patented multisynth fractional output divider technology to deliver period jitter less than 100 ps pk-pk (m ax) for any frequency configur ation. this level of jitter performance is guaranteed across process, temperature and voltage. the SI5356 provides superior performance to traditional multi-pll solutions which may suffer from degraded jitter performance depending on frequency plan and the number of active plls. multisynth bank a +1.8v, +2.5v, +3.3v vddoa clk0 clk1 multisynth bank c +1.8v, +2.5v, +3.3v vddoc clk4 clk5 multisynth bank d +1.8v, +2.5v, +3.3v vddod clk6 clk7 multisynth bank b +1.8v, +2.5v, +3.3v vddob clk2 clk3 pll 50 50 50 50 50 50 50 50 SI5356 free datasheet http://www.datasheet-pdf.com/
SI5356 12 preliminary rev. 0.1 3.7. i 2 c interface the SI5356 control interface is a 2-wire bus for bidirectio nal communication. the bus consists of a bidirectional serial data line (sda) and a serial clock input (scl). the device operates as a slave device on the 2-wire bus and is compatible with i 2 c specifications. both lines must be connected to the positive supply via an external pull-up. standard-mode (100 kbps) and fast-mode (400 kbps) operation and 7-bit addressing are supported as specified in the i 2 c-bus specification standard. to accommodat e multiple SI5356 devices on the same i 2 c bus, the SI5356 has pin 3 as i2c_lsb. the complete 7-bit i2c bus address for the device is 70h or 71h depending upon the state of the i2c_lsb pin. in binary, this is written as 111 000[i2c_lsb]. see figure 5 for the command format for both read and write access. data is always sent msb first. table 7 includes the ac and dc electrical parameters for the scl and sda i/os, respectively. the timing specificat ions and timing diagram for the i 2 c bus can be found in the i 2 c-bus specification standard. sda timeout support is supported for compatibility with smbus interfaces. the i 2 c interface is 3.3 v tolerant. the i 2 c bus can be operated at a bus voltage of 1.71 to 3. 63 v and should have a pullup resistor as recommended by the i 2 c-bus specification. figure 5. i 2 c/smbus-compatible command format 3.8. custom device configurations the SI5356 is fully configurable by writ ing to internal registers through the i 2 c interface. after each power cycle the register settings are restored to their factory default values. for applications that require a custom configuration at power-up, the SI5356 is orderable with a custom default r egister setting. see "7. ordering guide" on page 20 more for details. from master to slave from slave to master 1 ? read 0 ? write a ? acknowledge (sda low) n ? not acknowledge (sda high). required after the last data byte to signal the end of the read comand to the slave. s ? start condition p ? stop condition repeated start read write a reg addr [7:0] a s slv addr [6:0] 0 s slv addr [6:0] 1 a a data [7:0] n p data [7:0] a a reg addr [7:0] a s slv addr [6:0] 0 a data [7:0] data [7:0] p read data a data [7:0] a s slv addr [6:0] 1 n p data [7:0] write data a reg addr [7:0] a s slv addr [6:0] 0 p two command read optional optional optional free datasheet http://www.datasheet-pdf.com/
SI5356 preliminary rev. 0.1 13 3.9. spread spectrum to reduce electro magnetic interference (emi), the SI5356 supports spread spectrum modulation. the output clock frequencies can be modulated to spread energy across a broader range of frequencies, lowering system emi. the modulation rate is the time required to transition from the maximum spread spectrum frequency to the minimum spread spectrum frequency and then back to the maxi mum frequency. the SI5356 implements spread spectrum using patented multisynth technology to achieve previously unattainable precision in both modulation rate and spreading magnitude as shown in figure 6. this enables th e SI5356 to provide ?triple a? spread spectrum. spread spectrum can be applied to any output clock, any clock frequency, and any spread amount. spread spectrum can be enabled or disabled on a per-bank basis. the device supports center spread (0.1% to 5%) and down spread (?0.1% to ?5%). in addition, the device has extensive on-chip voltage regulation such that power supply variation does not influence the device?s spread spectrum clock waveforms. the programming of spread spectrum is made easy by us ing the SI5356 programmer. spread spectrum on all the outputs can be enabled or disabled using the ssc_dis pin, or independently for each output bank through the i 2 c interface. figure 6. configurable spread spectrum -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -10% -8% -6% -4% -2% 0% 2% 4% 6% 8% 10% relative f requency relative power (db ) 1.0% 2.5% 5.0% no spread free datasheet http://www.datasheet-pdf.com/
SI5356 14 preliminary rev. 0.1 3.10. power supply considerations the SI5356 has two core supply voltage pins (v dd ) and four clock output bank supply voltage pins (v ddoa ? v ddod ), enabling the device to be used in mixed supply applications. the SI5356 does not require ferrite beads for power supply filtering. the device has extensive on-chip power supply regulation to minimize the impact of power supply noise on output jitter. figure 7 shows that the a dditive jitter created when a significant amount of noise is applied to the device powe r supply is very small. figure 7. peak-to-peak additive jitter from 100 mv sine wave on supply 0 1 2 3 4 5 6 7 8 9 10 0.0001 0.001 0.01 0.1 1 modulation frequency (mhz) additive jitter (pk-pk) vddo vdd free datasheet http://www.datasheet-pdf.com/
SI5356 preliminary rev. 0.1 15 4. pin descriptions?SI5356 note: center pad must be tied to gnd for normal operation. table 8. SI5356 pin descriptions pin # pin name i/o description 1xa i external crystal. if a 25 or 27 mhz crystal is used as the dev ice frequency reference, connect it across xa and xb. if no input clock is used, this pin should be tied to gnd. 2xb i external crystal. if a 25 or 27 mhz crystal is used as the dev ice frequency reference, connect it across xa and xb. if no input clock is used, this pin should be tied to gnd. 3 i2c_lsb i i 2 c lsb address bit this pin is the least significant bit of the SI5356 i 2 c address allowing up to two SI5356 devices to occupy the same i 2 c bus. 4clkin i single-ended input clock. if a single-ended clock is used as the device frequency reference, connect it to this pin. this pin functions as a high-impedance inpu t for cmos clock signals. the input should be dc coupled. if a crystal is used as the device frequency reference, this pin should be tied to gnd. xa clk5 clk4 vddoc vddob clk3 clk2 vdd vdd scl clk6 clk7 intr sda vddoa clk1 clk0 gnd vddod gnd gnd xb i2c_lsb clkin ssc_dis oeb top view 1 6 5 4 3 2 712 1110 98 18 13 14 15 16 17 24 1920212223 free datasheet http://www.datasheet-pdf.com/
SI5356 16 preliminary rev. 0.1 5 ssc_dis i spread spectrum disable. this pin allows disabling of the spread spectrum feature on the output clocks. connect to 1.2 v to disable spread spectrum on all outputs. connect to gnd to enable spread spectrum. note that the maximum voltage le vel on this pin must not exceed 1.2 v. a resistor voltage divider is recommended when controlled by a signal greater than 1.2 v. see the typical application circuit for details. 6oeb i output enable (active low) this pin allows disabling the output clocks. connect to 1.2 v to disable all outputs. connect to gnd to enable all outputs. note that the maximum voltage level on this pin must not exceed 1.2 v. a resistor voltage di vider is recommended when controlled by a signal greater than 1.2 v. see the typi cal application circuit for details. 7vddvdd core supply voltage. the device operates from a 1.8, 2.5, or 3.3 v supply. a 0.1 f bypass capacitor should be located very close to this pin. 8intro interrupt this pin functions as an maskable interrupt output. 0 = no interrupt 1 = interrupt present this pin is open drain and requires an external > 1k : pullup resistor. 9clk7o output clock 7. cmos output clock. if unused, this pin must be left floating. 10 clk6 o output clock 6. cmos output clock. if unused, this pin must be left floating. 11 vddod vdd clock output bank d supply voltage. power supply for clock outputs 6 and 7. may be operated from a 1.8, 2.5, or 3.3 v sup- ply. a 0.1 f bypass capacitor should be located very close to this pin. if clk6/7 are not used, this pin must be tied to pin 7 and/or pin 24. 12 scl i i 2 c serial clock input. 13 clk5 o output clock 5. cmos output clock. if unused, this pin must be left floating. 14 clk4 o output clock 4. cmos output clock. if unused, this pin must be left floating. 15 vddoc vdd clock output bank c supply voltage. power supply for clock outputs 4 and 5. may be operated from a 1.8, 2.5 or 3.3 v sup- ply. a 0.1 f bypass capacitor should be located very close to this pin. if clk4/5 are not used, this pin must be tied to pin 7 and/or pin 24. 16 vddob vdd clock output bank b supply voltage. power supply for clock outputs 2 and 3. may be operated from a 1.8, 2.5, or 3.3 v sup- ply. a 0.1 f bypass capacitor should be located very close to this pin. if clk2/3 are not used, this pin must be tied to pin 7 and/or pin 24. 17 clk3 o output clock 3. cmos output clock. if unused, this pin must be left floating. 18 clk2 o output clock 2. cmos output clock. if unused, this pin must be left floating. table 8. SI5356 pin descriptions (continued) free datasheet http://www.datasheet-pdf.com/
SI5356 preliminary rev. 0.1 17 19 sda i/o i 2 c serial data. 20 vddoa vdd clock output bank a supply voltage. power supply for clock outputs 0 and 1. may be operated from a 1.8, 2.5, or 3.3 v sup- ply. a 0.1 f bypass capacitor should be located very close to this pin. if clk0/1 are not used, this pin must be tied to pin 7 and/or pin 24. 21 clk1 o output clock 1. cmos output clock. if unused, this pin must be left floating. 22 clk0 o output clock 0. cmos output clock. if unused, this pin must be left floating. 23 gnd gnd ground. must be connected to system ground. minimize the ground path impedance for optimal performance of the device. 24 vdd vdd core supply voltage. the device operates from a 1.8, 2.5, or 3.3 v supply. a 0.1 f bypass capacitor should be located very close to this pin. gnd pad gnd gnd ground pad. this is the large pad in the center of the package. nine or more vias should be used to connect this pad to a ground plane. device specifications canno t be guaranteed unless the ground pad is properly connected to a ground plane on the pcb. table 8. SI5356 pin descriptions (continued) free datasheet http://www.datasheet-pdf.com/
SI5356 18 preliminary rev. 0.1 5. package outline: 24-lead qfn figure 8. 24-lead quad flat no-lead (qfn) table 9. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d 4.00 bsc. d2 2.35 2.50 2.65 e 0.50 bsc. e 4.00 bsc. e2 2.35 2.50 2.65 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jede c outline mo-220, variation vggd-8. 4. recommended card reflow profile is per the jede c/ipc j-std-020c specification for small body components. free datasheet http://www.datasheet-pdf.com/
SI5356 preliminary rev. 0.1 19 6. recommended pcb layout table 10. pcb land pattern dimension min nom max p1 2.50 2.55 2.60 p2 2.50 2.55 2.60 x1 0.20 0.25 0.30 y1 0.75 0.80 0.85 c1 3.90 c2 3.90 e0 . 5 0 notes: general 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. solder mask design 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 5. a stainless steel, laser-cut and electro-polished stencil wit h trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 8. a 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the jedec/ ipc j-std-020c specificatio n for small body components. free datasheet http://www.datasheet-pdf.com/
SI5356 20 preliminary rev. 0.1 7. ordering guide SI5356a axxxxx g i 2 c programmable any-rate 1?200 mhz quad frequency 8-output clock generator a = product revision xxxxx = 5-digit custom code assigned to each unique device configuration. leave xxxxx blank for standard factory default configuration (SI5356a-a-gmr) m = rohs6, pb-free qfn m r r = tape & reel blank = tubes g = ?40 to +85 o c free datasheet http://www.datasheet-pdf.com/
SI5356 preliminary rev. 0.1 21 n otes : free datasheet http://www.datasheet-pdf.com/
SI5356 22 preliminary rev. 0.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories, silicon labs, and clockbuilder are trademar ks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. free datasheet http://www.datasheet-pdf.com/

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